IEEE TRANSACTIONS ON COMPUTERS, VOL. C-22, NO. 11, NOVEMBER 1973

Complete Test Sets for Logic FunctionsSUDHAKAR M. REDDY

Abstract-The problem of designing fault detecting test sets fromthe functional description rather than the structural description ofthe networks realizing the logic function is studied. The concept ofan expanded truth table for logic functions is introduced. It is provedthat the set of minimal true vertices and maximal false vertices ofthe expanded truth table constitutes a test set to detect any numberof stuck-at-faults in a network belonging to a class of restricted net-works, called unate gate networks. It is further indicated that even

in the presence of redundancies in the network, the test sets givenremain valid.

Index Tenns-Complete test sets, expanded truth table, fault detect-ing test sets, logic networks, multiple stuck-at-faults, restricted gatenetworks, stuck-at-faults, unate gate networks.

I. INTRODUCTIONSOLUTIONS to the problem of designing test sets to de-

tect faults in an arbitrary realization of a logic functionare extremely important, since, normally attempts to derivetest sets for a given realization are unwieldy. Also, the givenrealization may have redundancies in it that might cause thetest sets to become invalid [2]. An elegant solution to thisproblem has been given by Betancourt [1] for the case ofunate functions, where the networks realizing these functionsare allowed to have a single permanent stuck-at-zero (s-a-0)or stuck-at-one (s-a-i) fault.In this paper we extend Betancourt's [1] result to multiple

stuck-at-faults and arbitrary logic functions.1 The importantdifference between the work reported now and the work re-

ported in [6] and [7] is that we do not assume that theactual network realizing a function is known.For the sake of completeness and ease in reading, we will

give several definitions and develop a certain amount of nota-tion in this section.

Notation

f n-variable logic function.F Network realizingf that is being tested for faults.u Unate function.X, Y, etc. Input vectors (vertices).X True vertex off iff(X) = 1.X False vertex off if (X) =0.Xi Input variable.

xl Input literal, which is xi or xi (complement ofxi).

Manuscript received October 8, 1972; revised December 26, 1972.This work was supported in part by the Office of Naval ResearchGrant N00014-68-A-0500 and in part by NSF Grant GK-36377.The author is with the Department of Electrical Engineering, Uni-

versity of Iowa, Iowa City, Iowa 52240.'Some of the results given in this paper were independently ob-

tained by Akers [8] . We will indicate these in the paper.

xi

xj Network N fS L.2_ of AND/OR Gates

'2

ir iI

Fig. 1. Restricted gate network realizing f.

Fig. 2. Restricted gate network realizing g.

Definition 1: A logic function f is positive unate in literalx4 if for every input vector X, such that f(X) = 1, with xitaking the value to make x4 = 0, also implies f(Y) = 1 whereY is obtained by complementing the value of xi in X. If a

function is not positive unate in xi or xi, then it is not unatein xi. If f is positive unate in xl, then f is not positive unatein i*. (We are assuming that f is not independent of xi.)Definition 2: A logic function f is a positive unate function

of literals x7, 42- , ix* if it is positive unate in xi1 < j < Q. Notice that this definition of a positive unatefunction differs from the usual definition, which is given interms of input variables.Definition 3: A logic network constructed from AND, OR,

NAND, NOR, and NOT gates is callQd a gate network. If onlyAND and/or OR gates are used and inverters, if necessary, are

used at the external inputs to gates, then it is called a re-stricted gate network. A block diagram of a general restrictedgate network, for a logic function f that is not unate invariables x;, , xj2, , x, and is positive unate in literals

XI1, X12, * * *,xr, is given in Fig. 1. The function g = ab +

ac + a7d + ac realized by a restricted gate network is givenin Fig. 2.Definition 4: If the network N of Fig. 1 is realized by a

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REDDY: COMPLETE TEST SETS

general gate network such that the number of inversions inany path connecting two points in the gate network are thesame, then the gate network is called a unate gate network.(An important point to note is that if f is positive unate inxl then we allow either x' or xl (but not both) as input tothe networkN when unate networks are considered.)We will give an example to illustrate Definition 4. In Fig.

3(a) a gate network that is not a unate gate network is given.There are two paths between the points ae and 3 of the net-work, one through gates 2 and 7, and the other through gates3 and 7. The number of inversions in the first path is twoand in the second path is one and hence the network is not aunate gate network. In Fig. 3(b) the network of Fig. 3(a)is modified to obtain a unate gate network. Notice that eventhough there are paths between two points, in the overall net-work of Fig. 3(b), with odd and even number of inversions,there are no pairs of paths of this type in that part of thenetwork that corresponds to network N of Fig. 1 (the portionof the network of Fig. 3(b) within the boundary defined bythe dashed lines). For example, there are two paths from -yto 6, one through gates 4 and 7 and the other through gates 5,6, and 7. The first path has one inversion and the secondpath has two inversions. But the point y is not inside thedashed lines. Notice that though the function X realized bythe network of Fig. 3(b) is positive unate in d, f, and g, thenetwork inputs are d, f, andg.Definition 5: A restricted gate network NR is said to be

an equivalent network for unate gate network Nu if and onlyif every test set T that detects all stuck-at-faults in NR alsodetects all stuck-at-faults in Nu. Clearly NR will be equiv-alent to Nu if for every stuck-at-fault in Nu there is a cor-responding stuck-at-fault in NR.In this paper we give an algorithm to derive test sets to

detect all stuck-at-faults in restricted and unate gate networks.Our strategy in deriving test sets to detect multiple stuck-at-faults is first to determine a method to derive test sets forrestricted gate networks. From the definition of the equiv-alent restricted gate network we can claim that the test setderived for the restricted gate networks will also detect faultsin unate gate networks, if we can show that for every unategate network there is an equivalent restricted gate network.We will next give an algorithm -to convert a unate gate net-

work to an equivalent restricted gate network. The validityof the algorithm and the validity of the claim that any faultin the unate gate network can be represented by a fault inthe resulting restricted gate network can be established in astraightforward manner. These proofs are not given here toconserve space.

Algorithm 1

Step 1: Change all NAND (NOR) gates to AND-NOT (OR-NOT)combination of gates.Step 2: Arrange the AND and OR gates into levels starting

with output gate as level 1. NOT gates are not considered increating levels. A gate is considered to be in (j + 1)th levelif j is the highest level of the gates driven by this gate. Leti = 1.

a a--%,

b

C

d

e

(a)

n~

)

(b)

Fig. 3. (a) Gate network realizing w. (b) Unate gate networkrealizing w.

Step 3: Replace a sequence of NOT gates by a single NOTgate (if odd number of NOT gates in the sequence) or by aninversionless line (if even number of NOT gates in the se-quence). Also, if the output of an AND (OR) gate in ith levelis fanned out to more than one input then each lead fromthe output of such an AND (OR) gate must either contain aninverter or no lead will have an invertor, because of Definition4. If each lead has an invertor, delete all these invertors andinclude an invertor at the output of the appropriate AND (OR)gate. If the modified network is a restricted gate networkstop.Step 4: Convert each AND-NOT (OR-NOT) pair (i.e., an

AND (OR) gate followed by a NOT gate), including an AND(OR) gate in ith level, to an OR (AND) gate with NOT gatesat its inputs by applying DeMorgan's laws.Step 5: If the modified network is a restricted gate network

stop; otherwise let i = i + 1 and got to Step 3.As an example, the restricted gate network obtained from

the unate gate network of Fig. 4(a) is given in Fig. 4(b). Itis not difficult to check that for every s-a-x (x = 0 or 1)fault in the network of Fig. 4(a) there is an equivalent stuck-at-fault in the network of Fig. 4(b). In general, it can beshown that if a restricted gate network N2 is obtained froma unate gate network N1 by applying Algorithm 1 then for

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IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1973

r - -7

_ JI_

a b c

* * * _

X1 X2** * Xn u 0 0 0

' 0 10 0. .0 0

0 1 0O O . 1 O0 1 1

* *10*1 0 1

1 0 1

1 1 01 1 1 1 1 1

(a) (b)

u

0

0

0

1

1

1

1

1

Fig. 5. (a) Truth table for positive unate functions. (b) Truth tablefor a + bc.

(a)a b b c f

O 0 1 0

O 0 1 1

0 1 0 0

0 1 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

0

1

0

0

0

1

1

1

I___-(b)

Fig. 4. (a) Unate gate network. (b) Restricted gate network equiva-lent to Fig. 4(a).

each s-a-x fault in N1 there is an equivalent stuck-at-fault inN2.We will be developing test sets for detecting multiple faults

in restricted gate networks realizing positive unate functionsand arbitrary logic functions. It is useful to develop a defini-tion of input vectors, slightly different from the usual one,to these networks. Note that if a logic function is positiveunate in x4, then only x4 need be applied as an input to arestricted gate network realizing f; i.e., we need not applyxl as an input to networkN of Fig. 1.The truth table for a n-variable logic function, as defined

normally, is a table of 2n rows or 2n n-dimensional binaryinput vectors and one column of binary functional values.It will be useful in the next section to define the input vectorsover input literals (or a set of expanded input literals) in-stead of over input variables.

NotationThe truth table of a positive unate function u over the set

of literals {xl, x2, X, - ,x} is written as given in Fig. 5(a).An example, the truth table of the function aT + b cF, is givenin Fig. 5(b).The truth table of a logic function that is positive unate in

the set of literals {x7, x , x7*} and not unate in the setof variables xi,, xj2, - , xjS is written as that of a positive

Fig. 6. Expanded truth table of ab + be.

unate function over the expanded set of literals 1x7 , x72,.**~~ JO Ii' /2' 12' 15' IS ~~ 1 1

1Xi,Xj Xjl, Xj2,) Xj2,***, XS,JXjs .

The n-dimensional ((n + s)-dimensional) binary vectors thatare the rows of the truth table (expanded truth table) arecalled input vectors (expanded input vectors).As an example, in Fig. 6, the expanded truth table of the

function a b + b c is given. Notice that even though thelength of the input vectors is larger in the expanded truthtable, the number of these vectors has not increased.Definition 6: An input vector (expanded input vector) X

covers the input vector (expanded input vector) Y if and onlyif X has l's everywhere Y has l's and we write X > Y. IfX ; Y and Y - X, then we say that X and Y are notcomparable.Definition 7: A minimal true vertex (minimal expanded

true vertex) of a logic function is the input vector (expandedinput vector) that does not cover any other true vertex ex-cept itself. A maximal false vertex (maximal expanded falsevertex) of a logic function is the input vector (expandedinput vector) that is not covered by any other false vertexexcept itself.For example, the minimal expanded true vertices of the

function given in Fig. 6 are [00O1, 1 100] and the maximalexpanded false vertices are [0101, 1010].Definition 8: A set of test inputs T is called a complete

test set for a logic function f if all stuck-at-faults in any unategate network realization off can be detected by the applica-tion of T.

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REDDY: COMPLETE TEST SETS

In the next section we will show that the set of minimalexpanded true vertices and maximal expanded false verticesof a logic function f constitutes a complete test set for f.

II. COMPLETE TEST SETS

In Theorem 1 we give an extension of Betancourt's [1]result that shows that for any restricted gate network realiza-tion of a positive unate function the set of maximal falsevertices and minimal true vertices constitutes a sufficient testset to detect all s-a-O and s-a-I faults in the network. Theorem1 is extended in Theorem 2 to include all logic functions.Akers [81 has independently obtained these two theorems.We will prove Theorem 1 since the proof technique is dif-ferent from Akers' [8] and also since no formal proof appearsin Akers' [8] paper.In the sequel we will be using U(X) or F(X) to refer to the

output of the network under test, that is realizing the logicfunction u or f, respectively, when input X is applied to thenetwork.Definition 9: A lead in a gate network is redundant if a

logical constant 1 or 0 can be assumed without changing thefunctional value of the output.Theorem 1: In any restricted gate network realization of a

positive unate function u, all stuck-at-faults can be detectedby applying the maximal false vertices and the minimal truevertices of u as test inputs.

Proof: Proof is obtained by showing that if U(X) = u(X)for every test input [i.e., the output of the network undertest, U(X), equals the functional value u(X)] , then U(Y) =u(Y)for every input. Assume u is positive unate over the literalsxl, x2, , xn. Let U(X) = u(X) for every test input andu(Y) = 1 and u(Z) = O for some Y and Z. u(Y) = 1 impliesthat Y > X, X is some minimal true vertex. If Y = X thenU(Y) = u(Y) = 1 by assumption and hence let Y > X andY # X. Therefore, X can be changed to Y by changing someentries in X from 0 to 1 and let these correspond to thepositions il, i2, * , il. Clearly, the outputs of all the gatesin the network connected toxl x * xl will changefrom 0 to 0 or 0 to 1 or I to 1 when x?'s change from O to 1and by repeating the argument we see that the output of thenetwork changes from 0 to 0 or 0 to 1 or I to 1.2 ButU(X) = I and hence the output of the network changes from1 to 1 when the input changes from X to Y and henceU(Y) = 1. By similar arguments we can show that U(Z) = 0for every Z such that u(Z) = 0. Therefore, if U(X) = u(X)for all test inputs then U(X) = u(X) for every input X, whichis the same as saying that the network correctly realizes u iffor no test input X, U(X) # u(X) and if for some test inputU(X) # u(X) clearly the network under test is not realizing u.

Q.E.D.Next we give a straightforward extension of Theorem 1 to

arbitrary n-variable logic functions. Let f be a function thatis positive unate in the literals, say xl,, x72, * * , x4, and not

2Notice that this happens since the restricted gate networks con-tain AND and OR gates only and their outputs cannot change from 1to 0 if the inputs change from 0 to 1.

xiIJl

Ij2Xisft5IxIs t-

jx*x2

XirFig. 7. Restricted gate network realizing f.

a b c d

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

(a)

a a b c dfi

0 0 1 0 0

O 0 1 0 0

1 0 1 0 1

1 0 1 0 1

0 0 1 1 0

0 0 1 1 0

1 0 1 1 1

1 0 1 1 1

0 1 0 0 0

0 1 0 0 0

0 1 0 01

1 1 0 0 1

1 1 0 1 0

1 1 0 io1 1 0 1 1

1 1 0 1 1

(b)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fi

0

0

1

1

0

0

1

1

0

0

0

1

1

1

1

Fig. 8. (a) Truth table for fi. (b) Expanded truth table for fi.

unate in the input variables x11, x12,, ,x1S. The restrictedgate network realization of such a function is given in Fig. 7.The important point to note in this realization is that onlyeither a complemented (if Xk = xlk) or the uncomplemented(if X7k = xik) form of the input variable Xik is applied to theAND-OR gate network N, 1 < k < r. When we say that theexpanded input vector X is applied to N, then the corre-

sponding input vector obtained from the original truth tableis applied as input to N. For exanple, consider the functionI1 whose truth table and the expanded truth table are givenin Fig. 8(a) and (b), respectively. A restricted gate networkrealizing fi is given in Fig. 9. When we say that the expandedinput 01010 is applied to the network of Fig. 9, we mean thatthe input 0010 is applied. Furthermore for every input (arow of the truth table) there is a unique expanded input (andvice versa) as is evident from the tables in Fig. 8.Theorem 2: The set of minimal expanded true vertices and

maximal expanded false vertices of f are sufficient to testfor all s-a-I and s-a-0 faults in any restricted gate networkrealization of f.

Notwork Nof AND/OR Gates

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f

IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1973

Fig. 9. Restricted gate network realizing fi.

The proof is deleted since it is a straightforward extensionof the proof of Theorem 1.In the proof of Theorems 1 and 2 we have not assumed

that the networks under test are irredundant and hence thetest sets given are sufficient even if there were redundanciesin the network. This fact is especially important in the lightof Friedman's [2] observation that faults in redundant leadsmay make some test sets invalid.The major drawback of the test sets of Theorem 2 is the

fact that these can be very large. For logic functions that arenot unate in any input variable, no two expanded input vec-tors are comparable and hence the complete test set containsall the 2n input vectors. Of course, if we want to test anyrealization (i.e., redundant or irredundant) of such logic func-tions, we cannot expect to do any better. But if we putsome reasonable restrictions on the networks realizing thelogic function, then we may be able to reduce the size ofthe test sets. An algorithm to design certain class of restrictednetworks and to derive test sets to detect stuck-at-faults inthese networks has been developed and may be given inanother paper.

It is not difficult to see that Theorems 1 and 2 can beextended to unate gate networks. This can be seen fromAlgorithm 1 and the observations made in the last section.The test set for a unate gate network Nu can be obtainedby generating the test set for the equivalent restricted gatenetwork obtained by applying Algorithm 1 to Nu. Clearly,this implies that the test set given by Theorem 2 detects allstuck-at-faults in unate gate networks also. We state theseobservations formally in Theorem 3.Theorem 3: The set of minimal expanded true vertices and

maximal expanded false vertices of a logic function f con-stitutes a complete test set forf.As an example, we will derive a test set for the function ft,

whose truth table is given in Fig. 8(a) and the expanded truth

table in Fig. 8(b). The minimal expanded true vertices of fiare [01010, 1001 1, 10100] and the maximal expanded falsevertices are [01101, 10001, 10010]. The input vectors(related to variables a, b, c, and d) corresponding to theseexpanded vectors are [0010, 1011, 1100] and [0101, 1001,1010] and these test inputs will detect all stuck-at-faults inan arbitrary restricted or unate gate network realizingf, evenif there were redundancies in these networks.

It is appropriate to point out that Akers [8] has given analgebraic method to derive the test sets given in Theorems 1and 2 and also discusses testing of the multiple output net-works. However, the results given for unate gate networksdo not appear in Akers' [8] paper.

III. CONCLUSIONSIn this paper the problem of designing fault detecting test

sets from the functional description rather than the structuraldescription of the networks realizing the logic functions wasstudied. The concept of an expanded truth table for logicfunctions was introduced. It is proved that the set of minimaltrue vertices and maximal false vertices of the expandedtruth table constitutes a test set to detect any number ofstuck-at-faults in a unate gate network.The results of this paper have been extended to general gate

networks and may be reported in another paper.

REFERENCES[1] R. Betancourt, "Derivation of minimum test sets for unate logical

circuits," IEEE Trans. Comput., vol. C-20, pp. 1264-1269, Nov.1971.

[2] A. D. Friedman, "Fault detection in redundant circuits," IEEETrans. Electron. Comput., vol. EC-16, pp. 99-100, Feb. 1967.

[31 S. M. Reddy, "Easily testable realizations for logic functions,"IEEE Trans. Comput., vol. C-21, pp. 1183-1188, Nov. 1972.

[4] -, "A design procedure for fault-locatable switching circuits,"IEEE Trans. Comput., vol. C-21, pp. 1421-1426, Dec. 1972.

[51 A. Mukhopadhyay, "Unate cellular logic," IEEE Trans. Comput.,vol. C-18, pp. 114-121, Feb. 1969.

[6] D. C. Bossen and S. S. Hong, "Cause-effect analysis of multiplefault detection in combinational network," IEEE Trans. Comput.,vol. C-20, pp. 1252-1258, Nov. 1971.

[71 A. R. Klayton and A. K. Susskind, "An algebraic approach tofault detection," presented at the 2nd Workshop on Fault Detec-tion and Diagnosis in Digital System, Lehigh Univ., Bethlehem,Pa., Dec. 1971.

[81 S. B. Akers, Jr., "Universal test sets for logic networks," in Proc.13th Annu. Switching and Automata Theory Symp., Oct. 1972,pp. 177-184.

Sudhakar M. Reddy (S'68-M'68), for a photograph and biography, seepage 669 of the July 1973 issue of this TRANSACTIONS.

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