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Rodrigo Martins ,* Arokia Nathan ,* Raquel Barros , Luís Pereira , Pedro Barquinha , Nuno Correia , Ricardo Costa , Arman Ahnood , Isabel Ferreira , and Elvira Fortunato *

Complementary Metal Oxide Semiconductor Technology With and On Paper

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One of today’s challenges in electronics is to produce port-able, fl exible, low cost, and easily recyclable products, [ 1 ] such as paper [ 2 ] since they do not require the high process temperatures used in crystalline silicon (c-Si) technologies. In addition, the devices should have low power energy consumption to allow densely packed integrated circuits for a plethora of applications such as computer memory chips, digital logic and microproc-essors, to (linear) analogue circuits, among others, to fuel the next-generation microelectronics revolution for information and communication technologies. [ 3 ] For illustrative purposes, we consider a temporary register as an example. In a static cir-cuit the contents of the register remain fi xed until new infor-mation arrives to be stored and remains active unless the power goes out or the computer is turned off. In a dynamic circuit, the contents of the register leak away and must be periodically refreshed. The advantage of dynamic circuits is that they do not draw current between refreshing; the disadvantage is that refreshing requires additional circuitry including clocks to syn-chronize the refresh cycle with the operation of the register. [ 3 , 4 ] As done in the past for c-Si, a complementary metal oxide semi-conductor (CMOS) architecture is required, [ 4 ] which naturally does not draw power and can easily be implemented as a static circuit without the need for clocking. An example is the logic inverter, a fundamental building block of the digital circuit. Indeed, CMOS technology has fueled the revolution in micro-electronics thanks to its low power consumption, high-density integration of electronic circuits, and architectural simplicity, which inherently lends itself to straightforwardness in design.

In this paper we present the proof of concept of a working low power electronic CMOS inverter circuit layered on a fl exible and recyclable fi ber-based paper substrate that simultaneously serves as the gate dielectric. [ 5 ] Indeed, paper is the lightest, most unbreakable, mechanically fl exible, and cheapest known mate-rial that is fully recyclable. Although paper is hydrophobic and

© 2011 WILEY-VCH Verlag GAdv. Mater. 2011, 23, 4491–4496

Prof. R. Martins , R. Barros , Dr. L. Pereira , Dr. P. Barquinha , N. Correia , R. Costa , Dr. I. Ferreira , Prof. E. Fortunato Departamento de Ciência dos MateriaisCENIMAT/I3N, Faculdade de Ciências e TecnologiaFCT, CEMOP/Uninova Universidade Nova de Lisboa, 2829-516 Caparica, PortugalE-mail: rm@uninova.pt; emf@fct.unl.pt Prof. A. Nathan , Dr. A. Ahnood London Center for NanotechnologyUniversity College LondonLondon WC1H 0AH, UKE-mail: anathan@ucl.ac.uk

DOI: 10.1002/adma.201102232

its hydrophibicity is circumvented when its surface is treated, for instance with poly(lactic acid) (PLA), we use hydrophobic paper having in its composition 2% fl uorine in addition to Al 3 + , Na + , Cl − , S 6 + , P 5 + , Ca 2 + , Si 4 + and Mg + , which is typical of any fully recy-clable paper. Layered on the paper substrate are low temperature oxide semiconductor and conductive layers for the realization of CMOS circuits. This combination of low power circuitry, low temperature process, and recyclable substrate is a signifi cant step toward green electronics, as demanded by our society towards a sustainable environment. This also opens up a myriad of new applications ranging from smart labels, sensors, and packaging to electronic displays printed on paper pages for use in newspapers, magazines, books, signs, and advertising billboards. Since the CMOS inverter circuit reported here is the fundamental building block for digital logic circuits, this development also creates the potential to have computers seamlessly layered onto paper.

Traditionally, the CMOS architecture has required a high temperature process and the use of crystalline silicon (c-Si) substrates. [ 3 ] The high temperatures required for conventional CMOS technology means that it cannot be used to meet the growing demand for light, fl exible [ 1,2 , 5 , 6 ] and cheap devices. This has resulted in a move towards newly emerging thin-fi lm semiconductor materials such as organics, [ 6–8 ] hybrids, [ 9 , 10 ] and inorganic semiconductors like amorphous/nanocrystal-line silicon [ 11–13 ] and metal oxides. [14– 21 ] Although these mate-rials cannot compete with c-Si CMOS in terms of the perform-ance required for high-speed computation and digital signal processing applications, they are an alternative for a range of newly emerging application areas such as disposable electronics and, in particular, for human–machine interfacing where the need for speed is intrinsically limited by biology.

The CMOS architecture is based on connecting two transis-tors of opposite switching polarities (so-called n- and p-type tran-sistors), leading to complementary operation. The circuit uses both n-channel and p-channel fi eld effect transistors (FETs) con-nected in series, with a common gate electrode. The input signal is applied simultaneously to the gate of both transistors having a common dielectric (paper) that also acts as the substrate. The output signal is taken from the node between serially connected drains of the two transistors. Previous attempts involving low temperature processes to implement CMOS circuits using thin-fi lm organic or amorphous silicon FETs [ 6 , 11 ] have met with lim-ited success because of the poor n-type conduction in organics [ 7 , 8 ] and the poor p-type conduction in amorphous silicon. [ 11 ] Recently we have demonstrated n-channel oxide FETs [ 1 , 11 ] with mobilities at least one order of magnitude higher than organic p-channel or n-channel amorphous silicon FET, even when processed at low temperatures and implemented on paper. [ 22–24 ]

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This together with the deposition of p-type oxide FETs at low

temperatures with mobilities exceeding 1.2 cm 2 V − 1 s − 1 [ [ 21 ] creates the opportunity for layering CMOS circuits using paper as both substrate and dielectric in which both p-channel and n-channel are seamlessly integrated.

In this work, the n- and p-type TFT of the CMOS inverter with and on paper uses as a channel layer, respectively, gallium-indium-zinc-oxide (GIZO) and non-stoichiometric tin oxide (SnO x , x < 2), 40 and 8 nm thick, while the gate electrode is based on transparent conductive indium zinc oxide (IZO), 450 nm thick, all processed by reactive magnetron sputtering, and drain/source contacts on a Ni/Au double-layer (8/120 nm) deposited by electron beam evaporation (see Figure 1 ). Both TFTs exhibit electron and hole mobilities greater than 21 and 0.8 cm 2 V − 1 s − 1 , respectively. As the paper itself can act as both substrate and dielectric, this means that the complexity of transferring a stand-alone electronic circuit onto a paper page is reduced. Indeed, paper substrates potentially enable the full integration of power management functionality with energy storage through the integration of circuits with carbon nano-tube (CNT)-based supercapacitors, [ 25 ] which use paper as sepa-rators in their structures.

In previous work we showed that the use of paper as the gate dielectric can lead to an enhancement of FET properties and, in particular, a high transconductance ( g m ) which favors a low turn-on gate voltage. [ 24 , 26 ] As a gate dielectric, paper offers a large capacitance at low frequencies because of its fi ber-based foam-like structure (see Figure S2a, Supporting Information), in addi-tion to possible contributions from ion motion from within the fi ber structure. For more compact papers, this behavior is not

© 2011 WILEY-VCH Verlag Gwileyonlinelibrary.com

Figure 1 . Cross-sectional schematic of the fabrication sequence of the papeinterconnect as well as an image of the real device.

so pronounced, and fl at regions are even observed (Figure S2b, Supporting Information). By virtue of the structure of the paper, there is drift of charged species through cation exchange at the negatively charged carboxy and phenolic hydroxy sites in the paper matrix, and anion migration because of the negative zeta potential of paper. [ 27 ] This behavior suggests the presence of a slow transient mechanism that prevails at lower frequencies, in which the movement of charged species within the paper leads to formation of an electrochemical double layer (EDL) at the interface between the paper dielectric and the semiconducting channel. Because of the relatively small thickness of the EDL, there is a high value capacitor in parallel with the paper’s smaller geometric capacitance, compared to what has been demonstrated in some electrolyte dielectrics used in organic thin fi lm transistors, [ 28 ] thus this dominates the total capaci-tance. At low enough frequencies, the charge species respond to the probing signal, allowing formation of the EDL to bring about the substantial increase in measured capacitance. Thus the effective dielectric thickness is much smaller than the geo-metric paper thickness as a consequence of its fi ber network. The paper roughness does not have a negative effect on the variation of capacitance with frequency. However it would affect the device mobility.

In conventional FETs, g m is limited by the geometric attributes of the device and the carrier mobility ( μ ), for a given drain to source voltage ( V DS ), i.e., g m = C ox × V DS × ( W / L ) × μ . Therefore since the gate capacitance C ox is an implicit function of gate dielectric thickness and dielectric constant, it is desir-able to be as large as possible as it leads to a high g m that favors a low turn-on gate voltage. Since the paper fi bers are more than

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r CMOS showing all layers that constitute the fi nal device and how they are

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two orders of magnitude thicker than the active channel layers, non-continuous mesh-like channel layers are formed, mainly covering the paper fi bers with large gaps between fi bers. Thus, charge transfer at low frequencies is mainly promoted by charge induced capacitance behavior, [ 24 ] with some contribu-tion from ion charge motion within the bulk of the paper (see Figure S1, Supporting Information). This behavior is much less pronounced for the gate electrode, whose thickness is at least one order of magnitude larger than the active channel layer.

From a circuit design standpoint, a high g m is advantageous as it allows the desired drain–source current to be achieved at lower operating voltages; and this is what the use of paper as a dielectric makes possible in this circuit. The foam like struc-ture of paper allows us to obtain a quasi-static gate capacitance of 40 nF cm − 2 (see Figure S2, Supporting Information), corre-sponding to an apparent active dielectric thickness of 0.5 μ m, which is signifi cantly smaller than the actual paper geometric thickness ( ≈ 75 μ m). At very low frequencies, discrete paper fi bers respond to the measurement signal according to the main carriers involved (holes or electrons) as depicted in Figure 2 and, therefore, the apparent dielectric thickness is the product of serial and parallel combinations of the discrete fi ber capaci-tors located at different planes within the paper matrix [ 24 ] whose capacitance increases as the frequencies tend to zero. From the CV measurements performed on the probed FET devices, they constitute a metal–semiconductor–insulating (MIS) structure, consisting of a gate electrode, paper dielectric, and metal-oxide semiconductor. This is evident from the shape of the C – V curves shown in Figure 2 a,b, which besides being frequency

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Figure 2 . Frequency dependence of capacitance–voltage characteristics of a)band diagram of an n-channel and p-channel FET, respectively, for V G = V T >

dependent, resemble the reverse of the transfer characteristics of the respective FETs (see Figure S4 in the Supporting Infor-mation). The C – V curves exhibit distinct regions of charge depletion and accumulation for both FETs. Figure 2 c–f show the simplifi ed band diagram for the n- and p-channel FET devices respectively, where parts c and e refer to the FET’s operation at the fl at-band condition [ 4 ] and parts d and f represent the device operated in the above-threshold regime. The band structure of the paper fi ber is yet to be fully investigated and it is, therefore, estimated as shown to depict energy levels consistent with that of an insulating material. However, included in these fi gures are charged species whose migration leads to the enhancement of gate capacitance. As shown in Figure 2 c,d, the n-channel FET is an enhancement mode device with a positive fl at-band voltage. A further increase in the positive bias leads to accu-mulation of electrons at the interface of the IGZO and paper dielectric where there is a downward bending of the energy bands. Figure 2 e,f represent the depletion mode p-channel FETs. In this mode of operation, the fl at-band voltage is posi-tive, therefore, at zero gate bias the device is switched on. Fur-ther reduction in the gate bias leads to an increase in the accu-mulation of holes in the channel because of upward bending of the energy bands. These band diagrams are consistent with the C – V plots achieved where, in the accumulation regime, a thin conductive sheet of charge is formed in the channel close to the interface of the channel/paper interface, and therefore the capacitance measured in this regime is effectively that of the paper dielectric. In the depletion regime, the capacitance drops as the total capacitance is a result of the combined channel and

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n-channel and b) p-channel FETs using a paper gate dielectric. Simplifi ed 0, (c,e); and V G > V T (d,f).

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paper dielectric capacitances. The C – V curves (both in accumu-

lation and depletion) show a strong frequency dependence in-line with the capacitance–frequency curve of the paper dielec-tric (see Figure S2, Supporting Information).

The CMOS inverter circuit structures along with the TFT test structures of different channel lengths ( L ) and widths ( W ) were fabricated using shadow masks (see Figure 1 ). The corresponding transfer and output characteristics of the n- and p-channel FETs are depicted in Figure S4 of the Supporting information. Both devices exhibit high gate leakage currents ( I GS ). This can be attrib-uted to the foam-like nature of the paper dielectric and ion bom-bardment of the paper during the growth process, coupled with the use of large gate electrodes. The gate leakage current den-sity can be decreased by using a more compact paper structure, with nanofi brils instead of microfi brils, along with full charge compensation of prevailing ions within the bulk of the paper. [ 5 ] Furthermore, a lower gate leakage current can be achieved by scaling down the device size and thus the gate electrode area. The anti-clockwise hysteresis behavior on the transfer curves of both devices is believed to stem from a combination of ion migration and charge trapping effects. [ 28 ] It is possible to decrease the hys-teresis and leakage currents by minimizing the number of charge carrier traps, increasing of the smoothness of the paper, and using low ion bombardment deposition processes.

© 2011 WILEY-VCH Verlag Gwileyonlinelibrary.com

Figure 3 . a) Image of the CMOS on paper where the large ( W / L ) p = 20.8b) VTCs of the CMOS inverter for the different confi gurations as numberedthe input and output voltages ( V IL, V OH and V IH , V OL ). c) Gain and circuit lea

The p-channel FET performance achieved is suffi cient for use in CMOS architecture, proving the feasibility of layering CMOS devices on, and integrating with, paper. This is despite the fact that the p-channel FET works in depletion mode with a gate leakage current about an order of magnitude higher than that of the n-channel FET. This behavior can be partly attributed to the high radio-frequency power density used during the deposi-tion of the SnO x fi lm and the subsequent damage to the paper dielectric. Furthermore, the polycrystalline nature of SnO x yields a fi lm [ 21 ] with a rougher surface and less compact structure than its IGZO [ 18 ] counterpart. This leads to an enhancement of defects at fi ber interfaces, thus contributing to the observed decrease in the ON/OFF ratio, sub-threshhold slope, and fi eld effect mobility, as compared to the n-channel FETs. The p-channel FET’s output characteristics do not show hard saturation behavior, which is in-line with previous arguments concerning leakage current and operation mode. As discussed later, this behavior would have an infl uence on the input–output characteristic of the CMOS inverter circuit presented here.

The CMOS inverters using the n- and p-channel FET devices described above were fabricated on the same substrate with different geometric aspect ratios ( W / L ) p /( W / L ) n (see Figure 3 a) and were tested under different supply voltages. Figure 3 b shows the associated voltage transfer characteristics (VTCs)

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and small ( W / L ) n = 10 correspond to the p-FET and n-FET, respectively. in Table 1 . This is used to extract the high and low states, associated with kage current, I DD , for different confi gurations as indicated in Table 1 .

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Table 1. Effect of FET geometry [( W / L ) p /( W / L ) n ] and supply voltage ( V DD ) on the direct current (DC) performance of the paper CMOS inverter.

Entry ( W / L ) p /( W / L ) n V DD [V]

NM H a) [V]

| NM L | b) [V]

TW c) [V]

V l d) [V]

1 2.08 17 9.8 ± 0.8 1.0 ± 0.1 4.7 ± 0.3 13.5 ± 0.7

2 2.08 15 9.8 ± 0.7 1.0 ± 0.1 4.3 ± 0.3 12.4 ± 0.6

3 1.90 17 6.5 ± 0.6 0.6 ± 0.1 3.5 ± 0.2 10.5 ± 0.5

a) NM H = V OH – V IH, high noise margin; b) NM L = V IL – V OL low noise margin; c) The transition width ( V IH – V IL ); d) The logic swing ( V OH – V OL ). Here, V OH , V IH , V IL , and V OL are associated with the knee points (∂ V OUT /∂ V IN = –1) of the VTC curves (see Figure S5, Supporting Information).

of the inverters along with their gain and leakage current in Figure 3 c. A summary of the electrical performance under the different testing conditions is given in Table 1 . The values shown represent a statistical average of measurements performed for various devices, taking into account measurement errors. Within the limits of experimental error, the results shown are consistent and reproducible. The absence of hard saturation in the p-channel device manifests itself in a relatively low gain. Regardless, the CMOS inverter does show a large voltage dis-crimination between the high ( V OH ) and low ( V OL ) states, where V OH and V OL defi ne the onset of the steep transitions in the VTC (see Figure S5, Supporting Information). [ 4 ] The inverter exhibits a logic voltage swing ( V l ) that is over 85% of V OH as required for most static CMOS applications (see Table 1 ).

The paper CMOS static power dissipation broadly com-pares favorably with modern silicon CMOS inverters [ 29 ] and their low power thin-fi lm counterparts. [ 8 ] In all cases, the static leakage current of the circuit (indicated as I DD in Figure 3 ) at the high or low states is less than 1.9 pA, which corresponds to a maximum static power dissipation of 32 pW per inverter. The static leakage current stems from a combined contribu-tion of sub-threshold and gate leakage, [ 29 , 30 ] both of which can be minimized by optimizing the geometric attributes of the circuit such as channel width and area. For example, the sub-threshold leakage can be reduced by minimizing the channel width. [ 31 ] The origin of gate leakage current can be attributed to ionic conduction along the cellulose fi bers, [ 32 ] as highlighted in Figure 2 (see also Figure S2, Supporting Information). Thus the gate leakage scales with the total number of ions available for conduction, and subsequently the gate electrode area. [ 33 ] Given the inherent scope for scalability, the size of the circuit pre-sented here can be signifi cantly reduced leading to a substantial reduction in the power consumed per inverter. Indeed the static power dissipation per channel width and per channel area is 16.1 fW μ m − 1 and 4.1 aW μ m − 2 respectively. The increase in the leakage current during the brief period of switching between states, shown in Figure 3 c, is characteristic of the CMOS archi-tecture. This is in contrast to a unipolar architecture such as nMOS, in which current fl ows as long as the input is active leading to higher power consumption.

Although in this fi rst attempt of fabricating a CMOS device with and on paper yields a high leakage current, it is not sur-prising given the advance from a rigid substrate to paper. In addition, the conventional FET gate dielectric is now replaced with paper. The use of paper dielectrics and layering of p- and n-channel FETs oxide based [ 34 ] is highly promising. The per-formance of the circuit presented here does not inhibit the

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implementation of CMOS on paper, thus creating an opportu-nity for light weight, low cost, and fully recyclable complemen-tary circuits, i.e., green electronics. This is expected to create applications in disposable and recyclable electronics that range from smart labels, tags, sensors, and memories to TFT driven electrochromic paper displays and integrated systems.

Supporting Information Supporting Information is available from the Wiley Online Library or from the author.

Acknowledgements This work was funded by the Portuguese Science Foundation (FCT-MCTES) through projects PTDC/CTM/103465/2008, PTDC/EEA-ELC/099490/2008, E. Fortunato’s ERC 2008 Advanced Grant (INVISIBLE contract number 228144), APPLE” FP7-NMP-2010-SME/262782-2 and a Royal Society Wolfson Research Award to A. N.

Received: June 14, 2011 Revised: August 4, 2011

Published online: September 5, 2011

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