compal la-9981p r0.2 schematics

7/24/2019 Compal La-9981p r0.2 Schematics

http://slidepdf.com/reader/full/compal-la-9981p-r02-schematics 1/56

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Compal Electronics, Inc.

Dell / Compal Confidential

X76@ : 76 level

46@ : 46 level

@ : Nopop component

CONN@ : Connector component

XDP@ : XDP function

UMA@ : Only for UMA

DIS@ : Only for Discrete

SUN@ : SUN XT

EMI@ : EMI parts

@EMI@ : Reserve EMI parts

ESD@ : ESD parts

RF@ : RF parts

Intel Shark Bay ULT

OAK Value2UMA/DIS AMD Sun XT

2013-03-09 Rev: 0.2

Schematic Document

MODEL NAME : VBW00

PROJECT CODE : ANRVBW0100

PCB NO : DA8000WK000 LA-9981P M/B

DA40001FO00 LS-9101P POWER BUTTON/B

DA40001FP00 LS-9102P USB/B

DA40001FQ00 LS-9103P TP BUTTON/B

BOM config

UMA : UMA@,EMI@,ESD@,RF@,XDP@

DIS SUN : SUN@,DIS@,EMI@,ESD@,RF@,XDP@

Title

Size Document Number Rev

Date: Sheet of

Security Classification Compal Secret Data

THIS SHEETOF ENGINEERINGDRAWING IS THE PROPRIETARY PROPERTY OF COMPALE LECTRONICS, INC. ANDCONTAINS CONFIDENTIAL ANDTRADE SECRETINFORMATION. THIS SHEETMAY NOTBE TRANSFEREDFROMTHE CUSTODY OFTHE COMPETENTDIVISIONOFR&DDEPARTMENTEXCEPT AS AUTHORIZEDBY COMPALELE CTRONICS, INC. NEITHERTHIS SHEETNOR THE INFORMATIONIT CONTAINSMAY BE USEDBY ORDISCLOSEDTOANY THIRDPARTY WITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS, INC.

Issued Date Deciphered Date

LA-9981P 0.2

Cover Pa

geCustom

1 55Saturday, March 09, 2013

2013/03/09 2014/04/01 Title


Date: Sheet of




LA-9981P 0.2

Cover Pa

geCustom


2013/03/09 2014/04/01 Title


Date: Sheet of




LA-9981P 0.2

Cover Pa

geCustom


2013/03/09 2014/04/01

ZZZ

PCB VBW01 LA9981P/LS9101P/LS9102P/LS9103P

R1@

DA8000WK000

ZZZ

PCB VBW01 LA9981P/LS9101P/LS9102P/LS9103P

R1@

DA8000WK000



A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

RTL8106E

Port 2 Card Reader RTS5179/5170

Port 10

USB 3.0 Conn. 2

Daughter board

64M

PS/2

8GB Max

PEG 2.0 x4

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7DDRIII-DIMM X2

1.35V DDR3 1600 MHz

P.42

P.25

USB 3.0 Conn. 1

Digital Camera

Mini Card

Port 11

Port 8

P.41

P.26

LPC Bus

P.40P.27

ENE KBC

KB9012Int.KBDP.27

Touch Pad

USB2.0 Port 0,1

Port 0

Audio Codec

ALC3223 Int. Speaker R / L

Headphone Jack / Mic. Jack combo HD Audio

Port 1,2

USB 2.0 Conn. 3

P.24

USB 3.0

Port 2,3

PCI-E

P.21

Port 1

SPI

Ethernet

RJ45

Intel

Haswell

Processor 15W DC

BGA1168

Intel Lynx Point-LP

SPI ROM P.9 P6~16

P.22

Dual Channel Memory Bus (DDR3L)

SATA HDD Conn. P.42

33MHz

SATA3.0

USB 2.0 Conn. 4

P.23

Half

Mini Card

WLAN/BT4.0

P.26

LVDS Conn.

HDMI Conn. HDMI

P.41

P.20

Port 1

Digital Mic.

P.27Fan Control

CPU XDP

Conn. P.6

SATA ODD Conn.

Venus Pro(HD8850M)2GB GDDR5 (128Mx16x8pcs)

P.22

P.22

P.21

P.17~18

(With Digital MIC)

WLAN (Half)

P.41Touch Screen Port 9

P.233 in 1 Socket

RTD2136RP.19

LVDS eDP

SMBus

P.34 P.35

128M*16

GDDR5*8

P.36

P.37

AMD

Venus Pro , 25W

P.28~33

64bit

64bit

128M*16

GDDR5*8

128M*16

GDDR5*8

128M*16

GDDR5*8

(OAK 15" only)

Title


Date: Sheet o

f


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFO RMATION. THI S SHEET MAY N OT BE TRANS FERED FROM T HE CUSTOD Y OF THE CO MPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


LA-9981P 0.2


2013/03/09 2014/04/01Compal Electronics, Inc.

Block diagramTitle


Date: Sheet o

f





LA-9981P 0.2



Block diagramTitle


Date: Sheet o

f





LA-9981P 0.2



Block diagram



A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Compal Confidential

Project Code : VAW00 / VAW01

File Name : LA-9981P / LA-9982P

USB

USB

USB

HP

RJ-45

HDMI

Led1 Led2

JSPK 4 pin

Led3 Led4

LA-9982P M/B

MINI Card

Battery

JMINI

PBATT

JODD

JHDD

Card

Reader

JREAD

5 pinPJPDC

JHDMI

JLAN

JUSB1

JUSB2

JUSB3

JHP

40 pinJLVDS

JDB8 pin

Bottom Side

Top Side

8 pin

Hot Bar

LS-9102P (USB/B)

USB JUSB4

SW1

(SN100004Y00)

4 pin-Hot Bar

Lid

LS-9101P (PWR/B)

4 pin PWR-BTN FFC

UE5

(SA00003VQ00)

8 pinUSB-DB FFC

JKB30 pin

SW2 SW3

4 pin

Hot Bar

LS-9103P (TP-BTN/B)

TP-Module

4 pinTP-BTN FFC

6 pinTP-MB FFC

6 pinJTOUCH

4 pinJPWR

6 pinJTP

JFAN3 pin

XDP

JXDP

(OAK 15")

RTC

JRTC2 pin

LA-9981P M/B

Title


Date: Sheet of


THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPALE LECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THIS SHEETMAYNOTBE TRANSFERED FROMTHE CUSTODYOF THE COMPETENTDIVISIONOFR&DDEPARTMENTE XCEPT AS AUTHORIZED BYC OMPALELE CTRONICS, INC. NEITHER THIS SHEETNOR THE INFORMATIONITCONTAINSMAYBE USED BYOR DISCLOSED TO ANYTHIRD PARTYWITHOUTPRIOR WRITTENCONSENTOFCOMPALELECTRONICS, INC.


LA-9981P 0.2



DB block dia

gramTitle


Date: Sheet of




LA-9981P 0.2


2013/03/09 2014/04/01Com

pal Electronics, Inc.

DB block diagramTitle


Date: Sheet of




LA-9981P 0.2


2013/03/09 2014/04/01Com

pal Electronics, Inc.

DB block diagram

A



A

A

1 1

V

WLANmini card

SMBCLKSMBDATA

ULT

DDR3LVGA

V V

Link V

XDP

ULT

V V

Charger

EC_SMB_CK2EC_SMB_DA2

SOURCE

KB9012

SMBUS Control Table

SML0CLKSML0DATA

ULT

EC_SMB_CK1EC_SMB_DA1

KB9012

V

RTD2136S

USB2.0

Port0

ULT

Touch Screen Panel

MINI Card (WLAN)

PCI EXPRESS

10/100 LAN

PEG (N14P)

PEG (N14P)

10/100 LAN

CLKOUT_PCIE0

CLOCK SIGNAL

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

Symbol Note :

: means Digital Ground

: means Analog Ground

BOARD ID Table

0.1

ID

0

1

23

4

5

6

7

PCB Revision

0.1

Vcc 3.3V +/- 1%

100K +/- 1%Ra

Rb V min

0

1

2

3

0 0.000V

0.347V

0.423V 0.430V

0.550V

0.360V

0.438V

AD_BID V typ AD_BID V AD_BID max

15K +/- 1%

20K +/- 1%

27K +/- 1%

33K +/- 1%

43K +/- 1%

1.200V

0.000V 0.300V

4

5

6

7 56K +/- 1%

0.541V

0.691V

0.819V

0.713V

0.807V

0.978V 0.992V

1.185V

0.831V

0.702V

0.559V

Board ID Table for AD channel

0x00 - 0x0B

EC AD3

0x0C - 0x1C

0x1D - 0x26

0x27 - 0x30

0x31 - 0x3B

0x3C - 0x46

0x47 - 0x54

0x55 - 0x64

12K +/- 1%

1.169V

1.006V

0.354V

USB connector 3

USB connector 2

USB connector 4 (DB)

USB connector 1

MINI Card (WLAN)

Card Reader

Camera

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

HDD

ODD

SATA0

SATA1

SATA2

SATA3

SATA

Port1

Port2

Port3

Port4

USB3.0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

USB connector 2

USB connector 1

CLKOUT_PCIE5

MINI Card (WLAN)

dGPU (N14P)

BATT

V

SML1CLKSML1DATA

Touch pad

8

9

10

11

75K +/- 1% 1.398V

1.634V

1.849V 1.865V

2.031V

1.667V

1.881V 130K +/- 1%

160K +/- 1%

200K +/- 1%

240K +/- 1%

270K +/- 1%

2.544V

1.414V 1.430V

12

13

14

15 330K +/- 1%

2.015V

2.185V

2.329V

2.215V

2.316V

2.395V 2.408V

2.533V

2.343V

2.200V

2.046V

0x65 - 0x76

0x77 - 0x87

0x88 - 0x96

0x97 - 0xA3

0xA4 - 0xAD

0xAE - 0xB7

0xB8 - 0xC0

0xC1 - 0xC9

100K +/- 1%

2.521V

2.421V

1.650V

430K +/- 1%

560K +/- 1%

750K +/- 1%

3.300V

16

17

18

19 NC

2.667V

2.800V

2.687V

2.791V

2.905V 2.912V

3.300V

2.808V

2.677V 0xCA - 0xD3

0xD4 - 0xDC

0xDD - 0xE6

0xE7 - 0xFF3.000V

2.919V

Board ID

8

9

10

11

12

13

14

15

UMA Sun XT Venus Pro Venus XT

0.10.1

0.2

0.2

0.20.2

0.3

0.3

0.3

0.3

1.0

1.0

1.0

1.0Title


Date: Sheet of


THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPALELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THIS SHEETMAYNOT BE TRANSFERED FROMTHE CUSTODYOFTHE COMPETENTDIVISIONOF R&DDEPARTMENT EXCEPT AS AUTHORIZED BYCOMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONITCONTAINSMAYBE USED BYOR DISCLOSED TO ANYTHIRD PARTYWITHOUTPRIOR WRITTENCONSENTOFCOMPALELECTRONICS, INC.


LA-9981P 0.2



Notes List Title

Size Document Number

Rev

Date: Sheet of




LA-9981P 0.2



Notes List Title

Size Document Number

Rev

Date: Sheet of




LA-9981P 0.2



Notes List

5 4 3 2 1



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MCHShark bay

SMBUS Address [0x9a]

MEM_SMBDATA

MEM_SMBCLK

AH1

AP2

+3.3V_ALW_PCH

2.2K

2.2K

53

51

30

32

DDR_XDP_WLAN_TP_SMBDAT

DDR_XDP_WLAN_TP_SMBCLK

10K

+3VS10K

DIMMA

SMBUS Address [A4]DIMMB

SMBUS Address [A0]

SMBUS Address [TBD]XDP1

SMBUS Address [TBD]JMINI

DDR_XDP_SMBDAT_R1

DDR_XDP_SMBCLK_R1

SMBUS Address [TBD]JTP

200

202

200

202

KBCKB9012A4

78

77

0 ohm

0 ohm

AN1

AK1

+3.3V_ALW_PCH

1K

1K

SML0CLK

SML0DATA

AN1

AK1

+3.3V_ALW_PCH

2.2K

2.2K

SML1_SMBCLK

SML1_SMBDATA

N-MOS

N-MOS

N-MOS

N-MOS

EC_SMB_CK2

EC_SMB_DA2

+3VALW

2.2K

2.2K

14

13 UV280 ohm

0 ohm

LVDSTranslator

0 ohm

0 ohmCSCL

CSDA

CIICSCL

CIICSDA

N-MOS

N-MOS

N-MOS

N-MOS

+3VALW

2.2K

2.2K

EC_SMB_CK1

EC_SMB_DA1

100 ohm

100 ohmPD13

1

4

6 5

3 BATTBAT_ALERT

BATT_PRS

PBATT1CONN

10

11

SDA

SCL POWERPU701Charger

0 ohm

0 ohm

SMBUS Address [0x16]

SMBUS Address [0x12]

SMBUS Address [TBD]79

80 EC_SMB_DA2

EC_SMB_CK2

2.2K

+3VS_VGA 2.2K

VGA_SMB_CK2

VGA_SMB_DA2 T3

T4 UV28 GPU SMBUS Address [0xXX]

5

6

Title


Date: Sheet of




LA-9981P 0.2

SMBus block dia

gram



Title


Date: Sheet of




LA-9981P 0.2

SMBus block dia

gram



Title


Date: Sheet of




LA-9981P 0.2

SMBus block dia

gram



5 4 3 2 1



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils ,Spacing=25mil,

Max length=100 mils.

reference SharkBay ULT Validation Customer Debug Port

Implementation Requirement Rev 1.0

CAD Note:

Trace width=12~15 mil, Spcing=20 mils

Max trace length= 500 mil

CAD Note:

Avoid stub in the PWRGD path

while placing resistors RC115

DDR3 COMPENSATION SIGNALS

Place near JXDP1.47

Place near JXDP1

PU/PD for JTAG signals

i5-4200U-15W-GT2-QS

i3-4010U-15W-GT2-QS

i7-4500U-15W-GT2-QS

PECI_EC

CFG3_R

H_PROCHOT#

H_PROCHOT#_R

RUNPWROK

RUNPWROK

RUNPWROK

RUNPWROK

TRST#_XDP XDP_TRST#

XDP_TMSTMS_XDP

XDP_TDITD I_XDP TDI_XD P_R

XDP_TDOTDO_XDPPCH_JTAG_TDO

H_CPUPWRGD

SYS_PWROK_XDP

H_CPUPWRGD

CPU_DETECT#

H_CPUPWRGD H_VCCST_PWRGD_XDP

H_CATERR#

SM_RCOMP1SM_RCOMP2

SM_RCOMP0

H_CATERR#

SM_RCOMP1

SM_RCOMP2

SM_RCOMP0

TRST#_XDPTDO_XDP

TDI_XDPTMS_XDP

CFG8CFG9

CFG15

CFG14

CFG18

CFG17

CFG16

CFG2

SYS_PWROK

CFG10CFG11CFG3

CFG3

XDP_OBS1_RXDP_OBS0_R

CFG13

CFG12

CFG19

CFD_PWRBTN#_XDP

XDP_TCLK

XDP

_PRDY#

XDP_PREQ#

XDP_RST#_R

DDR_XDP_SMBCLK_R1DDR_XDP_SMBDAT_R1

CPU_PWR_DEBUG#_R PLT_RST#

CFG0CFG1

CFG4

CFG7

CFG6

CFG5

SYS_PWROK_XDP

XDP_PREQ#

XDP_TCK

XDP_TMSXDP_TRST#XDP_TDIXDP_TDO

PCH_JTAG_RST#

XDP_TDIXDP_TMS

XDP_PREQ#

CLK_XDPCLK_XDP#

XDP_PRDY#

XDP

_OBS1_RXDP_OBS0_R

EDP_DISP_UTIL

EDP_CPU_AUX

EDP_CPU_LANE_P1EDP_CPU_LANE_N1

EDP_COMP

EDP_CPU_AUX#

EDP_CPU_LANE_N0EDP_CPU_LANE_P0

DDI1_LANE_N3

DDI1_LANE_P0DDI1_LANE_N0

DDI1_LANE_N2

DDI1_LANE_N1

DDI1_LANE_P3

DDI1_LANE_P2

DDI1_LANE_P1

XDP_TRST#XDP_TCK

PCH_JTAG_TCK

XDP_DBRESET#

XDP_TCLK

TDO_XDP

P CH _J TA G_ RS T# X DP _T RS T#

PCH_JTAG_TCK

P CH _J TA G_ TD O T DI _X DP _R

XDP_TCLK

SYS_RESET#XDP_DBRESET#

TDO_XDP

XDP_TDO

RUNPWROK<30>

PCH_JTAG_TMS<8>

PCH_JTAG_TDI<8>

PCH_JTAG_TDO<8>

H_PROCHOT#<30,36>

PECI_EC<30>

DDR3_DRAMRST#_CPU<17>DDR_PG_CTRL<17>

CPU_DETECT#<30>

CFG17 <16>

CFG16 <16>

CFG8 <16>

CFG9 <16>

CFG10 <16>CFG11 <16>

CFG19 <16>CFG18 <16>

CFG12 <16>CFG13 <16>

CFG14 <16>

CFG15 <16>

CFG0<16>

DDR_XDP_WLAN_TP_SMBDAT<17,18,19,26,27,9>DDR_XDP_WLAN_TP_SMBCLK<17,18,19,26,27,9>

CPU_PWR_DEBUG#<13>

CFG1<16>

CFG2<16>CFG3<16>

CFG4<16>CFG5<16>

CFG6<16>

CFG7<16>

PBTN_OUT#<10,30>

PCH_JTAG_RST# <8>

CLK_CPU_ITP# <9>CLK_CPU_ITP <9>

EDP_CPU_LANE_N1 <19>EDP_CPU_LANE_P1 <19>

DDI1_LANE_N0<20>

EDP_CPU_AUX# <19>

DDI1_LANE_P0<20>

DDI1_LANE_N1<20>DDI1_LANE_P1<20>DDI1_LANE_N2<20>

DDI1_LANE_P2<20>DDI1_LANE_N3<20>

DDI1_LANE_P3<20>

EDP_CPU_AUX <19>

EDP_CPU_LANE_N0 <19>EDP_CPU_LANE_P0 <19>

PLT_RST# <10,21,26,30,48>

EDP_BIA_PWM <10,19>

PCH_JTAG_JTAGX<8>

SYS_RESET# <10>

SYS_PWROK<10,30>

PCH_JTAG_TCK<8>

+1.05VS

+3VS

+3VALW_PCH

+1.05VS+1.05VS

+1.05VS

+1.05VS

+VCCIOA_OUT

+3VS

Title


Date: Sheet of

SecurityClassification Compal Secret Data

THISSHEETOFENGINEERINGDRAWINGISTHEPROPRIETARY PROPERTY OFCOMPALELECTRONICS,INC.AND CONTAINSCONFIDENTIAL

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODY OFTHECOMPETENTDIVISIONOFR&D

DEPARTMENTEXCEPTAS AUTHORIZEDBY COMPALELECTRONICS,INC.NEITHERTHISSHEETNOR THEINFORMATIONITCONTAINS

MAY BEUSEDBY ORDISCLOSEDTO ANY THIRDPARTY WITHOUTPRIORWRITTENCONSENTOFCOMPAL ELECTRONICS,INC.

IssuedDate DecipheredDate

LA-9981P 0.2

6 55Saturday,March 09,2013


MCP(1,2/19) eDP ,XDP,MISC Title


Date: Sheet of







LA-9981P 0.2



MCP(1,2/19) eDP ,XDP,MISC Title


Date: Sheet of







LA-9981P 0.2



MCP(1,2/19) eDP ,XDP,MISC

T115@ T115@

RC620_0402_5% XDP@ RC620_0402_5% X

DP@

12

R C6 0 6 2_ 04 02 _5 %R C6 0 6 2_ 04 02 _5 %

1 2

RC49 0_0402_5%XDP@RC49 0_0402_5%X

DP@1 2

MISC

JTAG

DDR3

PWR

THERMAL

HASWELL_MCP_E

Rev1p22 OF19

UC1B

MISC

JTAG

DDR3

PWR

THERMAL

HASWELL_MCP_E

Rev1p22 OF19

UC1B

PREQK62PRDYJ62

PROC_TCK

E60

PROC_TRSTE59

PROCHOTK63

PROCPWRGDC61

CATERRK61

PECIN62

PROC_DETECTD61

PROC

_TMS E61

PROC_TDIF63

PROC_TDOF62

BPM#0J60

BPM#2H61BPM#1H60

BPM#3H62

BPM#7J61

SM_RCOMP0 AU60

SM_RCOMP1 AV60

SM_RCOMP2 AU61

SM_PG_CNTL1 AV61

BPM#6K60BPM#5H63BPM#4K59

SM_DRAMRST AV15

RC51

1K_0402_5%XDP@

RC51

1K_0402_5%XDP@

12

R C1 40 0 _0 40 2_ 5%

XDP@R C1 40 0 _0 40 2_ 5%

XDP@1 2

CC17

0.1U_0402_10V7K

CC17

0.1U_0402_10V7K

1 2

RC712 4. 9_ 04 02 _1 %~ D R C7 124.9_0402_1%~D

12

R C6 7 5 6_ 04 02 _5 %R C6 7 5 6_ 04 02 _5 %

1 2

RP4451_8P4R_5%

@RP4451_8P4R_5%

@

1 82 73 64 5

R C 44 0 _0 40 2_ 5%R C 44 0 _0 40 2_ 5%

1 2

C C 1 5

0 .1 U _ 0 4 0 2 _1 0 V 7 K

X D P @

C C 1 5

0 .1 U _ 0 4 0 2 _1 0 V 7 K

X D P @

1

2

RC52 0_0402_5%XDP@RC52 0_0402_5%X

DP@1 2

R2341

0_0402_5%

@R2341

0_0402_5%

@

1 2

RP45

51_8P4R_5%

RP45

51_8P4R_5%

1 82 73 64 5

CC13

0.1U_0402_10V7K

CC13

0.1U_0402_10V7K

12

T116@ T116@

C C 1 4

0 .1 U _ 0 4 0 2 _1 0 V 7 K

X D P @

C C 1 4

0 .1 U _ 0 4 0 2 _1 0 V 7 K

X D P @

1

2

R C1 41 0 _0 40 2_ 5%R C1 41 0 _0 40 2_ 5%1 2

RC50 0_0402_5%X

DP@RC50 0_0402_5%X

DP@1 2

R C5 6 1 K_ 04 02 _5 %XDP@R C5 6 1 K_ 04 02 _5 %XDP@

1 2RP460_8P4R_5%

XDP@

RP460_8P4R_5%

XDP@

1 82 73 64 5

RC682 00 _0 40 2_ 1% R C6 8200_0402_1% 12

R C 43 0 _0 40 2_ 5%R C 43 0 _0 40 2_ 5%

1 2

RC590_0402_5% R C590_0402_5%

12

T114@ T114@

RC701 00 _0 40 2_ 1% R C7 0100_0402_1% 12

T112@ T112@

RC570_0402_5% R C570_0402_5%

12

JXDP1

SAMTE_BSH-030-01-L-D-ACONN@

JXDP1

SAMTE_BSH-030-01-L-D-ACONN@

GND01

OBSFN_A03

OBSFN_A15

GND27

OBSDATA_A09

OBSDATA_A111

GND413

OBSDATA_A215

OBSDATA_A317

GND619

OBSFN_B021

OBSFN_B123

GND825

OBSDATA_B027

OBSDATA_B129

GND1031

OBSDATA_B233

OBSDATA_B335

GND1237

PWRGOOD/HOOK039

HOOK141

VCC_OBS_AB43

HOOK245

HOOK347

GND1449

SDA51SCL

53

TCK155

TCK057

GND1659

GND12

OBSFN_C04

OBSFN_C16

GND38

OBSDATA_C010

OBSDATA_C112

GND514

OBSDATA_C216

OBSDATA_C318

GND720

OBSFN_D022

OBSFN_D124

GND926

OBSDATA_D028

OBSDATA_D130

GND1132

OBSDATA_D234

OBSDATA_D336

GND1338

ITPCLK/HOOK440

ITPCLK#/HOOK542

VCC_OBS_CD44

RESET#/HOOK646

DBR#/HOOK748

GND1550

TD0 52TRST#

54

TDI56

TMS58

GND1760

HASWELL_MCP_E

DDI EDP

Rev1p21 OF19

UC1AHASWELL_MCP_E

DDI EDP

Rev1p21 OF19

UC1A

EDP_DISP_UTIL A43EDP_RCOMPD20

DDI2_TXP3B53 DDI2_TXN3 A53 DDI2_TXP2B50 DDI2_TXN2C49

DDI2_TXN1C53

DDI2_TXN0C51

DDI2_TXP0C

50

DDI2_TXP1B54

DDI1_TXP3B57

EDP_AUXN A45

EDP_AUXPB45

EDP_TXP3B49EDP_TXN3 A49EDP_TXP2C46EDP_TXN2C47

EDP_TXP1B47EDP_TXN1 A47

EDP_TXN0C45

EDP_TXP0B46

DDI1_TXN3 A57 DDI1_TXP2 A55 DDI1_TXN2B55 DDI1_TXP1C58 DDI1_TXN1B58 DDI1_TXP0C55 DDI1_TXN0C54

RC630_0402_5% X

DP@ RC630_0402_5% X

DP@

12

UC1

CL8064701477702-QEVE-C0-1.6G_BGA1168~D

4200Ui5G2R1@

SA00006SM0L

UC1

CL80

64701477702-QEVE-C0-1.6G_BGA1168~D

4200Ui5G2R1@

SA00006SM0L

RC641K_0402_5%

@

RC641K_0402_5%

@

1

2

R C1 39 0 _0 40 2_ 5%XDP@R C1 39 0 _0 40 2_ 5%

XDP@1 2

RC691 20 _0 40 2_ 1% R C6 9120_0402_1% 12

RC650_0402_5% XDP@ RC650_0402_5% X

DP@

12

RC260_0402_5%RC260_0402_5%

1 2

R C5 8 4 9. 9_ 04 02 _1 %@ R C5 8 4 9. 9_ 04 02 _1 %@

1 2

T113@ T113@

RC6610K_0402_5%RC6610K_0402_5%

1

2

UC1

CL8064701477202-QEVD-C0-1.8G_BGA1168~D

4500Ui7G2R1@

SA00006SL0L

UC1

CL80

64701477202-QEVD-C0-1.8G_BGA1168~D

4500Ui7G2R1@

SA00006SL0L

RC3621K_0402_1%RC3621K_0402_1%

12

T111@ T111@

R C48 1K_0402_5%XDP@R C48 1K_0402_5%XDP

@1 2

UC1

CL8064701478202-QEVG-C0-1.7G_BGA1168~D

4010Ui3G2R1@

SA00006SX0L

UC1

CL80

64701478202-QEVG-C0-1.7G_BGA1168~D

4010Ui3G2R1@

SA00006SX0L

UC4

74CBTLV3126BQ_DHVQFN14_2P5X3

@UC4

74CBTLV3126BQ_DHVQFN14_2P5X3

@

1OE1

1A2

1B3

2OE4

2A5

2B6

GND7

3B8

3A9

3OE10

4B11

4A12

4OE13

VCC14

GNDPAD15

RC72

0_0402_5%

@RC72

0_0402_5%

@

1 2

R C 45 0 _0 40 2_ 5%R C 45 0 _0 40 2_ 5%

1 2

CC160.1U_0402_10V7K

XDP@

CC160.1U_0402_10V7K

XDP@1

2

R C 46 0 _0 40 2_ 5%R C 46 0 _0 40 2_ 5%

1 2

5 4 3 2 1



5

5 4

3

3 2 1

D D

C C

B B

A A

change 22nFchange 22nF change 22nF

confirm by intel request PDG P141

DDR_CKE2_DIMMBDDR_CKE1_DIMMA

DDR_A_DQS7

DDR_A_DQS1

DDR_A_DQS2

DDR_A_DQS5

DDR_A_DQS3DDR_A_DQS4

DDR_A_DQS0

DDR

_A_DQS6

DDR_A_DQS#5

DDR_A_DQS#7

DDR_A_DQS#2DDR_A_DQS#1

DDR_A_DQS#0

DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#6

DDR_B_BS2

DDR_B_BS0

DDR_B_BS1

DDR_CKE3_DIMMB

DDR_B_D29

DDR_B_D59

DDR_B_D50

DDR_B_D49

DDR_B_D13

DDR_B_D19

DDR_B_D14

DDR_B_D3

DDR_B_D55

DDR_B_D47

DDR_B_D52

DDR_B_D44

DDR_B_D41

DDR_B_D8

DDR_B_D5

DDR_B_D56

DDR_B_D48

DDR_B_D38

DDR_B_D35

DDR_B_D26

DDR

_B_D25

DDR_B_D4

DDR_B_D63

DDR_B_D34

DDR_B_D32

DDR_B_D10

DDR_B_D17

DDR_B_D51

DDR_B_D40

DDR_B_D36

DDR_B_D31

DDR

_B_D21DDR_B_D20

DDR_B_D15

DDR_B_D7

DDR_B_D62

DDR_B_D46

DDR_B_D42

DDR_B_D18

DDR_B_D12

DDR_B_D1

DDR_B_D53

DDR_B_D37

DDR_B_D22

DDR_B_D57

DDR_B_D27

DDR_B_D54

DDR_B_D45

DDR_B_D39

DDR_B_D30

DDR_B_D9

DDR_B_D60

DDR_B_D58

DDR_B_D33

DDR_B_D0

DDR_B_D61

DDR_B_D43

DDR_B_D28

DDR_B_D23

DDR_B_D24

DDR_B_D16

DDR_B_D6

DDR_B_D2

DDR_B_D11

DDR_A_MA0

DDR_A_MA1

DDR_A_MA3

DDR_A_MA7

DDR_A_MA8

DDR_A_MA13

DDR_A_MA2

DDR_A_MA14

DDR_A_MA5

DDR_A_MA10

DDR_A_MA4

DDR_A_MA11

DDR_A_MA9

DDR_A_MA6

DDR_A_MA12

DDR_CS1_DIMMA#

DDR

_CS0_DIMMA#

DDR_A_MA15

DDR_B_CAS#

DDR_B_RAS#

DDR_B_WE#

DDR_A_BS0DDR_A_BS1

DDR_A_BS2

DDR_B_DQS3DDR_B_DQS2

DDR_B_DQS7

DDR_B_DQS4

DDR

_B_DQS1

DDR_B_DQS5DDR_B_DQS6

DDR_B_DQS0

M_CLK_DDR0

M_CLK_DDR#0

M_CLK_DDR1

M_CLK_DDR#1

M_CLK_DDR3M_CLK_DDR#3

M

_CLK_DDR#2M_CLK_DDR2

DDR_B_MA10DDR_B_MA9

DDR_B_MA14

DDR_B_MA5

DDR_B_MA13

DDR_B_MA11

DDR_B_MA7

DDR

_B_MA2

DDR_B_MA0

DDR_B_MA6

DDR_B_MA1

DDR_B_MA12

DDR_B_MA4

DDR_B_MA8

DDR_B_MA3

DDR_B_MA15

DDR_A_RAS#

DDR_A_WE#

DDR_A_CAS#

DDR_A_D27

DDR_A_D35

DDR_A_D56

DDR_A_D23

DDR_A_D53

DDR_A_D47

DDR_A_D49

DDR_A_D29

DDR_A_D42

DDR_A_D61

DDR_A_D30

DDR_A_D36

DDR_A_D57

DDR_A_D59

DDR_A_D24

DDR_A_D48

DDR_A_D50

DDR_A_D28

DDR_A_D43

DDR_A_D62

DDR_A_D31

DDR_A_D37

DDR_A_D39

DDR_A_D58

DDR_A_D25

DDR_A_D33

DDR_A_D54

DDR

_A_D51

DDR_A_D44

DDR_A_D46

DDR_A_D32

DDR_A_D38

DDR_A_D40

DDR_A_D26

DDR_A_D34

DDR_A_D55

DDR_A_D52

DDR_A_D45

DDR

_A_D63

DDR_A_D41

DDR_A_D60

DDR_A_D0

DDR_A_D1DDR_A_D2

DDR_A_D3DDR_A_D4

DDR_A_D5DDR_A_D6

DDR_A_D9

DDR_A_D18

DDR_A_D14

DDR_A_D8

DDR_A_D17

DDR_CS2_DIMMB#DDR_CS3_DIMMB#

DDR_A_D13

DDR_A_D22DDR_A_D21

DDR_A_D7

DDR_A_D16

DDR_A_D12

DDR_A_D20

DDR

_A_D10

DDR_A_D15

DDR_A_D11

DDR_A_D19

DDR_CKE0_DIMMA

DDR_B_DQS#3

DDR_B_DQS#6

DDR_B_DQS#1

DDR_B_DQS#2

DDR_B_DQS#0

DDR_B_DQS#5

DDR_B_DQS#7

DDR_B_DQS#4

DDR_A_BS2 <17>

DDR_A_D[0..63]<17>

DDR_A_DQS[0..7] <17>

DDR_A_DQS#[0..7] <17>

DDR_A_MA[0..15] <17>

DDR_A_WE# <17>DDR_A_CAS# <17>

DDR_A_BS0 <17>DDR_A_BS1 <17>

DDR_A_RAS# <17>

M_CLK_DDR#0 <17>M_CLK_DDR0 <17>

M_CLK_DDR#1 <17>

DDR_CKE0_DIMMA <17>DDR_CKE1_DIMMA <17>

M_CLK_DDR1 <17>

DDR_CS0_DIMMA# <17>DDR_CS1_DIMMA# <17>

DDR_B_D[0..63]<18>

DDR_B_DQS[0..7] <18>

DDR_B_DQS#[0..7] <18>

DDR_B_MA[0..15] <18>

DDR_B_BS1 <18>

DDR_CS2_DIMMB# <18>

DDR_CS3_DIMMB# <18>

DDR_B_BS2 <18>

DDR_B_RAS# <18>

M_CLK_DDR#2 <18>

M_CLK_DDR2 <18>M_CLK_DDR#3 <18>

DDR_CKE2_DIMMB <18>DDR_CKE3_DIMMB <18>

M_CLK_DDR3 <18>

DDR_B_WE# <18>

DDR_B_CAS# <18>

DDR_B_BS0 <18>

+SM_VREF_CA

+SM_VREF_DQ0+SM_VREF_DQ1

+1.35V

+SM_VREF_CA +SM_VREF_DQ1

+1.35V

+SM_VREF_DQ0

+1.35V

+SM_VREF_DQ0_DIMM1+SM_VREF_CA_DIMM +SM_VREF_DQ1_DIMM2

Title


Date: Sheet of




LA-9981P 0.2

7 55Saturda

y, March 09, 2013


MCP(3,4/19) DDR3Title


Date: Sheet of




LA-9981P 0.2

7 55Saturda

y, March 09, 2013


MCP(3,4/19) DDR3Title


Date: Sheet of




LA-9981P 0.2

7 55Saturda

y, March 09, 2013


MCP(3,4/19) DDR3

RC211.82K_0402_1%RC211.82K_0402_1%

1

2 RC24

24.9_0402_1%~D

RC24

24.9_0402_1%~D

1

2

CC10

0.022U_0402_16V7K

CC10

0.022U_0402_16V7K

1

2

CC9

0.022U_0402_16V7K

CC9

0.022U_0402_16V7K

1

2

DDRCHANNELB

HASWELL_MCP_E

Rev1p24 OF 19

UC1D

DDRCHANNELB

HASWELL_MCP_E

Rev1p24 OF 19

UC1D

SB_DQSP4 AV22

SB_DQSP5 AW18

SB_DQSP6 AM21

SB_DQSP3 AM25

SB_DQSP7 AM18

SB_DQSP2 AM28

SB_DQSN7 AN18

SB_DQSP0 AV30

SB_DQSP1

AW26

SB_DQSN6 AN21

SB_DQSN2 AN28

SB_DQSN3 AN25

SB_DQSN4 AW22

SB_DQSN5 AV18

SB_DQSN1 AV26SB_DQSN0 AW30

SB_MA14 AR46

SB_MA15 AP46

SB_MA13 AK33

SB_MA9 AU46

SB_MA10

AK36

SB_MA11 AV47

SB_MA8 AY47

SB_MA12 AU47

SB_MA4 AR45

SB_MA5 AP45

SB_MA6 AW46

SB_MA3 AR42

SB_MA7 AY46

SB_MA2 AP42

SB_MA0 AP40

SB_MA1

AR40

SB_BA2 AU49

SB_WE AK35

SB_CAS AM33

SB_BA0 AL35

SB_BA1

AM36

SB_RAS AM35

SB_CS#1 AK32

SB_ODT0

AL32

SB_CS#0 AM32

SB_CKE1 AU50

SB_CKE2

AW49

SB_CKE3 AV50

SB_CKE0 AY49

SB_CK#1 AK38

SB_CK1 AL38

SB_CK0 AN38SB_CK#0 AM38

SB_DQ61 AM20

SB_DQ63 AP18 SB_DQ62 AR1

8

SB_DQ57 AR20 SB_DQ56 AN20

SB_DQ58 AK18

SB_DQ59 AL1

8

SB_DQ60 AK20

SB_DQ51 AM22SB_DQ52

AN22

SB_DQ53 AP21

SB_DQ54 AK21

SB_DQ55 AK22

SB_DQ46 AV17

SB_DQ47 AU17

SB_DQ48 AR21

SB_DQ49 AR22

SB_DQ50 AL21

SB_DQ45 AU19

SB_DQ41 AW19

SB_DQ42 AY1

7

SB_DQ43 AW17

SB_DQ44 AV19

SB_DQ40 AY19

SB_DQ36 AV23

SB_DQ37 AU23

SB_DQ38 AV21

SB_DQ39 AU21

SB_DQ35 AW21

SB_DQ31 AL25

SB_DQ32 AY2

3

SB_DQ33 AW23

SB_DQ30 AK25

SB_DQ34 AY21

SB_DQ26 AR25 SB_DQ25 AR26

SB_DQ27 AP25

SB_DQ28 AK26

SB_DQ29 AM26

SB_DQ20 AR29

SB_DQ21 AN29

SB_DQ22 AR28

SB_DQ23 AP28

SB_DQ24 AN26

SB_DQ15 AU25

SB_DQ16 AM2

9

SB_DQ17 AK29

SB_DQ18 AL28

SB_DQ19 AK28

SB_DQ10 AY25

SB_DQ11 AW25

SB_DQ13

AU27

SB_DQ5 AU31

SB_DQ6 AV29

SB_DQ7 AU29

SB_DQ8 AY27

SB_DQ9 AW27

SB_DQ0 AY31

SB_DQ1 AW31

SB_DQ2 AY29

SB_DQ3 AW29

SB_DQ4 AV31

SB_DQ14 AV25

SB_DQ12 AV27

RC151.82K_0402_1%RC151.82K_0402_1%

1

2

CC8

0.022U_0402_16V7K

CC8

0.022U_0402_16V7K

1

2

RC23

24.9_0402_1%~D

RC23

24.9_0402_1%~D

1

2

RC201.82K_0402_1%RC201.82K_0402_1%

1

2

RC161.82K_0402_1%RC161.82K_0402_1%

1

2

RC221.82K_0402_1%RC221.82K_0402_1%

1

2

RC18

2.2_0402_1%

RC18

2.2_0402_1%

1 2

RC19

2.2_0402_1%

RC19

2.2_0402_1%

1 2

RC141.82K_0402_1%RC141.82K_0402_1%

1

2

RC17

2.2_0402_1%

RC17

2.2_0402_1%

1 2

RC25

24.9_0402_1%~D

RC25

24.9_0402_1%~D

1

2

DDRCHANNELA

HASWELL_MCP_E

Rev1p23 OF 19

UC1C

DDRCHANNELA

HASWELL_MCP_E

Rev1p23 OF 19

UC1C

SA_DQ25 AR55

SA_DQ28 AL55

SA_CLK1 AY36SA_CLK#1 AW36SA_CLK0 AV37SA_CLK#0 AU37

SA_DQ0 AH63

SA_DQ1 AH6

2

SA_DQ2 AK63

SA_DQ3 AK62

SA_DQ4 AH61

SA_DQ5 AH60

SA_DQ6 AK61

SA_DQ7 AK60

SA_DQ8 AM63

SA_DQ9 AM62

SA_DQ10 AP63

SA_DQ11 AP62

SA_DQ12 AM61

SA_DQ13 AM60

SA_DQ14

AP61

SA_DQ16 AP58

SA_DQ17 AR58

SA_DQ18 AM57

SA_DQ19 AK57

SA_DQ20 AL58

SA_DQ21 AK58

SA_DQ22 AR57

SA_DQ23 AN57

SA_DQ24 AP55

SA_DQ27 AK54 SA_DQ26 AM54

SA_DQ29 AK55

SA_DQ30 AR54

SA_DQ31 AN54

SA_DQ32 AY58

SA_DQ33 AW58

SA_DQ34 AY56

SA_DQ35 AW56

SA_DQ36 AV58

SA_DQ37 AU58

SA_DQ38 AV56

SA_DQ39 AU56

SA_DQ40 AY54

SA_DQ41 AW54

SA_DQ42 AY52

SA_DQ43 AW52

SA_DQ44 AV54

SA_DQ45 AU54

SA_DQ46 AV52

SA_DQ47 AU52

SA_DQ48 AK40

SA_DQ49 AK42

SA_DQ50 AM43

SA_DQ51 AM45

SA_DQ52 AK45SA_DQ53

AK43

SA_DQ54 AM40

SA_DQ55 AM42

SA_DQ56 AM46

SA_DQ57 AK46

SA_DQ58 AM49

SA_DQ59 AK49

SA_DQ60 AM48

SA_DQ61 AK48

SA_DQ62 AM51

SA_DQ63 AK51

SA_DQ15 AP60

SA_CKE2 AY42SA_CKE1 AW43SA_CKE0 AU43

SA_CKE3

AY43

SA_CS#1 AR32SA_CS#0 AP33

SA_ODT0 AP32

SA_RAS AY34

SA_CAS AU34SA_WE AW34

SA_BA0 AU35

SA_BA1

AV35

SA_BA2 AY41

SA_MA1 AY37SA_MA0 AU36

SA_MA2 AR38

SA_MA3

AP36

SA_MA4 AU39

SA_MA5 AR36

SA_MA7 AW39SA_MA6 AV40

SA_MA9 AU40SA_MA8 AY39

SA_MA11 AW41

SA_MA12 AU41

SA_MA10

AP35

SA_MA14 AV42SA_MA13 AR35

SA_MA15 AU42

SA_DQSN0 AJ61

SA_DQSN2 AM58SA_DQSN1

AN62

SA_DQSN3 AM55

SA_DQSN5 AV53SA_DQSN4 AV57

SA_DQSN7 AL48SA_DQSN6 AL43

SA_DQSP1 AN61SA_DQSP0 AJ62

SA_DQSP4 AW57SA_DQSP3 AN55

SA_DQSP2

AN58

SA_DQSP6 AL42SA_DQSP5 AW53

SA_DQSP7 AL49

SM_VREF_CA AP49

SM_VREF_DQ1 AP51SM_VREF_DQ0

AR51

5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

LOW = DESABLED (DEFAULT)

HIGH = ENABLED

FLASH DESCRIPTOR SECURITY OVERRIDE

High - Enable Internal VRs

Low - Enable External VRs

INTVRMEN - INTEGRATED SUS 1.05V VRM

ENABLE

CMOS setting

Shunt Clear CMOS

Keep CMOS

TPM setting

S hu nt C le ar ME RT C R eg is te rsKeep ME RTC Registers

ME_CLR1

Open

CMOS_CLR1

Open

SATA HDD

SATA ODD

RTC Battery

W=20mils

W=20mils

CMOS place near DIMM

PCH Rx side need use strap pin to update PCIE +/-

within 500 mils

SATA Impedance Compensation

CAD note:

Place the resistor within 500 mils of the PCH. Avoid

routing next to clock pins.

reference FFRD sch 0.5

W=20mils

HDA for Codec

EMI depop location

For GCLK

PCH_AZ_SDOUT

PCH_INTVRMEN

INTRUDER#PCH_RTCX2

PCH_JTAG_TMS

PCH _JTAG_TDIPCH_JTAG_TDO

PCH_RTCX1

PCH_JTAG_RST#

PCH_INTVRMENSRTCRST#

PCH_RTCRST#

PCH_AZ_BITCLK

PCH_AZ_SYNCPCH_AZ_RST#

PCH_AZ_CODEC_SDIN0

PCH_AZ_SDOUT

PCH_GPIO37

PCH_JTAG_TCK

PCH_JTAG_JTAGX

PCH_GPIO37

PCH_GPIO35ODD_DETECT#

SATA_ACT#SATA_RCOMP

SATA_IREF

PCH_JTAG_TCK

PCH_JTAG_JTAGX

PCH_JTAG_TDIPCH_JTAG_TDO

PCH_JTAG_TMS

ODD_DETECT#

PCH_GPIO35EC_SMI#

PCH_AZ_RST#

PCH_AZ_SYNC

PCH_AZ_SDOUT

PCH_AZ_BITCLK

PCH_RTCX1

ME_EN<30>

PCH_AZ_CODEC_SDIN0<22>

PCH_JTAG_TCK<6>PCH_JTAG_TDI<6>

PCH_JTAG_TDO<6>PCH_JTAG_TMS<6>

EC_SMI# <30>

SATA_PRX_DTX_P0_C <32>SATA_PTX_DRX_N0_C <32>SATA_PTX_DRX_P0_C <32>

SATA_PRX_DTX_N0_C <32>

SATA_PRX_DTX_P1_C <32>SATA_PTX_DRX_N1_C <32>

SATA_PTX_DRX_P1_C <32>

SATA_PRX_DTX_N1_C <32>

SATA_ACT# <26>

PCH_JTAG_JTAGX<6>

PCH_JTAG_RST#<6>

ODD_DETECT# <32>

PCH_AZ_CODEC_RST#<22>

PCH_AZ_CODEC_SYNC<22>

PCH_AZ_CODEC_SDOUT<22>

PCH_AZ_CODEC_BITCLK<22>

PCH_RTCX1<29>

+RTCVCC

+3VS

+RTCVCC

+3VS

+1.05VS_ASATA3PLL

+1.05VS

+1.05VS

+CHGRTC

+RTCBATT

+RTCVCC

+3VLP+CHGRTC

+3VS

Title


Date: Sheet of




LA-9981P 0.2



MCP(5/19) RTC,SATA,HDA,JTAG Title


Date: Sheet of




LA-9981P 0.2



MCP(5/19) RTC,SATA,HDA,JTAG Title


Date: Sheet of




LA-9981P 0.2



MCP(5/19) RTC,SATA,HDA,JTAG

R2 357 33_0 402 _5%EMI@ R2 357 33_0 402 _5%EMI@ 1 2

RC130 1K_0402_1%@RC130 1K_0402_1%@ 12

RC135 51_0402_1%

@

RC135 51_0402_1%

@ 12

YC1

32.768KHZ_12.5PF_Q13FC1350000

XTAL@

YC1

32.768KHZ_12.5PF_Q13FC1350000

XTAL@

1

2

RC5 20K_0402_5%RC5 20K_0402_5%

1 2

CC261U_0603_10V6KCC261U_0603_10V6K

1

2

JP12

JUMP_43X39

JP12

JUMP_43X39

11

22

SATA AUDIO

RTC

JTAG

HASWELL_MCP_E

Rev1p25 OF 19

UC1E

SATA AUDIO

RTC

JTAG

HASWELL_MCP_E

Rev1p25 OF 19

UC1E

INTVRMEN AV7

SRTCRST AV6

RTCRST AU7

RTCX1 AW5

SATA_RN0/PERN6_L3J5

SATA_RP0/PERP6_L3H5

SATA_TN0/PETN6_L3B15

SATA_TP0/PETP6_L3 A15

SATA_RP1/PERP6_L2H8SATA_RN1/PERN6_L2J8

SATA_TN1/PETN6_L2 A17

SATA_TP1/PETP6_L2B17

SATA_RP2/PERP6_L1H6SATA_RN2/PERN6_L1J6

SATA_TN2/PETN6_L1B14

SATA_TP2/PETP6_L1C15

SATA_RN3/PERN6_L0F5

SATA_RP3/PERP6_L0E5

SATA_TN3/PETN6_L0C17

SATA_TP3/PETP6_L0D17

SATA0GP/GPIO34V1

SATA1GP/GPIO35U1

SATA2GP/GPIO36V6

SATA3GP/GPIO37 AC1

SATA_IREF A12

SATA_RCOMPC12

INTRUDER AU6 RTCX2 AY5

JTAGX AE63

SATALEDU3

I2S1_SCLK AY8

RSVD AV2

RSVD AL11

RSVD AC4

HDA_BCLK/I2S0_SCLK AW8

HDA_SYNC/I2S0_SFRM AV11

HDA_RST/I2S_MCLK AU8

HDA_SDI0/I2S0_RXD AY10

HDA_SDO/I2S0_TXD AU11 HDA_SDI1/I2S1_RXD AU12

HDA_DOCK_EN/I2S1_TXD AW10

HDA_DOCK_RST/I2S1_SFRM AV10

PCH_TRST AU62

PCH_TCK AE62

PCH_TDI AD61

PCH_TDO AE61

PCH_TMS AD62 RSVD

K10RSVDL11

RC2330K_0402_1%

@

RC2330K_0402_1%

@ 1

2

CC5

27P_0402_50V8J

@EMI@CC5

27P_0402_50V8J

@EMI@1

2

ME1 SHORT PADS~D@ME1 SHORT PADS~D@

11

22

R2 358 33_0 402 _5%EMI@ R2 358 33_0 402 _5%EMI@ 1 2

RC1

330K_0402_1%

RC1

330K_0402_1%

1

2

CC4 1U_0402_6.3V6KCC4 1U_0402_6.3V6K1 2

R C1 31 3 .0 1K _0 40 2_ 1%R C1 31 3 .0 1K _0 40 2_ 1%1 2

CC2

15P_0402_50V8J

XTAL@CC2

15P_0402_50V8J

XTAL@

1 2

CC1

15P_0402_50V8J

XTAL@

CC1

15P_0402_50V8J

XTAL@

1 2

RC410M_0402_5%

XTAL@RC410M_0402_5%

XTAL@

1

2

RP3710K_8P4R_5%RP3710K_8P4R_5%

1 82 73 64 5

RC3 1K_0 402_ 5%@ RC3 1K_0 402_ 5%@1 2

CMOS1 SHORT PADS~D@CMOS1 SHORT PADS~D@

11

22

RC10710K_0402_5%RC10710K_0402_5%

1

2

RC6 20K_0402_5%RC6 20K_0402_5%

1 2

RC12 6 0 _060 3_5 %RC12 6 0 _060 3_5 %1 2

RC10

1K_0402_5%

RC10

1K_0402_5%

1

2

DC1

BAT54CW_SOT323-3

DC1

BAT54CW_SOT323-3

2 3

1

RC7 1M_0402_5%RC7 1M_0402_5%1 2

R2 359 33_0 402 _5%EMI@ R2 359 33_0 402 _5%EMI@ 1 2

RP4851_8P4R_5%RP4851_8P4R_5%

1 82 73 64 5

CC3 1U_0402_6.3V6KCC3 1U_0402_6.3V6K

1 2

R2 356 33_0 402 _5%EMI@ R2 356 33_0 402 _5%EMI@ 1 2

R C8 1 K_ 04 02 _5 %R C8 1 K_ 04 02 _5 %1 2



5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

WLAN (Mini Card)

10/100 LAN

CAD NOTE:

Route single-end 50-ohms and max 500-mils length.

Avoid routing next to clock pins or under stitching capacitors.

Recommended minimum spacing to other signal traces is 15 mils.

USB Conn JUSB2

USB Conn JUSB1

USB Conn JUSB3

USB Conn 4 (DB)

Mini Card (WLAN)

Card Reader

Camera

USB Conn JUSB2

USB Conn JUSB1

Touch screen panel"USB20_TOUCH_N5/USB20_TOUCH_P5" for OAK 15 only

USB_OC0#

USB_OC2#USB_OC3#

PCIE_PTX_WLANRX_N4

PCIE_PRX_WLANTX_P4

PCIE_PRX_WLANTX_N4

PCIE_PTX_WLANRX_P4

USB20_JUSB3_N2

USB20_JUSB3_P2

USB20_USBDB_P3USB20_USBDB_N3

USB20_MINI1_P4USB20 _MINI1_N4

USB20_CAM_P7USB20_CAM_N7

USB20_CR_N6

USB20_CR_P6

USB20_JUSB1_P1USB20_JUSB1_N1

USB_OC0#

USB_OC1#USB_OC2#

USB3RN2_JUSB1USB3RP2_JUSB1

USB3TN2_JUSB1

USB3TP2_JUSB1

USB3RN1_JUSB2USB3RP1_JUSB2

USB3TN1_JUSB2

USB3TP1_JUSB2

PCH_PCIE_RCOMP

PCIE_PRX_LANTX_P3

PCIE_PRX_LANTX_N3

USB_OC1#

USB20_JUSB2_N0

USB20_JUSB2_P0

USB_OC3#

USBRBIAS

PEG_CTX_GRX_C_N0

PEG_CRX_GTX_N3

PEG_CRX_GTX_P3

PEG_CRX_GTX_N0

PEG_CTX_GRX_C_N1PEG_CTX_GRX_N1PEG_CTX_GRX_C_P1PEG_CTX_GRX_P1


PEG_CRX_GTX_N1

PEG_CRX_GTX_P1

PEG_CRX_GTX_P0

PEG_CTX_GRX_C_P0


PEG_CRX_GTX_N2PEG_CRX_GTX_P2

PEG_CTX_GRX_P0

PCIE_PTX_LANRX_N3PCIE_PTX_LANRX_P3

PCIE_PTX_LANRX_N3_CPCIE_PTX_LANRX_P3_C

USB20_TOUCH_P5USB20_TOUCH_N5

PEG_CTX_GRX_N0

PCIE_PRX_LANTX_N3<21>PCIE_PRX_LANTX_P3<21>

PCIE_PRX_WLANTX_N4<26>PCIE_PRX_WLANTX_P4<26>

PCIE_PTX_WLANRX_N4<26>

PCIE_PTX_WLANRX_P4<26>

USB_OC0# <24>

USB20_JUSB2_N0 <24>USB20_JUSB2_P0 <24>

USB20_JUSB1_N1 <24>

USB20_JUSB1_P1 <24>

USB20_JUSB3_N2 <25>USB20_JUSB3_P2 <25>

USB20_USBDB_N3 <25>USB20_USBDB_P3 <25>

USB20_MINI1_N4 <26>USB20_MINI1_P4 <26>

USB20_CR_N6 <23>USB20_CR_P6 <23>

USB20_CAM_N7 <31>

USB20_CAM_P7 <31>

USB3RN1_JUSB2 <24>

USB3TN1_JUSB2 <24>

USB3TN2_JUSB1 <24>

USB3RP1_JUSB2 <24>

USB3RP2_JUSB1 <24>

USB3TP2_JUSB1 <24>

USB3TP1_JUSB2 <24>

USB3RN2_JUSB1 <24>

USB_OC1# <25>

PEG_CRX_GTX_N3<48>PEG_CRX_GTX_P3<48>

PEG_CTX_GRX_N0<48>

PEG_CTX_GRX_P0<48>

PEG_CRX_GTX_N0<48>

PEG_CTX_GRX_N1<48>PEG_CTX_GRX_P1<48>

PEG_CTX_GRX_N2<48>

PEG_CTX_GRX_P2<48>


PEG_CTX_GRX_N3<48>

PEG_CTX_GRX_P3<48>


PEG_CRX_GTX_P0<48>

PCIE_PTX_LANRX_N3<21>

PCIE_PTX_LANRX_P3<21>

USB20_TOUCH_N5 <31>

USB20_TOUCH_P5 <31>

+1.05VS_AUSB3PLL

+3VALW_PCH

Title


Date: Sheet of




LA-9981P 0.2



MCP(11/19) PCIE,USBTitle


Date: Sheet of




LA-9981P 0.2



MCP(11/19) PCIE,USBTitle


Date: Sheet of




LA-9981P 0.2



MCP(11/19) PCIE,USB

C C2 1 0 .1 U_ 0 40 2_ 1 0V 7KDIS@ C C2 1 0 .1 U_ 0 40 2_ 1 0V 7KDIS@ 12

C C4 0 0 .1 U_ 0 40 2_ 1 0V 7KC C4 0 0 .1 U_ 0 40 2_ 1 0V 7K1 2

T120PAD~D@ T120PAD~D@



RC9022.6_0402_1%~DRC9022.6_0402_1%~D

1

2


T121PAD~D@ T121PAD~D@


RP55

10K_8P4R_5%

RP55

10K_8P4R_5%

1 82 73 64 5

T119PAD~D @T119PAD~D @


RC913.01K_0402_1%RC913.01K_0402_1%1 2


C C3 2 0 .1 U_ 0 40 2_ 1 0V 7KC C3 2 0 .1 U_ 0 40 2_ 1 0V 7K1 2PCIe USB

HASWELL_MCP_E

Rev1p211 OF 19

UC1K

PCIe USB

HASWELL_MCP_E

Rev1p211 OF 19

UC1K

PETP5_L2C21

PERP5_L0E10

PERN5_L1F8

PETN5_L3B22

PETP5_L3 A21

PERP3F11

PETN3C29

PETN1/USB3TN3C30

OC3/GPIO43 AV3OC2/GPIO42 AH2OC1/GPIO41 AT1OC0/GPIO40 AL3

PCIE_RCOMP A27

PCIE_IREFB27

PERN5_L0F10

PERN5_L2H10

PERP5_L2G10

PETN5_L2B21

PERP5_L3F6 PERN5_L3E6

PETP3B30

PERN4F13

PERP4G13

PETP4 A29 PETN4B29

PERP1/USB3RP3F17

PETP1/USB3TP3C31

PERN2/USB3RN4F15

PETN2/USB3TN4B31

PERP2/USB3RP4G15

USB2N0 AN8

USB2N1 AR7

USB2N2 AR8

USB2P2 AP8

USB2N3 AR10

USB2P3 AT10

USB2N4 AM15

USB2P4 AL15

USB2P6 AN11

USB2N5 AM13

USB2P5 AN13

USB2N6 AP11

USB2P7 AP13USB2N7 AR13

USB3TN2B33

USB3TP2 A33

USB3RP2F18USB3RN2E18

USB3TN1C33

USB3TP1B34

USB3RP1H20USB3RN1G20

PETP5_L1 A23 PETN5_L1B23

PERP5_L1E8

USBRBIAS AJ11USBRBIAS AJ10

PETP5_L0C22 PETN5_L0C23

PERN3G11

USB2P0 AM8

USB2P1 AT7

PERN1/USB3RN3G17

PETP2/USB3TP4 A31

RSVDE15

RSVDE13

RSVD AN10

RSVD AM10



5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

RF

SVID DATA

Define EC OD pin, need double confirm.

SVID ALERT

Place the PU

resistors close to CPU

Place the PU

resistors close to CPU

CAD Note: PD resistor on HW side

CAD Note: PU resistor on HW side

R253

INTEL Check list , XDP use only

+1.35V : 470UF/2V/7343 *2 (PWR)

10UF/6.3V/0603 * 6

2.2UF/6.3V/0402 * 4

VDDQ DECOUPLING

SVID_DAT need to pull-up double side

( PWR_VR & CPU )

ESD solution

H_CPU_SVIDCLK

VCCST_PG_EC

+VCCIO_OUT_R

VCCST_PG_ECVR12.5_VR_ON_R

VR_READY_R

CPU_PWR_DEBUG#

H_CPU_SVIDALRT#

H_CPU_SVIDDATAH_CPU_SVIDCLK

VCCSENSE

H_CPU_SVIDALRT#

H_CPU_SVIDDATA

CPU _PWR_DEBUG#

VSSSENSE

VCCSENSE

VCCST_PG_EC<30>

VR_SVID_CLK<42>

VR_ON<30,42>

VR_SVID_ALRT#<42>

VSSSENSE<15,42>

VCCSENSE<42>

H_VR_READY<42>

VR_SVID_DAT<42>

CPU_PWR_DEBUG#<6>

+1.05VS

+CPU_CORE

+VCCIOA_OUT

+CPU_CORE

+1.35V

+CPU_CORE

+1.35V

+VCCIO_OUT

+1.05VS

+1.05VS

+CPU_CORE

+1.05VS

+1.05VS

+CPU_CORE +1.35V

Title


Date: Sheet of




LA-9981P 0.2



MCP(12/19) Power Title


Date: Sheet of




LA-9981P 0.2





Date: Sheet of




LA-9981P 0.2



MCP(12/19) Power

T50 @T50 @

C 3 5

2 .2 U _ 0 4 0 2 _ 6 . 3 V 6 M

C 3 5

2 .2 U _ 0 4 0 2 _ 6 . 3 V 6 M

1

2

C 4 5

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 4 5

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

T49 @T49 @

C 4 1

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 4 1

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

R2

100_0402_1%

R2

100_0402_1%

1

2

R254

43_0402_1%

R254

43_0402_1%12

R257

0_0402_1%

@R257

0_0402_1%

@

12

T48 @T48 @

C 3 8

2 .2 U _ 0 4 0 2 _ 6 . 3 V 6 M

C 3 8

2 .2 U _ 0 4 0 2 _ 6 . 3 V 6 M

1

2

R245

0_0603_5%

@R245

0_0603_5%

@

1

2

R256130_0402_1%R256130_0402_1%

1

2

C521268P_0402_50V8J

RF@

C521268P_0402_50V8J

RF@1

2

T41 @T41 @T42 @T42 @

C 7 2

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 7 2

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

T51 @T51 @

R253150_0402_1%

@

R253150_0402_1%

@

1

2

R1100_0402_1%R1100_0402_1%

1

2

T40 @T40 @

R25275_0402_5%R25275_0402_5%

1

2

T39 @T39 @

T44 @T44 @

T46 @T46 @

HSWULTPOWER

HASWELL_MCP_E

Rev1p2

12OF19

UC1L

HSWULTPOWER

HASWELL_MCP_E

Rev1p2

12OF19

UC1L

VCCST AE22

VCCST

AE23

VCC AB57

VCC AD57

VCC

K23

VCCC44VCCC40VCCC36

VCCC52VCCC48

VCCE25VCCE23VCCC56

VCCE29VCCE27

VCCE35VCCE33VCCE31

VCCE39VCCE37

VCCE45VCC E43

VCCE41

VCCE49VCCE47

VCCE55VCCE53VCCE51

VCCE57

VCCF24

VCCF36VCCF32VCCF28

VCCF40

VCCF44

VCCF48

VCCF56VCCF52

VCCG23

VCCG25

VCCG27

VCCG31VCCG29

VCCG33

VCCG35

VCCG37

VCCG41VCCG39

VCCG43

VCCG47VCCG45

VCCG53VCCG51VCCG49

VCCG57VCCG55

VCCJ23VCCH23

VCCK57

VCCL22

VCCP57VCCM57VCCM23

VCCU57

VCCW57

VCC AG57

VCCC32 VCCC28 VCCC24

RSVDL59

RSVDJ58

VDDQ AH26

VDDQ AJ31

VDDQ AJ33

VDDQ AJ37

VDDQ AN33

VDDQ AP43

VDDQ AR48

VIDSCLKN63

VIDSOUTL63

VR_ENF60

RSVD_TPP60 VSSP62 PWR_DEBUGH59 VSSD63

VR_READYC59

VCCST_PWRGDB59

VIDALERTL62

RSVD AE59 RSVD AA23

VCC_SENSEE63

RSVDN58

VDDQ AY50

RSVD_TPP61

VCCST AC22

RSVD_TPN59

RSVDT59

RSVD AD60

RSVD AD59

RSVD AE60

RSVD AC59

RSVD AG58

RSVDV59 RSVDU59

RSVD AA59

RSVD_TPN61

VDDQ AY35

VDDQ AY40

VDDQ AY44

VCCF59

RSVD AC58

RSVD AB23

RSVD AD23 VCCIOA_OUT

E20 VCCIO_OUT A59

T43 @T43 @

R2480_0402_5% R2480_0402_5% 1 2

R2510_0402_5% R2510_0402_5% 1 2

C40

22U_0603_6.3V6M

ESD@

C40

22U_0603_6.3V6M

ESD@

1 2

R255

10K_0402_5%

@R255

10K_0402_5%

@

1

2

C 7 4

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 7 4

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

C 3 9

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 3 9

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

C 3 7

2 .2 U _ 0 4 0 2 _ 6 . 3 V 6 M

C 3 7

2 .2 U _ 0 4 0 2 _ 6 . 3 V 6 M

1

2

C 3 6

2 .2 U _ 0 4 0 2 _ 6 . 3 V 6 M

C 3 6

2 .2 U _ 0 4 0 2 _ 6 . 3 V 6 M

1

2

T47 @T47 @

R2500_0402_5% R2500_0402_5% 1 2

R286

10K_0402_5%

R286

10K_0402_5%

1

2

T45 @T45 @

C 4 2

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 4 2

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

T38 @T38 @

5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

Close to N8

Close to AC9/AA9/AE20/AE21

Close to V8

Close to J17

Close to R21

Close to AH14

Close to AH10

Close to K9,M9

Reserve for HDA issue, C77 close to AH14

ESD solution

ESD solution

+PCH_VCCDSW

+VCCRTCEXT

+PCH_VCCDSW_R

+3VS

+1.05VS

+1.05VS

+1.05VS_AUSB3PLL

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

+1.05VS

+3VALW_PCH

+3VALW_PCH

+3VS

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL+1.05VS+1.05VS

+1.5VS

+RTCVCC

+3VS

+1.05VS

+3VS

+1.05VS

+1.05VS

+1.05VS

+3VALW_PCH

+3VS

+1.05VS

+1.05VS

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

+3VALW_PCH

+3VALW_PCH

+ 1. 05 VS + 1. 05 VS _A US B3 PL L

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

+VCCHDA

+3VALW_PCH

+1.05VS

+1.5VS +3VS

+VCCHDA

+VCCHDA+3VALW_PCH

+1.05VS +3VS

+1.35V+1.05VS

+RTCVCC

Title


Date: Sheet of




LA-9981P 0.2





Date: Sheet of




LA-9981P 0.2





Date: Sheet of




LA-9981P 0.2



MCP(13/19) Power

C 65 1 0 0U _1 2 06 _6 . 3V 6MC 65 1 0 0U _1 2 06 _6 . 3V 6M1 2

T59 @T59 @

C 57 1 U_ 04 02 _6 .3 V6 K@C 57 1 U_ 04 02 _6 .3 V6 K@1 2

C 66 2 2 U_ 06 0 3_ 6 .3 V6 M@ C 66 2 2 U_ 06 0 3_ 6 .3 V6 M@ 1 2

R2640_0603_5% R2640_0603_5% 12

RC1 28 0_0 402_ 5%@RC1 28 0_0 402_ 5%@1 2

C 51 1 U_ 04 02 _6 .3 V6 KC 51 1 U_ 04 02 _6 .3 V6 K1 2

C 53 1 U_ 04 02 _6 .3 V6 KC 53 1 U_ 04 02 _6 .3 V6 K1 2

C44

22U_0603_6.3V6M

ESD@

C44

22U_0603_6.3V6M

ESD@

1 2

C 52 0 . 1U _0 4 02 _1 0 V7 KC 52 0 . 1U _0 4 02 _1 0 V7 K1 2

C 68 0 . 1U _0 4 02 _1 0 V7 K@ C 68 0 . 1U _0 4 02 _1 0 V7 K@ 1 2

RC1 27 0_0 402_ 5%RC1 27 0_0 402_ 5%1 2

C 69 1 U_ 04 02 _6 .3 V6 KC 69 1 U_ 04 02 _6 .3 V6 K1 2

C 59 1 0 0U _1 2 06 _6 . 3V 6MC 59 1 0 0U _1 2 06 _6 . 3V 6M1 2

C 61 1 U_ 04 02 _6 .3 V6 KC 61 1 U_ 04 02 _6 .3 V6 K1 2

C 58 1 U_ 04 02 _6 .3 V6 KC 58 1 U_ 04 02 _6 .3 V6 K1 2

L4

2.2UH_LQM2MPN2R2NG0L_30%

L4


1 2

C 75 0 .1 U_ 0 40 2 _1 0V 7KC 75 0 .1 U_ 0 40 2 _1 0V 7K12

L1


L1


1 2

C 87 1 U_ 04 02 _6 .3 V6 KC 87 1 U_ 04 02 _6 .3 V6 K1 2

C 63 1 U_ 04 02 _6 .3 V6 KC 63 1 U_ 04 02 _6 .3 V6 K1 2

C 82 2 2U _0 6 03 _ 6. 3V 6MC 82 2 2U _0 6 03 _ 6. 3V 6M1 2

T58 @T58 @

L2


L2


1 2

C 85 1 U_ 04 02 _6 .3 V6 KC 85 1 U_ 04 02 _6 .3 V6 K1 2

L32.2UH_LQM2MPN2R2NG0L_30%

@L32.2UH_LQM2MPN2R2NG0L_30%

@1 2

C 86 1 00 U_ 1 20 6 _6 .3 V6 MC 86 1 00 U_ 1 20 6 _6 .3 V6 M1 2

C 60 1 0 U_ 06 0 3_ 6 .3 V6 MC 60 1 0 U_ 06 0 3_ 6 .3 V6 M1 2

C 71 0 .1 U_ 0 40 2 _1 0 V7 KC 71 0 .1 U_ 0 40 2 _1 0 V7 K1 2

C 5 6

0 . 1 U_ 0 4

0 2_

1 0 V 7 K

C 5 6

0 . 1 U_ 0 4

0 2_

1 0 V 7 K

1

2

C 73 1 U_ 04 02 _6 .3 V6 KC 73 1 U_ 04 02 _6 .3 V6 K1 2

C 50 1 U_ 04 02 _6 .3 V6 KC 50 1 U_ 04 02 _6 .3 V6 K1 2

T56 @T56 @

T53 @T53 @

C 67 1 U_ 04 02 _6 .3 V6 KC 67 1 U_ 04 02 _6 .3 V6 K1 2

RC1 29 0_0 402_ 5%@RC1 29 0_0 402_ 5%@1 2

C 62 1 U_ 04 02 _6 .3 V6 KC 62 1 U_ 04 02 _6 .3 V6 K1 2

R 26 5 0 _0 40 2_ 5%

R 26 5 0 _0 40 2_ 5%

1 2

C 5 4

1 U_

0 4 0 2_

6 . 3 V 6 K

C 5 4

1 U_

0 4 0 2_

6 . 3 V 6 K

1

2

R2670_0805_5%R2670_0805_5%

1 2

C 88 1 U_ 04 02 _6 .3 V6 K

C 88 1 U_ 04 02 _6 .3 V6 K

1 2

C43

22U_0603_6.3V6M

ESD@

C43

22U_0603_6.3V6M

ESD@

1 2

C 77 0 .1 U_ 0 40 2 _1 0V 7KC 77 0 .1 U_ 0 40 2 _1 0V 7K1 2

AXALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

THERMALSENSOR

HASWELL_MCP_E

mPHY

OPI

CORE

USB2

LPTLPPOWER

USB3

SDIO/PLSS

SUSOSCILLATOR

RTC

SPI

Rev1p213OF19

UC1M

AXALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

THERMALSENSOR

HASWELL_MCP_E

mPHY

OPI

CORE

USB2

LPTLPPOWER

USB3

SDIO/PLSS

SUSOSCILLATOR

RTC

SPI

Rev1p213OF19

UC1M

VCCHSIOK9

VCCHSIOM9

VCC1_05N8

VCC1_05P9

RSVDY20

DCPSUS2 AH13

VCCAPLLW21

DCPSUS3J13

VCCSUS3_3 AC9

VCCSUS3_3 AA9

VCCUSB3PLLB18

VCCSATA3PLLB11

VCCDSW3_3 AH10

VCCSDIOU8

VCCSDIO

T9

VCC3_3K14

VCC3_3K16

VCCASW AG13VCCASW AG14

VCCSPIY8

DCPRTC AE7VCCRTC AG10VCCSUS3_3 AH11

VCCCLKJ18

VCCACLKPLL

A20 VCCCLKK19

VCCCLKJ17

RSVDM20

VCCCLKT21 VCCCLKR21

VCCSUS3_3 AE20

VCCSUS3_3 AE21

VCCAPLL AA21

VCCASW AG8VCCASW AF9VCCASW AE9

VCC1_05 AE8VCC1_05H15VCC1_05H11VCC1_05J11

VCC3_3W9 VCC3_3V8

DCPSUS4 AB8

RSVD AC20

VCC1_05 AG16

VCC1_05 AG17

RSVDV21

RSVDK18

VCCHSIOL10

VCC1_05 AF22

DCPSUSBYP AG19

DCPSUSBYP AG20

DCPSUS1 AD10

DCPSUS1 AD8

VCCTS1_5J15

VCCHDA AH14

C 5 5

0 . 1 U_ 0 4

0 2_

1 0 V 7 K

C 5 5

0 . 1 U_ 0 4

0 2_

1 0 V 7 K

1

2

C 84 1 00 U_ 1 20 6 _6 .3 V6 MC 84 1 00 U_ 1 20 6 _6 .3 V6 M1 2

C 76 1 U_ 04 02 _6 .3 V6 KC 76 1 U_ 04 02 _6 .3 V6 K1 2

C 78 2 2U _0 6 03 _ 6. 3V 6MC 78 2 2U _0 6 03 _ 6. 3V 6M1 2

C 83 1 U_ 04 02 _6 .3 V6 KC 83 1 U_ 04 02 _6 .3 V6 K1 2

C 81 0 .1 U_ 0 40 2 _1 0V 7K@

C 81 0 .1 U_ 0 40 2 _1 0V 7K@

1 2



1 2

C641U_0402_6.3V6KC641U_0402_6.3V6K1 2

C 70 1 00 U_ 12 06 _6 .3 V6 M@C 70 1 00 U_ 12 06 _6 .3 V6 M@1 2

T55 @T55 @

5 4 3 2 1


http://slidepdf.com/reader/full/compal-la-9981p-r02-schematics 15/565 4 3 2 1

D D

C C

B B

A A

CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU

VSSSENSE <13,42>

Title


Date: Sheet of




LA-9981P 0.2



MCP(14,15,16/19) VSS Title


Date: Sheet of




LA-9981P 0.2



MCP(14,15,16/19) VSS Title


Date: Sheet of




LA-9981P 0.2



MCP(14,15,16/19) VSS

HASWELL_MCP_E

Rev1p214 OF 19

UC1N HASWELL_MCP_E

Rev1p214 OF 19

UC1N

VSS AH34

VSS AH36

VSS AJ39

VSS AJ41

VSS AJ35

VSS AJ47

VSS AJ54

VSS AF15

VSS AF18

VSS AP20VSS AP17

VSS AN7VSS AN63VSS AN60VSS AN52VSS AN51



VSS AN17VSS AM52VSS AM31VSS AM23VSS AM17

VSS AL61VSS AL60VSS

AL57VSS AL54VSS AL52

VSS AL46VSS AL45VSS AL40VSS AL39VSS AL36VSS AL33VSS AL31VSS AL29VSS AL26VSS AL23VSS AL22VSS AL20VSS AL17VSS AL13VSS AL10VSS AK52VSS AK3VSS AK23VSS AJ63VSS AJ60VSS AJ58VSS AJ56

VSS AJ52VSS AJ50

VSS AJ45VSS AJ43

VSS AJ29 VSS AJ27 VSS AJ25 VSS AJ23 VSS AJ14 VSS AJ13 VSS AH57 VSS AH55 VSS AH53

VSS AH42 VSS AH40

VSS AH32 VSS AH30 VSS AH28 VSS AH24 VSS AH22 VSS AH20 VSS AH19 VSS AH17 VSS AG63 VSS AG62 VSS AG61 VSS AG60 VSS

AG23 VSS AG21 VSS AG11 VSS AG1

VSS AF17

VSS AF14 VSS AF12 VSS AF11 VSS AE58 VSS AE5 VSS

AE10 VSS AD63 VSS AD3 VSS

AD21 VSS AC61 VSS AB7 VSS

AB22 VSS AB20 VSS AB10 VSS AA58 VSS AA1 VSS A56 VSS A52 VSS A48 VSS A44 VSS A40 VSS A36 VSS A32

VSS A24 VSS A18 VSS A14 VSS A11

VSS A28

VSS AL51

VSS AM1

VSS AN23

VSS AN40

VSS AN49

VSS AP10

VSS AH38

VSS AH51 VSS AH49 VSS AH44

HASWELL_MCP_E

Rev1p216 OF 19

UC1P HASWELL_MCP_E

Rev1p216 OF 19

UC1P

VSSD49

VSSV3

VSSV7

VSSW20

VSSW22

VSS_SENSEE62VSSV23VSS

AH46VSSV58

VSSJ10VSS

D33

VSSL7

VSSH57

VSSD41

VSSD42

VSSH13 VSSG8

VSSG5 VSSG3

VSSG18 VSSF61 VSS

F58 VSSF54

VSSF46

VSSF26 VSSF20

VSSE11 VSSD8 VSS

D62

VSSD57 VSSD55 VSSD54 VSSD53 VSSD51 VSSD50 VSSD5

VSSD47 VSSD46 VSSD45 VSSD43

VSSD34

VSSD35

VSSD37

VSSD38

VSSD39

VSSG6

VSSG22

VSSF30

VSSE17

VSSF34

VSSF42

VSS AH16

VSSF50

VSSF38

VSSH17

VSSJ22

VSSJ59

VSSJ63

VSSK1

VSSK12

VSSL13

VSSL15

VSSL17

VSSL18

VSSL20

VSSL58

VSSL61

VSSM22

VSSN10

VSSN3

VSSP59

VSSP63

VSSR10

VSSR8VSSR22

VSST1

VSST58

VSSU20

VSSU61VSSU22

VSSU9

VSSV10

VSS

Y10

VSSY59

VSSY63

VSSD59

HASWELL_MCP_E

Rev1p215 OF 19

UC1O HASWELL_MCP_E

Rev1p215 OF 19

UC1O

VSS AU28

VSSC14VSSC11

VSS AW60

VSS AW40

VSS AW16VSS AV8VSS AV59

VSS AP22

VSS AV34

VSSD31VSSD30VSSD29

VSSD21VSSD2VSSD18VSSD14VSSD12VSSC57VSSC39VSSC38VSSC27VSSC25VSSC20VSSC18

VSSB60VSSB56VSSB52VSSB48VSSB44VSSB40VSSB4VSSB36VSS

B32VSSB28VSSB26VSSB24VSSB20VSS

AY6VSS AY59VSS AY57VSS AY53VSS AY51VSS AY4VSS AY33VSS AY30VSS AY26VSS AY24VSS AY22VSS AY18VSS AY16VSS AY11

VSS AW59VSS AW51VSS AW50VSS AW47VSS AW44VSS AW42

VSS AW4VSS AW37VSS AW35VSS AW33VSS AW24

VSS AV51 VSS AV49 VSS AV46 VSS AV43 VSS AV41 VSS AV39 VSS AV36

VSS AV14 VSS AU59 VSS AU57

VSS AU53 VSS AU51

VSS AU30

VSS AU26 VSS AU24 VSS AU22 VSS AU20 VSS AU18 VSS AU16 VSS

AU1 VSS AT63 VSS AT62 VSS AT61 VSS AT49 VSS AT46 VSS AT43 VSS AT42 VSS AT40 VSS AT37 VSS AT35 VSS AT13 VSS AR52 VSS AR5 VSS

AR49 VSS AR43 VSS AR39 VSS AR33 VSS AR31 VSS AR23 VSS AR17 VSS AR15

VSS AP57 VSS AP54 VSS AP52 VSS AP48 VSS AP39

VSS AP31

VSS AP29 VSS AP26 VSS AP23

VSS AP38

VSS AP3

VSS AV55

VSSD23

VSSD25

VSSD27VSSD26

VSS AU55

VSS AU33

VSS AR11

VSS AV20

VSS AV28

VSS AV33

VSS AV24

VSS AV16

RC163

100_0402_1%

X@RC163

100_0402_1%

X@

1

2



5 4 3 2 1



D D

C C

B B

A A

60mils

60mils

40mils

Close to 11 pin Close to 43 pin

30mil30mil

Close to 18 pin Close to 22 pinClose to 5 pin

RTD2136S : SA00004NW10RTD2136R : SA000067100

EEPROMEEPROM

ROMLESSROMLESS

Close to 15 pin

AUX termination

Vendor advise reserve it

For eDP co-layout

Close to UX4

Close to UX4

Across to UX4.19 & UX4.21

Close to UX2

for layout smoothly,

will swap NET on cable

LVDS_A0+

LVDS_BCLK+LVDS_BCLK-

LVDS_B0+

LVDS_B0-

LVDS_B2+

LVDS_ACLK+LVDS_ACLK-

LVDS_A0-

LVDS_A1+LVDS_A1-

LVDS_A2+

LVDS_A2-

LVDS_B1+LVDS_B1-

LVDS_B2-

EC_SMB_CK2

EC_SMB_DA2CSDA

CSCL

EDP_CPU_LANE_P1EDP_CPU_LANE_N1

EDP_CPU_LANE_P0

EDP_CPU_LANE_N0

EDP_CPU_AUX

EDP_CPU_AUX#

CPU_EDP_P0_C

CPU_EDP_N0_C

CPU_EDP_P1_CCPU_EDP_N1_C

CPU_EDP_AUX_C

CPU_EDP_AUX#_C

EDP_BIA_PWM


MIIC_SCL

CSDA

+SWR_V12

TL_BKOFF#_R

EDP_CPU_HPD

EDID_CLKEDID_DATA

TL_INVT_PWM

+AVCC33

+DVCC33


MIIC _SDA

+SW_LX

CSCL

TL_ENVDD

+SWR_V12

+AVCC33 +DVCC33

MIIC_SCLMIIC_SDA

EDP_CPU_AUX#EDP_CPU_AUX

EDP_CPU_HPD

EDP_BIA_PWM

CSCL

EDID_DATAEDID_CLK

CSDA

TL_BKOFF#_R

CPU_EDP_N0_C

CPU_EDP_P1_C

EDP_N0 LVDS_B1+

EDP_P1 LVDS_B2-

CPU _EDP_P0_C EDP_P0 LVDS_B1-

CPU_EDP_N1_C EDP_N1 LVDS_B2+

CPU_EDP_AUX_C

CPU_EDP_AUX#_C

LVDS_B0+

LVDS_B0-

EDP_AUX

EDP_AUX#

EDP_HPD_PANEL

EDP_BIA_PWM TL_INVT_PWM

TL_ENVDD

EDP_CPU_HPD

TL_BKOFF#BKOFF#

ENVDD_PCH

EDP_CPU_HPD<10>

EC_SMB_DA2 <30,49,9>

LVDS_ACLK+ <31>

LVDS_ACLK- <31>

LVDS_A0- <31>LVDS_A0+ <31>

LVDS_A1- <31>

LVDS_A1+ <31>

LVDS_A2- <31>LVDS_A2+ <31>

LVDS_B2- <31>LVDS_B2+ <31>

LVDS_BCLK- <31>

LVDS_B0- <31>LVDS_B0+ <31>

LVDS_BCLK+ <31>

LVDS_B1- <31>

LVDS_B1+ <31>

TL_INVT_PWM <31>TL_ENVDD <31>

EDP_CPU_LANE_P0<6>EDP_CPU_LANE_N0<6>

EDP_CPU_LANE_P1<6>

EDP_CPU_LANE_N1<6>

EDP_CPU_AUX<6>EDP_CPU_AUX#<6>

EDID_CLK <31>EDID_DATA <31>

EC_SMB_CK2 <30,49,9>

EDP_BIA_PWM<10,6>


BKOFF#<30>TL_BKOFF# <31>

EDP_HPD_PANEL <31>

ENVDD_PCH<10,30>

+3VS_RT

+3VS_RT

+DVCC33

+3VS_RT+3VS +SWR_V12

+3VS_RT+3VS_RT

+3VS_RT

+DVCC33

+3VS_RT

Title


Date: Sheet of




LA-9981P 0.2



eDP to LVDS converter Title


Date: Sheet of




LA-9981P 0.2



eDP to LVDS converter Title


Date: Sheet of




LA-9981P 0.2



eDP to LVDS converter

RX33100K_0402_5%

LVDS@RX33100K_0402_5%

LVDS@

1

2

C X 4 5

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

L V D S @

C X 4 5

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

L V D S @

1

2

C X 3 6

2 2 U _ 0 8 0 5 _ 6 . 3 V 6 M

L V D S @

C X 3 6

2 2 U _ 0 8 0 5 _ 6 . 3 V 6 M

L V D S @

1

2

RX3 9 0_04 02_5 %eDP@RX3 9 0_04 02_5 %eDP@1 2

RX4 5 0_04 02_5 %eDP@RX4 5 0_04 02_5 %eDP@1 2

RX51 0_ 0402 _5%eDP@RX51 0_ 0402 _5%eDP@1 2

RX4 2 0_04 02_ 5%eDP@RX4 2 0_04 02_ 5%eDP@1 2 G

S D

QX6B

DMN66D0LDW-7_SOT363-6

LVDS@ G

S D

QX6B


LVDS@

61

2

RX5 12K_0402_1%

LVDS@

RX5 12K_0402_1%

LVDS@

1 2

C X4 3 0 . 1U _0 40 2 _1 0 V7 KC X4 3 0 . 1U _0 40 2 _1 0 V7 K1 2

C X 4 7

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

C X 4 7

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

1

2

RP562.2K_8P4R_5%

[email protected]_8P4R_5%

LVDS@

1 82 73 64 5

C X 3 5

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

L V D S @

C X 3 5

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

L V D S @

1

2

LX7FBMA-L11-201209-221LMA30T_0805

LVDS@ LX7FBMA-L11-201209-221LMA30T_0805

LVDS@ 12

C X3 9 0 . 1U _0 40 2 _1 0 V7 KC X3 9 0 . 1U _0 40 2 _1 0 V7 K1 2

C X 4 8

2 2 U _ 0 8 0 5 _ 6 . 3 V 6 M

L V D S @

C X 4 8

2 2 U _ 0 8 0 5 _ 6 . 3 V 6 M

L V D S @

1

2

RX4 4 0_04 02_ 5%eDP@RX4 4 0_04 02_ 5%eDP@1 2

C X 3 3

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

C X 3 3

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

1

2

UX2MC74VHC1G08DFT2G_SC70-5

LVDS@UX2MC74VHC1G08DFT2G_SC70-5

LVDS@

IN11

IN22 OUT

4 V C C

5

G N D

3

C X 3 4

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

C X 3 4

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

1

2

RX31 0_0402_5%@RX31 0_0402_5%@1 2

RX4 7 0_04 02_5 %eDP@RX4 7 0_04 02_5 %eDP@1 2

RX1684.7K_0402_5%

@

RX1684.7K_0402_5%

@ 1

2

C X 3 1

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

C X 3 1

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

1

2

RX3 7 0_04 02_5 %eDP@RX3 7 0_04 02_5 %eDP@1 2

RX25

100K_0402_5%

@

RX25

100K_0402_5%

@

1

2

RX4 6 0_04 02_ 5%eDP@RX4 6 0_04 02_ 5%eDP@1 2

LX94.7UH_PG031B-4R7MS_1.1A_20%

LVDS@ LX94.7UH_PG031B-4R7MS_1.1A_20%

LVDS@ 1 2

CX100.1U_0402_10V7K

[email protected]_0402_10V7K

LVDS@

1 2

RX1694.7K_0402_5%

LVDS@

RX1694.7K_0402_5%

LVDS@

1

2

RTD2136R

PWR

DP

L V D S

G N D

O THER S

UX4

RTD2136R-CG_QFN48_6x6

LVDS@

RTD2136R

PWR

DP

L V D S

G N D

O THER S

UX4

RTD2136R-CG_QFN48_6x6

LVDS@

TXOC-36TXOC+35

TXO3-34TXO3+33

TXO2-38TXO2+37

TXO1-40TXO1+39

TXO0-42TXO0+41

TXEC-26TXEC+25

TXE0-32TXE0+31

TXE1-30TXE1+29

TXE2-28TXE2+27

TXE3-24TXE3+23

DP_V335

LANE0P7

LANE0N8

LANE1P9

LANE1N10

AUX-CH_P4

AUX-CH_N3

DP_HPD1

DP_GND6

PWMIN

21

PANEL_VCC20

PWMOUT19

BL_EN44

CIICSCL113

CIICSDA114

MODE_CFG148

MODE_CFG047

MIICSCL1 46

MIICSDA145

DP_V1211

VCCK43

SWR_VCCK15

GND16

SWR_LX17

SWR_VDD18

PVCC22

TESTMODE2

DP_REXT12

PAD49

LX8FBMA-L11-201209-221LMA30T_0805

LVDS@ LX8FBMA-L11-201209-221LMA30T_0805

LVDS@ 12

RX35100K_0402_5%

@ RX35100K_0402_5%

@

1

2

RX30

100K_0402_5%

@

RX30

100K_0402_5%

@

1

2

S

G

D

QX6ADMN66D0LDW-7_SOT363-6

LVDS@

S

G

D

QX6ADMN66D0LDW-7_SOT363-6

LVDS@

5

34

RX6 0_0402_5%@RX6 0_0402_5%@1 2

C X3 8 0 . 1U _0 40 2 _1 0 V7 KC X3 8 0 . 1U _0 40 2 _1 0 V7 K1 2

RX50 0_ 0402 _5%eDP@RX50 0_ 0402 _5%eDP@1 2

C X4 6 0 . 1U _0 40 2 _1 0 V7 KC X4 6 0 . 1U _0 40 2 _1 0 V7 K1 2

RX4 0 0_04 02_ 5%eDP@RX4 0 0_04 02_ 5%eDP@1 2

RX36

100K_0402_5%

@ RX36

100K_0402_5%

@

1

2

RX4 3 0_04 02_5 %eDP@RX4 3 0_04 02_5 %eDP@1 2

RX4 1 0_04 02_5 %eDP@RX4 1 0_04 02_5 %eDP@1 2

C X 4 0

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

C X 4 0

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

1

2 RX40_0805_1%

@

RX40_0805_1%

@

1 2

RX1714.7K_0402_5%

@

RX1714.7K_0402_5%

@ 1

2

RX49 0_ 0402 _5%eDP@RX49 0_ 0402 _5%eDP@1 2

C X4 2 0 . 1U _0 40 2 _1 0 V7 KC X4 2 0 . 1U _0 40 2 _1 0 V7 K1 2

RX4 8 0_04 02_ 5%eDP@RX4 8 0_04 02_ 5%eDP@1 2

RX3 8 0_04 02_ 5%eDP@RX3 8 0_04 02_ 5%eDP@1 2

RX52 0_ 0402 _5%eDP@RX52 0_ 0402 _5%eDP@1 2

RP57

2.2K_8P4R_5%

@RP57

2.2K_8P4R_5%

@

1 82 73 64 5

C X 4 1

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

C X 4 1

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

1

2

C X4 4 0 . 1U _0 40 2 _1 0 V7 KC X4 4 0 . 1U _0 40 2 _1 0 V7 K1 2

C X 3 2

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

C X 3 2

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

1

2

C X 3 7

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

C X 3 7

0 .1 U _ 0 4 0 2 _1 0 V 7 K

L V D S @

1

2

RX1704.7K_0402_5%

LVDS@

RX1704.7K_0402_5%

LVDS@

1

2

5 4 3 2 1



D D

C C

B B

A A

W=40milsPlace close to JHDMI1

TMDS_TXCP

TMDS_L_TX0P

TMDS_L_TX1N

TMDS_L_TX0N

TMDS_L_TX1P

TMDS_L_TXCP

TMDS_TXCN TMDS_L_TXCN

TMDS_TX0N

TMDS_TX1P

TMDS_TX1N

TMDS_TX0P

CPU_DPB_CTRLDAT_RCPU_DPB_CTRLCLK_R

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TX0P

TMDS_L_TX2N

TMDS_L_TX2P

TMDS_L_TX0N

TMDS _L_TXCN

TMDS_L_TXCP

HDMI_HPLUG

TMDS_TX1N

TMDS_TX2P

TMDS_TX2N

TMDS_TX1P

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TX0P

TMDS_L_TX2N

TMDS_L_TX2P

TMDS_L_TX0N

TMDS_L_TXCN

TMDS_L_TXCP

TMDS_TX2N

TMDS_TX2P TMDS_L_TX2P

TMDS_L_TX2N

CPU_DPB_CTRLCLK_R

CPU_DPB_CTRLDAT_R

TMDS_TXCNTMDS_TXCP

TMDS_TX0PTMDS_TX0N

HDMI_HPLUG

CPU_DPB_CTRLCLK<10>

CPU_DPB_CTRLDAT<10>

DPB_HPD<10>

DDI1_LANE_N3<6>DDI1_LANE_P3<6>

DDI1_LANE_N2<6>DDI1_LANE_P2<6>

DDI1_LANE_P1<6>

DDI1_LANE_N1<6>

DDI1_LANE_P0<6>

DDI1_LANE_N0<6>

+VDISPLAY_VCC

+3VS

+3VS

+3VS

+5VS

+3VS

+5VS

Title


Date: Sheet of




LA-9981P 0.2

HDMI



Title


Date: Sheet of




LA-9981P 0.2

HDMI



Title


Date: Sheet of




LA-9981P 0.2

HDMI



RX16

2.2K_0402_5%

RX16

2.2K_0402_5%

1

2

RX13100K_0402_5%

RX13100K_0402_5%

1

2

C X2 6 3 .3 P_ 0 40 2_ 5 0V 8C@EMI@ C X2 6 3 .3 P_ 0 40 2_ 5 0V 8C@EMI@ 1 2

C X1 9 0 .1 U_ 0 40 2_ 1 0V 7KC X1 9 0 .1 U_ 0 40 2_ 1 0V 7K12


C X1 5 0 .1 U_ 0 40 2_ 1 0V 7KC X1 5 0 .1 U_ 0 40 2_ 1 0V 7K12

JHDMI

LOTES_ABA-HDM-022-K01CONN@

JHDMI

LOTES_ABA-HDM-022-K01CONN@

D2+1 D2_shield2 D2-3 D1+4 D1_shield5 D1-6 D0+7 D0_shield8 D0-9 CK+

10 CK_shield11 CK-12 CEC13 Reserved14 SCL15 SDA16 DDC/CEC_GND17 +5V18 HP_DET19

GND20

GND21

GND22

GND23

E

B

C

QX5MMBT3904_NL_SOT23-3

E

B

C

QX5MMBT3904_NL_SOT23-3

2

3

1

C X1 7 0 .1 U_ 0 40 2_ 1 0V 7KC X1 7 0 .1 U_ 0 40 2_ 1 0V 7K12

C X1 3 0 .1 U_ 0 40 2_ 1 0V 7KC X1 3 0 .1 U_ 0 40 2_ 1 0V 7K12


C X1 2 0 .1 U_ 0 40 2_ 1 0V 7KC X1 2 0 .1 U_ 0 40 2_ 1 0V 7K12


S

G

D

QX4A


S

G

D

QX4A


5

34

C X1 4 0 .1 U_ 0 40 2_ 1 0V 7KC X1 4 0 .1 U_ 0 40 2_ 1 0V 7K12

FX1

1.5A_6V_1206L150PR~D

FX1

1.5A_6V_1206L150PR~D

12

CX22

1 0 U_

0 6 0 3_

6 . 3 V 6 M

CX22

1 0 U_

0 6 0 3_

6 . 3 V 6 M 1

2LX2

WCM-2012HS-900T_4P

EMI@LX2

WCM-2012HS-900T_4P

EMI@

11

22

33

44

RX1210K_0402_5%RX1210K_0402_5%

1

2

LX4

WCM-2012HS-900T_4P

EMI@LX4

WCM-2012HS-900T_4P

EMI@

11

22

33

44

RX34

20K_0402_5%

@RX34

20K_0402_5%

@

1

2


LX3

WCM-2012HS-900T_4P

EMI@LX3

WCM-2012HS-900T_4P

EMI@

11

22

33

44


CX20220P_0402_50V8JCX20220P_0402_50V8J

1

2

C X1 8 0 .1 U_ 0 40 2_ 1 0V 7KC X1 8 0 .1 U_ 0 40 2_ 1 0V 7K12

G

D

S

QX3

2N7002K_SOT23-3G

D

S

QX3

2N7002K_SOT23-3

2

1

3


RX14

100K_0402_5%

RX14

100K_0402_5%

1

2

RX15150K_0402_5%RX15150K_0402_5%

1 2

RP58

680_8P4R_5%

RP58

680_8P4R_5%

1

8

2

7

3

6

4

5

RP59

680_8P4R_5%

RP59

680_8P4R_5%

1

8

2

7

3

6

4

5

C X 2 1

0 . 1 U_

0 4 0 2_

1 6 V 7 K C

X 2 1

0 . 1 U_

0 4 0 2_

1 6 V 7 K 1

2


LX5

WCM-2012HS-900T_4P

EMI@LX5

WCM-2012HS-900T_4P

EMI@

11

22

33

44

C X1 6 0 .1 U_ 0 40 2_ 1 0V 7KC X1 6 0 .1 U_ 0 40 2_ 1 0V 7K12

RX17

2.2K_0402_5%

RX17

2.2K_0402_5%

1

2

G

S D

QX4B

DMN66D0LDW-7_SOT363-6 G

S D

QX4B


61

2

5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

1.5A

Reserve 10K pull LAN_IO

W=20mils

These caps close to Pin 8,30

For 8106E pop capacitor close to pin 8,30

These caps close to Pin 23,32

For 8106E pop the capacitor close pin 23,32

Place close to TCT pin

+LAN_IO rising time : >1ms and <100ms

W=40mils

W=40mils

W=40mils

CL30, CL31 close to UL1 Pin 17, 18

For GCLK

Change CPN to SP050007J00 only

Need CIS symbol

XTLOXTLI

ISOLATEB

PCIE_WAKE#

PCIE_WAKE# XTLO

XTLI

ISOLATEB

LAN_CLKREQ#

WOL_EN

MCT1

MCT0

MCT1

MDO1+MDO1-

MDI0-MDI0+

MDO0-MDO0+

MDI1+MDI1-

MCT0

MDO0-

MDO1+

MDO1-

MDO0+

PCIE_PTX_LANRX_P3PCIE_PTX_LANRX_N3

MDI1-

MDI1+MDI0-

MDI0+PCIE _PRX_LANTX_P3_CPCIE_PRX_LANTX_N3_C

WOL_EN

XTLIPLT_RST#<10,26,30,48,6>

PCIE_WAKE#<10,30>

PCIE_PTX_LANRX_P3<12>PCIE_PTX_LANRX_N3<12>

CLK_PCIE_LAN <9>CLK_PCIE_LAN# <9>

LAN_CLKREQ# <9>

PCIE_PRX_LANTX_P3<12>PCIE_PRX_LANTX_N3<12>

WOL_EN<30>

XTLI<29>

+LAN_VDD

+LAN_VDD

+LAN_IO

+LAN_VDD

+LAN_IO

+3VS

+LAN_IO

+LAN_IO

+3VALW

Title


Date: Sheet of


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFOR MATION. THIS SHEET MAY NO T BE TRANSFE RED FROM TH E CUSTODY OF THE COM PETENT DIVISIO N OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


LA-9981P 0.2



LAN RTL8106E Title


Date: Sheet of





LA-9981P 0.2



LAN RTL8106E Title


Date: Sheet of





LA-9981P 0.2



LAN RTL8106E

RL331K_0402_5%RL331K_0402_5%

1

2

C L3 1 0 .1 U_ 0 40 2 _1 0 V7 KC L3 1 0 .1 U_ 0 40 2 _1 0 V7 K1 2

R L3 1 2 .4 9K _0 40 2_ 1%R L3 1 2 .4 9K _0 40 2_ 1%12

CL15

0 . 1 U_

0 4 0 2_

1 0 V 7 K

CL15

0 . 1 U_

0 4 0 2_

1 0 V 7 K

1

2

YL2

25MHZ_10PF_7V25000014

XTAL@YL2

25MHZ_10PF_7V25000014

XTAL@

OSC

1

OSC3

GND

2

GND4

TL1

X'FORM_ NS0014

TL1

X'FORM_ NS0014

RD+1

RD-2

CT3

CT6

TD+7

TD-8

TX-9TX+10CT11

CT14RX-15RX+16

NC4

NC5 NC

13

NC12

CL36

10P_0402_50V8JXTAL@

CL36

10P_0402_50V8JXTAL@

1 2

CL37

10P_0402_50V8JXTAL@

CL37

10P_0402_50V8JXTAL@

1 2

CL22

0 . 1 U_

0 4 0 2_

1 0 V

7 K

CL22

0 . 1 U_

0 4 0 2_

1 0 V

7 K

1

2

CL34

0 . 1 U_

0 4 0 2_

1 0 V 7 K

CL34

0 . 1 U_

0 4 0 2_

1 0 V 7 K

1

2

T94 PAD~D@ T94 PAD~D@

RL27100K_0402_5%RL27100K_0402_5%

1

2

APL3512ABI-TRG_SOT23-5

UL2

APL3512ABI-TRG_SOT23-5

UL2

SS4

VIN5

GND2

EN3

VOUT1

RL3410K_0402_5%RL3410K_0402_5%

1 2

RL1975_0603_5%RL1975_0603_5%

1 2

CL380.1U_0603_25V7K

@CL380.1U_0603_25V7K

@1

2

CL20

0 . 1 U_

0 4 0 2_

1 0 V

7 K

CL20

0 . 1 U_

0 4 0 2_

1 0 V

7 K

1

2

RL2075_0603_5%RL2075_0603_5%

1 2

CL41

0.01U_0402_16V7K

CL41

0.01U_0402_16V7K1

2


RL3515K_0402_5%RL3515K_0402_5%

1

2

JLAN

SANTA_130456-311CONN@

JLAN

SANTA_130456-311CONN@

PR1-2

PR1+1

PR2+3

PR3+4

PR3-5

PR2-6

PR4+7

PR4-8

SHLD210

SHLD19

CL19

0 . 1 U_

0 4 0 2_

1 0 V 7 K

CL19

0 . 1 U_

0 4 0 2_

1 0 V 7 K

1

2

T95 PAD~D@ T95 PAD~D@

C L3 0 0 .1 U_ 0 40 2 _1 0 V7 KC L3 0 0 .1 U_ 0 40 2 _1 0 V7 K1 2

UL1

RTL8106E-CG_QFN32_4X4

UL1

RTL8106E-CG_QFN32_4X4

MDIP01

MDIP14

MDIN02

MDIN15

AVDD108

AVDD1030

AVDD3332

DVDD3323

REFCLK_P15

REFCLK_N16

CLKREQB12

CKXTAL128

CKXTAL229

LED027

LED1

25

RSET31

GND33

HSOP17

HSON18

HSIP13

HSIN14

PERSTB19

ISOLATEB20

LANWAKEB21

GPO26

NC3

NC6

NC

7

NC9

NC10

NC11

NC22

NC24

RL38 10K_0402_5%

@

RL38 10K_0402_5%

@

1 2

CL35

1 U_

0 4 0 2_

6 . 3 V 6 K

CL35

1 U_

0 4 0 2_

6 . 3 V 6 K

1

2

CL391U_0402_6.3V6K

CL391U_0402_6.3V6K

12

CL3310P_1206_2KV8J

EMI@CL3310P_1206_2KV8J

EMI@1

2

CL26

0 . 1 U_

0 4 0 2_

1 0 V

7 K

CL26

0 . 1 U_

0 4 0 2_

1 0 V

7 K

1

2

RL37 10K_0402_5%@

RL37 10K_0402_5%@

1 2

JP3

2MM

@JP3

2MM

@2 1

5 4 3 2 1

Reserve for HDA issue



D D

C C

B B

A A

CA53,CA55 change Value

from10U_0603_6.3V6M~D to

4.7U_0603_6.3V6K

GNDA GND

40mil

40mil

CA71, CA51 place close to Pin 26

CA57,CA58 closeto UA1 pin1

Place on the moat between GND & GNDA.

iPhone and Nokia type Combo Jack

Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R-

Speaker 4 ohm : 40mil

Speaker 8 ohm : 20mil

Reserve for cancel Delay circutis

RA51, RA33 place close to UA1

JACK_PLUG Delay circutis

PC Beep

MCU Beep

EC Beep

close to Codec

Close to UA1

Pin11,13,14,16

SM01000BV00need CIS symbol

AUD_HP_OUT_L_CN

AUD_HP_OUT_R_CN

JACK_PLUG#

JACK_SENSE#

JACK_PLUG#

RING2_R

MIC_IN_R

JACK_PLUG#

MIC_IN

RING2

RING2

MIC1-L

EC_MUTE#

MIC_CLK_C

MIC_CLK

Line1-VREFO-R

Line1-VREFO-L

MIC_IN

AUD_HP_OUT_R_CN

HPOUT-L AUD_HP_OUT_L_CN

MIC_IN_R

RING2_R

HPOUT-R

+MIC2-VREFO

JACK_SENSE#

LINE1-L

LINE1-R

LINE1-R

LINE1-L

Line-IN-R

Line-IN-L

PC_BEEP

PC_BEEP

INT-SPK-R-

INT-SPK-R+

INT-SPK-L-

INT-SPK-L+

HPOUT-LHPOUT-R

Line1-VREFO-LLine1-VREFO-R

RING2

MIC_IN

PCH _AZ_CODEC_RST#

SPK_R1-_CONN

SPK_L1-_CONNSPK_R2+_CONN

SPK_L2+_CONN

MIC_IN

JACK_SENSE#

PCH_AZ_CODEC_BITCLK

INT-SPK-L-

INT-SPK-L+

INT-SPK-R-

INT-SPK-R+

Line-IN-L

Line-IN-R

MIC_CLK_C

EC_MUTE# <30>

BEEP#<30>

MIC_DATA <31>

MIC_CLK <31>

PCH_AZ_CODEC_SDOUT<8>PCH_AZ_CODEC_BITCLK<8>

PCH_AZ_CODEC_SYNC<8>PCH_AZ_CODEC_RST#<8>

PCH_AZ_CODEC_SDIN0<8>

HDA_SPKR<11>

+3VS +3VS

+MIC2-VREFO

+MIC2-VREFO

+5V_PVDD+5V_PVDD +5VA

+3VS

+3VS

+3VALW

+3VS

+CODEC_AVDD2

+3VS +CODEC_AVDD2+1.5VS

+5VA

+5VS+5V_PVDD

+5VS

Title


Date: Sheet of




LA-9981P 0.2



Audio Codec ALC3223Title


Date: Sheet of




LA-9981P 0.2



Audio Codec ALC3223Title


Date: Sheet of




LA-9981P 0.2



Audio Codec ALC3223

L A7 F BM A- L1 0- 16 08 08 -8 00 LM T_ 2PEMI@

L A7 F BM A- L1 0- 16 08 08 -8 00 LM T_ 2PEMI@

12

LA4 0_0603_5%EMI@ LA4 0_0603_5%EMI@ 1 2

RA31 0_0603_1%@RA31 0_0603_1%@1 2

RV59

0_0603_1%@

RV59

0_0603_1%@

12

JSPK

E&T_3703-Q04N-11R

CONN@

JSPK

E&T_3703-Q04N-11R

CONN@

11

22

33

44 GND

5

GND6

LA3 0_0603_5%EMI@ LA3 0_0603_5%EMI@ 1 2

G

S

D

QA5BDMN66D0LDW-7_SOT363-6

@

G

S

D

QA5BDMN66D0LDW-7_SOT363-6

@

6

1

2

L A1 0 F BM A- L1 0 -1 6 08 0 8- 8 00 LM T_ 2 PEMI@

L A1 0 F BM A- L1 0 -1 6 08 0 8- 8 00 LM T_ 2 PEMI@

12

DA8

BAT54C-7-F_SOT23-3

DA8

BAT54C-7-F_SOT23-3

2

3

1

R A8 1 1 0K _0 40 2_ 5%@ R A8 1 1 0K _0 40 2_ 5%@ 12

CA2222P_0402_50V8J

@EMI@

CA2222P_0402_50V8J

@EMI@1

2

CA110U_0603_6.3V6M

@

CA110U_0603_6.3V6M

@

1

2

R2355

0_0402_5%

@EMI@R2355

0_0402_5%

@EMI@

1 2

S

G

D

QA6ADMN66D0LDW-7_SOT363-6 S

G

D

QA6ADMN66D0LDW-7_SOT363-6

5

3

4

RA2

100K_0402_5%

@

RA2

100K_0402_5%

@ 1

2

C A6 2 1 0 U_ 06 0 3_ 6 .3 V6 MC A6 2 1 0 U_ 06 0 3_ 6 .3 V6 M1 2

C A2 5 1 U_ 0 40 2 _6 .3 V6 KC A2 5 1 U_ 0 40 2 _6 .3 V6 K1 2

RA82 1K_0402_1%RA82 1K_0402_1%1 2CA68

4.7U_0603_6.3V6KCA68

4.7U_0603_6.3V6K1 2

RA1654.7K_0402_5%RA1654.7K_0402_5%

1

2

RA80 1K_0402_1%RA80 1K_0402_1%

1 2

RA29 0_0603_1%@RA29 0_0603_1%@1 2

CA210U_0603_6.3V6M

@

CA210U_0603_6.3V6M

@

1

2

LA5 0_0603_5%EMI@ LA5 0_0603_5%EMI@ 1 2

C A 5 6

0 .1 U _ 0 4 0 2 _1 6 V 7 K

C A 5 6

0 .1 U _ 0 4 0 2 _1 6 V 7 K

1

2

C A 5 3

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

C A 5 3

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

1

2

CA61

4.7U_0603_6.3V6K

CA61

4.7U_0603_6.3V6K

1

2

CA594.7U_0603_6.3V6K

CA594.7U_0603_6.3V6K

1

2

C A 5 8

0 .1 U _ 0 4 0 2 _1 6 V 7 K

C A 5 8

0 .1 U _ 0 4 0 2 _1 6 V 7 K

1

2

R A5 1 3 9. 2K_ 04 02 _1 %R A5 1 3 9. 2K_ 04 02 _1 %1 2

C A 2 9

1 0 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

C A 2 9

1 0 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

1

2

JHP

SINGA_2SJ3080-000111FCONN@

JHP

SINGA_2SJ3080-000111FCONN@

13

2

5

4

6

7

C A 5 4

0 .1 U _ 0 4 0 2 _1 6 V 7 K

C A 5 4

0 .1 U _ 0 4 0 2 _1 6 V 7 K

1

2

LA6 0_0603_5%EMI@ LA6 0_0603_5%EMI@ 1 2

RA9 0_0402_5%@RA9 0_0402_5%@1 2

D A 1 2

A Z 5 1 2 5 - 0 2 S .R 7 G _ S OT 2 3 - 3

E S D @

D A 1 2

A Z 5 1 2 5 - 0 2 S .R 7 G _ S OT 2 3 - 3

E S D @

2 3

1

RA4 0_0402_1%@RA4 0_0402_1%@1 2

CA65

0.1U_0402_16V7K

CA65

0.1U_0402_16V7K

1 2

C A 3 3

1 0 0 P _ 0 4 0 2 _ 5 0 V 8 J

E MI @

C A 3 3

1 0 0 P _ 0 4 0 2 _ 5 0 V 8 J

E MI @

1

2

RA310K_0402_5%

@

RA310K_0402_5%

@1 2

RA8 0_0402_5%RA8 0_0402_5%1 2

C A 5 1

0 .1 U _ 0 4 0 2 _1 6 V 7 K

C A 5 1

0 .1 U _ 0 4 0 2 _1 6 V 7 K

1

2

C A6 3 1 0 U_ 06 0 3_ 6 .3 V6 MC A6 3 1 0 U_ 06 0 3_ 6 .3 V6 M1 2

RA55

8.2_0402_1%

RA55

8.2_0402_1%1 2

CA600.1U_0402_16V7KCA600.1U_0402_16V7K

1

2

S

G

D


@

S

G

D


@5

3

4 C A 5 7

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

C A 5 7

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

1

2

L A9 F BM A- L1 0- 16 08 08 -8 00 LM T_ 2PEMI@

L A9 F BM A- L1 0- 16 08 08 -8 00 LM T_ 2PEMI@

12

RA1910K_0402_5%

@

RA1910K_0402_5%

@

1

2

RA56

8.2_0402_1%

RA56

8.2_0402_1%

1 2

C A2 3 2 .2 U_ 06 03 _6 .3 V6 KC A2 3 2 .2 U_ 06 03 _6 .3 V6 K1 2

C A 3 8

1 0 0 P _ 0 4 0 2 _ 5 0 V 8 J

E MI @

C A 3 8

1 0 0 P _ 0 4 0 2 _ 5 0 V 8 J

E MI @

1

2

C A 7 1

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

C A 7 1

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

1

2

RA130 2 2_0 402_ 5%RA130 2 2_0 402_ 5%1 2

CA74 10U_0603_6.3V6MCA74 10U_0603_6.3V6M1 2

C A6 9 1 00 P_ 0 40 2_ 5 0V 8J@ C A6 9 1 00 P_ 0 40 2_ 5 0V 8J@ 1 2

CA21

22P_0402_50V8J

@EMI@CA21

22P_0402_50V8J

@EMI@1

2

LA1

BLM15BB221SN1D_2P

EMI@LA1

BLM15BB221SN1D_2P

EMI@1 2

R A1 53 2 0K_ 04 02 _1 %R A1 53 2 0K_ 04 02 _1 %1 2

R A5 3 2 .2 K_ 04 02 _5 %R A5 3 2 .2 K_ 04 02 _5 %12

RA83

10K_0402_5%

RA83

10K_0402_5%

1

2

C A 3 1

1 0 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

C A 3 1

1 0 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

1

2

C A6 4 1 0 U_ 06 0 3_ 6 .3 V6 MC A6 4 1 0 U_ 06 0 3_ 6 .3 V6 M1 2

G

S

D

QA6B


G

S

D

QA6B

DMN66D0LDW-7_SOT363-6 6

1

2

R A1 10 9 2 .2 K_ 04 02 _5 %R A1 10 9 2 .2 K_ 04 02 _5 %12

C A 4 0

1 0 0 P _ 0 4 0 2 _ 5 0 V 8 J

E MI @

C A 4 0

1 0 0 P _ 0 4 0 2 _ 5 0 V 8 J

E MI @

1

2

R A7 1 0K _0 40 2_ 5%R A7 1 0K _0 40 2_ 5%1 2

L A8 F BM A- L1 0- 16 08 08 -8 00 LM T_ 2PEMI@

L A8 F BM A- L1 0- 16 08 08 -8 00 LM T_ 2PEMI@

12

C A 5 5

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

C A 5 5

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

1

2

RA30 0_0603_1%@RA30 0_0603_1%@1 2

RA79

1K_0402_1%

RA79

1K_0402_1%

1 2

D A 1 0

A Z 5 1 2 5 - 0 2 S .R 7 G _ S OT 2 3 - 3

E S D @

D A 1 0

A Z 5 1 2 5 - 0 2 S .R 7 G _ S OT 2 3 - 3

E S D @

2 3

1

RA32 0_0603_1%@RA32 0_0603_1%@1 2

RA1

100K_0402_5%

@

RA1

100K_0402_5%

@ 1

2

C A 3 9

1 0 0 P _ 0 4 0 2 _ 5 0 V 8 J

E MI @

C A 3 9

1 0 0 P _ 0 4 0 2 _ 5 0 V 8 J

E MI @

1

2

C A 3 0

1 0 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

C A 3 0

1 0 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

1

2

RA166

4.7K_0402_5%

RA166

4.7K_0402_5%

1

2

C A2 4 1 U_ 0 40 2 _6 .3 V6 KC A2 4 1 U_ 0 40 2 _6 .3 V6 K1 2

C A 3 2

1 0 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

C A 3 2

1 0 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

1

2

RV540_0603_1%@

RV540_0603_1%@

12

RA5

100K_0402_5%

RA5

100K_0402_5%

1

2

R A6 1 0K _0 40 2_ 5%

@

R A6 1 0K _0 40 2_ 5%

@1 2

RA84

10K_0402_5%

RA84

10K_0402_5%

1

2

UA1

ALC3223-CG_MQFN48_6X6~D

UA1

ALC3223-CG_MQFN48_6X6~D

AVSS125

AVDD126

LDO1-CAP27

VREF28

MIC2-VREFO29 MIC1-VREFO-R30 MIC1-VREFO-L31

HPOUT-L(PORT-I-L)32HPOUT-R(PORT-I-R)33

PVDD141

AVDD240

LDO2-CAP39

AVSS238

CBP37

CPVDD36

CBN35

CPVEE34

SPK-OUT-L+42SPK-OUT-L-43SPK-OUT-R-44SPK-OUT-R+45

PVDD246

PDB47

LINE2-L(PORT-E-L)24

LINE2-R(PORT-E-R)23

LINE1-L(PORT-C-L)22

LINE1-R(PORT-C-R)

21

MIC1-R(PORT-B-R)20

MIC1-L(PORT-B-L)19

MIC2-R(PORT-F-R)18

MIC2-L(PORT-F-L)17

MONO-OUT16

JDREF15

SENSE B14

SENSE A13

SPDIF-OUT/GPIO248

PCBEEP12

RESETB11 SYNC10

DVDD-IO

9

SDATA-IN8

LDO3-CAP7

DVDD1

GPIO0/DMIC-DATA2

GPIO1/DMIC-CLK3

DVSS4

BCLK6 SDATA-OUT5

ThermalPAD49

CA674.7U_0603_6.3V6K

CA674.7U_0603_6.3V6K

1 2

5 4 3 2 1



D D

C C

B B

A A

close to chip side

Trace width:40mil

MS_D2_SD_CLK Conn pin 13 SD_CLK 打Via拉 pin 10 MS_D2

拉MS_CLK_SD_WP Conn pin 5 MS_CLK 打Via拉 pin 20 SD_W

Close to JREAD

For EMI request.

Place close to JREAD

For EMI request. Place close to UR1

SD_D1

SD_D0

MS_CLK_SD_WP

MS _BSMS_D2_SD_CLKMS_D1_SD_D3

MS _D0

MS_D2_SD_CLK

MS_INS#MS_D3

SD_CMDMS_CLK_SD_WP

MS _D1_SD_D3

SD_D2

SD_CD#

USB20_CR_P6 USB20_CR_P6_R

USB20_CR_N6_RUSB20_CR_N6

MS_BS

SD_D2MS_D1_SD_D3

SD_CMDMS_D0MS_D2_SD_CLK_R MS_D2_SD_CLK

SD_CD#MS_D3

SD_D0SD_D1

MS_INS#MS_CLK_SD_WP_R MS_CLK_SD_WPV18

RREF

USB20_CR_P6_RUSB20_CR_N6_R

SD_CMD

SD_CD# MS_INS#

USB20_CR_P6<12>

USB20_CR_N6<12>

+VCC_3IN1

+3VS

+VCC_3IN1

+VCC_3IN1+3VS

Title


Date: Sheet of




LA-9981P 0.2



Card Reader RTS5179Title


Date: Sheet of




LA-9981P 0.2



Card Reader RTS5179Title


Date: Sheet of




LA-9981P 0.2



Card Reader RTS5179

CR11

10P_0402_50V8J

EMI@CR11

10P_0402_50V8J

EMI@ 1

2

JREAD

T-SOL_143-2300302602_RVCONN@

JREAD

T-SOL_143-2300302602_RVCONN@

SD-CD20 SD-DAT119 SD-DAT0 MMC-DAT18

MS-VSS216

SD-VSS MMC-VSS217

MS-BS15

MS-DATA113

SD-CLK MMC-CLK14

MS-DATA012 SD-VDD MMC-VDD11 MS-DATA210 SD-VSS MMC-VSS19 MS-INS8 MS-DATA37

MS-SCLK5 MS-VCC4 SD-CD/DAT3 MMC-RSV3

SD-CMD MMC-CMD6

SD-DAT21

MS-VSS12

SD-GND21

GND123

GND224

SD-WP(SW)22

C R 3

1 U _ 0 4 0 2 _ 6 . 3 V 6 K

C R 3

1 U _ 0 4 0 2 _ 6 . 3 V 6 K

1

2

RR2

22_0402_5%

EMI@RR2

22_0402_5%

EMI@

1 2

CR8

4.7U_0603_6.3V6K

CR8

4.7U_0603_6.3V6K

1

2

C R 5

5 P _ 0 4 0 2 _ 5 0 V 8 C

E MI @

C R 5

5 P _ 0 4 0 2 _ 5 0 V 8 C

E MI @

1

2

CR10

0.1U_0402_10V7K

EMI@CR10

0.1U_0402_10V7K

EMI@1

2

R R1 6 .1 9K _0 40 2_ 1%R R1 6 .1 9K _0 40 2_ 1%12

CR1

0.1U_0402_10V7K

CR1

0.1U_0402_10V7K

1

2

CR2

4.7U_0603_6.3V6K

CR2

4.7U_0603_6.3V6K

1

2

CR9

0.1U_0402_10V7K

EMI@CR9

0.1U_0402_10V7K

EMI@1

2

C R 4

1 U _ 0 4 0 2 _ 6 . 3 V 6 K

C R 4

1 U _ 0 4 0 2 _ 6 . 3 V 6 K

1

2

CR7

0.1U_0402_10V7K

CR7

0.1U_0402_10V7K

1

2

C R 6

5 P _ 0 4 0 2 _ 5 0 V 8 C

E MI @

C R 6

5 P _ 0 4 0 2 _ 5 0 V 8 C

E MI @

1

2

RTS5179-GR_QFN24

UR1

RTS5179-GR_QFN24_4X4

RTS5179-GR_QFN24

UR1

RTS5179-GR_QFN24_4X4

RREF1

DM2

DP3

3 V 3

_ I N

4

C A R D

_ 3 V 3

5

V1824

XD_CD#7

SDREG6

XD_D723

T h e r m a

l p a

d

2 5

GPIO017

SP1422

SP1321

SP1220

SP1119

SP1018

SP916

SP815

SP714

SP613

SP512

SP411

SP310

SP29

SP18

LR2

WCM-2012HS-900T_4P

EMI@

LR2

WCM-2012HS-900T_4P

EMI@

11

22

33

44

RR3

22_0402_5%

EMI@RR3

22_0402_5%

EMI@

1 2

5 4 3 2 1



D D

C C

B B

A A

2.0A

2.0A

USB connector1

USB20 port1USB30 port2

USB connector2

USB20 port0USB30 port1

80mil

80mil

USB20_JUSB1_P1_R

USB20_JUSB1_N1_R

USB_OC0#USB_EN#

USB3RP2_JUSB1

USB3RN2_JUSB1

USB3RP1_JUSB2_RUSB3RP1_JUSB2

USB3RN1_JUSB2_RUSB3RN1_JUSB2

USB_EN# USB_OC0#

USB20_JUSB2_P0_R

USB20_JUSB2_N0_R

USB3TN2_JUSB1_C

USB3TP2_JUSB1_C USB3TP2_JUSB1_R

USB3TN2_JUSB1_R

USB20_JUSB1_N1_RUSB20_JUSB1_N1

USB20_JUSB1_P1_R

USB3TN2_JUSB1

USB3TP2_JUSB1

USB20_JUSB1_P1

USB3TP2_JUSB1_R

USB3RP2_JUSB1_R

USB3RN2_JUSB1_R

USB3TN2_JUSB1_RUSB3TN2_JUSB1_R

USB3TP2_JUSB1_R

USB3RN2_JUSB1_R

USB3RP2_JUSB1_R

USB3RP2_JUSB1_R

USB3TN2_JUSB1_R

USB3TP2_JUSB1_R

USB3RN2_JUSB1_R

USB3RP1_JUSB2_R

USB3TN1_JUSB2_R

USB3TP1_JUSB2_R

USB3RN1_JUSB2_R

USB20_JUSB2_N0_RUSB20_JUSB2_N0

USB20_JUSB2_P0

USB3TN1_JUSB2_C

USB3TP1_JUSB2_C USB3TP1_JUSB2_R

USB3TN1_JUSB2_RUSB3TN1_JUSB2

USB3TP1_JUSB2

USB20_JUSB2_P0_R

USB3RP1_JUSB2_R

USB3TP1_JUSB2_R

USB3RN1_JUSB2_R

USB3TN1_JUSB2_R

USB3TP1_JUSB2_R

USB3RP1_JUSB2_R

USB3TN1_JUSB2_R

USB3RN1_JUSB2_R

USB3RP2_JUSB1_R

USB3RN2_JUSB1_R

USB_EN#<25,30>

USB20_JUSB1_P1<12>

USB20_JUSB1_N1<12>

USB20_JUSB2_P0<12>

USB20_JUSB2_N0<12>

USB3RN1_JUSB2<12>

USB3TN1_JUSB2<12>

USB3TN2_JUSB1<12>

USB3RP1_JUSB2<12>

USB3RP2_JUSB1<12>

USB3TP2_JUSB1<12>

USB3TP1_JUSB2<12>

USB3RN2_JUSB1<12>

USB_OC0# <12>

+5V_USB_PWR1

+5V_USB_PWR1

+5VALW

+5V_USB_PWR2

+5VALW

+5V_USB_PWR2

Title


Date: Sheet of




LA-9981P 0.2



USB3.0Title


Date: Sheet of




LA-9981P 0.2



USB3.0Title


Date: Sheet of




LA-9981P 0.2



USB3.0

CI10 0 .1U_0402_10V7KCI10 0 .1U_0402_10V7K

12

C I 9

0 .1 U _ 0 4 0 2 _1 6 V

7 K

C I 9

0 .1 U _ 0 4 0 2 _1 6 V

7 K

1

2

CI4 0 .1U_0402_10V7KCI4 0 .1U_0402_10V7K12

CI11 0 .1U_0402_10V7KCI11 0 .1U_0402_10V7K

12

UI3

AP2301MPG-13_MSOP8

UI3

AP2301MPG-13_MSOP8

FLG5VIN

3VOUT

6

GND1

EN4

VOUT7

VIN2 VOUT

8

E P A D

9

DI5

L30ESDL5V0C3-2_SOT23-3

ESD@

DI5


ESD@

1

2 3

CI14

0.1U_0402_16V7K

CI14

0.1U_0402_16V7K

1

2

CI17

0.1U_0402_16V7K

CI17

0.1U_0402_16V7K

1

2

DI4

IP4292CZ10-TBR_XSON10_2.5X1~D

ESD@

DI4


ESD@

4

5

1

6

2

7

3

10

9

8

+CI1

220U_6.3V_M

+CI1

220U_6.3V_M

1

2

LI6

DLW21SN670HQ2L_4P

EMI@LI6

DLW21SN670HQ2L_4P

EMI@1 2

34

CI12

4.7U_0805_10V4Z

CI12

4.7U_0805_10V4Z

1

2

DI1


ESD@DI1


ESD@

4

5

1

6

2

7

3

10

9

8LI2

WCM-2012HS-900T_4P

EMI@

LI2

WCM-2012HS-900T_4P

EMI@

11

22

33

44

CI13

0 .1 U _ 0 4 0 2 _1 6 V 7 K

CI13

0 .1 U _ 0 4 0 2 _1 6 V 7 K

1

2

C I 2

0 .1 U _ 0 4 0 2 _1 6

V 7 K

C I 2

0 .1 U _ 0 4 0 2 _1 6

V 7 K

1

2

CI6

4.7U_0805_10V4Z

CI6

4.7U_0805_10V4Z

1

2

CI15

0.1U_0402_16V7K

CI15

0.1U_0402_16V7K

1

2

CI26

0 .1 U _ 0 4 0 2 _1 6 V 7 K

CI26

0 .1 U _ 0 4 0 2 _1 6 V 7 K

1

2

CI18

47U_0805_6.3V4Z

CI18

47U_0805_6.3V4Z

1

2

UI2

AP2301MPG-13_MSOP8

UI2

AP2301MPG-13_MSOP8

FLG5VIN

3VOUT

6

GND1

EN4

VOUT7

VIN2 VOUT

8

E P A D

9

LI5

WCM-2012HS-900T_4P

EMI@LI5

WCM-2012HS-900T_4P

EMI@

11

22

33

44

JUSB1

ACON_TARA4-9K1311CONN@

JUSB1

ACON_TARA4-9K1311CONN@

SSTX-8

SSTX+9

GND10

GND11

VBUS1

D+3

D-2

GND

4

SSRX-5

SSRX+6

GND7

GND 13GND

12

LI1

DLW21SN670HQ2L_4P

EMI@LI1

DLW21SN670HQ2L_4P

EMI@1 2

34

JUSB2

ACON_TARA4-9K1311

CONN@JUSB2

ACON_TARA4-9K1311

CONN@

SSTX-8

SSTX+9

GND10

GND11

VBUS1

D+3

D-2

GND4

SSRX-5

SSRX+6

GND7

GND13GND12

C I 4 0

1 0 U _ 0 6 0 3 _ 6 . 3

V 6 M

C I 4 0

1 0 U _ 0 6 0 3 _ 6 . 3

V 6 M

1

2

+CI8

220U_6.3V_M

+CI8

220U_6.3V_M

1

2

LI4

DLW21SN670HQ2L_4P

EMI@LI4

DLW21SN670HQ2L_4P

EMI@1 2

34

CI3 0 .1U_0402_10V7KCI3 0 .1U_0402_10V7K12

C I 4 3

1 0 U _ 0 6 0 3 _ 6 . 3 V

6 M

C I 4 3

1 0 U _ 0 6 0 3 _ 6 . 3 V

6 M

1

2

LI3

DLW21SN670HQ2L_4P

EMI@LI3

DLW21SN670HQ2L_4P

EMI@1 2

34

DI2


ESD@

DI2


ESD@

1

2 3

CI7

0.1U_0402_16V7K

CI7

0.1U_0402_16V7K

1

2

5 4 3 2 1



D D

C C

B B

A A

80mil

2.0A

80mil

2.0A

USB connector3

USB20 port2

USB connector4

USB20 port3

Place close to JUSB3

SP01001AA00

SP01001EX00

Main:

2nd:

Change CONN symbol for DFB

USB20_JUSB3_P2_R

USB20_JUSB3_N2_R

USB_OC1#USB_EN#

USB20_USBDB_P3_R

USB20_USBDB_N3_RUSB20_USBDB_N3

USB20_USBDB_P3

USB_OC1#USB_EN#

USB20_JUSB3_N2_RUSB20_JUSB3_P2_R

USB20_USBDB_N3_RUSB20_USBDB_P3_R

USB20_JUSB3_P2

USB20_JUSB3_N2

USB_EN#<24,30>

USB20_USBDB_P3<12>

USB20_USBDB_N3<12>

USB_OC1# <12>

USB20_JUSB3_P2<12>

USB20_JUSB3_N2<12>

+5V_USB_PWR3

+5VALW

+5V_USB_PWR4

+5V_USB_PWR4

+5VALW

+5V_USB_PWR3+5V_USB_PWR3

Title


Date: Sheet of




LA-9981P 0.2



MB to USB2.0 DBTitle


Date: Sheet of




LA-9981P 0.2



MB to USB2.0 DBTitle


Date: Sheet of




LA-9981P 0.2



MB to USB2.0 DB

UI5

AP2301MPG-13_MSOP8

UI5

AP2301MPG-13_MSOP8

FLG5VIN

3VOUT

6

GND1

EN4

VOUT7

VIN2 VOUT

8

E P A D

9

JDB

JESS_UCNR2210M008-0CONN@

JDB

JESS_UCNR2210M008-0CONN@

11

22

33

44

55

66

77

88

G19

G210

+CI20

220U_6.3V_M

+CI20

220U_6.3V_M

1

2

C I 4 4

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C I 4 4

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

CI31

4.7U_0805_10V4Z

CI31

4.7U_0805_10V4Z

1

2

JUSB3

ACON_UARBG-4K1926CONN@

JUSB3

ACON_UARBG-4K1926CONN@

VBUS1

D-2

D+3

GND4

GND5

GND6

GND7

GND8DI7


ESD@

DI7


ESD@

1

2 3

CI23

4.7U_0805_10V4Z

CI23

4.7U_0805_10V4Z

1

2

C I 1 9

0 .1 U _ 0 4 0 2 _1 6 V 7 K

C I 1 9

0 .1 U _ 0 4 0 2 _1 6 V 7 K

1

2

CI24

0.1U_0402_16V7K

CI24

0.1U_0402_16V7K

1

2

CI27

47U_0805_6.3V4Z

CI27

47U_0805_6.3V4Z

1

2

CI22

0.1U_0402_16V7K

CI22

0.1U_0402_16V7K

1

2

CI30

0.1U_0402_16V7K

CI30

0.1U_0402_16V7K

1

2

CI25

0 .1 U _ 0 4 0 2 _1 6 V 7 K

CI25

0 .1 U _ 0 4 0 2 _1 6 V 7 K

1

2

CI21

47U_0805_6.3V4Z

CI21

47U_0805_6.3V4Z

1

2

CI16

0 .1 U _ 0 4 0 2 _

1 6 V 7 K

CI16

0 .1 U _ 0 4 0 2 _

1 6 V 7 K

1

2

UI4

AP2301MPG-13_MSOP8

UI4

AP2301MPG-13_MSOP8

FLG5VIN

3VOUT

6

GND1

EN4

VOUT7

VIN2 VOUT

8

E P A D

9

LI10

WCM-2012HS-900T_4P

EMI@

LI10

WCM-2012HS-900T_4P

EMI@

11

22

33

44

CI32

0.1U_0402_16V7K

CI32

0.1U_0402_16V7K

1

2

LI7

WCM-2012HS-900T_4P

EMI@LI7

WCM-2012HS-900T_4P

EMI@

11

22

33

44

5 4 3 2 1



D D

C C

B B

A A

Mini WLAN/WIMAX H=6.7

HDD LED

Power LED

Battery LED

Wireless LED

10mils, All pins

CC47靠近wlan connector

ESD solution

BT_ON#



CLK_PCIE_WLAN#CLK_PCIE_WLAN

WLAN_CLKREQ#

WLAN_WAKE#

WL_OFF#WLAN_RADIO_DIS#_R

SATA_ACT# BATT_CHG_LED#

BATT_LOW_LED#

USB20_MINI1_N4USB20_MINI1_P4

EC_TX

EC_RX

PCIE_PTX_WLANRX_P4_CPCIE_PTX_WLANRX_N4_C

PLT_RST#

WL_BT_LED#

WL_BT_LED#

DDR_XDP_WLAN_TP_SMBCLK <17,18,19,27,6,9>DDR_XDP_WLAN_TP_SMBDAT <17,18,19,27,6 ,9>

CLK_PCIE_WLAN#<9>CLK_PCIE_WLAN<9>

WLAN_CLKREQ#<9>

EC_TX<30>EC_RX<30>

WLAN_WAKE#<30>

BT_ON#<11>

SATA_ACT#<8> BATT_CHG_LED#<30>

BATT_LOW_LED#<30>

PLT_RST# <10,21,30,48,6>

USB20_MINI1_N4 <12>

USB20_MINI1_P4 <12>

PCIE_PTX_WLANRX_N4<12>

PCIE_PRX_WLANTX_N4<12>

PCIE_PTX_WLANRX_P4<12>

PCIE_PRX_WLANTX_P4<12>

WL_OFF# <11>

PWR_PWM_LED#<30>

+3V_WLAN

+1.5VS

+3V_WLAN

+3VS

+3VS

+5VALW

+3V_WLAN+3VS

+5VS

+5VALW

+5VALW

+3VS

+3V_WLAN

+5VALW

+3VS +CPU_CORE

Title


Date: Sheet of




LA-9981P 0.2



Mini Card/LEDTitle


Date: Sheet of




LA-9981P 0.2



Mini Card/LEDTitle


Date: Sheet of




LA-9981P 0.2



Mini Card/LED

RM1 3 1 K_ 0402 _1%RM1 3 1 K_ 0402 _1%12

RM110

10K_0402_5%

RM110

10K_0402_5%

1

2

RD45

100K_0402_5%

RD45

100K_0402_5%

1

2

C M4 8

0 .1 U _ 0 4 0 2 _1 0 V 7 K

C M4 8

0 .1 U _ 0 4 0 2 _1 0 V 7 K 1

2 C M4 0

0 . 0 4 7 U _ 0 4 0 2 _1 6 V 4 Z

C M4 0

0 . 0 4 7 U _ 0 4 0 2 _1 6 V 4 Z

1

2

RD14390_0402_5%RD14390_0402_5%

1 2

RM11

100K_0402_5%

RM11

100K_0402_5%

1

2

RM26

0_0805_1%

@RM26

0_0805_1%

@

1 2

RD15390_0402_5%RD15390_0402_5%

1 2

LED112-21C-T3D-CM2P1B18X-2C_WHITELED112-21C-T3D-CM2P1B18X-2C_WHITE

1 2

3

RD18

680_0402_1%

RD18

680_0402_1%

1 2

G

D S

QD182N7002K_SOT23-3

G

D S

QD182N7002K_SOT23-3

2

13

RD17

390_0402_5%

RD17

390_0402_5%

1 2

C M4 4 0 .1 U_ 04 02 _1 0V 7KC M4 4 0 .1 U_ 04 02 _1 0V 7K1 2C M4 9 0 .1 U_ 04 02 _1 0V 7KC M4 9 0 .1 U_ 04 02 _1 0V 7K1 2

G

D S

QM302N7002K_SOT23-3

G

D S

QM302N7002K_SOT23-3

2

1 3

RM25

0_0805_1%

@RM25

0_0805_1%

@

1 2

CM45

22U_0603_6.3V6M

ESD@

CM45

22U_0603_6.3V6M

ESD@

1 2

C M4 7

0 .1 U _ 0 4 0 2 _1 0 V 7 K

@

C M4 7

0 .1 U _ 0 4 0 2 _1 0 V 7 K

@

1

2

C M4 3

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

C M4 3

4 .7 U _ 0 6 0 3 _ 6 . 3 V 6 K

1

2

RD16680_0402_1%RD16680_0402_1%

1 2


1 2

3

RD46

100K_0402_5%

@ RD46

100K_0402_5%

@

1

2

C M4 6

0 .1 U _ 0 4 0 2 _1 0 V 7 K

C M4 6

0 .1 U _ 0 4 0 2 _1 0 V 7 K 1

2

White

Amber

LED3HT-210UD5-BP5_AMBER-WHITE

White

Amber

LED3HT-210UD5-BP5_AMBER-WHITE

2

13


1 2

3

JMINI

CONCR_525B01BE17ACONN@

JMINI

CONCR_525B01BE17ACONN@

11

33

55

77

99

1111

1313

1515

1717

19

19

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

4545

4747

4949

5151

GND153

22

44

66

88

1010

1212

1414

1616

1818

20

20

22 22

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

4646

4848

5050

5252

GND254

5 4 3 2 1



D D

C C

B B

A A

40mil

40mil

Power ON Circuit

ON/OFF switch

POWER/B

INT_KBD Connector

Touch pad

FAN Control circuit

TOP Side

Bottom Side

Pop only before MP

SP01000R910

SP01001BG00

Main:

2nd:

Change CONN symbol for DFB

TP_CLKTP_DATA

KSO[0..16]

KSI[0..7]

EN_DFAN1

ON/OFFBTN#

KB_CAPS_PWR

KSI0

KSI1

KSI4

KSI2

KSI3

KSI5

KSI6

KSI7

KSO16

KSO2

KSO4

KSO3KSO1

KSO0

KSO8

KSO7

KSO6

KSO5

KSO9

KSO10

KSO13

KSO12

KSO11

KSO14

KSO15

LID _SW#



TP_CLK<30>

TP_DATA<30>

ON/OFFBTN# <30>

KSO[0..16]<30>

KSI[0..7]<30>

FAN_SPEED1<30>

EN_DFAN1<30>

CAPS_LED<30>

LID_SW#<30>


+3VS

+FAN_POWER

+3VS

+5VS

+FAN_POWER

+3VLP

+5VS

+3VALW

Title


Date: Sheet of




LA-9981P 0.2

FA N/TP/PWR SW



Title


Date: Sheet of




LA-9981P 0.2

FA N/TP/PWR SW



Title


Date: Sheet of




LA-9981P 0.2

FA N/TP/PWR SW



RE60

240_0402_1%

RE60

240_0402_1%

1 2

SW1

SMT1-05-A_4P

SW1

SMT1-05-A_4P3

2

1

4

5 6

JFAN

ACES_85204-0300NCONN@

JFAN

ACES_85204-0300NCONN@

11

22

33

GND4

GND5RE49

100K_0402_5%RE49100K_0402_5%

1

2

CE240.01U_0402_16V7KCE240.01U_0402_16V7K

1

2

UE3

APE8873MSOP 8P

UE3

APE8873MSOP8P

VEN1

VIN2

GND

5GND6

GND8

VO3

VSET

4

GND7

CE200.1U_0402_16V7KCE200.1U_0402_16V7K

1

2

CE252.2U_0603_6.3V6KCE252.2U_0603_6.3V6K

1 2

RE5010K_0402_5%RE5010K_0402_5%

1

2

CE22

2 . 2 U_

0 6 0 3_

6 . 3 V 6 K

CE22

2 . 2 U_

0 6 0 3_

6 . 3 V 6 K

1

2

JKBHB_A823020-SBHR21

CONN@JKBHB_A823020-SBHR21

CONN@

11

44

22

55

33

88

7

7

66

1010

99

1111 1212 1313 1414

1717

1616

1919 2020

1515

2222

2121

1818

2323

2525

2424

2626 2727 2828 2929 3030

GND31GND32

JTP

PS_HPF10052-06M000R

CONN@

JTP

PS_HPF10052-06M000R

CONN@

1

1

22

33

44

55

66 G1

7

G28

SW2SMT1-05-A_4PSW2SMT1-05-A_4P

3

2

1

4

5 6

JPWR

HB_A090420-SAHR21

CONN@

JPWR

HB_A090420-SAHR21

CONN@

11

22

33

44

GND5

GND

6

CE23

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

CE23

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K 1

2

A B C D E


http://slidepdf.com/reader/full/compal-la-9981p-r02-schematics 28/56 A B C D E

1 1

2 2

3 3

4 4

+5VS and +3VS switch

For Intel S3 Power Reduction

10mil

10mil

+3VALW_PCH switch

SHORT DEFAULT

SHORT DEFAULT

SHORT DEFAULT

SUSP

SUSP#

5VS

5VS_GATE

3VS_GATE

3VS

SUSP SUSP

+3VALW_PCH_GATE

3VALW_PCH

PCH_PWR_EN

SUSP#<30,39,40>

PCH_PWR_EN<30>

+5VALW

+5VALW

+5VALW

+3VALW

+3VALW

+5VS

+3VS

+0.675VS +1.05VS

+3VALW

+3VALW

+3VALW_PCH

Title


Date: Sheet of




LA-9981P 0.2



DC/DC InterfaceTitle


Date: Sheet of




LA-9981P 0.2



DC/DC InterfaceTitle


Date: Sheet of




LA-9981P 0.2



DC/DC Interface

J513

JUMP_43X79@

J513

JUMP_43X79@

11

22

G

D

S Q23072N7002K_SOT23-3

G

D

S Q23072N7002K_SOT23-3

2

1

3

G

D

S Q23082N7002K_SOT23-3

@

G

D

S Q23082N7002K_SOT23-3

@

2

1

3

C 2 3 1 0

1 0 U _ 0 8 0 5 _1 0 V 4 Z

@

C 2 3 1 0

1 0 U _ 0 8 0 5 _1 0 V 4 Z

@

1

2

C 2 3 1 6

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 1 6

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

R16

100K_0402_5%

R16

100K_0402_5%

1

2

C 2 3 0 8

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 0 8

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

C 2 3 2 4

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

@

C 2 3 2 4

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

@

1

2

C 2 3 1 2

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 1 2

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

C 2 3 0 6

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 0 6

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

C 2 3 1 1

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 1 1

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

C 2 3 1 8

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 1 8

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

C 2 3 2 3

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 2 3

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

C2309 0 . 0 1 U _ 0 6 0 3 _2 5 V 7 K

C2309 0 . 0 1 U _ 0 6 0 3 _2 5 V 7 K

1

2

U2304

TPS22966DPUR_SON14_2X3

U2304


GND11

VIN26

VBIAS4

ON25

VOUT29

VIN27

CT112

VOUT114

VOUT28

VOUT113

VIN12

ON13

VIN11

CT210

GPAD15

J511

JUMP_43X79@

J511

JUMP_43X79@

11

22

J510

JUMP_43X79@

J510

JUMP_43X79@

11

22

R2318470K_0402_5%

R2318470K_0402_5%1 2

C 2 3 0 5

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 0 5

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

R10100K_0402_5%R10100K_0402_5%

1

2

C2314 0 . 0 1 U _ 0 6 0 3 _2 5 V 7 K

C2314 0 . 0 1 U _ 0 6 0 3 _2 5 V 7 K

1

2

C2322 0 . 0 1 U _ 0 6 0 3 _2 5 V 7 K

C2322 0 . 0 1 U _ 0 6 0 3 _2 5 V 7 K

1

2G

D

S

Q8

2N7002K_SOT23-3G

D

S

Q8

2N7002K_SOT23-3

2

1

3

U2301


U2301


GND11

VIN26

VBIAS4

ON25

VOUT29

VIN2

7

CT112

VOUT114

VOUT2

8

VOUT113

VIN12

ON13

VIN11

CT210

GPAD15

R2315

470_0603_5%@

R2315

470_0603_5%@

1

2

R4160_0402_5%R4160_0402_5%

1 2

R2314

22_0603_5%

R2314

22_0603_5%

1

2

C 2 3 0 7

1 0 U _ 0 8 0 5 _1 0 V 4 Z

@

C 2 3 0 7

1 0 U _ 0 8 0 5 _1 0 V 4 Z

@

1

2

C 2 3 1 3

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

C 2 3 1 3

1 0 U _ 0 6 0 3 _ 6 . 3 V 6 M

1

2

R2313

82K_0402_5%

R2313

82K_0402_5%1 2

5 4 3 2 1



D D

C C

B B

A A

SLG3NB3374V is for DIS by output 24M*1,25M*1, 27M*1, 32K*1SLG3NB3375V is for UMA by output 24M81, 25M*1, 32K*1

CPU_RTC 32.768k(P.8)Place RG3 close to YC1

VGA 27M(P.29)Place RG7 close to YV1

LAN 25M(P.21)Place RG8 close to YL2

CPU_CLK 24M(P.9)Place RG6 close to YC2

RG3, RG7,RG8, RG6 0ohm_0402for isolated CLK tail

Depop if GCLK with UMA

Place closeto UG1.8

Reserve CG11 for vendorPlace close to RG4

PCH_RTCX1_R

LAN_X1_R

PCH_X1_R

CLK_X2CLK_X1

RTC_VOUT

VGA_X1_R

CLK_X1

CLK_X2

GCLK_VRTC

XTALIN_R

XTLI_R

XTALIN_R

XTAL24_IN <9>

XTLI <21>

PCH_RTCX1 <8>

XTALIN <49>

+3VLP

+1.05VS

+1.8VGS

+LAN_IO

+RTCBATT

+RTCVCC

+3VALW

+3VLP+1.05VS+1.8VGS +LAN_IO +3VALW

Title


Date: Sheet of




LA-9981P 0.2

GCLK

55Saturday, March 09, 2013


23

Title


Date: Sheet of




LA-9981P 0.2

GCLK



23

Title


Date: Sheet of




LA-9981P 0.2

GCLK



23

CG9

12P_0402_50V8J~D

GCLK@CG9

12P_0402_50V8J~D

GCLK@12

RG7 0_0402_5%

GCLKDIS@

RG7 0_0402_5%

GCLKDIS@1 2

CG8

12P_0402_50V8J~D

GCLK@CG8

12P_0402_50V8J~D

GCLK@12

RG1

330_0402_5%

GCLK@RG1

330_0402_5%

GCLK@

1

2

RG6 0_0402_5%

GCLK@

RG6 0_0402_5%

GCLK@1 2

YG1

25MHZ_10PF_7V25000014

GCLK@YG1

25MHZ_10PF_7V25000014

GCLK@

OSC1

OSC3

GND2

GND4

RG3

0_0402_5%

GCLK@RG3

0_0402_5%

GCLK@1 2

CG10

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLK@

CG10

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLK@1

2

RG2

0_0402_5%

@RG2

0_0402_5%

@

1

2

CG3

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLK@

CG3

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLK@1

2

UG1

SLG3NB274VTR_TQFN16_2X3

@

UG1

SLG3NB274VTR_TQFN16_2X3

@

XTAL_IN1

VDD2

VDDIO_25M_B3

G N D 1

4

25MHz_B 5

25MHz_A6

G N D 2

7

VDDIO_25M_A8

32kHz9

VBAT10

VDDIO_27M11

27MHz12

G N D 3

1 3

VDD_RTC_OUT14

+V3.3A15

XTAL_OUT16

G N D 4

1 7

CG75P_0402_50V8C

GCLK@

CG75P_0402_50V8C

GCLK@1

2

RG4 10 _040 2_1 %GCLKDIS@

RG4 10 _040 2_1 %GCLKDIS@

1 2

C G 6

2 .2 U _ 0 6 0 3 _ 6 . 3 V 6 K

GCLK@ C G 6

2 .2 U _ 0 6 0 3 _ 6 . 3 V 6 K

GCLK@

1

2

RG8 0_0402_5%GCLK@RG8 0_0402_5%GCLK@1 2

CG1

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLKDIS@

CG1

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLKDIS@ 1

2

RG5 33 _040 2_5 %

GCLK@

RG5 33 _040 2_5 %

GCLK@1 2

UG1

SLG3NB244VTR TQFN 16P CLK GEN

GCLKUMA@UG1


GCLKUMA@

CG2

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLK@

CG2

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLK@1

2

CG115P_0402_50V8C

@

CG115P_0402_50V8C

@1

2

CG4

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLK@

CG4

0 . 1 U_

0 4 0 2_

1 0 V 7 K

GCLK@1

2CG5

22U_0805_6.3V6M

GCLK@

CG5

22U_0805_6.3V6M

GCLK@

1

2

UG2


GCLKDIS@UG2


GCLKDIS@

5 4 3 2 1

27K 0402 1%SD034100300

12K_0402_1%SD034120280



5 4 3 2 1

D D

C C

B B

A A


Ra

Rb

Venus DIS@UMA UMA@

KB9012A3 change to

KB9012A4 SA00004OB30

ME_FWP PCH has internal 20K PD.

(suspend power rail)

Board ID

Please close to EC

Please close to EC

Reserve for ESD

20mil

100K_0402_1%SD034100380

43K_0402_1%SD034430280

27K_0402_1%SD034100300

"TOUCH_RST" for OAK 15 only

"KB_LED_PWM" for OAK 17 only

Place CE30,CE31,CE32,CE33 close to UE1

Place DE1 close to UE1

75K_0402_1%SD034750280

Place CE34between DE1 and RE12

SD034560280 56K_0402_1%

33K_0402_1%SD034430280

KSO[0..16]

KSI[0..7]

ECAGND

KSI1

KSO9

BKOFF#

KSI7

FAN_SPEED1

LPC_LAD1

KSI3

KSO4

PLT_RST#

+3VALW

+V18R

KSO8

KSO2

EC_SMI#

SUSP#

KSO16

EN _DFAN1

BATT_TEMP

KSI0

KSO1

SERIRQ

EC_RST#

LPC_LAD2

ECAGND

KSO14

KB_RST#

ADP_I

KSI4

EC_SCI#

LPC_LAD3

VCOUT0 _PH#

KSO15

KSO10

KSO0

ACOFF

LPC_LAD0

LPC_LFRAME#

KSO13

KSI2

KSO11

KSO3

KSI6

BEEP#

+EC_VCCA

KSO12

KSI5

KSO7

EC_TX

BATT_CHG_LED#

KSO6KSO5

EC_RX

WLAN_WAKE#

PWR_PWM_LED#CAPS_LED

BATT_LOW_LED#

PECI_KB9012

VCOUT1_PH

SIO_SLP_S3#SIO_SLP_S5# EC_LID_OUT#

H_PROCHOT#

ACIN

ON/OFFBTN#

PBTN_OUT#

VCOUT1_PH

EC_SMB_DA1

EC_SMB_CK1

EC_ENVDD

PCIE _WAKE#

PCH_PWROK

ME_EN

PS_ID

65W/90W#

EN_INVPWR

LCD_TEST

WOL_EN

EC _SMB_DA2

EC_ON

EC_MUTE#

PANEL_BKLEN

CE_EN

DBC_EN

PCH_PWROK

SIO_SLP_S5#

SIO_SLP_S3#

FAN_SPEED1

LID_SW#

IMVP_PWRGD

WLAN_WAKE#

LID_SW#

AD_BID0

ME_EN

ME_SUS_PWR_ACK

RUNPWROK

EC_SMB_CK2

TP_CLKTP_DATA

VCIN1_PH

EC_SMB_DA2

EC_SMB_DA1

EC_SMB_CK2

EC _SMB_CK1

DGPU_PWROK

ENVDD_PCH

VCCST_PG_EC

SUSACK#

ECAGND

SIO_SLP_S0#

ACIN

TOUCH_RST

+1.05V_PGOOD

CLK_PCI_LPC

SYSON

AD_BID0

USB_EN#

SIO_SLP_S4#

ACIN_65W

CPU_DETECT#

SYS_PWROK

TP_DATA

TP_CLK

VCIN0_PH

PCH_HOT#

VR_HOT#

EC _RSMRST#

EC_SPI_MISO_1EC_SPI_MOSI_1

EC_SPI_CS0#EC _SPI_CLK_R

KB_LED_PWM

LID_SW#

PCH_PWROK

SYS_PWROK

CPU_DETECT#

VR_ON

VCCST_PG_EC

VR_ON_EC VR_ON

VR_ON

KSI[0..7]<27>

KSO[0..16]<27>

LPC_LFRAME#<9>

LPC_LAD2<9>

LPC_LAD0<9>

LPC_LAD3<9>

LPC_LAD1<9>

SERIRQ<11>

BEEP# <22>

EC_SMI#<8>

KB_RST#<11>

FAN_SPEED1<27>

ADP_I <36,37>

EC_RSMRST# <10>

SYSON <41>

CLK_PCI_LPC<9>

EN_DFAN1 <27>

BATT_CHG_LED# <26>

EC_SCI#<11>

CAPS_LED <27>

BATT_LOW_LED# <26>

H_PROCHOT#<36,6>

SIO_SLP_S3#<10>

SIO_SLP_S5#<10> EC_LID_OUT# <11>

BKOFF# <19>

EC_TX<26>

EC_RX<26>

PBTN_OUT# <10,6>

VCIN1_PH <36>

EC_SMB_DA1<36,37>EC_SMB_CK1<36,37>

VCOUT0_PH# <38>

ACOFF <37>

EC_ENVDD <31>

PWR_PWM_LED# <26>

ME_EN <8>

PS_ID<36>

65W#/90W <36>

EN_INVPWR <31>

LCD_TEST <31>

WOL_EN <21>

WLAN_WAKE# <26>

PCH_PWROK<10>

BATT_TEMP <36,37>

ON/OFFBTN# <27>

ACIN <10,36,37,49>EC_ON <38>

PLT_RST#<10,21,26,48,6>

EC_MUTE# <22>

EC_SMB_DA2<19,49,9>EC_SMB_CK2<19,49,9>

CE_EN<31>

DBC_EN<31>

IMVP_PWRGD <42>

PECI_EC <6>

ME_SUS_PWR_ACK<10>RUNPWROK<6>

PCIE_WAKE#<10,21>

LID_SW# <27>

TP_CLK <27>

TP_DATA <27>

VCOUT1_PH <36>

DGPU_PWROK<10,44>ENVDD_PCH<10,19>

VCCST_PG_EC<13>

SUSACK# <10>

SUSP# <28,39,40>

ECAGND <36>

SIO_SLP_S0# <10>

TOUCH_RST<31>

+1.05V_PGOOD<40>

PANEL_BKLEN <10>

VR_ON <13,42>

USB_EN# <24,25>

SIO_SLP_S4# <10>

PCH_PWR_EN <28>

PCH_DPWROK<10>

ACIN_65W <49>

CPU_DETECT# <6>

SYS_PWROK <10,6>

VCIN0_PH <36>

PCH_HOT# <9>

VR_HOT#<42>

EC_SPI_MISO_1 <9>

EC_SPI_MOSI_1 <9>

EC_SPI_CS0# <9>EC_SPI_CLK_R <9>

KB_LED_PWM

+3VALW

+3VS

+3VALW

+3VALW

+3VALW

+3VLP

+3VALW

+EC_VCCA

+3VALW

+3VS

Title


Date: Sheet of




LA-9981P 0.2

EC E NE-KB9012


2013/03/09 2014/04/01 Title


Date: Sheet of




LA-9981P 0.2

EC E NE-KB9012


2013/03/09 2014/04/01 Title


Date: Sheet of




LA-9981P 0.2

EC E NE-KB9012


2013/03/09 2014/04/01

C E1 1 0 .1 U_ 04 02 _1 0V 7KC E1 1 0 .1 U_ 04 02 _1 0V 7K12

CE18

100P_0402_50V8J

CE18

100P_0402_50V8J12

R2354

0_0402_5%

@EMI@R2354

0_0402_5%

@EMI@

1 2

LE1

FBMA-L11-160808-800LMT_0603

EMI@LE1

FBMA-L11-160808-800LMT_0603

EMI@

1 2

R E1 1 1 00 K_ 04 02 _5 %R E1 1 1 00 K_ 04 02 _5 %1 2

CE7

0.1U_0402_10V7K

CE7

0.1U_0402_10V7K

1

2

R E7 1 1 0K _0 40 2_ 5%R E7 1 1 0K _0 40 2_ 5%1 2

CE10.1U_0402_10V7KCE10.1U_0402_10V7K

1

2

RE5

75K_0402_1%

UMA@

SD034750280

RE5

75K_0402_1%

UMA@

SD034750280

CE12

0.1U_0402_10V7K

@EMI@CE12

0.1U_0402_10V7K

@EMI@

12

CE270.1U_0402_10V7K


ESD@

12

CE30 0 .1U_0402_10V7K

ESD@

CE30 0 .1U_0402_10V7K

ESD@1 2

RP36

2.2K_0804_8P4R_5%

RP36

2.2K_0804_8P4R_5%

18273645

CE31 0 .1U_0402_10V7K

ESD@

CE31 0 .1U_0402_10V7K

ESD@1 2

RE1810K_0402_5%RE1810K_0402_5%

12

UE2

SN74LVC1G06DCKR_SC70-5

UE2

SN74LVC1G06DCKR_SC70-5

Y4

A2

P

5

G

3

N C

1

CE6

1000P_0402_50V7K

@EMI@CE6

1000P_0402_50V7K

@EMI@

1

2

CE5

1000P_0402_50V7K

@EMI@CE5

1000P_0402_50V7K

@EMI@

1

2

RE104 .7 K_ 04 02 _5 % R E1 04.7K_0402_5%

12

RE7

0_0402_5%

@RE7

0_0402_5%

@

12

CE34

0.1U_0402_10V7K

ESD@CE34

0.1U_0402_10V7K

ESD@1

2

CE8

0.1U_0402_10V7K

CE8

0.1U_0402_10V7K

1

2

RE210K_0402_5%RE210K_0402_5%

1

2

RE3261K_0402_5%

@

RE3261K_0402_5%

@ 1

2

CE19

47P_0402_50V8J

CE19

47P_0402_50V8J

1

2

LPC & MISC

Int. K/B

Matrix

SM Bus

GPIO

GPIO

AD Input

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPO

GPI

UE1

KB9012QF-A4_LQFP128_14X14

LPC & MISC

Int. K/B

Matrix

SM Bus

GPIO

GPIO

AD Input

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPO

GPI

UE1

KB9012QF-A4_LQFP128_14X14

GATEA20/GPIO001

KBRST#/GPIO012

SERIRQ3

LPC_FRAME#4

LPC_AD35

PM_SLP_S3#/GPIO046

LPC_AD27

LPC_AD18

E C

_ V D D / V C C

9

LPC_AD010

G N D / G N D

1 1

CLK_PCI_EC12

PCIRST#/GPIO0513

PM_SLP_S5#/GPIO0714

EC_SMI#/GPIO0815

GPIO0A16

GPIO0B17

GPIO0C18

GPIO0D19

EC_SCII#/GPIO0E20

GPIO0F21

E C

_ V D D / V C C

2 2

BEEP#/GPIO1023

G N D / G N D

2 4

EC_INVT_PWM/GPIO1125

GPIO1226

ACOFF/GPIO1327

FAN_SPEED1/GPIO1428

EC_PME#/GPIO1529

EC_TX/GPIO1630

EC_RX/GPIO1731

PCH_PWROK/GPIO1832

E C

_ V D D / V C C

3 3

SUSP_LED#/GPIO1934

G N D / G N D

3 5

NUM_LED#/GPIO1A36

EC_RST#37

GPIO1D38

KSO0/GPIO2039

KSO1/GPIO2140

KSO2/GPIO2241

KSO3/GPIO2342

KSO4/GPIO2443

KSO5/GPIO2544

KSO6/GPIO2645

KSO7/GPIO2746

KSO8/GPIO2847

KSO9/GPIO2948

KSO10/GPIO2A49

KSO11/GPIO2B50

KSO12/GPIO2C51

KSO13/GPIO2D52

KSO14/GPIO2E53

KSO15/GPIO2F54

KSI0/GPIO3055

KSI1/GPIO3156

KSI2/GPIO3257

KSI3/GPIO3358

KSI4/GPIO3459

KSI5/GPIO3560

KSI6/GPIO3661

KSI7/GPIO3762

BATT_TEMP/GPIO3863

GPIO3964

ADP_I/GPIO3A65

GPIO3B66

E C

_ V D D / A V C C

6 7

DAC_BRIG/GPIO3C68

A G N D / A G N D

6 9

EN_DFAN1/GPIO3D70

IREF/GPIO3E71

CHGVADJ/GPIO3F72

ENBKL/GPIO4073

PECI_KB930/GPIO4174

GPIO4275

IMON/GPIO4376

EC_SMB_CK1/GPIO4477

EC_SMB_DA1/GPIO4578

EC_SMB_CK2/GPIO4679

EC_SMB_DA2/GPIO4780

KSO16/GPIO4881

KSO17/GPIO4982

EC_MUTE#/GPIO4A83

USB_EN#/GPIO4B84

CAP_INT#/GPIO4C85

EAPD/GPIO4D86

TP_CLK/GPIO4E87

TP_DATA/GPIO4F88

FSTCHG/GPIO5089

BATT_CHG_LED#/GPIO5290

CAPS_LED#/GPIO5391

PWR_LED#/GPIO5492

BATT_LOW_LED#/GPIO5593

G N D / G N D

9 4

SYSON/GPIO5695

E C

_ V D D / V C C

9 6

CPU1.5V_S3_GATE/GPXIOA0097

WOL_EN/GPXIOA0198

ME_EN/GPXIOA0299

EC_RSMRST#/GPXIOA03100

EC_LID_OUT#/GPXIOA04101

PROCHOT_IN/GPXIOA05102

H_PROCHOT#_EC/GPXIOA06103

VCOUT0_PH/GPXIOA07104

BKOFF#/GPXIOA08105

PBTN_OUT#/GPXIOA09106

PCH_APWROK/GPXIOA10107

SA_PGOOD/GPXIOA11108

VCIN0_PH/GPXIOD00109

AC_IN/GPXIOD01110

E C

_ V D D 0

1 1 1

EC_ON/GPXIOD02112

G N D 0

1 1 3

ON/OFF/GPXIOD03114

LID_SW#/GPXIOD04115

SUSP#/GPXIOD05116

GPXIOD06117

PECI_KB9012/GPXIOD07118

SPIDI/GPIO5B119

SPIDO/GPIO5C120

VR_ON/GPIO57121

XCLKI/GPIO5D122

XCLKO/GPIO5E123

V18R124

E C

_ V D D / V C C

1 2 5

SPICLK/GPIO58126

PM_SLP_S4#/GPIO59127

SPICS#/GPIO5A128

CE20.1U_0402_10V7KCE20.1U_0402_10V7K

1

2

RE370_0402_5%RE370_0402_5%

1 2

CE33 0 .1U_0402_10V7K

ESD@

CE33 0 .1U_0402_10V7K

ESD@1 2

C E9 1 00 P_ 04 02 _5 0V 8JC E9 1 00 P_ 04 02 _5 0V 8J12

RE36 43_0402_1%RE36 43_0402_1%12

CE29

220P_0402_50V8J

CE29

220P_0402_50V8J

1

2

CE280.1U_0402_10V7K


ESD@

12

C E 1 5

0 .1 U _ 0 4 0 2 _1 0 V 7 K

C E 1 5

0 .1 U _ 0 4 0 2 _1 0 V 7 K

1

2

LE2

FBMA-L11-160808-800 LMT_0603

LE2

FBMA-L11-160808-800 LMT_0603

12

RE533K_0402_1%

DIS@

RE533K_0402_1%

DIS@

1

2

RE3100K_0402_1%RE3100K_0402_1%

1

2

RE440_0402_1%

@RE44

0_0402_1%

@

1

2

RE8 4 7K_040 2_5 %RE8 4 7K_040 2_5 %12

RE110K_0402_5%

@

RE110K_0402_5%

@

1

2

CE32 0 .1U_0402_10V7K

ESD@

CE32 0 .1U_0402_10V7K

ESD@1 2

CE260.1U_0402_10V7KCE260.1U_0402_10V7K

1

2

RE4343_0402_1%RE4343_0402_1%

1 2

RE47100K_0402_5%RE47100K_0402_5%

1

2

DE1

ESD@

L03ESDL5V0CG3-2_SOT-523-3

DE1

ESD@


1

1

2

2

3

3

CE16

4.7U_0805_10V4Z

CE16

4.7U_0805_10V4Z

1

2

RE12 0_0402_5%

@

RE12 0_0402_5%

@1 2

R E7 0 1 0K _0 40 2_ 5%R E7 0 1 0K _0 40 2_ 5%1 2

RE94 .7 K_ 04 02 _5 % R E94.7K_0402_5%12


http://slidepdf.com/reader/full/compal-la-9981p-r02-schematics 31/56 A B C D E F G H



A B C D E F G H

1 1

2 2

3 3

4 4

+5V_HDD Source

SATA HDD Connector

ODD Power Control SATA ODD Connector

Pleace near ODD Connector

SHORT DEFAULT

Place CS17 close to JODD

ODD_ENSATA_PRX_DTX_P1

SATA_PRX_DTX_N1

SATA_PTX_DRX_P1SATA _PTX_DRX_N1

SATA_PRX_DTX_P0SATA_PRX_DTX_N0

SATA_PTX_DRX_P0

HDD_DET#

SATA_PTX_DRX_N0

JHDD_P10

ODD_DETECT#<8>

ODD_DA#<11>

SATA_PRX_DTX_N1_C<8>

SATA_PTX_DRX_P1_C<8>

SATA_PRX_DTX_P1_C<8>

SATA_PTX_DRX_N1_C<8>

HDD_DET#<11>

SATA_PTX_DRX_P0_C<8>

SATA_PTX_DRX_N0_C<8>

SATA_PRX_DTX_P0_C<8>

SATA_PRX_DTX_N0_C<8>

ODD_EN#<11>

DEVSLP0<11>

+5VS

B+

+5VS_ODD

+5VS_ODD

+5V_HDD

+5V_HDD +5VS

+5V_HDD

+3VS

Title


Date: Sheet of




LA-9981P 0.2

HDD/ODD



Title


Date: Sheet of




LA-9981P 0.2

HDD/ODD



Title


Date: Sheet of




LA-9981P 0.2

HDD/ODD



JODD

SANTA_202801-1

CONN@

JODD

SANTA_202801-1

CONN@

GND1

A+2

A-3

GND4

B-5

B+6

GND7

DP8

+5V9

+5V10

MD

11

GND12

GND13

NPTH217NPTH1 16GND

15GND14CS16

0.1U_0603_25V7K

CS16

0.1U_0603_25V7K

1

2

CS17

0.1U_0402_25V6KESD@

CS17

0.1U_0402_25V6KESD@

1

2

G

D

S

QS3

2N7002KW_SOT323-3G

D

S

QS3

2N7002KW_SOT323-32

1

3

C S1 08 0 .0 1 U_ 04 0 2_ 16 V7 KC S1 08 0 .0 1 U_ 04 0 2_ 16 V7 K12

C S1 4 0 .0 1U _0 40 2_ 16 V7 KC S1 4 0 .0 1U _0 40 2_ 16 V7 K12

C S1 09 0 .0 1 U_ 04 0 2_ 16 V7 KC S1 09 0 .0 1 U_ 04 0 2_ 16 V7 K12

JP7

JUMP_43X79

@ JP7

JUMP_43X79

@

11

22

C S1 06 0 .0 1 U_ 04 0 2_ 16 V7 KC S1 06 0 .0 1 U_ 04 0 2_ 16 V7 K12

C S 1 1

0 .1 U _ 0 4 0 2 _2 5 V 6 K

C S 1 1

0 .1 U _ 0 4 0 2 _2 5 V 6 K

1

2

C S8 0 .0 1U _0 40 2_ 16 V7 KC S8 0 .0 1U _0 40 2_ 16 V7 K12

CS5

1 0 0 0 P _ 0 4 0 2 _ 5 0 V 7 K

CS5

1 0 0 0 P _ 0 4 0 2 _ 5 0 V 7 K

1

2

C S 1 0

1 0 0 0 P _ 0 4 0 2 _ 5 0 V 7 K

C S 1 0

1 0 0 0 P _ 0 4 0 2 _ 5 0 V 7 K

1

2

C S1 5 0 .0 1U _0 40 2_ 16 V7 KC S1 5 0 .0 1U _0 40 2_ 16 V7 K12

RS6

470K_0402_5%

RS6

470K_0402_5%

1

2

JP13

JUMP_43X79

@JP13

JUMP_43X79

@

11

22

RS7 0_0402_5%RS7 0_0402_5%1 2

CS7

1 0 U _ 0 8 0 5 _1 0 V 6 K

CS7

1 0 U _ 0 8 0 5 _1 0 V 6 K

1

2

CS13

1 U_

0 4 0 2_

6 . 3 V 6 K

CS13

1 U_

0 4 0 2_

6 . 3 V 6 K

1

2

1 0 U _ 0 8 0 5 _1 0 V 6 K

C S 1 2

1 0 U _ 0 8 0 5 _1 0 V 6 K

C S 1 2

1

2

CS6

0 .1 U _ 0 4 0 2 _2 5 V 6 K

CS6

0 .1 U _ 0 4 0 2 _2 5 V 6 K

1

2

RS8 0_0402_5%@RS8 0_0402_5%@1 2

C S9 0 .0 1U _0 40 2_ 16 V7 KC S9 0 .0 1U _0 40 2_ 16 V7 K12

JHDD

SANTA_193202-1CONN@

JHDD

SANTA_193202-1CONN@

GND1

A+2

A-3

GND4

B-5

B+6

GND7

VCC3.38

VCC3.39

VCC3.310

GND11

GND12

GND13

VCC514

VCC515

VCC516

GND17

RESERVED18

GND19

VCC1220

VCC1221

VCC1222

GND23

GND24

S

G

D

QS2

SI3456BDV-T1-E3 1NTSOP6

S

G

D

QS2

SI3456BDV-T1-E3 1NTSOP6

3

6

245

1

C S1 05 0 .0 1 U_ 04 0 2_ 16 V7 KC S1 05 0 .0 1 U_ 04 0 2_ 16 V7 K12

5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

CPU bracket

VGA stand-off

FAN stand-off

Screw Hole

Title


Date: Sheet of




LA-9981P 0.2



Screw HoleTitle


Date: Sheet of




LA-9981P 0.2



Screw HoleTitle


Date: Sheet of




LA-9981P 0.2



Screw Hole

H12

H_2P8@

H12

H_2P8@

1

H4

H_2P8@

H4

H_2P8@

1

FD2FIDUCIAL@FD2FIDUCIAL@

1

H32

H_3P7@

H32

H_3P7@

1

H35

H_3P7X3P2N@

H35

H_3P7X3P2N@

1

H2

H_2P8@

H2

H_2P8@

1

H5

H_2P8@

H5

H_2P8@

1

H10

H_3P3@

H10

H_3P3@

1

H31

H_3P7@

H31

H_3P7@

1

H6

H_3P3@

H6

H_3P3@

1

FD3FIDUCAL@FD3FIDUCAL@

1

H17

H_2P8@

H17

H_2P8@

1

H16

H_2P8@

H16

H_2P8@

1

H33

H_3P7@

H33

H_3P7@

1

FD1FIDUCAL@FD1FIDUCAL@

1

H8

H_2P8@

H8

H_2P8@

1

H9

H_2P8@

H9

H_2P8@

1

H34

H_3P7@

H34

H_3P7@

1

FD4FIDUCIAL@FD4FIDUCIAL@

1

H11

H_2P8@

H11

H_2P8@

1

H18

H_3P3@

H18

H_3P3@

1

H7

H_3P3@

H7

H_3P3@

1

5 4 3 2 1

Page 1Version Change List ( P. I. R. List )



5 4 3 2 1

D D

C C

B B

A A

HW2012/04/2734 Card Reader

27

28

29

30

31

32

33

34

35

17

10

16

14

4

0.2

Solution Description Rev.age TitleItem Issue Descriptionate

Request

Owner

1

2

3

15

12

13

19

20

5

21

22

23

24

25

26

6

7

8

9

The Card reader USB signal is incorrect. SWAP UR1 USB signal P/N

11

18

36

37

38

39

40

41

Title


Date: Sheet of




LA-9981P 0.2

HW-PIR Pa ge.1



Title


Date: Sheet of




LA-9981P 0.2

HW-PIR Pa ge.1



Title


Date: Sheet of




LA-9981P 0.2

HW-PIR Pa ge.1



5 4 3 2 1

Page 2Version Change List ( P. I. R. List )



5 4 3 2 1

D D

C C

B B

A A

Solution Description Rev.age TitleItem Issue Descriptionate

Request

Owner

40

41

43

44

45

46

47

42

48

49

50

51

52

53

54

Title


Date: Sheet of




LA-9981P 0.2

HW-PIR Pa ge.2



Title


Date: Sheet of




LA-9981P 0.2

HW-PIR Pa ge.2



Title


Date: Sheet of




LA-9981P 0.2

HW-PIR Pa ge.2



A B C D

VIN



A B C D

1 1

2 2

3 3

4 4

SMART

Battery:

01 GND1

02 GND2

03 BAT_ALERT

04 SYS_PRES

05 BATT_PRS

06 DAT_SMB

07 CLK_SMB

08 BATT1

09 BATT2

Battery protection:asserts H_PROCHOT# when adaptor isunplugged, keep low for 10mstill SW PROCHOT# is issued by EC

Adapter protection:if battery removed, adaptor only,then trigger the H_PROCHOT#,keep @ in BOM since battery can notbe removed by end user

Other component (37.1)

ADP_I(with selector) Delay adaptor OC H_PROCHOT#

2ms while hybrid power

transition

PH1 under CPU bottem side :

CPU thermal protection at 93 +/- 3 degree C

Erp lot6 Circuit

B A

T T +

BATT++

PSID

H_PROCHOT#

H_PROCHOT#

BATT_PRS

ADPIN PSID-3

PSID-1

PSID-2

H_PROCHOT#

SYS_PRESBAT_ALERT

DAT_SMB

CLK_SMB

BATT_PRS

H_PROCHOT# <30,6>

VCOUT1_PH <30>65W#/90W <30>

VCIN0_PH<30>

ECAGND<30>

VCIN1_PH<30>

ADP_I<30,37>

ACIN <10,30,37,49>

BATT_TEMP <30,37>

EC_SMB_CK1 <30,37>

EC_SMB_DA1 <30,37>

PS_ID <30>

VIN

+5VALW

+3VALW

+3VALW

BATT++BATT+

+EC_VCCA

+3VALW VIN

VIN

+RTCBATT

Title


Date: Sheet of




LA-9981P 0.2


2013/03/09 2014/04/01Com pal Electronics, Inc.

PWR_DCIN/BATT CONN/OTP Title


Date: Sheet of




LA-9981P 0.2



PWR_DCIN/BATT CONN/OTP Title


Date: Sheet of




LA-9981P 0.2



PWR_DCIN/BATT CONN/OTP

PR18

100_0402_5%

PR18

100_0402_5%1 2

PR16

10K_0402_1%

PR16

10K_0402_1%1 2

JRTCLOTES_AAA-BAT-054-K01

CONN@

JRTCLOTES_AAA-BAT-054-K01

CONN@

+1

-2

PH1100K_0402_1%_TSM0B104F4251RZ

PH1100K_0402_1%_TSM0B104F4251RZ

1

2

P Q 1 B

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

P Q 1 B

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

3

5

4

PJPDC

ACES_50299-00501-003

CONN@

PJPDC

ACES_50299-00501-003

CONN@

11

22

33

44

55

GND6

GND7

P C 4

1 0 0 P_

0 4 0 2_

5 0 V 8 J

E M I @

P C 4

1 0 0 P_

0 4 0 2_

5 0 V 8 J

E M I @

1

2

PR2412.1K_0402_1%

PR2412.1K_0402_1%

1

2

PR3

2.2K_0402_5%

PSID@PR3

2.2K_0402_5%

PSID@

1

2

PR1

200K_0402_1%

PR1

200K_0402_1%

1

2

PR26

499K_0402_1%

PR26

499K_0402_1%

1

2

P R 9

1 5 K_

0 4 0 2_

1 %

P S I D @ P R 9

1 5 K_

0 4 0 2_

1 %

P S I D @

1

2

PL4C8BBPH853025_2PEMI@ PL4C8BBPH853025_2PEMI@

1 2

P Q 2 B

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

P Q 2 B

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

3

5

4

PR8

10K_0402_1%

PSID@PR8

10K_0402_1%

PSID@12

P C 8

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

P C 8

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

1

2

P R 6

1 0 0 K_

0 4 0 2_

1 %

P S I D @ P R 6

1 0 0 K_

0 4 0 2_

1 %

P S I D @

1

2

PR31

1M_0402_1%

PR31

1M_0402_1%

1

2

PR15

100_0402_5%

PR15

100_0402_5%1 2

PC5

0.1U_0402_25V6

PC5

0.1U_0402_25V6

1

2

P Q 3 B

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

P Q 3 B

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

3

5

4 P

Q 1 A

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

P Q 1 A

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

6

1

2PR10

1M_0402_1%

PR10

1M_0402_1% 1

2

P C 2

1 0 0 P_

0 4 0 2_

5 0 V 8 J

E M I @

P C 2

1 0 0 P_

0 4 0 2_

5 0 V 8 J

E M I @

1

2

PR433_0402_5%

PSID@PR433_0402_5%

PSID@

1 2

PR33

1M_0402_1%

PR33

1M_0402_1%

1

2

P C 1

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

P C 1

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

1

2

PC14.1U_0402_16V7K

PC14.1U_0402_16V7K

1 2

PBATT

SUYIN_200028MR009G502ZL

CONN@

PBATT

SUYIN_200028MR009G502ZL

CONN@

11

33

44

55

66

88

99

22

77

GND10

GND11

PR20

100_0402_5%

PR20

100_0402_5%1 2

PR27

392K_0402_1%

PR27

392K_0402_1%

1

2

PR7

1M_0402_1%

PR7

1M_0402_1%

1

2

G

D

SPQ4

2N7002W-T/R7_SOT323-3

G

D

SPQ4

2N7002W-T/R7_SOT323-3

2

1

3

PD1

AZC099-04S.R7G_SOT23

EMI@PD1

AZC099-04S.R7G_SOT23

EMI@

VI/O1

VI/O3

VI/O6

VI/O4

Ground2

VBUS5

P R 3 2

1 0 0 K_

0 4 0 2_

1 %

P R 3 2

1 0 0 K_

0 4 0 2_

1 % 1

2

P C 1 5

0 . 0 1 U_

0 4 0 2_

2 5 V 7 K

P C 1 5

0 . 0 1 U_

0 4 0 2_

2 5 V 7 K

1

2

P R 5

3 . 3 K_ 1

2 0 6_

5 % ~ D

P R 5

3 . 3 K_ 1

2 0 6_

5 % ~ D

1

2

P C 3

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

P C 3

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

1

2

E

B

C

PQ5MMST3904-7-F_SOT323~D

PSID@

E

B

C

PQ5MMST3904-7-F_SOT323~D

PSID@2

3

1

PC16.1U_0402_16V7K

PC16.1U_0402_16V7K

1 2 P Q 2 A

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

P Q 2 A

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

6

1

2

PR30

160K_0402_1%

PR30

160K_0402_1%

1 2

P C 7

0 . 0 1 U_

0 4 0 2_

2 5 V 7 K

E M I @

P C 7

0 . 0 1 U_

0 4 0 2_

2 5 V 7 K

E M I @

1

2

G

D S

PQ6FDV301N_G 1NSOT23-3

PSID@

G

D S

PQ6FDV301N_G 1NSOT23-3

PSID@

2

1 3

P R 2 9

1 0 0 K_

0 4 0 2_

1 %

P R 2 9

1 0 0 K_

0 4 0 2_

1 % 1

2

PL2

C8BBPH853025_2P

EMI@

PL2

C8BBPH853025_2P

EMI@

1 2

PL1C8BBPH853025_2P

EMI@PL1C8BBPH853025_2P

EMI@

1 2

PL3

SMB3025500YA_2P

EMI@

PL3

SMB3025500YA_2P

EMI@

1 2

P C 1 3

. 1 U_

0 4 0 2_

1 6 V 7 K

@

P C 1 3

. 1 U_

0 4 0 2_

1 6 V 7 K

@

1

2

P R 2 8

1 0 K_

0 4 0 2_

1 %

P R 2 8

1 0 K_

0 4 0 2_

1 % 1

2

P Q 3 A

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

P Q 3 A

L 2 N 7 0 0 2 D W 1 T 1 G_

S C 8 8 - 6

6

1

2

PR23

150K_0402_1%

PR23

150K_0402_1%

1

2

A B C D



A B C D

1 1

2 2

3 3

4 4

For DT Mode

Iada=0~3.33A(65W)

3S2P : CV = 13.3V CC: 1.54A

4S1P: CV = 17.7V CC: 1.1A

ADP_I = 40*Iadapter*Rsense

Iada=0~4.62A(90W)

Near PL701

for LEARN mode disable

(pulse)

PC720 Close EC pin

DL_CHG

ACDET

C S I N

C S I P

BST

LX_CHG

VCC

R E G N

ACIN

ACDRV

CMSRC

REGN

BST_CHGA

/BATDRV

/BATDRV

DH_CHG

REGN

EC_SMB_DA1<30,36>

EC_SMB_CK1<30,36>

ACIN <10,30,36,49>

ADP_I<30,36>

ACOFF<30>

BATT_TEMP<30,36>

VIN

VIN

+VCHGR

B+

CHG_B+

VIN

BATT++VCHGR

Title


Date: Sheet of




LA-9981P 0.2



PWR_CHARGERTitle


Date: Sheet of




LA-9981P 0.2



PWR_CHARGERTitle


Date: Sheet of




LA-9981P 0.2



PWR_CHARGER

PC7091U_0603_10V6KPC7091U_0603_10V6K

1

2

P R 7 2 0

3 . 3 K_

1 2 0 6_

5 % ~ D

P R 7 2 0

3 . 3 K_

1 2 0 6_

5 % ~ D

1

2

P C 7 1 6

1 0 U_

0 8 0 5_

2 5 V 5 K ~ D

P C 7 1 6

1 0 U_

0 8 0 5_

2 5 V 5 K ~ D

1

2

PD701BAT54HT1G_SOD323-2~D

PD701BAT54HT1G_SOD323-2~D

12

PR716

0.01_1206_1%

PR716

0.01_1206_1%

1

3

4

2

P C 7 0 8

0 . 1 U_

0 4 0 2_

2 5 V 6

P C 7 0 8

0 . 1 U_

0 4 0 2_

2 5 V 6

1

2

P R 7 2 2

4 . 7_

1 2 0 6_

5 %

@ E M I @

P R 7 2 2

4 . 7_

1 2 0 6_

5 %

@ E M I @

1

2

P C 7 1 2

1 0 U_

0 8 0 5_

2 5 V 5 K ~ D

@ P C 7 1 2

1 0 U_

0 8 0 5_

2 5 V 5 K ~ D

@

1

2

PR7092.2_0603_5%

PR7092.2_0603_5%

1 2

PC720100P_0402_50V8J

PC720100P_0402_50V8J

1

2

PC7170.1U_0402_25V6

PC7170.1U_0402_25V6

1 2

PR702

0.01_1206_1%

PR702

0.01_1206_1%

1

3

4

2

PC719

0.1U_0402_25V6

@PC719

0.1U_0402_25V6

@

1 2

P C 7 1 0

1 U_

0 6 0 3_

2 5 V 6 K

P C 7 1 0

1 U_

0 6 0 3_

2 5 V 6 K 1

2

P R 7 1 2

1 5 8 K_

0 4 0 2_

1 %

P R 7 1 2

1 5 8 K_

0 4 0 2_

1 %

1

2

P Q 7 0 4

M D U 1 5 1 6 U R H_

P O W E R D F N 5 6 - 8 - 5

@ P Q 7 0 4

M D U 1 5 1 6 U R H_

P O W E R D F N 5 6 - 8 - 5

@4

5

1 2 3

P R 7 0 7

1 0 0 K_

0 4 0 2_

1 %

P R 7 0 7

1 0 0 K_

0 4 0 2_

1 %

1

2

PR721

4.02K_0402_1%

PR721

4.02K_0402_1%

1

2

P C 7 0 6

0 . 1 U_

0 6 0 3_

2 5 V 7 K

@ E M I @

P C 7 0 6

0 . 1 U_

0 6 0 3_

2 5 V 7 K

@ E M I @

1

2

PR7064.02K_0402_1%

PR7064.02K_0402_1%

12

PC7210.047U_0603_25V7K

PC7210.047U_0603_25V7K

1 2

PR708 0_0402_5%PR708 0_0402_5%1 2

P Q 7 0 5

S I R A 1 4 D P - T 1 G E 3_

P O W E R P A K - S O 8 - 5

P Q 7 0 5

S I R A 1 4 D P - T 1 G E 3_

P O W E R P A K - S O 8 - 5

4

5

1 2 3

PU701

BQ24717

PU701

BQ24717

PHASE19

SRN12

LODRV15

T P

2 1

SCL9

IOUT7

A C P

2

VCC20

CMSRC3

ACDET6

SDA8

ACDRV4

ACOK5

BTST17

HIDRV18

REGN16

A C N

1

/BATDRV11

SRP13

GND14

CELL10

PL7021UH_PCMB053T-1R0MS_7A_20%

EMI@


EMI@

1 2

P C 7 0 2

0 . 1 U_

0 4 0 2_

2 5 V 6

P C 7 0 2

0 . 1 U_

0 4 0 2_

2 5 V 6

1

2

PR710 0_0402_5%PR710 0_0402_5%

1 2

PR714 0_0402_5%~D@ PR714 0_0402_5%~D@ 1 2

P R 7 1 3

1 0 K_

0 4 0 2_

1 %

P R 7 1 3

1 0 K_

0 4 0 2_

1 %

1

2

PL7012.2UH_FDVE1040-H-2R2M-P3_14.2A_20%

PL7012.2UH_FDVE1040-H-2R2M-P3_14.2A_20%

1 2

PR717

0_0402_5%

PR717

0_0402_5%

1

2

P R 7 2 3

3 2 4 K_

0 4 0 2_

1 %

P R 7 2 3

3 2 4 K_

0 4 0 2_

1 %

1

2

PR711

49.9K_0402_1%

PR711

49.9K_0402_1%1 2

PR704

0_0402_5%

PR704

0_0402_5%

1

2

G

D

S

PQ7062N7002KW_SOT323-3G

D

S

PQ7062N7002KW_SOT323-3

2

1

3

PC723

0.01U_0402_25V7K

PC723

0.01U_0402_25V7K

12

P C 7 1 5

6 8 0 P_

0 4 0 2_

5 0 V

7 K

@ E M I @

P C 7 1 5

6 8 0 P_

0 4 0 2_

5 0 V

7 K

@ E M I @

1

2

CSD87312Q3E_SON8-4

PQ701

CSD87312Q3E_SON8-4

PQ701

D11

D23

G2

S4

P Q 7 0 3

M D U 1 5 1 6 U R H_

P O W E R D F N 5 6 - 8 - 5

P Q 7 0 3

M D U 1 5 1 6 U R H_

P O W E R D F N 5 6 - 8 - 5

4

5

1 2 3

PR7034.02K_0402_1%PR7034.02K_0402_1%

1

2

PR705

10_1206_5%

PR705

10_1206_5%1 2

P R 7 2 4

1 0 0 K_

0 4 0 2_

1 %

P R 7 2 4

1 0 0 K_

0 4 0 2_

1 %

1

2

P C 7 1 3

1 0 U_

0 8 0 5_

2 5 V 5 K ~ D

P C 7 1 3

1 0 U_

0 8 0 5_

2 5 V 5 K ~ D

1

2

PQ702 AO4407AL_SO8

PQ702 AO4407AL_SO8

3 65

78

2

4

1

PR715 0_0402_5%~D@ PR715 0_0402_5%~D@1 2

PC71410U_0805_25V5K~D

PC71410U_0805_25V5K~D

1 2

P C 7 0 4

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 7 0 4

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2

+

P C 7 2 4

1 0 0 U_

2 5 V_

M+

P C 7 2 4

1 0 0 U_

2 5 V_

M1

2

PC711

0.01UF_0402_25V7K

PC711

0.01UF_0402_25V7K1 2

P C 7 0 3

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 7 0 3

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2

PC722

0.1U_0402_25V6

PC722

0.1U_0402_25V6

1 2

P C 7 0 5

2 2 0 0 P_

0 4 0 2_

2 5 V 7 K

E M I @

P C 7 0 5

2 2 0 0 P_

0 4 0 2_

2 5 V 7 K

E M I @

1

2

G

D

S

P Q

7 0 8

2 N 7 0 0 2 K W

_ S O T 3 2 3 - 3

G

D

S

P Q

7 0 8

2 N 7 0 0 2 K W

_ S O T 3 2 3 - 3

2

1

3

P C 7 0 1

0 . 1 U_

0 6 0 3_

2 5 V 7 K

P C 7 0 1

0 . 1 U_

0 6 0 3_

2 5 V 7 K 1

2 P R 7 0 1

4 . 7_

0 4 0 2_

1 %

P R 7 0 1

4 . 7_

0 4 0 2_

1 %

1

2

P C 7 0 7 1

U_

0 6 0 3_

2 5 V 6 K

P C 7 0 7 1

U_

0 6 0 3_

2 5 V 6 K

1

2

PC71810U_0805_25V5K~D

PC71810U_0805_25V5K~D

1 2

A B C D E



A B C D E

1 1

2 2

3 3

4 4

3VALWP

TDC 5.95A Peak Current 8.5A OCP current 10.2A

TYP MAXH/S Rds(on): 22mohm , 30mohm L/S Rds(on):10.8mohm ,13.6mohm

5VALWPTDC 5.96A Peak Current 8.51A OCP current 10.2A TYP MAXH/S Rds(on):22mohm , 30mohm L/S Rds(on):10.8mohm , 13.6mohm

Change to 4.7u for TPS51285

VFB=2V

E S R =

1 7 m

o h m

E S R =

1 7 m

o h m

VFB=2V

POK need pull high, it will pull high on VStransfer circuit

Output capacitor ESR need follow

below equation to make sure feed backloop stabilityESR=20mV*L*fsw/2V

Place PD101 close to PU100

5V_EN

3V_EN

C S 1

BST_5V

LX_5V

F B_

5 V

UG_5V

BST_3V

LG _5V

5V_EN

C S 2

F B_

3 V

3/5V_B+

LX_3V

UG_3V

LG_3V

3/5V_B+

3V_EN

3V_EN

5V_EN

VCOUT0_PH#<30>

EC_ON<30>

+5VALWP+3VALW +5VALW+3VALWP

+5VALWP+3VALWP

B+

+5VALWP

+3VLP

VL

3/5V_B+

Title


Date: Sheet of




LA-9981P 0.2



PWR_3.3VALWP/5VALWP Title


Date: Sheet of




LA-9981P 0.2



PWR_3.3VALWP/5VALWP Title


Date: Sheet of




LA-9981P 0.2



PWR_3.3VALWP/5VALWP


EMI@


EMI@

1 2

PJP103

PAD-OPEN4x4m

@ PJP103

PAD-OPEN4x4m

@1 2

PR10610K_0402_1%

PR10610K_0402_1%1 2

PR1112.2_0402_5%

PR1112.2_0402_5%

1 2

PR102

2.2K_0402_5%

PR102

2.2K_0402_5%1 2

P R 1 1 3

4 . 7_

1 2 0 6_

5 %

@ E M I @

P R 1 1 3

4 . 7_

1 2 0 6_

5 %

@ E M I @

1

2

+

P C 1 0 1

2 2 0 U_

6 . 3 V_

M

+

P C 1 0 1

2 2 0 U_

6 . 3 V_

M

1

2

PR103

2.2_0402_5%

PR103

2.2_0402_5%1 2

PL100

2.2UH_PCMB063T-2R2MS_8A_20%

PL100

2.2UH_PCMB063T-2R2MS_8A_20%12

P Q 1 0 4

M D V 1 5 2 5 U R H 1 N P D F N 3 3 - 8

P Q 1 0 4

M D V 1 5 2 5 U R H 1 N P D F N 3 3 - 8

3

5

2

4

1

P C 1 1 5

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 1 1 5

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2

P C 1 0 0

4 . 7 U_

0 6 0 3_

6 . 3 V 6 K

P C 1 0 0

4 . 7 U_

0 6 0 3_

6 . 3 V 6 K

1

2

P C 1 0 6

1 U_

0 6 0 3_

1 0 V 6 K

P C 1 0 6

1 U_

0 6 0 3_

1 0 V 6 K

1

2

PJP102

PAD-OPEN4x4m

@PJP102

PAD-OPEN4x4m

@1 2

PR105

84.5K_0402_1%

PR105

84.5K_0402_1%

1 2

PC1100.1U_0402_10V7K

PC1100.1U_0402_10V7K

1 2

PC102100P_0402_50V8J@ PC102100P_0402_50V8J@

1 2

PR10415K_0402_1%

PR10415K_0402_1%1 2

PC108100P_0402_50V8J

@PC108100P_0402_50V8J

@

1 2

PL1012.2UH_PCMB063T-2R2MS_8A_20%

PL1012.2UH_PCMB063T-2R2MS_8A_20%

1 2

P C 1 0 5

1 U_

0 6 0 3_

2 5 V 6 K

@

P C 1 0 5

1 U_

0 6 0 3_

2 5 V 6 K

@

1

2

P Q 1 0 3

M D V 1 5 2

8 U R H 1 N P D F N 3 3 - 8

P Q 1 0 3

M D V 1 5 2

8 U R H 1 N P D F N 3 3 - 8

3

5

2

4

1

PR10710K_0402_1%

PR10710K_0402_1%1 2

P C 1 1 1

6 8 0 P_

0 6 0 3_

5 0 V 8 J

@ E M I @

P C 1 1 1

6 8 0 P_

0 6 0 3_

5 0 V 8 J

@ E M I @

1

2

TPS51225CRUKR_QFN20_3X3

PU100

TPS51225CRUKR_QFN20_3X3

PU100

C S 1

1

V F B 1

2

V R E G 3

3

V F B 2

4

C S 2

5

EN26

PGOOD7

SW28

VBST29

DRVH210

D R V L 2

1 1

V I N

1 2

V R E G 5

1 3

V O 1

1 4

D R V L 1

1 5

DRVH116

VBST117

SW118

VCLK19

EN120

PAD21

P Q 1 0 2

M D V 1 5 2 5 U R H 1 N P D F N 3 3 - 8

P Q 1 0 2

M D V 1 5 2 5 U R H 1 N P D F N 3 3 - 8

3

5

2

4

1

PC1091U_0603_10V6K

PC1091U_0603_10V6K

1 2

PD101

EMI@


PD101

EMI@


1

1

2

2

3

3

PJP100

PAD-OPEN4x4m

@PJP100

PAD-OPEN4x4m

@

1 2

P C 1 1 4

2 2 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

P C 1 1 4

2 2 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

1

2

PR101 0_0402_5%~D@ PR101 0_0402_5%~D@

1 2

PR114200_0402_5%

@PR114200_0402_5%

@

1 2

PJP101

PAD-OPEN4x4m

@ PJP101

PAD-OPEN4x4m

@

1 2

P C 1 1 3

0 . 1 U_

0 4 0 2_

2 5 V 6

@ E M I @

P C 1 1 3

0 . 1 U_

0 4 0 2_

2 5 V 6

@ E M I @

1

2

P Q 1 0 1

M D

V 1 5 2 8 U R H 1 N P D F N 3 3 - 8

P Q 1 0 1

M D

V 1 5 2 8 U R H 1 N P D F N 3 3 - 8

3

5

2

4

1

+

P C 1 0 7

2 2 0 U_

6 . 3 V_

M

+

P C 1 0 7

2 2 0 U_

6 . 3 V_

M

1

2

PR100 0_0402_5%~D@ PR100 0_0402_5%~D@1 2

P C 1 1 2

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 1 1 2

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2

P C 1 0 3

6 8 0 P_

0 6 0 3_

5 0 V 8 J

@ E M I @

P C 1 0 3

6 8 0 P_

0 6 0 3_

5 0 V 8 J

@ E M I @

1

2

P R 1 1 2

4 . 7_

1 2 0 6_

5 %

@ E M I @

P R 1 1 2

4 . 7_

1 2 0 6_

5 %

@ E M I @

1

2

PR1096.49K_0402_1%

PR1096.49K_0402_1%1 2

PC104

0.1U_0402_10V7K

PC104

0.1U_0402_10V7K1 2

PR108

90.9K_0402_1%

PR108

90.9K_0402_1%

1

2

A B C D

PJP401 @PJP401 @



A B C D

1 1

2 2

3 3

4 4

Note:Iload(max)=3AFB=0.6V

Note:Iload(max)=2.5A

Rup

Rdown

Note:Iload(max)=3AFB=0.6V

Note:Iload(max)=2.5A

Rup

Rdown

SUSP#

FB_1.5VSP

LX_1.5VSP

+1.5VSP_ON

PXS_PWREN

FB_1.8VSP

LX_1.8VSP

+1.8VSP_ON

SUSP# <28,30,40>

PXS_PWREN <10,11,43,44,50>

+3VALW

+1.5VSP +1.5VS

+1.5VSP

+3VALW

+1.8VSP +1.8VS

+1.8VSP

Title


Date: Sheet of




LA-9981P 0.2



PWR_1.5VSP / 1.8VSP Title


Date: Sheet of




LA-9981P 0.2



PWR_1.5VSP / 1.8VSP Title


Date: Sheet of




LA-9981P 0.2



PWR_1.5VSP / 1.8VSP

JUMP_43X79JUMP_43X79

11

22

PC40522U_0805_6.3VAM

PC40522U_0805_6.3VAM

1

2

PR402

10K_0402_1%

PR402

10K_0402_1%

1

2

P C 4 0 0

2 2 U

_ 0 8 0 5_

6 . 3 V A M

P C 4 0 0

2 2 U

_ 0 8 0 5_

6 . 3 V A M 1

2

PU400

SY8003DFC_DFN8_2X2

PU400

SY8003DFC_DFN8_2X2

NC5

IN3

PGND4

PG2

FB1

LX6

EN7

SGND8PGND9

P C 4 0 2

2 2 U

_ 0 8 0 5_

6 . 3 V A M

P C 4 0 2

2 2 U

_ 0 8 0 5_

6 . 3 V A M 1

2

P C 4 0 1

6 8 0 P_

0 4 0 2_

5 0 V 7 K

@ E M I @

P C 4 0 1

6 8 0 P_

0 4 0 2_

5 0 V 7 K

@ E M I @

1

2

P R 4 0 5

4 . 7_

0 6 0 3_

5 %

@ E M I @

P R 4 0 5

4 . 7_

0 6 0 3_

5 %

@ E M I @

1

2

PR401

0_0402_5%

PR401

0_0402_5%1 2

P C 6 0 1

6 8 0 P_

0 4 0 2_

5 0 V 7 K

@ E M I @

P C 6 0 1

6 8 0 P_

0 4 0 2_

5 0 V 7 K

@ E M I @

1

2

P C 6 0 2

2 2 U_

0 8 0 5_

6 . 3 V A M

V G A @

P C 6 0 2

2 2 U_

0 8 0 5_

6 . 3 V A M

V G A @

1

2

PJP600

JUMP_43X79

@PJP600

JUMP_43X79

@

11

22

PR40315K_0402_1%

PR40315K_0402_1%

1

2

PJP601

JUMP_43X79

@PJP601

JUMP_43X79

@

11

22

P C 4 0 4

6 8 P_

0 4 0 2_

5 0 V 8 J

P C 4 0 4

6 8 P_

0 4 0 2_

5 0 V 8 J

1

2

PL6001UH_PH041H-1R0MS_3.8A_20%

VGA@

PL6001UH_PH041H-1R0MS_3.8A_20%

VGA@

1 2

P R 6 0 5

4 . 7_

0 6 0 3_

5 %

@ E M I @

P R 6 0 5

4 . 7_

0 6 0 3_

5 %

@ E M I @

1

2

P C 4 0 3

0 . 1 U_

0 4 0 2_

1 6 V 7 K

@ P C 4 0 3

0 . 1 U_

0 4 0 2_

1 6 V 7 K

@

1

2

PU600

SY8003DFC_DFN8_2X2

VGA@

PU600

SY8003DFC_DFN8_2X2

VGA@

NC5

IN3

PGND4

PG2

FB1

LX6

EN7

SGND8PGND9

P C 6 0 3

0 . 1 U_ 0

4 0 2_

1 6 V 7 K

@

P C 6 0 3

0 . 1 U_ 0

4 0 2_

1 6 V 7 K

@

1

2

PR60210K_0402_1%

VGA@PR602

10K_0402_1%

VGA@

1

2

PC605

22U_0805_6.3VAMVGA@

PC605

22U_0805_6.3VAMVGA@

1

2

PR6041M_0402_5%

VGA@PR6041M_0402_5%

VGA@

1

2

PR404

1M_0402_5%

PR404

1M_0402_5%

1

2

PJP400

JUMP_43X79

@PJP400

JUMP_43X79

@

11

22

PR6010_0402_5%

VGA@PR6010_0402_5%

VGA@

1 2

PL400

1UH_PH041H-1R0MS_3.8A_20%

PL400

1UH_PH041H-1R0MS_3.8A_20%1 2

P C 6 0 4

6 8 P_

0 4 0 2_

5 0 V 8 J

V G A @

P C 6 0 4

6 8 P_

0 4 0 2_

5 0 V 8 J

V G A @

1

2

P C 6 0 0

2 2 U_

0 8 0 5_

6 . 3 V A M

V G A @

P C 6 0 0

2 2 U_

0 8 0 5_

6 . 3 V A M

V G A @

1

2

PR603

20K_0402_1%

VGA@PR603

20K_0402_1%

VGA@

1

2

5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A


FB = 0.6V

The current limit is set to 6A, 8A or 12A when this pinis pull low, floating or pull high

EN pin don't floatingIf have pull down resistor at HW side, pls delete PR301

Pin 7 BYP is for CS.Common NB can delete +3VALW and PC313

Rup

Rdown

Vout=0.6V* (1+Rup/Rdown) Vout=1.05V

VFB=0.6V

+1.05VSPTDC 5A Peak Current 6.6A OCP current 8A

SNB_1.05V

B+_1.05V

LX_1.05V

ILMT_1.05V

ILMT_1.05V LDO_3V

BST_1.05V

+1.05V_PGOOD

SUSP# <28,30,39>

+1.05V_PGOOD<30>

+3VALW

B+

+1.05VSPLDO_3V

+1.05VSP

+1.05VS

+3VS

Title


Date: Sheet of





0.2

PWR_+VCCIO

C


2013/03/09 2014/04/01 Title


Date: Sheet of





0.2

PWR_+VCCIO

C


2013/03/09 2014/04/01 Title


Date: Sheet of





0.2

PWR_+VCCIO

C


2013/03/09 2014/04/01

PR307

20K_0402_1%

PR307

20K_0402_1%

1

2

P C 3 0 8

4 7 U_

0 8 0 5_

6 . 3 V 6 M

P C 3 0 8

4 7 U_

0 8 0 5_

6 . 3 V 6 M 1

2

PR3000_0402_5%

PR3000_0402_5%1 2

PR3024.7_1206_5%

@EMI@ PR3024.7_1206_5%

@EMI@

1 2

P C 3 0 6

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 3 0 6

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2

P R 3 0 5

1 5 K_

0 4 0 2_ 1 %

P R 3 0 5

1 5 K_

0 4 0 2_ 1 % 1

2

PR306

0_0402_5%

@ PR306

0_0402_5%

@

1

2

P C 3 0 5

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 3 0 5

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2

PJP300

JUMP_43X118

@ PJP300

JUMP_43X118

@

11

22

P C 3 1 0

2 2 U_

0 8 0 5_

6 . 3 V A M

P C 3 1 0

2 2 U_

0 8 0 5_

6 . 3 V A M 1

2

P C 3 1 2

4 . 7 U_

0 6 0 3_

6 . 3 V 6 K

P C 3 1 2

4 . 7 U_

0 6 0 3_

6 . 3 V 6 K

1

2

P C 3 0 7

3 3 0 P_

0 4 0 2_

5 0 V 7 K

P C 3 0 7

3 3 0 P_

0 4 0 2_

5 0 V 7 K

1

2

PL301

1UH_PCMB063T-1R0MS_12A_20%

PL301

1UH_PCMB063T-1R0MS_12A_20%1 2

PR3030_0603_5%PR3030_0603_5%

1 2

P C 3 0 4

0 . 1 U_ 0 4 0 2_

2 5 V 6

@ E M I @

P C 3 0 4

0 . 1 U_ 0 4 0 2_

2 5 V 6

@ E M I @

1

2 P C 3 0 3

2 2 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

P C 3 0 3

2 2 0 0 P_ 0

4 0 2_

5 0 V 7 K

E M I @

1

2

PC3020.1U_0603_25V7K

PC3020.1U_0603_25V7K

1 2

PR30810K_0402_5%

PR30810K_0402_5%

1 2

PL302SUPPRE_ FBMA-L11-453215-800LMA90T_1812

EMI@ PL302SUPPRE_ FBMA-L11-453215-800LMA90T_1812

EMI@

1 2

PC300

0.22U_0402_10V6K

@ PC300

0.22U_0402_10V6K

@

1

2

P C 3 0 9

4 7 U_

0 8 0 5_

6 . 3 V 6 M

P C 3 0 9

4 7 U_

0 8 0 5_

6 . 3 V 6 M 1

2

PU300

SY8206DQNC_QFN10_3X3

PU300


IN8

BYP7

PG2

ILMT3

LX10

FB4

LDO5

GND9

EN1

BS6

P C 3 1 3

4 . 7 U_

0 6 0 3_

6 . 3 V 6 K

P C 3 1 3

4 . 7 U_

0 6 0 3_

6 . 3 V 6 K

1

2

P C 3 1 1

2 2 U_

0 8 0 5_

6 . 3 V A M

P C 3 1 1

2 2 U_

0 8 0 5_

6 . 3 V A M 1

2

PC301680P_0603_50V7K

@EMI@ PC301680P_0603_50V7K

@EMI@

1 2

PR301

1M_0402_1%

PR301

1M_0402_1%

1

2

PR304

0_0402_5%

@ PR304

0_0402_5%

@

1

2

5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

1.35VPTDC 6A Peak Current 8A

OCP current 10A

0.675Volt +/- 5%TDC 0.7A Peak Current 1A

DL_1.35V

T O N_

1 . 3 5 V

BOOT_1.35V

1.35V_B+

1.35V_B+

DH_1.35V

SW_1.35V

CS_1.35V

BST_1.35V

VDD_1.35V

F B_

1 . 3 5 V

VTTREF_1.35V

E N_

1 . 3 5 V

E N_

0 . 6 7 5 V S P

SYSON<30>

0.675V_DDR_VTT_ON<17>

B+

+1.35VP

+5VALW

+5VALW

+1.35VP

+0.675VSP

+1.35VP

+1.35VP

+1.35VP +1.35V

+0.675VSP +0.675VS

Title


Date: Sheet of




LA-9981P 0.2



PWR_+1.35VP/0.675VSP Title


Date: Sheet of




LA-9981P 0.2



PWR_+1.35VP/0.675VSP Title


Date: Sheet of




LA-9981P 0.2



PWR_+1.35VP/0.675VSP

PC2100.033U_0402_16V7KPC2100.033U_0402_16V7K

1

2

PC200

0.1U_0603_25V7K

PC200

0.1U_0603_25V7K

1

2

PR2010_0402_5%

PR2010_0402_5%

1 2

PR206

5.1_0603_5%

PR206

5.1_0603_5%1 2

PJP201

JUMP_43X118

@ PJP201

JUMP_43X118

@

11

22

PJP200

JUMP_43X118

@ PJP200

JUMP_43X118

@

11

22

PQ200 AON7408L

PQ200 AON7408L 4

5

1 2 3

PR2002.2_0603_5%

PR2002.2_0603_5%1 2

PR2034.7_1206_5%

@EMI@ PR2034.7_1206_5%

@EMI@

1

2

P C 2 1 1

1 0 U_

0 8 0 5_

6 . 3 V 6 K

P C 2 1 1

1 0 U_

0 8 0 5_

6 . 3 V 6 K

1

2

PC207680P_0402_50V7K

@EMI@ PC207680P_0402_50V7K

@EMI@

1

2

PQ201 AON7702A

PQ201 AON7702A 4

5

1 2 3

PC2091U_0603_10V6K

PC2091U_0603_10V6K

1

2

PR20754.9K_0402_1%

PR20754.9K_0402_1%1 2

PL200

1UH_PCMB063T-1R0MS_12A_20%

PL200

1UH_PCMB063T-1R0MS_12A_20%1 2

PC2030.1U_0402_10V7K

@ PC2030.1U_0402_10V7K

@

1

2

PC2041U_0603_10V6K

PC2041U_0603_10V6K

1 2

P C 2 1 2

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 2 1 2

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2


EMI@


EMI@

1 2

PR2081M_0402_1%

PR2081M_0402_1%

1 2

PR2020_0402_5%

PR2020_0402_5%1 2

PC202

0.1U_0402_10V7K

@PC202

0.1U_0402_10V7K

@ 1

2

P C 2 0 1

2 2 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @ P C 2 0 1

2 2 0 0 P_

0 4 0 2_

5 0 V 7 K

E M I @

1

2

PR20468.1K_0402_1%PR20468.1K_0402_1%

1

2

PU200

RT8207MZQW_WQFN20_3X3

PU200

RT8207MZQW_WQFN20_3X3

VTTSNS2

F B

6

S 5

8

P G O O D

1 0

VDDP12

P H A S E

1 6

B O O T

1 8

VTTREF4

PGND14

VTTGND1

GND3

VDDQ5

S 3

7

T O N

9

VDD11

CS13

LGATE15 U

G A T E

1 7

V T T

2 0

V L D O I N

1 9

PAD21

+

P C 2 1 3

3 3 0 U_

2 . 5 V_

M

+

P C 2 1 3

3 3 0 U_

2 . 5 V_

M 1

2

PR205

11.8K_0402_1%

PR205

11.8K_0402_1%1 2

P C 2 0 8

0 . 1 U_

0 4 0 2_

2 5 V 6

@ E M I @ P C 2 0 8

0 . 1 U_

0 4 0 2_

2 5 V 6

@ E M I @

1

2

PJP203

JUMP_43X39

@ PJP203

JUMP_43X39

@

11

22

P C 2 0 6

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 2 0 6

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2

P C 2 0 5

1 0 U_

0 8 0 5_

6 . 3 V 6 K

P C 2 0 5

1 0 U_

0 8 0 5_

6 . 3 V 6 K

1

2

5 4 3 2 1

IMON CPU

VREF_CPU

%%

%%



5 4 3 2 1

D D

C C

B B

A A

CPU_CORETDC 10A Peak Current 32A OCP current 40A Load line -2mV/A

B value:4250K Near PU502.

B value:3435K

Near PL502.

TI recommend 1nF

EMI Part (47.1)

Check are there a pair 100Ω

at HW side and close to CPU.

+VCC_PWR_SRC

SW_CPU2PWM1

V R_

S V I D_

D A T

V R_

S V I D_

A L R T #

V R_

S V I D_

C L K

VREF_CPU

COMP_CPU

DROOP_CPU

V 5 A_ C

P U

CSN1_CPU

CSP1_CPU

+VCC_PWR_SRC VBAT_CPU

O-USR

F-IMAX

B-RAMPOCP_CPU

IMON_CPU

THERM_CPU

SLEWA_CPU

CSN1_CPU

CSP1_CPU

PWM1

SKIP#1

SKIP#

VR _ENABLE

SKIP#1

VR_ON <13,30>

VR_SVID_ALRT#<13>

VR_SVID_DAT<13>

VR_SVID_CLK<13>

VSSSENSE<13,15>

VCCSENSE<13>

H _V R_ RE AD Y < 13 >

VR_HOT#<30>

IMVP_PWRGD <30>

+CPU_CORE

B+

+3VS

+1.05VS

+3VS

+5VS

+5VS

+3VS

+3VS

Title


Date: Sheet of




LA-9981P 0.2



PWR_VCORE Title


Date: Sheet of




LA-9981P 0.2



PWR_VCORE Title


Date: Sheet of




LA-9981P 0.2



PWR_VCORE

P R 5 1 4

7 5_

0 4 0 2_

1 %@

P R 5 1 4

7 5_

0 4 0 2_

1 %@

1

2

PR533

56_0402_1%

PR533

56_0402_1%

1 2

PR535

0_0402_5%~D

@PR535

0_0402_5%~D

@

1 2

P R 5 1 3

3 9 K_

0 4 0 2_

5 %

P R 5 1 3

3 9 K_

0 4 0 2_

5 %

1

2

PR528

75_0402_5%

@

PR528

75_0402_5%

@

1

2

P R 5 0 9

1 5 0 K_

0 4 0 2_

1 %

P R 5 0 9

1 5 0 K_

0 4 0 2_

1 %

1

2

P R 5 0 2

9 . 3 1 K_

0 4 0 2_

1 %

P R 5 0 2

9 . 3 1 K_

0 4 0 2_

1 %

1

2

PC5110.082U_0402_16V7K

PC5110.082U_0402_16V7K

1

2

P C 5 0 6

4 7 P_

0 4 0 2_

5 0 V 8 J

P C 5 0 6

4 7 P_

0 4 0 2_

5 0 V 8 J

1

2

PR531

3.65K_0402_1%

PR531

3.65K_0402_1%12

P C 5 1 7

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 5 1 7

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2

P R 5 3 4

4 . 7_

1 2 0 6_

5 %

@ E M I @

P R 5 3 4

4 . 7_

1 2 0 6_

5 %

@ E M I @

1

2

PU502

CSD97374CQ4M_SON8_3P5X4P5

PU502

CSD97374CQ4M_SON8_3P5X4P5

PGND13

VDD2

SKIP#1

VSW4PWM

8

VIN5

BOOT7

BOOT_R6

PGND29

P R 5 0 6

1 5 0 K_

0 4 0 2_

1 %

P R 5 0 6

1 5 0 K_

0 4 0 2_

1 %

1

2

PR5295.76K_0402_1%

PR5295.76K_0402_1%

12PR517

16.5K_0402_1%

PR517

16.5K_0402_1%

1

2

P C 5 2 1

2 2 0 0 P_

0 4 0 2_

2 5 V 7 K

E M I @

P C 5 2 1

2 2 0 0 P_

0 4 0 2_

2 5 V 7 K

E M I @

1

2

PC512

.1U_0402_16V7K

@

PC512

.1U_0402_16V7K

@

1

2

PU501

TPS51622RSM_QFN32_4X4

PU501

TPS51622RSM_QFN32_4X4

S L E W A

1 5

V B A T

1 6

T H E R M

1 4

GFB23

PU321

C O M P

2 6

V C L K

3 1

V 5 A

2 8

D R O O P

2 5

A L E R T #

3 2

VFB24

N/C22

P A D

3 3

G N D

2 9

PGOOD3

V R

_ H O T #

3 0

V R E F

2 7

VDIO1

VDD2

N/C4

PWM25

PWM16

SKIP#7

VR_ON8

I M O N

1 3

O C P - I

1 2

B - R

A M P

1 1

F - I M

A X

1 0

O - U

S R

9

CSP220

CSP117

CSN219

CSN118

PC5100.082U_0402_16V7K

PC5100.082U_0402_16V7K

1

2

PR510

75_0402_1%

@PR510

75_0402_1%

@ 1

2

PR5153.01K_0402_1%

PR5153.01K_0402_1%

1

2

PL502

0.22UH_PCMB104T-R22MS_35A_20%

PL502

0.22UH_PCMB104T-R22MS_35A_20%1

3

4

2

PR540

0_0402_5%

@ PR540

0_0402_5%

@ 12

PR532

10K_0402_1%

PR532

10K_0402_1%1 2

PC502

1000P_0402_50V7K

PC502

1000P_0402_50V7K1 2

PH50110K_0402_1%_TSM0A103F34D1RZPH50110K_0402_1%_TSM0A103F34D1RZ

1

2


EMI@PL501SUPPRE_ FBMA-L11-453215-800LMA90T_1812

EMI@

1 2

PR530

130_0402_1%

PR530

130_0402_1%

1

2

PC501 0.1U_0402_25V6PC501 0.1U _0402_25V6

1 2

P C 5 1 8

1 0 U_

0 8 0 5_

2 5 V 6 K

P C 5 1 8

1 0 U_

0 8 0 5_

2 5 V 6 K

1

2 P C 5 1 9

0 . 1 U_

0 4 0 2_

2 5 V 6

@ E M I @

P C 5 1 9

0 . 1 U_

0 4 0 2_

2 5 V 6

@ E M I @

1

2

+

P C 5 1 5

1 0 0 U_

2 5 V_

M

+

P C 5 1 5

1 0 0 U_

2 5 V_

M1

2

PR516

1_0603_5%

PR516

1_0603_5%

12

PH502100K_0402_1%_TSM0B104F4251RZ

PH502100K_0402_1%_TSM0B104F4251RZ

1

2

PC507

0.33U_0402_10V6K

PC507

0.33U_0402_10V6K

1

2

P R 5 0 1

5 2 3 K_

0 4 0 2_

1 %

P R 5 0 1

5 2 3 K_

0 4 0 2_

1 %

1

2

PC505

1U_0603_10V6K

PC505

1U_0603_10V6K

1

2

PR526

54.9_0402_1%

PR526

54.9_0402_1%

1

2

P R 5 0 7

7 5_

0 4 0 2_

1 %

@

P R 5 0 7

7 5_

0 4 0 2_

1 %

@

1

2

PC503

1U_0603_10V6K

PC503

1U_0603_10V6K

1

2

P R 5 0 3

7 5 K_

0 4 0 2_

1 %

P R 5 0 3

7 5 K_

0 4 0 2_

1 %

1

2

PC513

390P_0402_50V7K

@ PC513

390P_0402_50V7K

@

12

PR536 2.2_0603_5%PR536 2.2_0603_5%

12

P R 5 0 4

4 9 9 K_

0 4 0 2_

1 %

P R 5 0 4

4 9 9 K_

0 4 0 2_

1 %

1

2

P C 5 0 9

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

P C 5 0 9

1 0 0 0 P_

0 4 0 2_

5 0 V 7 K

1

2

PR519

10_0603_1%

PR519

10_0603_1%1 2

PC504

1U_0402_6.3V6K

PC504

1U_0402_6.3V6K

1

2

PR524

10K_0402_1%~D

PR524

10K_0402_1%~D

12

PC522

1U_0402_6.3VX5R

@PC522

1U_0402_6.3VX5R

@ 1

2

+

P C 5 1 6

1 0 0 U_

2 5 V_

M

+

P C 5 1 6

1 0 0 U_

2 5 V_

M1

2

PC5141500P_0402_50V7K

PC5141500P_0402_50V7K

1 2

PR522

0_0402_5%

PR522

0_0402_5%1 2

P R 5 0 5

7 5 K_

0 4 0 2_

1 %

P R 5 0 5

7 5 K_

0 4 0 2_

1 %

1

2

PR50810K_0402_5%~D

PR50810K_0402_5%~D

1 2

P C 5 2 0

6 8 0 P_

0 4 0 2_

5 0 V 7 K

@ E M I @

P C 5 2 0

6 8 0 P_

0 4 0 2_

5 0 V 7 K

@ E M I @

1

2

P C 5 0 8

4 7 0 0 P_

0 6 0 3_

5 0 V 7 K

P C 5 0 8

4 7 0 0 P_

0 6 0 3_

5 0 V 7 K

1

2

P R 5 1 2

1 0 K_

0 4 0 2_

5 % ~ D

P R 5 1 2

1 0 K_

0 4 0 2_

5 % ~ D

1

2

PR5182.32K_0402_1%

PR5182.32K_0402_1%

1 2

5 4 3 2 1

+1.2VSP_B+B+

PL1100HCB2012KF-121T50_0805

VGA@_EMI@ PL1100HCB2012KF-121T50_0805

VGA@_EMI@

1 2



5 4 3 2 1

D D

C C

B B

A A

TDC=9A Peak Current=13A OCP=16A

+VDDCIPTDC 7A Peak Current 13A

OCP current 16A FB = 0.6V

The current limit is set to 8A, 12A or 16A when this pinis pull low, floating or pull high

Pin 7 BYP is for CS.Common NB can delete +3VALW and PC1205

Vout=0.6V* (1+Rup/Rdown)

Vout=0.9V

VFB=0.6V

Rup

Rdown

Low 0.9V

0.95VHigh

VDDCI_VID (GPIO_6)

BST_+1.2VSP

SW_+1.2VSP

UG_+1.2VSP

LG_+1.2VSP

PXS_PWREN

TRIP_+1.2VSP

EN_+1.2VSP

FB_+1.2VSP

RF_+1.2VSP

SNB_1.05V

B+_VDDCI

PXS_PWREN

LX_VDDCI

ILMT_VDDCI

ILMT_VDDCI LDO_3V_VDDCI

BST_VDDCI

V DDCI_S EN < 52>

PXS_PWREN <10,11,39,44,50>

GPU_GPIO6 < 49>

B+

+5VALW

+1.35VGPUP

+1.35VGPUP +1.35VS_VGA

+3VS

+3VALW

B+

+VDDCIPLDO_3V_VDDCI

+VDDCIP +VDDCI

+3VGS

Title

Size D ocument Number Rev

Date: Sheet of


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFOR MATION. THIS SHEET MAY NO T BE TRANSFERE D FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


LA-9981P 0.2



PWR_+1.35VGPU/VDDCIP Title


Date: Sheet of




LA-9981P 0.2



PWR_+1.35VGPU/VDDCIP Title


Date: Sheet of




LA-9981P 0.2



PWR_+1.35VGPU/VDDCIP

P C

1 2 0 5

4 . 7

U_

0 6 0

3_

6 . 3

V 6 K

V G A @

P C

1 2 0 5

4 . 7

U_

0 6 0

3_

6 . 3

V 6 K

V G A @

1

2

PC12100.1U_0603_25V7K

VGA@PC1210

0.1U_0603_25V7K

VGA@

1 2

PU1100

TPS51212DSCR_SON10_3X3

VGA@PU1100

TPS51212DSCR_SON10_3X3

VGA@

EN3

TRIP2

V5IN7

DRVH9

SW8

DRVL6

VBST10

TST5

VFB4

PGOOD1

TP11

PC11030.1U_0603_25V7K

VGA@PC1103

0.1U_0603_25V7K

VGA@

1 2

P C 1 1 0 0

0 . 1

U_

0 4 0 2

_ 2 5 V 6

@ E M I @

P C 1 1 0 0

0 . 1

U_

0 4 0 2

_ 2 5 V 6

@ E M I @

1

2

P C 1 1 0 4

0 . 1

U_

0 4 0 2

_ 1 6 V 7 K

@

P C 1 1 0 4

0 . 1

U_

0 4 0 2

_ 1 6 V 7 K

@

1

2

PR121210K_0402_5%

VGA@PR121210K_0402_5%

VGA@

12

PR120910K_0402_1%

VGA@ PR120910K_0402_1%

VGA@

1 2


VGA@ PL11011UH_PCMB063T-1R0MS_12A_20%

VGA@

1 2

PR11012.2_0603_5%

VGA@PR1101

2.2_0603_5%

VGA@

1 2

G

D

S

PQ12012N7002W-T/R7_SOT323-3

VGA@

G

D

S

PQ12012N7002W-T/R7_SOT323-3

VGA@

2

1

3

PR1201

1M_0402_1%

VGA@

PR1201

1M_0402_1%

VGA@

1

2

P C 1 1 0 1

2 2 0 0 P

_ 0 4 0 2

_ 5 0 V 7 K

V G A @

_ E M I @

P C 1 1 0 1

2 2 0 0 P

_ 0 4 0 2

_ 5 0 V 7 K

V G A @

_ E M I @

1

2

PC1106680P_0402_50V7K

@EMI@PC1106680P_0402_50V7K

@EMI@ 1

2

PR11044.7_1206_5%

@[email protected]_1206_5%

@EMI@

1

2

P C 1 2 0 2

1 0 U

_ 0 8 0 5

_ 2 5 V 6 K

V G A @

P C 1 2 0 2

1 0 U

_ 0 8 0 5

_ 2 5 V 6 K

V G A @

1

2

PR120420K_0402_1%

VGA@PR120420K_0402_1%

VGA@

1

2

PC11051U_0603_10V6K

VGA@PC11051U_0603_10V6K

VGA@ 1

2

PR1105

470K_0402_1%

VGA@PR1105

470K_0402_1%

VGA@

1

2

PR12000_0603_5%

VGA@PR12000_0603_5%

VGA@

1 2

P C 1 2

1 3

4 . 7

U_

0 6 0 3

_ 6 . 3

V 6 K

V G A @

P C 1 2

1 3

4 . 7

U_

0 6 0 3

_ 6 . 3

V 6 K

V G A @

1

2

P C 1 2 0 4

1 0 U

_ 0 8 0 5

_ 2 5 V 6 K

V G A @

P C 1 2 0 4

1 0 U

_ 0 8 0 5

_ 2 5 V 6 K

V G A @

1

2

PR12100_0402_5%~D

VGA@ PR12100_0402_5%~D

VGA@

1 2

PQ1101 AON7702A

VGA@PQ1101 AON7702A

VGA@

4

5

1 2 3

PJP1100

JUMP_43X118

@PJP1100

JUMP_43X118

@

11

22

PR12074.7_1206_5%

@EMI@ PR12074.7_1206_5%

@EMI@

1 2

PR1202

0_0402_5%

@ PR1202

0_0402_5%

@

1

2

P C 1 2 0 3

0 . 1

U_

0 4 0 2

_ 2 5 V 6

@ E M I @

P C 1 2 0 3

0 . 1

U_

0 4 0 2

_ 2 5 V 6

@ E M I @

1

2

PR1102154K_0402_1%

VGA@PR1102154K_0402_1%

VGA@

1 2

P C 1 2 0 1

2 2 U

_ 0 8 0 5

_ 6

. 3 V A M

V

G A @

P C 1 2 0 1

2 2 U

_ 0 8 0 5

_ 6

. 3 V A M

V

G A @

1

2


VGA@ PL12001UH_PCMB063T-1R0MS_12A_20%

VGA@

1 2

P C 1 2 0 7

4 7 U

_ 0 8 0 5

_ 6

. 3 V 6 M

V

G A @

P C 1 2 0 7

4 7 U

_ 0 8 0 5

_ 6

. 3 V 6 M

V

G A @

1

2

P C 1 1 0 2

1 0 U

_ 0 8 0 5

_ 2 5 V 6 K

V G A @

P C 1 1 0 2

1 0 U

_ 0 8 0 5

_ 2 5 V 6 K

V G A @

1

2

P C 1 2 0 9

2 2 0 0 P

_ 0 4 0 2

_ 5 0 V 7 K

V G A @

_ E M I @

P C 1 2 0 9

2 2 0 0 P

_ 0 4 0 2

_ 5 0 V 7 K

V G A @

_ E M I @

1

2

PR1211

120K_0402_1%

VGA@PR1211

120K_0402_1%

VGA@1 2

PR11079.09K_0402_1%

[email protected]_0402_1%

VGA@

1 2

P C 1 2 1 1

4 7 U

_ 0 8 0 5

_ 6

. 3 V 6 M

V

G A @

P C 1 2 1 1

4 7 U

_ 0 8 0 5

_ 6

. 3 V 6 M

V

G A @

1

2

PR1110100K_0402_5%

@PR1110100K_0402_5%

@

1

2

PU1200


VGA@

PU1200


VGA@

IN8

BYP7

PG2

ILMT3

LX10

FB4

LDO5

GND9

EN1

BS6


VGA@_EMI@ PL1201SUPPRE_ FBMA-L11-453215-800LMA90T_1812

VGA@_EMI@

1 2

PR1214100K_0402_5%

@PR1214100K_0402_5%

@

1

2

PR11030_0402_5%~D

VGA@PR11030_0402_5%~D

VGA@

1 2

PC1212680P_0603_50V7K

@EMI@ PC1212680P_0603_50V7K

@EMI@

1 2

PJP1200

JUMP_43X118

@PJP1200

JUMP_43X118

@

11

22

+

P C 1 1 0 8

3 3 0 U

_ 2

. 5 V

_ M

V G A @

+

P C 1 1 0 8

3 3 0 U

_ 2

. 5 V

_ M

V G A @

1

2

PJP1101

JUMP_43X118

@PJP1101

JUMP_43X118

@

11

22

PR12060_0402_5%

VGA@ PR12060_0402_5%

VGA@

1 2

PR1203

0_0402_5%

VGA@ PR1203

0_0402_5%

VGA@

1

2

PR121310K_0402_5%

VGA@PR121310K_0402_5%

VGA@

1

2

PQ1100 AON7408L

VGA@PQ1100 AON7408L

VGA@

4

5

1 2 3

PC1200

0.22U_0402_10V6K

@ PC1200

0.22U_0402_10V6K

@

1

2

P C 1 2 0 6

2 2 U

_ 0 8 0 5

_ 6

. 3 V A M

V

G A @

P C 1 2 0 6

2 2 U

_ 0 8 0 5

_ 6

. 3 V A M

V

G A @

1

2

PR110810K_0402_1%

VGA@PR110810K_0402_1%

VGA@

1

2

PC12144700P_0402_25V7K@ PC12144700P_0402_25V7K@

1

2

P R 1 2 0 8

1 0

_ 0 4 0 2

_ 5 %

V G A @

P R 1 2 0 8

1 0

_ 0 4 0 2

_ 5 %

V G A @

1

2

5 4 3 2 1

GPU_B+

B+

PL800

FBMA-L11-453215-800LMA90T_1812

VGA@_EMI@PL800

FBMA-L11-453215-800LMA90T_1812

VGA@_EMI@

1 2



5 4 3 2 1

D D

C C

B B

A A

VGA_COREFrequency 300kHzTDC 23A(25W)/33A(32W)

Peak Current 30A(25W)/47A(32W)OCP current 36A(25W)/56A(32W) TYP MAXH/S Rds(on) :12.2mohm , 15mohm L/S Rds(on) :2.75mohm , 3.5mohm Choke DCR 1.1mohm(Typ)/1.3mohm(Max)Load line : -1.5mV/A

+VGA_PCIETDC 3A Peak Current 4.2A OCP current 6A

01 11 0.8V

0.825V

0.85V

0.875V

0.9V

0.925V

0.95V

0.975V

1111 0

1 0

0

011

0 0 1

0 0

1

0

0

0

1V

1.025V

1.05V

1.075V

1.1V

1.125V

1

11

1111

111 0

111 00

000 11

111 00

000 11

11 000

00001

11110

1 1 1 10 0.775V

Initial voltage:0.85V(Venus) 0.9V(Sun)

25W 32W

PR813

PR821

PR825

909

97.6K

976

1.4K

143K

1.5K

GPU_VID5(GPIO_10)

GPU_VID4(GPIO_14)

GPU_VID3(GPIO_15)

GPU_VID2(GPIO_16)

GPU_VID1(GPIO_20) Core Voltage Level

1.15V

1.175V

1.2V

0 1 1 1 0

0 1 1 0 1

1 10 0 0

SUN XT VENUS PRO/XT

Load line

PR824

No need Need

pop un-pop

Vout=0.95V

LX_PCIE

+ V G A_

P C I E P

EN_PCIE

FB_PCIE

PCIE_B+

PXS_PWREN

S N U B_

P C I E

G P U_

B +

BST_VGA_CORE

GFX_FB-1

GFX_FB-2

62881_FB62881_FB

62881_VW62881_VW

62881_COMP62881_COMP

62881_RBIAS

6 2 8 8 1_

V I D 0

6 2 8 8 1_

V R_

O N

6 2 8 8 1_

V I D 1

6 2 8 8 1_

V I D 2

6 2 8 8 1_

V I D 3

6 2 8 8 1_

V I D 4

6 2 8 8 1_

V I D 5

6 2 8 8 1_

V I D 6

SW_VGA_CORE

6 2 8 8 1_

V I N

GPU_B+62881_VDD

I S U M -

I S U M +

62881_VCCP

UG_VGA_CORE

ISUM-2

ISUM-

I S U M - 1

ISUM+

GPU_VID1

GPU_VID2

GPU_VID3

GPU_VID4

GPU_VID5

VCCSENSE_VGA<52>

DGPU_PWROK<10,30>

PXS_PWREN <10,11,39,43,50>

GPU_VID1 <49>

GPU_VID2 <49>GPU_VID3 <49>

GPU_VID4 <49>GPU_VID5 <49>

VSSSENSE_VGA<52>

+VGA_CORE

+VGA_PCIEP +VGA_PCIE

+VGA_PCIEP+3VALW

+5VALW

+5VALW

+VGA_CORE

+3VS

+3VS

+3VGS

+5VALW

Title


Date: Sheet of




LA-9981P 0.2



PWR_VGA_CORE/PCIE Title


Date: Sheet of




LA-9981P 0.2



PWR_VGA_CORE/PCIE Title


Date: Sheet of




LA-9981P 0.2



PWR_VGA_CORE/PCIE

PR818

715_0402_1%

VGA@PR818

715_0402_1%

VGA@

12

PC8190.15U_0402_10V6K


VGA@

1 2

P C 8 3 2

2 2 0 0 P_

0 4 0 2_

5 0 V 7 K ~ D

V G A @_

E M I @

P C 8 3 2

2 2 0 0 P_

0 4 0 2_

5 0 V 7 K ~ D

V G A @_

E M I @

1

2

PR824

0_0402_5%

LL@

PR824

0_0402_5%

LL@

1

2

PC806390P_0402_50V7KVGA@ PC806390P_0402_50V7KVGA@

1 2

PL13000.47UH_FDVE0630-H-R47M=P3_17.7A_20%

VGA@ PL13000.47UH_FDVE0630-H-R47M=P3_17.7A_20%

VGA@

1 2

P R 8 1 5

4 7 K_

0 4 0 2_

1 %

V G A @

P R 8 1 5

4 7 K_

0 4 0 2_

1 %

V G A @

1

2

PC803

2.2U_0603_6.3V6K

VGA@PC803

2.2U_0603_6.3V6K

VGA@

1

2

PC816

1000P_0402_50V7K

VGA@PC816

1000P_0402_50V7K

VGA@1 2

P R 8 2 3

0_

0 6 0 3_

5 %

V G A @

P R 8 2 3

0_

0 6 0 3_

5 %

V G A @

1

2

PC807

0.1U_0603_25V7K

VGA@PC807

0.1U_0603_25V7K

VGA@

1 2

PR819

10K_0402_1%

VGA@PR819

10K_0402_1%

VGA@

1 2

PR8030_0402_5% VGA@PR8030_0402_5% VGA@12

P C 8 0 5

1 0 U_

0 8 0 5_

2 5 V 6 K

V G A @

P C 8 0 5

1 0 U_

0 8 0 5_

2 5 V 6 K

V G A @

1

2

PR817

8.06K_0402_1%

VGA@PR817

8.06K_0402_1%

VGA@

12

PR130110K_0402_1%VGA@ PR130110K_0402_1%VGA@

1

2

PQ800

M D U 1 5 1 6 U

R H 1 N P O W E R D F N 5 6 - 8

32W@PQ800

M D U 1 5 1 6 U

R H 1 N P O W E R D F N 5 6 - 8

32W@

4

5

1 2 3

P C 1 3 0 4

6 8 0 P_

0 4 0 2_

5 0 V 7 K

@ E M I @

P C 1 3 0 4

6 8 0 P_

0 4 0 2_

5 0 V 7 K

@ E M I @

1

2

PR821

143K_0402_1%

32W@PR821

143K_0402_1%

32W@

PR826

10K_0402_1%

VENUS@PR826

10K_0402_1%

VENUS@1 2

PC814

56P_0402_50V8

VGA@ PC814

56P_0402_50V8

VGA@

1 2

PQ801

M D U 1 5 1 1 R H 1 N P O W E R D F N 5 6

VGA@PQ801

M D U 1 5 1 1 R H 1 N P O W E R D F N 5 6

VGA@

4

5

3 2 1

P C 1 3 0

3

2 2 U_

0 8 0 5_ 6 . 3 V A M

V G A @

P C 1 3 0

3

2 2 U_

0 8 0 5_ 6 . 3 V A M

V G A @

1

2

PU1300

SY8036LDBC_DFN10_3x3

VGA@

PU1300

SY8036LDBC_DFN10_3x3

VGA@

EN5

P G

4

LX3

FB6

SVIN8

T P

1 1

LX2

PVIN10

S S

7

PVIN9

L X

1

PR834

10K_0402_1%

SUN@PR834

10K_0402_1%

SUN@1 2

P C 8 0 8

1 0 U_

0 8 0 5_

2 5 V 6 K

V G A @

P C 8 0 8

1 0 U_

0 8 0 5_

2 5 V 6 K

V G A @

1

2 P C 8 0 4

1 0 U_

0 8 0 5_

2 5 V 6 K

V G A @

P C 8 0 4

1 0 U_

0 8 0 5_

2 5 V 6 K

V G A @

1

2

P R 8 4 2

1 K_

0 4 0 2_

1 % V G A @

P R 8 4 2

1 K_

0 4 0 2_

1 % V G A @

1

2

P C 1 3 0 2

0 . 1 U_

0 4 0 2_

1 0 V 7 K

V G A @

P C 1 3 0 2

0 . 1 U_

0 4 0 2_

1 0 V 7 K

V G A @

1

2 P C 1 3 0 7

0 . 1 U_

0 4 0 2_

1 0 V 7 K V

G A @

P C 1 3 0 7

0 . 1 U_

0 4 0 2_

1 0 V 7 K V

G A @

1

2

PR835

10K_0402_1%

@PR835

10K_0402_1%

@1 2

PR838

10K_0402_1%

@PR838

10K_0402_1%

@

1 2

PQ803

M D U 1 5 1 6 U R H 1 N P O W E R D F N 5 6 - 8

VGA@PQ803

M D U 1 5 1 6 U R H 1 N P O W E R D F N 5 6 - 8

VGA@

4

5

1 2 3

PJP1300

JUMP_43X79

@PJP1300

JUMP_43X79

@

11

22

PR8060_0402_5%~D @PR8060_0402_5%~D @12

P C 8 1 5

6 8 0 P_

0 6 0 3_

5 0 V 7 K

@ E M I @

P C 8 1 5

6 8 0 P_

0 6 0 3_

5 0 V 7 K

@ E M I @

1

2

PR8120_0402_5%~D @PR8120_0402_5%~D @12

PC1306

22P_0402_50V8J

VGA@ PC1306

22P_0402_50V8J

VGA@12

PR8040_0402_5%~D @PR8040_0402_5%~D @12

P C 8 6 9

0 . 1 U_

0 4 0 2_

1 0 V 7 K

V G A @

P C 8 6 9

0 . 1 U_

0 4 0 2_

1 0 V 7 K

V G A @

1

2

P C 8 2 1

. 1 U_

0 4 0 2_

1 6 V 7 K V

G A @

P C 8 2 1

. 1 U_

0 4 0 2_

1 6 V 7 K V

G A @

1

2

PC130122U_0805_6.3VAM

VGA@

PC130122U_0805_6.3VAM

VGA@ 1

2

PR8100_0402_5%~D @PR8100_0402_5%~D @12

PC8181000P_0402_50V7K

VGA@PC8181000P_0402_50V7K

VGA@

12

P C 8 3 1

0 . 1 U_

0 4 0 2_

2 5 V 6 K ~ D

@ E M I @

P C 8 3 1

0 . 1 U_

0 4 0 2_

2 5 V 6 K ~ D

@ E M I @

1

2

PJP1301

JUMP_43X79

@PJP1301

JUMP_43X79

@

11

22

PR828

10K_0402_1%

@PR828

10K_0402_1%

@1 2

P C 1 3 0

0

2 2 U_

0 8 0 5_ 6 . 3 V A M

V G A @

P C 1 3 0

0

2 2 U_

0 8 0 5_ 6 . 3 V A M

V G A @

1

2

PQ802

M D U 1 5 1 1 R H 1 N P O W E R D F N 5 6

VGA@PQ802

M D U 1 5 1 1 R H 1 N P O W E R D F N 5 6

VGA@

4

5

3 2 1

PR814

0_ 0603_5%

VGA@PR814

0_ 0603_5%

VGA@1 2

PH80010KB_0402_5%_ERTJ0ER103J

VGA@PH80010KB_0402_5%_ERTJ0ER103J

VGA@1 2

PC817

1000P_0402_50V7K

VGA@ PC817

1000P_0402_50V7K

VGA@

12

PR836

10K_0402_1%

VGA@PR836

10K_0402_1%

VGA@1 2

PR8110_0402_5%~D @PR8110_0402_5%~D @12

PC8111U_0603_10V6K

VGA@PC8111U_0603_10V6K

VGA@

1

2

PR840

10K_0402_1%

@PR840

10K_0402_1%

@1 2

PR820

10_0402_5%

@PR820

10_0402_5%

@12

PR8070_0402_5%~D @PR8070_0402_5%~D @12

PC809330P_0402_50V7K

@PC809330P_0402_50V7K

@

1

2

PR1304

47K_0402_5%

@ PR1304

47K_0402_5%

@

1

2

PR833

10_0402_5%

@PR833

10_0402_5%

@12

PR822

1_0603_5%

VGA@PR822

1_0603_5%

VGA@12

P R 1 3 0 3

4 . 7_

1 2 0 6_

5 %

@ E M I @

P R 1 3 0 3

4 . 7_

1 2 0 6_

5 %

@ E M I @

1

2

PR1300

200K_0402_5%

VGA@ PR1300

200K_0402_5%

VGA@

1 2

PR8090_0402_5%~D @PR8090_0402_5%~D @12

PC820

0.033U_0402_16V7K

VGA@PC820

0.033U_0402_16V7K

VGA@1 2

PR802

0_0603_5%

VGA@ PR802

0_0603_5%

VGA@

1 2

PR846

0_0402_5%

VGA@PR846

0_0402_5%

VGA@12

PR813

1.4K_0402_1%

32W@PR813

1.4K_0402_1%

32W@

PR839

10K_0402_1%

VGA@PR839

10K_0402_1%

VGA@1 2

P R 8 0 5

4 . 7_

1 2 0 6_

5 %

@ E M I @

P R 8 0 5

4 . 7_

1 2 0 6_

5 %

@ E M I @

1

2

PR825

1.5K_0402_1%

32W@PR825

1.5K_0402_1%

32W@

PR813909_0402_1%

25W@PR813909_0402_1%

25W@

12

P R 8 2 5

9 7 6_

0 4 0 2_

1 %

2 5 W @

P R 8 2 5

9 7 6_

0 4 0 2_

1 %

2 5 W @ 1

2

PU800

ISL62881CHRTZ-T_QFN28_4X4

VGA@PU800

ISL62881CHRTZ-T_QFN28_4X4

VGA@FB

6

CLK_EN#1

PGOOD2

I S U M +

1 0

I S U M

9

V I D 5

2 5

VID121

LGATE18

VSSP17

V I D 2

2 2

UGATE15

R T N

8

RBIAS3

VW4

COMP5

VID020

VCCP19

V I D 3

2 3

V I D 4

2 4

V I D 6

2 6

V R

_ O N

2 7

D P R S L P V R

2 8

VSEN7

V D D

1 1

V I N

1 2

I M O N

1 3

B O O T

1 4

PHASE16

A G N D

2 9

P R 8 3 0

0 _ 0 4 0 2 _ 5 %

V GA @

P R 8 3 0

0 _ 0 4 0 2 _ 5 %

V GA @

1

2 P R 8 2 9

3 . 6 5 K_

0 4 0 2_

1 %

V G A @

P R 8 2 9

3 . 6 5 K_

0 4 0 2_

1 %

V G A @

1

2

PR82197.6K_0402_1%


25W@

1 2

P C 8 1 0

0 . 2 2 U_

0 6 0 3_

2 5 V 7 K

V G A @

P C 8 1 0

0 . 2 2 U_

0 6 0 3_

2 5 V 7 K

V G A @

1

2

P C 1 3 0

8

2 2 U_

0 8 0 5_ 6 . 3 V A M

V G A @

P C 1 3 0

8

2 2 U_

0 8 0 5_ 6 . 3 V A M

V G A @

1

2

P R 8 0 8

1 0 K_ 0

4 0 2_

1 %

@

P R 8 0 8

1 0 K_ 0

4 0 2_

1 %

@ 1

2

PR8162.61K_0402_1%


VGA@1 2

PR837

10K_0402_1%

VGA@PR837

10K_0402_1%

VGA@

1 2

PR8450_0402_5%

VGA@PR8450_0402_5%

VGA@

12

PR1302

5.9K_0402_1%

VGA@PR1302

5.9K_0402_1%

VGA@

12

PL802

0.36UH_MMD-12CE-R36M-M1L_34A_20%

VGA@ PL802

0.36UH_MMD-12CE-R36M-M1L_34A_20%

VGA@

1 2

PR82711K_0402_1%

VGA@PR82711K_0402_1%

VGA@1 2

P C 1 3 0

5

2 2 U_

0 8 0 5_ 6 . 3 V A M

V G A @

P C 1 3 0

5

2 2 U_

0 8 0 5_ 6 . 3 V A M

V G A @

1

2

PC813330P_0402_50V7K

@PC813330P_0402_50V7K

@

1 2



5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

+1.8VSP: TDC:2.5ASY8003DFC

PXS_PWREN

Page 48

+VCCIO: TDC:5ASY8206DQNC

Page 49

SUSP#

+3VALW

Page 50

+1.35VP/+0.675VSP: TDC:6A/0.7A

RT8207MZQW

B+

EC_ON DC IN +3VALWP: TDC:5.4A+5VALWP: TDC:5.6ATPS51225CRUKR

Power block

CHARGER CC:0A~1A(4cell) or 2.1A(6cell)CV:17.7V(4cell) / 13.3V(6cell)BQ24717

SYSON

VR_ON +CPU_CORE TDC: 14A

TPS51622RSM

+1.5VSP: TDC:2.5ASY8003DFC

Page 48

Page 47

Input Switch

Page 51

CPU OTP

Turn Off

Page 45

Page 46

Battery

SUSP#

+VGA_CORE TDC: 23A / 33AISL62881CHRTZ-T

PXS_PWREN

Page 53

PXS_PWREN +VGA_PCIEP: TDC:3ASY8036LDBC

Page 53

PXS_PWREN

Page 52

+VDDCIP: TDC:7ASY8208DQNC

+1.35VGPUP: TDC:9ATPS51212DSCR

PXS_PWREN

Page 52

+3VALW

+3VALW

Title


Date: Sheet of




LA-9981P 0.2



PWR_POWER BLOCK DIAGRAM Title


Date: Sheet of




LA-9981P 0.2



PWR_POWER BLOCK DIAGRAM Title


Date: Sheet of




LA-9981P 0.2



PWR_POWER BLOCK DIAGRAM

5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

Page 1

Solution Description Rev.age Title

Version Change List ( P. I. R. List )

Item Issue Descriptionate

Request

Owner

1 45 CHARGER 13/01/30 Morris adjust design parameter from vendor recommend delete PD702change PC712 to unpopchange PQ704 to unpopchange PC707 from 0.1uF_0402 to 1uF_0603change PC720 from 0.1uF to 100pFchange PC711 from 1000pF to 0.01uFchange PQ705 from SB00000SD00 to SB00000WY00

2 50 VCORE 13/01/30 Morris adjust design parameter from vendor recommend change PC509 from 0.1uF to 1000pFchange PR529 from 3.83K to 5.76Kchange PR504 from 523K to 499K

3 44 DCIN/BATT CONN/OTP 13/01/30 Morris change from ESD request change PD1 from SC300002E00 to SC300001G00

0.2

0.2

0.2

4 46 3.3VALWP/5VALWP 13/02/01 Morris add ESD diode from ESD request add PD101(SCA00002A00) 0.2

5 50 VCORE 13/02/21 Morris adjust design parameter from fine tune result change PR501 from 422K to 523Kchange PR503 from 56K to 75K

6 52 VGA_CORE/PCIE 13/02/21 Morris

0.2

0.2unpop from EE request unpop PR808

VGA_CORE/PCIE527 0.2adjust output voltage from vender requestMorris13/03/05 unpop PR826 and pop PR834 (only for Sun XT)

Title


Date: Sheet of




LA-9981P 0.2



PWR-PIRTitle


Date: Sheet of




LA-9981P 0.2



PWR-PIRTitle


Date: Sheet of




LA-9981P 0.2



PWR-PIR

5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

THAMES XT M2

Place CV326 Close to UV13

LVDS Interface

GFX PCIE LANE REVERSAL

CLK_PEG_VGA

PEG_CTX_GRX_P3PEG_CTX_GRX_N3




PCIE_CRX_C_GTX_P1PCIE_CRX_C_GTX_N1 PEG_CRX_GTX_N1

PEG_CRX_GTX_P1

PCIE_CRX_C_GTX_P0PCIE_CRX_C_GTX_N0

PEG_CRX_GTX_P0PEG_CRX_GTX_N0

PCIE_CRX_C_GTX_P3PCIE_CRX_C_GTX_N3 PEG_CRX_GTX_N3

PEG_CRX_GTX_P3

PCIE_CRX_C_GTX_P2PCIE_CRX_C_GTX_N2

PEG_CRX_GTX_P2PEG_CRX_GTX_N2

CLK_PEG_VGA#

GPU_RST#

GPU_RST#

PEG_CTX_GRX_P0<12>PEG_CTX_GRX_N0<12>




PEG_CRX_GTX_P1 <12>PEG_CRX_GTX_N1 <12>




CLK_PEG_VGA<9>

CLK_PEG_VGA#<9>

DGPU_HOLD_RST#<10>

PLT_RST#<10,21,26,30,6>

+VGA_PCIE

+VGA_PCIE

+3VGS

Title


Date: Sheet of




0.2

ATI_Sun XT_M2_PCIE/LVDS


2013/03/09 2014/04/01


LA-9981P

Title


Date: Sheet of




0.2



2013/03/09 2014/04/01


LA-9981P

Title


Date: Sheet of




0.2



2013/03/09 2014/04/01


LA-9981P

CV430.1U_0402_10V7K~D [email protected]_0402_10V7K~D DIS@12

R V6 4 1 K_ 04 02 _5 %

DIS@

R V6 4 1 K_ 04 02 _5 %

DIS@

1 2

CV470.1U_0402_10V7K~D [email protected]_0402_10V7K~D [email protected]_0402_10V7K~D [email protected]_0402_10V7K~D DIS@12

RV1981.69K_0402_1%~D

[email protected]_0402_1%~D

DIS@

1 2

P CI EXPRE S S INTER

FA CE

CLOCK

CALIBRATION

UV1A

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

VENUS@

P CI EXPRE S S INTER

FA CE

CLOCK

CALIBRATION

UV1A


VENUS@

PWRGOOD AH16

PCIE_CALRNY29

PCIE_CALRPY30

PCIE_REFCLKN AA36 PCIE_REFCLKP AB35

PCIE_RX0NY37 PCIE_RX0P

AA38

PCIE_RX10NK37 PCIE_RX10PL38

PCIE_RX11NJ36PCIE_RX11P

K35

PCIE_RX12NH37 PCIE_RX12PJ38

PCIE_RX13NG36 PCIE_RX13PH35

PCIE_RX14NF37 PCIE_RX14PG38

PCIE_RX15NE37 PCIE_RX15PF35

PCIE_RX1NW36 PCIE_RX1PY35

PCIE_RX2NV37 PCIE_RX2PW38

PCIE_RX3NU36 PCIE_RX3PV35

PCIE_RX4NT37 PCIE_RX4PU38

PCIE_RX5NR36 PCIE_RX5PT35

PCIE_RX6NP37 PCIE_RX6PR38

PCIE_RX7NN36 PCIE_RX7PP35

PCIE_RX8NM37 PCIE_RX8PN38

PCIE_RX9NL36 PCIE_RX9PM35

PERSTB AA30

PCIE_TX0NY32PCIE_TX0PY33

PCIE_TX10NL32PCIE_TX10PL33

PCIE_TX11N L29PCIE_TX11P

L30

PCIE_TX12NK32PCIE_TX12PK33

PCIE_TX13NJ32PCIE_TX13PJ33

PCIE_TX14NK29PCIE_TX14PK30

PCIE_TX15NH32PCIE_TX15PH33

PCIE_TX1NW32PCIE_TX1PW33

PCIE_TX2NU32PCIE_TX2P U33

PCIE_TX3NU29PCIE_TX3PU30

PCIE_TX4NT32PCIE_TX4PT33

PCIE_TX5NT29PCIE_TX5PT30

PCIE_TX6NP32PCIE_TX6PP33

PCIE_TX7NP29PCIE_TX7PP30

PCIE_TX8NN32PCIE_TX8PN33

PCIE_TX9NN29PCIE_TX9PN30

UV13MC74VHC1G08DFT2G_SC70-5

DIS@

UV13MC74VHC1G08DFT2G_SC70-5

DIS@

IN11

IN22 OUT

4 V C C

5

G N D

3


CV326

0.1U_0402_25V6K

DIS@CV326

0.1U_0402_25V6K

DIS@

1

2



LVTMDP

LVDS CONTROL

UV1G

216-0833000-A11- THAMES-XT-M2_FCBGA962~D

VENUS@

LVTMDP

LVDS CONTROL

UV1G

216-0833000-A11- THAMES-XT-M2_FCBGA962~D

VENUS@

DIGON AJ27

TXCLK_LN_DPE3N AR34TXCLK_LP_DPE3P AP34

TXCLK_UN_DPF3N AL36TXCLK_UP_DPF3P AK35

TXOUT_L0N_DPE2N AU35TXOUT_L0P_DPE2P AW37

TXOUT_L1N_DPE1N AU39TXOUT_L1P_DPE1P AR37

TXOUT_L2N_DPE0N AR35TXOUT_L2P_DPE0P AP35

TXOUT_L3N AP37TXOUT_L3P AN36

TXOUT_U0N_DPF2N AK37TXOUT_U0P_DPF2P AJ38

TXOUT_U1N_DPF1N AJ36TXOUT_U1P_DPF1P AH35

TXOUT_U2N_DPF0N AH37TXOUT_U2P_DPF0P AG38

TXOUT_U3N AG36TXOUT_U3P AF35

VARY_BL AK27

RV66

100K_0402_5%

DIS@RV66

100K_0402_5%

DIS@

1

2



RV203

1K_0402_1%

DIS@RV203

1K_0402_1%

DIS@

1 2



5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

PX_MODE=1 for Normal OperationPX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

Power seguence of Sun XT,Venus Pro,Venus XT

+3VGS

+VGA_CORE

+VDDCI(+VGA_PCIE)

+1.35V_MEM_GFX

+1.0VGS

+1.8VGS <20ms

PX4.0 +VGA_CORE,VDDCI,+1.5VGS ONPX4.0 +3VGS, +1.0VGS,+1.8VGS OFFPX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF

Note:

60mil

for PX5.0

60mil

+3VS TO +3VGS+1.8VS TO +1.8VGS

+1.35VS_VGA TO +1.35V_MEM_GFX

Switch circuits in BACO desingns for Thames/Seymour only

[email protected], in BACO mode

SHORT DEFAULT

SHORT DEFAULT

for PX4.0 and PX5.0

PXS_PWREN

PXS_PWREN

PXS_PWREN#

PXS_PWREN<10,11,39,43,44>

+1.35VS_VGA +1.35V_MEM_GFX

+3VS +3VGS

+5VALW

+1.8VS +1.8VGS

+VGA_CORE+VGA_PCIE +BIF_VDDC+3VGS

+3VALW

Title


Date: Sheet of




LA-9981P 0.2

ATI_Sun XT_M2_BACO POW ER


2013/03/09 2014/04/01

Compal Electronics, Inc.Title


Date: Sheet of




LA-9981P 0.2



2013/03/09 2014/04/01

Compal Electronics, Inc.Title


Date: Sheet of




LA-9981P 0.2



2013/03/09 2014/04/01


G

D

S

QV252N7002K_SOT23-3

DIS@

G

D

S

QV252N7002K_SOT23-3

DIS@2

1

3

CV103

0.1U_0603_25V7K

DIS@CV103

0.1U_0603_25V7K

DIS@1

2

QV22 AP2301GN-HF_SOT23-3

DIS@QV22 AP2301GN-HF_SOT23-3

DIS@

2

3 1

R V1 03 0 _0 80 5_ 5%VENUS@R V1 03 0 _0 80 5_ 5%VENUS@

1 2

RV107

20K_0402_5%

DIS@

RV107

20K_0402_5%

DIS@

G

D

S QV24

2N7002K_SOT23-3

DIS@G

D

S QV24

2N7002K_SOT23-3

DIS@

2

1

3

JP9

2MM

@JP9

2MM

@

2 1

J92MM

@

J92MM

@

2 1

R V2 34 0 _0 60 3_ 5% ~DSUN@R V2 34 0 _0 60 3_ 5% ~DSUN@

1 2

RV10520K_0402_5%

@

RV10520K_0402_5%

@

1

2

CV1021U_0603_10V6K

DIS@

CV1021U_0603_10V6K

DIS@1

2

JP8

2MM

@JP8

2MM

@

2 1

CV9722U_0805_6.3V6M

DIS@

CV9722U_0805_6.3V6M

DIS@1

2

RV108

1K_0402_5%

DIS@

RV108

1K_0402_5%

DIS@

1 2

RV109100K_0402_5%

DIS@

RV109100K_0402_5%

DIS@

1

2

CV10110U_0603_6.3V6M

DIS@

CV10110U_0603_6.3V6M

DIS@1

2

5 4 3 2 1

UV1FUV1F



5 4 3 2 1

D D

C C

B B

A A

130mA

130mA

110mA

110mA

20mA

20mA

1.8V@300mA DPAB_VDD18)

(1.0V@220mA DPAB_VDD10)

1.8V@300mA DPCD_VDD18)

1.0V@220mA DPCD_VDD10)

1.8V@300mA DPEF_VDD18)

1.0V@240mA DPEF_VDD10)

(30mA)

(220mA)

(330mA)

Thames/Seymour Only

Do not install for Heathrow/Mars Pro

PS_0 Should be tied to GND on Thames/Seymour

(220mA)

(30mA)

(330mA)

20mil

20mil

20mil

20mil

20mil

20mil

20mil

20mil

20mA

20mA

20mA

20mA 10mil

10mil

10mil

10mil

10mil

10mil

20mil

20mil

20mil

20mil

0.95V@Venus

0.95V@Venus

0.95V@Venus

PS0:

PS1:

PS2:

PS3:

11001

11000

00000

11000

MLPS Bit AMD recommended setting

RV243=8.45K

RV237=NC

RV239=NC

RV241=NC

RV201=2K CV335=NC

RV238=4.75K CV329=NC

RV240=4.75K CV331=0.68u

RV242=4.75K CV333=NC

R_PU R_PD Cstrap

+DPCD_VDD18

+DPEF_VDD10

MECH#1

MECH#2MECH#3

+DPAB_VDD18

+DPAB_VDD10

+DPEF_VDD18

+DPCD_VDD10

PS_0

PS_0

+1.8VGS

+VGA_PCIE

+DPEF_VDD10

+VGA_PCIE

+1.8VGS

+DPAB_VDD18

+DPAB_VDD10

+DPAB_VDD18

+DPAB_VDD18

+DPCD_VDD18

+DPCD_VDD18

+DPEF_VDD18

+DPEF_VDD18

+DPCD_VDD10

+DPCD_VDD18

+DPCD_VDD18

+DPCD_VDD10

+DPEF_VDD10

+DPEF_VDD18

+DPEF_VDD10

+1.8VGS +DPEF_VDD18

+VGA_PCIE+DPCD_VDD10

+DPAB_VDD18

+DPAB_VDD10

+1.8VGS

Title


Date: Sheet of




0.2

ATI_Sun XT_M2_PWR_GND


2013/03/09 2014/04/01


LA-9981P

Title


Date: Sheet of




0.2



2013/03/09 2014/04/01


LA-9981P

Title


Date: Sheet of




0.2



2013/03/09 2014/04/01


LA-9981P

RV1190_0402_1%

@VENUS@

RV1190_0402_1%

@VENUS@

1 2

C V 1

1 3

0 . 1 U_

0 4 0 2_

1 6 V 7 K

@ C V 1

1 3

0 . 1 U_

0 4 0 2_

1 6 V 7 K

@

1

2

RV1254.7K_0402_5%

@

RV1254.7K_0402_5%

@

1

2

C V 1 2 2

0 . 1 U_

0 4 0 2_

1 6 V 7 K

V E N U S @

C V 1 2 2

0 . 1 U_

0 4 0 2_

1 6 V 7 K

V E N U S @

1

2

C V 1 1 6

1 0 U_

0 6 0 3_

6 . 3 V 6 M

V E N U S @

C V 1 1 6

1 0 U_

0 6 0 3_

6 . 3 V 6 M

V E N U S @

1

2

C V 1 2 5

0 . 1 U_

0 4 0 2_

1 6 V 7 K

@

C V 1 2 5

0 . 1 U_

0 4 0 2_

1 6 V 7 K

@

1

2

RV121

0_0402_1%

@VENUS@RV121

0_0402_1%

@VENUS@

1 2

CV3350.68U_0402_10V

@

CV3350.68U_0402_10V

@1

2

C V 1

1 1

1 0 U_

0 6 0 3_

6 . 3 V 6 M

@ C V 1

1 1

1 0 U_

0 6 0 3_

6 . 3 V 6 M

@

1

2

C V 1

1 2

1 U_

0 4 0 2_

6 . 3 V 6 K

@ C V 1

1 2

1 U_

0 4 0 2_

6 . 3 V 6 K

@

1

2

C V 1 1 5

1 U_

0 4 0 2_

6 . 3 V 6 K

V E N U S @

C V 1 1 5

1 U_

0 4 0 2_

6 . 3 V 6 K

V E N U S @

1

2

C V 1 2 4

1 U_

0 4 0 2_

6 . 3 V 6 K

@

C V 1 2 4

1 U_

0 4 0 2_

6 . 3 V 6 K

@

1

2

RV1260_0402_1%

@VENUS@

RV1260_0402_1%

@VENUS@

1 2

RV122150_0402_1% DIS@ RV122150_0402_1% DIS@ 12

T84 PADT84 PAD

GND

216-0833000-A11-THAMES-XT-M2_FCBGA962~DVENUS@

GND

216-0833000-A11- THAMES-XT-M2_FCBGA962~DVENUS@

PCIE_VSS#1 AB39

PCIE_VSS#10J31

PCIE_VSS#11J34

PCIE_VSS#12K31

PCIE_VSS#13K34

PCIE_VSS#14K39

PCIE_VSS#15L31

PCIE_VSS#16L34

PCIE_VSS#17M34

PCIE_VSS#18M39

PCIE_VSS#19N31

PCIE_VSS#2E39

PCIE_VSS#20N34

PCIE_VSS#21P31

PCIE_VSS#22P34

PCIE_VSS#23P39

PCIE_VSS#24R34

PCIE_VSS#25T31

PCIE_VSS#26T34

PCIE_VSS#27T39

PCIE_VSS#28U31PCIE_VSS#29

U34

PCIE_VSS#3F34

PCIE_VSS#30V34

PCIE_VSS#31V39

PCIE_VSS#32W31

PCIE_VSS#33W34

PCIE_VSS#34Y34

PCIE_VSS#35Y39

PCIE_VSS#4F39

PCIE_VSS#5G33

PCIE_VSS#6G34

PCIE_VSS#7H31

PCIE_VSS#8H34

PCIE_VSS#9H39

VSS_MECH#1 A39

VSS_MECH#2 AW1

VSS_MECH#3 AW39

GND#1 A3

GND#10 AA6

GND#98F13

GND#100F15

GND#101F17

GND#102F19

GND#103F21

GND#104F23

GND#105F25

GND#106F27

GND#107F29

GND#108F31

GND#11 AB12

GND#109F33

GND#110F7

GND#111F9

GND#112G2

GND#113G6

GND#114H9

GND#115J2

GND#116J27

GND#117J6

GND#118J8

GND#12 AB15

GND#119K14

GND#120K7

GND#121L11

GND#122L17

GND#123L2

GND#124L22

GND#125L24

GND#126L6

GND#127M17

GND#128M22

GND#13 AB17

GND#129M24

GND#130N16

GND#131N18

GND#132N2

GND#133N21

GND#134N23

GND#135N26

GND#136N6

GND#137R15

GND#138R17

GND#14 AB20

GND#139R2

GND#140R20

GND#141R22

GND#142R24

GND#143R27

GND#144R6

GND#145T11

GND#146T13

GND#147T16

GND#148T18

GND#15 AB22

GND#149T21

GND#150T23

GND#151T26

GND#153U15

GND#154U17

GND#155U2

GND#156U20

GND#157U22

GND#158U24

GND#159U27

GND#16 AB24

GND#160U6

GND#161

V11

GND#163V16

GND#164V18

GND#165V21

GND#166V23

GND#167V26

GND#168W2

GND#169W6

GND#170Y15

GND#17 AB27

GND#171Y17

GND#172Y20

GND#173Y22

GND#174Y24

GND#175Y27

GND#18 AC11

GND#19 AC13

GND#2 A37

GND#20 AC16

GND#21 AC18

GND#22 AC2

GND#23 AC21

GND#24 AC23

GND#25 AC26

GND#26 AC28

GND#27 AC6

GND#28 AD15GND#29

AD17

GND#3 AA16

GND#30 AD20

GND#31 AD22

GND#32 AD24

GND#33 AD27

GND#34 AD9

GND#35 AE2

GND#36 AE6

GND#37 AF10

GND#38 AF16

GND#39 AF18

GND#4 AA18

GND#40 AF21

GND#41 AG17

GND#42 AG2

GND#43 AG20

GND#44 AG22

GND#45 AG6

GND#46 AG9

GND#47 AH21

GND#48 AJ10

GND#5 AA2

GND#49 AJ11

GND#50 AJ2

GND#51 AJ28

GND#52 AJ6

GND#53 AK11

GND#54 AK31

GND#55 AK7

GND#56 AL11

GND#57 AL14

GND#58 AL17

GND#6 AA21

GND#59 AL2

GND#60 AL20

GND/PX_EN#61 AL21

GND#62 AL23

GND#63 AL26

GND#64 AL32

GND#65 AL6

GND#66 AL8

GND#67 AM11

GND#68 AM31

GND#7 AA23

GND#69 AM9

GND#70 AN11

GND#71 AN2

GND#72 AN30

GND#73 AN6

GND#74 AN8

GND#75 AP11

GND#76 AP7

GND#77 AP9

GND#78 AR5

GND#8 AA26

GND#79B11

GND#80B13

GND#81B15

GND#82B17

GND#83B19

GND#84B21

GND#85B23

GND#86B25

GND#87B27

GND#9 AA28

GND#88B29

GND#89B31

GND#90B33

GND#91B7

GND#92B9

GND#93C1

GND#94C39

GND#95E35

GND#96E5

GND#97F11

GND#152U13

GND#162V13

RV201

SUN@

2K_0402_1%RV201

SUN@

2K_0402_1%

1

2

C V 1 1 7

1 0 U_

0 6 0 3_

6 . 3 V 6 M

@

C V 1 1 7

1 0 U_

0 6 0 3_

6 . 3 V 6 M

@

1

2

C V 1 1 0

1 0 U_

0 6 0 3_

6 . 3 V 6 M

V E N U S @

C V 1 1 0

1 0 U_

0 6 0 3_

6 . 3 V 6 M

V E N U S @

1

2

RV1240_0402_1%

@VENUS@

RV1240_0402_1%

@VENUS@

1 2

C V 1 2 1

1 U_

0 4 0 2_

6 . 3 V 6 K

V E N U S @

C V 1 2 1

1 U_

0 4 0 2_

6 . 3 V 6 K

V E N U S @

1

2

RV1180_0402_1%

@

RV1180_0402_1%

@

1 2

RV243

8.45K_0402_1%

SUN@RV243

8.45K_0402_1%

SUN@

1

2

C V 1 1 8

1 U_

0 4 0 2_

6 . 3 V 6 K

@

C V 1 1 8

1 U_

0 4 0 2_

6 . 3 V 6 K

@

1

2

RV1200_0402_1%

@

RV1200_0402_1%

@

1 2

T83 PADT83 PAD

C V 1 1 4

0 . 1 U_

0 4 0 2_

1 6 V 7 K

V E N U S @

C V 1 1 4

0 . 1 U_

0 4 0 2_

1 6 V 7 K

V E N U S @

1

2

C V 1 1 9

0 . 1 U_

0 4 0 2_

1 6 V 7 K

@

C V 1 1 9

0 . 1 U_

0 4 0 2_

1 6 V 7 K

@

1

2

C V 1 2 3

1 0 U_

0 6 0 3_

6 . 3 V 6 M

@

C V 1 2 3

1 0 U_

0 6 0 3_

6 . 3 V 6 M

@

1

2

C V 1 0 9

1 U_

0 4 0 2_

6 . 3 V 6 K

V E N U S @

C V 1 0 9

1 U_

0 4 0 2_

6 . 3 V 6 K

V E N U S @

1

2 C V 1 0 8

0 . 1 U_

0 4 0 2_

1 6 V 7 K

V E N U S @

C V 1 0 8

0 . 1 U_

0 4 0 2_

1 6 V 7 K

V E N U S @

1

2

DP PLL POWER

DP A/B POWERDP C/D POWER

DP E/F POWER

UV1H


DP PLL POWER

DP A/B POWERDP C/D POWER

DP E/F POWER

UV1H

216-0833000-A11- THAMES-XT-M2_FCBGA962~DVENUS@

DPAB_VDD18/DPA_PVDD AU28

DP_VSSR/DPA_PVSS AV27

DPAB/DPA_VDD10#1 AP31


DPAB/DPA_VDD18#1 AN24


DP/DPA_VSSR#1 AN27

DP/DPA_VSSR#2 AP27

DP/DPA_VSSR#3 AP28

DP/DPA_VSSR#4 AW24

DP/DPA_VSSR#5 AW26

DPAB_CALR AW28

DPAB_VDD18/DPB_PVDD AV29

DP_VSSR/DPB_PVSS AR28

DPAB/DPB_VDD10#1 AN33

DPAB/DPB_VDD10#2 AP33



DP/DPB_VSSR#1 AN29

DP/DPB_VSSR#2 AP29

DP/DPB_VSSR#3 AP30

DP/DPB_VSSR#4 AW30

DP/DPB_VSSR#5 AW32

DPCD_VDD18/DPC_PVDD AU18

DP_VSSR/DPC_PVSS AV17

DPCD/DPC_VDD10#1 AP13

DPCD/DPC_VDD10#2 AT13



DP/DPC_VSSR#1 AN17

DP/DPC_VSSR#2 AP16

DP/DPC_VSSR#3 AP17

DP/DPC_VSSR#4 AW14

DP/DPC_VSSR#5 AW16

DPCD_CALR AW18

DPCD_VDD18/DPD_PVDD AV19

DP_VSSR/DPD_PVSS AR18

DPCD/DPD_VDD10#1 AP14




DP/DPD_VSSR#1 AN19

DP/DPD_VSSR#2 AP18

DP/DPD_VSSR#3 AP19

DP/DPD_VSSR#4 AW20

DP/DPD_VSSR#5 AW22

DPEF_VDD18/DPE_PVDD AM37

DP_VSSR/DPE_PVSS AN38

DPEF/DPE_VDD10#1 AL33

DPEF/DPE_VDD10#2 AM33

DPEF/DPE_VDD18#1 AH34

DPEF/DPE_VDD18#2 AJ34

DP/DPE_VSSR#1 AN34

DP/DPE_VSSR#2 AP39

DP/DPE_VSSR#3 AR39

DP/DPE_VSSR#4 AU37

DPEF_CALR AM39

DPEF_VDD18/DPF_PVDD AL38

DP_VSSR/DPF_PVSS AM35

DPEF/DPF_VDD10#1 AK33

DPEF/DPF_VDD10#2 AK34

DPEF/DPF_VDD18#1 AF34

DPEF/DPF_VDD18#2 AG34

DP/DPF_VSSR#1 AF39

DP/DPF_VSSR#2 AH39

DP/DPF_VSSR#3 AK39

DP/DPF_VSSR#4 AL34

DP/DPF_VSSR#5 AM34

RV127

150_0402_1%

VENUS@RV127

150_0402_1%

VENUS@ 1

2

RV123

150_0402_1%

VENUS@RV123

150_0402_1%

VENUS@

1 2

C V 1 2 0

1 0 U_

0 6 0 3_

6 . 3 V 6 M

V E N U S @

C V 1 2 0

1 0 U_

0 6 0 3_

6 . 3 V 6 M

V E N U S @

1

2

T82 PADT82 PAD



5 4 3 2 1

MAA0

MAB0

MDB0MDA0

DDR2

GDDR5/GDDR3

DDR3

DDR2

GDDR3/GDDR5

DDR3

UV1D DDR2

GDDR5/GDDR3

DDR3

DDR2

GDDR3/GDDR5

DDR3

UV1D

C5

P8

DDR2

GDDR3/GDDR5

DDR3

DDR2

GDDR5/GDDR3

DDR3

UV1CDDR2

GDDR3/GDDR5

DDR3

DDR2

GDDR5/GDDR3

DDR3

UV1C

C37

G24



5 4 3 2 1

D D

C C

B B

A A

route 50ohms single-ended/100ohms diffand keep shortDebug only, for clock observation, if not needed, DNI5mil 5mil

This basic topology should be used for DRAM_RST for DDR3/GDDR5.TheseCapacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to becalculated for different Memory ,DRAM Load and board to pass ResetSignal Spec.Place all these components very close to GPU (Within25mm) and keep all component close to each Other (within5mm) except Rser2

+VDD_MEM15_REFSA

+VDD_MEM15_REFSA

+VDD_MEM15_REFSB

+VDD_MEM15_REFSB

+VDD_MEM15_REFDA

+VDD_MEM15_REFDA

+VDD_MEM15_REFDB

+VDD_MEM15_REFDB

DRAM_RST#_R

DRAM_RST#_R

TESTEN

CASA0#CASA1#

CKEA0

CKEA1

CLKA0

CLKA0#

CLKA1CLKA1#

CSA0#_0

CSA1#_0

MAA14

ODTA0ODTA1

RASA0#

RASA1#

WEA0#WEA1#

CASB0#CASB1#

CKEB0

CKEB1

CLKB0

CLKB0#

CLKB1CLKB1#

CSB0#_0

CSB1#_0

MAB13MAB14

ODTB0ODTB1

RASB0#

RASB1#

WEB0#WEB1#

A_BA0 A_BA1

A_BA2

DQMA#0

DQMA#1DQMA#2

DQMA#3DQMA#4DQMA#5DQMA#6

DQMA#7

MAA0MAA1

MAA10MAA11MAA12

MAA2MAA3

MAA4MAA5

MAA6MAA7

MAA8MAA9

QSA#0QSA#1QSA#2

QSA#3QSA#4

QSA#5QSA#6

QSA#7

QSA0QSA1

QSA2QSA3

QSA4QSA5

QSA6QSA7

B_BA0B_BA1

B_BA2

DQMB#0

DQMB#1DQMB#2

DQMB#3DQMB#4DQMB#5DQMB#6

DQMB#7

MAB0MAB1

MAB10MAB11MAB12

MAB2MAB3

MAB4MAB5

MAB6MAB7

MAB8MAB9

QSB#0QSB#1QSB#2

QSB#3QSB#4

QSB#5QSB#6

QSB#7

QSB0QSB1

QSB2QSB3

QSB4QSB5

QSB6QSB7

MDB0MDB1

MDB10MDB11MDB12MDB13

MDB14MDB15

MDB16MDB17

MDB18MDB19

MDB2


MDB24MDB25

MDB26MDB27

MDB28MDB29

MDB3

MDB30MDB31

MDB32MDB33


MDB38MDB39

MDB4

MDB40MDB41

MDB42MDB43

MDB44MDB45

MDB46MDB47

MDB48MDB49

MDB5

MDB50MDB51

MDB52MDB53

MDB54MDB55

MDB56MDB57

MDB58MDB59

MDB6

MDB60MDB61

MDB62MDB63

MDB7

MDB8MDB9

MDA10MDA11MDA12MDA13

MDA14MDA15

MDA16MDA17

MDA18MDA19


MDA24MDA25

MDA26MDA27

MDA28MDA29

MDA30MDA31

MDA32MDA33


MDA38MDA39

MDA40MDA41

MDA42MDA43

MDA44MDA45

MDA46MDA47


MDA52MDA53

MDA54MDA55

MDA56MDA57

MDA58MDA59

MDA60MDA61

MDA62MDA63

MDA8MDA9

MDA[0..63]

MAA[14..0]

A_BA[2..0]

MDB[0..63]

MAB[14..0]

B_BA[2..0]

MDA0MDA1

MDA2MDA3

MDA4MDA5

MDA6MDA7

MAA13

DRAM_RST#<54,55>

C LK A1 < 54 >

C LK A0 < 54 >

R AS A0 # < 54 >

C LK A1 # < 54 >

C LK A0 # < 54 >

C SA 0# _ 0 < 54 >

W EA 0# < 54 >

C AS A0 # < 54 >

C SA 1# _ 0 < 54 >

R AS A1 # < 54 >

O DT A1 < 54 >

O DT A0 < 54 >

W EA 1# < 54 >

C AS A1 # < 54 >

C KE A0 < 54 >C KE A1 < 54 >

C L KB 1 < 55 >

C L KB 0 < 55 >

R AS B0 # < 55 >

C KE B0 < 55 >

C L KB 1# < 55 >

C L KB 0# < 55 >

C SB 0# _0 < 55 >

W EB 0# < 55 >

C AS B0 # < 55 >

C KE B1 < 55 >

C SB 1# _0 < 55 >

R AS B1 # < 55 >

O DT B 1 < 55 >

O DT B 0 < 55 >

W EB 1# < 55 >

C AS B1 # < 55 >

A_BA[2..0] <54>

MAA[14. .0] <54>

MDA[0..63]<54>

QSA#[7..0] <54>

Q SA [7 . .0 ] < 54 >

DQMA#[7. .0] <54>

B_BA[2. .0] <55>

MAB[14. .0] <55>

MDB[0..63]<55>

QSB#[7..0] <55>

Q SB [7 .. 0 ] < 55 >

DQMB#[7. .0] <55>

+1. 35V_MEM_GF X +1. 35V_MEM_GF X

+1.35V_MEM_GFX +1.35V_MEM_GFX

+1.35V_MEM_GFX

Title


Date: Sheet of




0.2

ATI_Sun XT_M2_MEM IF


2013/03/09 2014/04/01


LA-9981P

Title


Date: Sheet of




0.2



2013/03/09 2014/04/01


LA-9981P

Title


Date: Sheet of




0.2



2013/03/09 2014/04/01


LA-9981P

CV224

0.1U_0402_16V7KDIS@

CV224

0.1U_0402_16V7KDIS@

1

2

RV146100_0402_1%

DIS@

RV146100_0402_1%

DIS@

1

2

M E M O R Y

I N T E R F A C E

B

G D D R 5

GDDR5/DDR2/GDDR3


M E M O R Y

I N T E R F A C E

B

G D D R 5

GDDR5/DDR2/GDDR3


DQB0_0/DQB_0C5

DQB0_1/DQB_1C3

DQB0_10/DQB_10J4

DQB0_11/DQB_11K6

DQB0_12/DQB_12K5

DQB0_13/DQB_13L4

DQB0_14/DQB_14M6

DQB0_15/DQB_15M1

DQB0_16/DQB_16M3

DQB0_17/DQB_17M5

DQB0_18/DQB_18N4

DQB0_19/DQB_19P6

DQB0_2/DQB_2E3

DQB0_20/DQB_20P5

DQB0_21/DQB_21R4

DQB0_22/DQB_22T6

DQB0_23/DQB_23T1

DQB0_24/DQB_24U4

DQB0_25/DQB_25V6

DQB0_26/DQB_26V1

DQB0_27/DQB_27V3

DQB0_28/DQB_28Y6

DQB0_29/DQB_29Y1

DQB0_3/DQB_3E1

DQB0_30/DQB_30Y3DQB0_31/DQB_31

Y5

DQB1_0/DQB_32 AA4

DQB1_1/DQB_33 AB6

DQB1_2/DQB_34 AB1

DQB1_3/DQB_35 AB3

DQB1_4/DQB_36 AD6

DQB1_5/DQB_37 AD1

DQB1_6/DQB_38 AD3

DQB1_7/DQB_39 AD5

DQB0_4/DQB_4F1

DQB1_8/DQB_40 AF1

DQB1_9/DQB_41 AF3

DQB1_10/DQB_42 AF6

DQB1_11/DQB_43 AG4

DQB1_12/DQB_44 AH5

DQB1_13/DQB_45 AH6

DQB1_14/DQB_46 AJ4

DQB1_15/DQB_47 AK3

DQB1_16/DQB_48 AF8

DQB1_17/DQB_49 AF9

DQB0_5/DQB_5F3

DQB1_18/DQB_50 AG8

DQB1_19/DQB_51 AG7

DQB1_20/DQB_52 AK9

DQB1_21/DQB_53 AL7

DQB1_22/DQB_54 AM8

DQB1_23/DQB_55 AM7

DQB1_24/DQB_56 AK1

DQB1_25/DQB_57 AL4

DQB1_26/DQB_58 AM6

DQB1_27/DQB_59 AM1

DQB0_6/DQB_6F5

DQB1_28/DQB_60 AN4

DQB1_29/DQB_61 AP3

DQB1_30/DQB_62 AP1

DQB1_31/DQB_63 AP5

DQB0_7/DQB_7G4

DQB0_8/DQB_8H5

DQB0_9/DQB_9H6

MVREFDBY12

MVREFSB AA12

TESTEN AD28

CASB0BW10

CASB1B AA10

CKEB0U10

CKEB1 AA11

CLKB0L9

CLKB0BL8

CLKB1 AD8

CLKB1B AD7

CLKTESTA AK10

CLKTESTB AL10

CSB0B_0P10

CSB0B_1L10

CSB1B_0 AD10

CSB1B_1 AC10

WCKB0_0/DQMB_0H3

WCKB0B_0/DQMB_1H1

WCKB0_1/DQMB_2T3

WCKB0B_1/DQMB_3T5

WCKB1_0/DQMB_4 AE4

WCKB1B_0/DQMB_5 AF5

WCKB1_1/DQMB_6 AK6

WCKB1B_1/DQMB_7 AK5

DRAM_RST AH11

MAB0_0/MAB_0P8

MAB0_1/MAB_1T9

MAB1_2/MAB_10 AC8

MAB1_3/MAB_11 AC9

MAB1_4/MAB_12 AA7

MAB1_5/BA2 AA8

MAB1_6/BA0Y8

MAB1_7/BA1 AA9

MAB0_2/MAB_2P9

MAB0_3/MAB_3N7

MAB0_4/MAB_4N8

MAB0_5/MAB_5N9

MAB0_6/MAB_6U9

MAB0_7/MAB_7U8

MAB1_0/MAB_8Y9

MAB1_1/MAB_9W9

ADBIB0/ODTB0T7

ADBIB1/ODTB1W7

RASB0BT10

RASB1BY10

EDCB0_0/QSB_0/RDQSB_0F6

EDCB0_1/QSB_1/RDQSB_1K3

EDCB0_2/QSB_2/RDQSB_2P3

EDCB0_3/QSB_3/RDQSB_3V5

EDCB1_0/QSB_4/RDQSB_4 AB5EDCB1_1/QSB_5/RDQSB_5

AH1

EDCB1_2/QSB_6/RDQSB_6 AJ9

EDCB1_3/QSB_7/RDQSB_7 AM5

DDBIB0_0/QSB_0B/WDQSB_0G7

DDBIB0_1/QSB_1B/WDQSB_1K1

DDBIB0_2/QSB_2B/WDQSB_2P1

DDBIB0_3/QSB_3B/WDQSB_3W4

DDBIB1_0/QSB_4B/WDQSB_4 AC4

DDBIB1_1/QSB_5B/WDQSB_5 AH3

DDBIB1_2/QSB_6B/WDQSB_6 AJ8

DDBIB1_3/QSB_7B/WDQSB_7 AM3

WEB0BN10

WEB1B AB11

MAB0_8T8

MAB1_8W8RV206 DIS@ 120_0402_1%RV206 DIS@ 120_0402_1%1 2

CV221

0.1U_0402_16V7KDIS@

CV221

0.1U_0402_16V7KDIS@

1

2

CV220

0.1U_0402_16V7KDIS@

CV220

0.1U_0402_16V7KDIS@

1

2

RV136

@

51.1_0402_1%RV136

@

51.1_0402_1%

1

2

CV223

0.1U_0402_16V7KDIS@

CV223

0.1U_0402_16V7KDIS@

1

2

CV222

120P_0402_50V9

DIS@CV222

120P_0402_50V9

DIS@ 1

2

CV218@

0.1U_0402_16V7K

CV218@

0.1U_0402_16V7K

1

2

RV133

5.11K_0402_1%

DIS@RV133

5.11K_0402_1%

DIS@1 2

RV147100_0402_1%

DIS@

RV147100_0402_1%

DIS@

1

2

CV219@

0.1U_0402_16V7K

CV219@

0.1U_0402_16V7K

1

2

RV142

40.2_0402_1%DIS@

RV142

40.2_0402_1%DIS@

1

2

RV149100_0402_1%

DIS@

RV149100_0402_1%

DIS@

1

2

RV144

10_0402_1%DIS@

RV144

10_ 0402_1%DIS@

1 2

RV137

@

51.1_0402_1%RV137

@

51.1_0402_1%

1

2

RV140

40.2_0402_1%DIS@

RV140

40.2_0402_1%DIS@

1

2 RV148

100_0402_1%

DIS@

RV148100_0402_1%

DIS@

1

2

RV139

40.2_0402_1%DIS@

RV139

40.2_0402_1%DIS@

1

2

RV145

4.99K_0402_1%

DIS@RV145

4.99K_0402_1%

DIS@

1

2

RV143

51.1_0402_1%DIS@

RV143

51.1_0402_1%DIS@

1 2

RV138

@

4.7K_0402_5%RV138

@

4.7K_0402_5%

1

2

M E M O R Y

I N T E R F A C E

A

GDDR5/DDR2/GDDR3

G D D R 5


VENUS@

M E M O R Y

I N T E R F A C E

A

GDDR5/DDR2/GDDR3

G D D R 5


VENUS@

DQA0_0/DQA_0C37

DQA0_1/DQA_1C35

DQA0_10/DQA_10C30

DQA0_11/DQA_11 A30

DQA0_12/DQA_12F28

DQA0_13/DQA_13C28

DQA0_14/DQA_14 A28

DQA0_15/DQA_15E28

DQA0_16/DQA_16D27

DQA0_17/DQA_17F26

DQA0_18/DQA_18C26

DQA0_19/DQA_19 A26

DQA0_2/DQA_2 A35

DQA0_20/DQA_20F24

DQA0_21/DQA_21C24

DQA0_22/DQA_22 A24

DQA0_23/DQA_23E24

DQA0_24/DQA_24C22

DQA0_25/DQA_25 A22

DQA0_26/DQA_26F22

DQA0_27/DQA_27D21

DQA0_28/DQA_28 A20

DQA0_29/DQA_29F20

DQA0_3/DQA_3E34

DQA0_30/DQA_30D19DQA0_31/DQA_31

E18

DQA1_0/DQA_32C18

DQA1_1/DQA_33 A18

DQA1_2/DQA_34F18

DQA1_3/DQA_35D17

DQA1_4/DQA_36 A16

DQA1_5/DQA_37F16

DQA1_6/DQA_38D15

DQA1_7/DQA_39E14

DQA0_4/DQA_4G32

DQA1_8/DQA_40F14

DQA1_9/DQA_41D13

DQA1_10/DQA_42F12

DQA1_11/DQA_43 A12

DQA1_12/DQA_44D11

DQA1_13/DQA_45F10

DQA1_14/DQA_46 A10

DQA1_15/DQA_47C10

DQA1_16/DQA_48G13

DQA1_17/DQA_49H13

DQA0_5/DQA_5D33

DQA1_18/DQA_50J13

DQA1_19/DQA_51H11

DQA1_20/DQA_52G10

DQA1_21/DQA_53G8

DQA1_22/DQA_54K9

DQA1_23/DQA_55K10

DQA1_24/DQA_56G9

DQA1_25/DQA_57 A8

DQA1_26/DQA_58C8

DQA1_27/DQA_59E8

DQA0_6/DQA_6F32

DQA1_28/DQA_60 A6

DQA1_29/DQA_61C6

DQA1_30/DQA_62E6

DQA1_31/DQA_63 A5

DQA0_7/DQA_7E32

DQA0_8/DQA_8D31

DQA0_9/DQA_9F30

MEM_CALRP1M12

MVREFDAL18

MVREFSAL20

MEM_CALRN0L27

MEM_CALRN1N12

MEM_CALRN2 AG12

MEM_CALRP0M27

MEM_CALRP2 AH12

CASA0BK20

CASA1BK17

CKEA0K21

CKEA1J20

CLKA0H27

CLKA0BG27

CLKA1J14

CLKA1BH14

CSA0B_0K24

CSA0B_1K27

CSA1B_0M13

CSA1B_1K16

WCKA0_0/DQMA_0 A32

WCKA0B_0/DQMA_1C32

WCKA0_1/DQMA_2D23

WCKA0B_1/DQMA_3E22

WCKA1_0/DQMA_4C14

WCKA1B_0/DQMA_5 A14

WCKA1_1/DQMA_6E10

WCKA1B_1/DQMA_7D9

MAA0_0/MAA_0G24

MAA0_1/MAA_1J23

MAA1_2/MAA_10L13

MAA1_3/MAA_11G16

MAA1_4/MAA_12J16

MAA1_5/MAA_13_BA2H16

MAA1_6/MAA_14_BA0J17

MAA1_7/MAA_A15_BA1H17

MAA0_2/MAA_2H24

MAA0_3/MAA_3J24

MAA0_4/MAA_4H26

MAA0_5/MAA_5J26

MAA0_6/MAA_6H21

MAA0_7/MAA_7G21

MAA1_0/MAA_8H19

MAA1_1/MAA_9H20

ADBIA0/ODTA0J21

ADBIA1/ODTA1G19

RASA0BK23

RASA1BK19

EDCA0_0/QSA_0/RDQSA_0C34

EDCA0_1/QSA_1/RDQSA_1D29


EDCA0_3/QSA_3/RDQSA_3E20

EDCA1_0/QSA_4/RDQSA_4 E16EDCA1_1/QSA_5/RDQSA_5

E12

EDCA1_2/QSA_6/RDQSA_6J10


MAA0_8H23

MAA1_8J19

DDBIA0_0/QSA_0B/WDQSA_0 A34

DDBIA0_1/QSA_1B/WDQSA_1E30

DDBIA0_2/QSA_2B/WDQSA_2E26

DDBIA0_3/QSA_3B/WDQSA_3C20



DDBIA1_2/QSA_6B/WDQSA_6J11

DDBIA1_3/QSA_7B/WDQSA_7F8

WEA0BK26

WEA1BL15

RV141

40.2_0402_1%DIS@

RV141

40.2_0402_1%DIS@

1

2



www.s-manuals.com

http://www.s-manuals.com/

http://www.s-manuals.com/

compal la-9981p r0.2 schematics

Documents