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COMP290-084COMP290-084

Clockless Logic and Silicon Clockless Logic and Silicon CompilersCompilers

ororHow do I take “hard” out of hardware How do I take “hard” out of hardware

design?design?

Montek SinghMontek Singh

Thu, Jan 12, 2006Thu, Jan 12, 2006

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Course Information (1)Course Information (1)Course Number: COMP290-084Course Number: COMP290-084

Time and PlaceTime and Place Tue/Thu 3:30-4:45pm, Sitterson Hall 115Tue/Thu 3:30-4:45pm, Sitterson Hall 115

Any conflicts?Any conflicts?

InstructorInstructor Montek SinghMontek Singh montek@cs.unc.edumontek@cs.unc.edu (not singh@cs!)(not singh@cs!) SN 245, 962-1832SN 245, 962-1832

Teaching AssistantTeaching Assistant NoneNone

Course Web PageCourse Web Page http://www.cs.unc.edu/~montekhttp://www.cs.unc.edu/~montek

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Course Information (2)Course Information (2)Prerequisites:Prerequisites:

undergraduate knowledge of: digital logic, algorithms, undergraduate knowledge of: digital logic, algorithms, discrete math (sets and graphs), programming discrete math (sets and graphs), programming languageslanguages

you are assumed to know the following topics:you are assumed to know the following topics:digital logic: Boolean algebra, logic gates, and latches and digital logic: Boolean algebra, logic gates, and latches and

registersregistersalgorithms: search techniques, enumeration, divide and algorithms: search techniques, enumeration, divide and

conquer, and time complexityconquer, and time complexitydiscrete math: elementary set theory and graph theorydiscrete math: elementary set theory and graph theory

no knowledge of advanced circuit design or of VLSI is no knowledge of advanced circuit design or of VLSI is assumedassumed relevant topics will be covered in class as neededrelevant topics will be covered in class as neededVLSI primer included in this classVLSI primer included in this class

no knowledge of compilers is assumedno knowledge of compilers is assumedonly undergraduate programming languages requiredonly undergraduate programming languages required

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Course Information (3)Course Information (3)Reading Material:Reading Material:

Lecture notesLecture notes Papers and technical reports supplied by instructorPapers and technical reports supplied by instructor

Reference Textbooks (optional):Reference Textbooks (optional): Principles of CMOS VLSI Design: A Systems Principles of CMOS VLSI Design: A Systems

PerspectivePerspectiveWeste and Eshraghian. Addison-Wesley, 1993.Weste and Eshraghian. Addison-Wesley, 1993.

Computer Aids for VLSI DesignComputer Aids for VLSI DesignSteven M. Rubin. Static Free Software. Steven M. Rubin. Static Free Software.

http://www.rulabinsky.com/cavdhttp://www.rulabinsky.com/cavd (Free, online) (Free, online) Principles of Asynchronous Circuit Design Principles of Asynchronous Circuit Design A A

Systems Perspective. Systems Perspective. Jens Sparsø and Steve Furber (eds.). Kluwer. (ASK ME!)Jens Sparsø and Steve Furber (eds.). Kluwer. (ASK ME!)

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Course Information (4): ContentCourse Information (4): ContentClockless logic:Clockless logic:

Introductory conceptsIntroductory concepts Data representation, and control signalingData representation, and control signaling

Graphical representation of asynchronous systemsGraphical representation of asynchronous systems Petri nets, state transition graphs, burst-mode machines, etc.Petri nets, state transition graphs, burst-mode machines, etc.

Algorithms for logic synthesisAlgorithms for logic synthesis Combinational and sequentialCombinational and sequential

Pipelining and ArchitecturePipelining and Architecture

Silicon Compilers:Silicon Compilers: High-level description languagesHigh-level description languages Compilation from algorithms to hardwareCompilation from algorithms to hardware State-of-the-art compilers and analysis toolsState-of-the-art compilers and analysis tools

Optional topics:Optional topics: Formal methodsFormal methods

Performance analysisPerformance analysis VerificationVerification

Case studies of real-world asynchronous processorsCase studies of real-world asynchronous processors

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Course Information (4)Course Information (4)GradingGrading

Homework: 30%Homework: 30% Project: 50%Project: 50% Presentation: 10%Presentation: 10% Class participation: 10%Class participation: 10%

Honor Code is in effectHonor Code is in effect encouraged to discuss ideas/conceptsencouraged to discuss ideas/concepts work handed in must be your ownwork handed in must be your own acknowledge all helpacknowledge all help

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Lecture 1: IntroductionLecture 1: Introduction

What is asynchronous design?What is asynchronous design? Why do we want to study it?Why do we want to study it? How is data represented in an asynchronous How is data represented in an asynchronous system?system? How is information exchanged?How is information exchanged?

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Introduction: Clocked Digital Introduction: Clocked Digital DesignDesignMost current digital systems are Most current digital systems are synchronous:synchronous:

Clock:Clock: a global signal that paces operation of all a global signal that paces operation of all componentscomponents

clockclock

Benefit of clocking: Benefit of clocking: enables discrete-time enables discrete-time representationrepresentation all components operate exactly once per clock all components operate exactly once per clock

ticktick component outputs need to be ready by next component outputs need to be ready by next

clock tickclock tickallows “glitchy” or incorrect outputs between clock ticksallows “glitchy” or incorrect outputs between clock ticks

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Microelectronics TrendsMicroelectronics TrendsCurrent and Future Trends: Current and Future Trends: Significant Significant

ChallengesChallenges

Large-Scale “Systems-on-a-Chip” (SoC)Large-Scale “Systems-on-a-Chip” (SoC)100 Million ~ 1 Billion transistors/chip100 Million ~ 1 Billion transistors/chip

Very High SpeedsVery High Speedsmultiple GigaHertz clock ratesmultiple GigaHertz clock rates

Explosive Growth in Consumer ElectronicsExplosive Growth in Consumer Electronicsdemand for ever-increasing functionality …demand for ever-increasing functionality …… … with very low power consumption (limited battery life)with very low power consumption (limited battery life)

Higher Portability/Modularity/ReusabilityHigher Portability/Modularity/Reusability““plug ’n play” components, robust interfacesplug ’n play” components, robust interfaces

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Challenges to Clocked DesignChallenges to Clocked DesignBreakdown of Single-Clock Paradigm:Breakdown of Single-Clock Paradigm:

Chip will be partitioned intoChip will be partitioned into multiple timing domainsmultiple timing domainschallenge: gluing together multiple timing domainschallenge: gluing together multiple timing domains

– glue logic is susceptible to “metastability” (=incorrect values glue logic is susceptible to “metastability” (=incorrect values

transferred) and latency overheadstransferred) and latency overheads

Increasing Difficulties with Clocked Design:Increasing Difficulties with Clocked Design: Clock distribution: requires Clock distribution: requires significantsignificant designer effort designer effort

Performance bottleneck: a single slow componentPerformance bottleneck: a single slow component

Clock burns large fraction of chip power (~40-70%)Clock burns large fraction of chip power (~40-70%)

Fixed clock rate: poor match forFixed clock rate: poor match fordesigning designing reusable componentsreusable components interfacing with interfacing with mixed-timing environmentsmixed-timing environments

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What is Asynchronous Design?What is Asynchronous Design? Digital design with Digital design with no centralized clockno centralized clock Synchronization using local Synchronization using local “handshaking”“handshaking”

Asynchronous SystemAsynchronous System(Distributed Control)(Distributed Control)

handshakinghandshakinginterfaceinterface

Synchronous SystemSynchronous System(Centralized Control)(Centralized Control)

clockclock

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Why Asynchronous Design? (1)Why Asynchronous Design? (1) Higher PerformanceHigher Performance

May obtain “average-case” operation (not “worst-May obtain “average-case” operation (not “worst-case”)case”)not limited by slowest componentnot limited by slowest component

Avoids overheads of multi-GHz clock distributionAvoids overheads of multi-GHz clock distribution

Lower PowerLower Power No clock power expendedNo clock power expended Inactive components consume negligible powerInactive components consume negligible power

Better Electromagnetic CompatibilityBetter Electromagnetic Compatibility Smooth radiation spectra: Smooth radiation spectra: no clock spikesno clock spikes Much less interference with sensitive receivers Much less interference with sensitive receivers [e.g., [e.g.,

Philips pagers, smartcards]Philips pagers, smartcards]

Greater Flexibility/ModularityGreater Flexibility/Modularity Naturally adapt to variable-speed environmentsNaturally adapt to variable-speed environments Supports reusable componentsSupports reusable components

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Why Asynchronous Design? (2)Why Asynchronous Design? (2) The world already is mostly asynchronous!The world already is mostly asynchronous!

Events at the level of (or in between) large-scale systems are Events at the level of (or in between) large-scale systems are asynchronousasynchronous several seconds to several millisecondsseveral seconds to several milliseconds e.g., PC-printer communication, keyboard inputs, network comm.e.g., PC-printer communication, keyboard inputs, network comm.

Events at the board level (or between chips) are often Events at the board level (or between chips) are often asynchronousasynchronous milliseconds to 100 nanosecondsmilliseconds to 100 nanoseconds e.g., CPU-memory interface, interface with I/O subsystem (interrupts)e.g., CPU-memory interface, interface with I/O subsystem (interrupts)

Events within a chip, at the level of functional units (e.g., Events within a chip, at the level of functional units (e.g., adders, control logic) are currently mostly synchronousadders, control logic) are currently mostly synchronous several nanoseconds to 100 picosecondsseveral nanoseconds to 100 picoseconds

Events at the level of a single logic gate are asynchronousEvents at the level of a single logic gate are asynchronous 10 picoseconds10 picoseconds

Events at the quantum level are asynchronousEvents at the quantum level are asynchronous picoseconds to femtosecondspicoseconds to femtoseconds

So, why bother with clocks at all?!So, why bother with clocks at all?! make everything asynchronous make everything asynchronous greater elegance and greater elegance and

robustnessrobustness

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Challenges of Asynchronous Challenges of Asynchronous DesignDesign

communication must be hazard-free!communication must be hazard-free! special design challenge =special design challenge = “hazard-free synthesis”“hazard-free synthesis”

Testability Issues:Testability Issues: absence of clock means no “single-stepping”absence of clock means no “single-stepping”

Lack of Commercial CAD Tools:Lack of Commercial CAD Tools: chicken-and-egg problemchicken-and-egg problem

Hazards: Hazards: potential “glitches” on wirepotential “glitches” on wire

clean signalsclean signals

hazardous signals

clockclock tick tick

no problemno problemfor for clockclockededsystemssystems

no problemno problemfor for clockclockededsystemssystems

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Asynchronous Design: Past & Asynchronous Design: Past & PresentPresentAsync Design: Async Design: In existence for 50 years, but … In existence for 50 years, but …

… … many recent technical advances:many recent technical advances: Hazard-Free Circuit Design:Hazard-Free Circuit Design:

several practical techniques for controllers several practical techniques for controllers [Stanford/Columbia][Stanford/Columbia]

Design for Testability:Design for Testability:several test solutions, e.g. Philips Researchseveral test solutions, e.g. Philips Research

Maturing Computer-Aided-Design (“CAD”) Tools:Maturing Computer-Aided-Design (“CAD”) Tools:software tools for automated design software tools for automated design

[Philips,Columbia,Manchester][Philips,Columbia,Manchester] recent DARPA program [Boeing,Philips,UNC,Columbia,…]recent DARPA program [Boeing,Philips,UNC,Columbia,…]

Successful Fabricated Chips:Successful Fabricated Chips:embedded processors, high-speed pipelines, consumer embedded processors, high-speed pipelines, consumer

electronics…electronics…

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Recent Commercial Interest (1)Recent Commercial Interest (1)Several commercial asynchronous chips:Several commercial asynchronous chips:

Philips: Philips: asynchronous 80c51 microcontrollersasynchronous 80c51 microcontrollersused in commercial pagers [1998] and smartcards [2001]used in commercial pagers [1998] and smartcards [2001]

Univ. of Manchester: Univ. of Manchester: async ARM processor [2000]async ARM processor [2000] Motorola: Motorola: async divider in PowerPC chip [2000]async divider in PowerPC chip [2000] HAL: HAL: async floating-point dividerasync floating-point divider

in HAL-I and II processors [early 1990’s]in HAL-I and II processors [early 1990’s]

Recent experimental chips:Recent experimental chips: IBM, Sun and Intel:IBM, Sun and Intel:

fast pipelines, arbiters, instruction-length decoder…fast pipelines, arbiters, instruction-length decoder… IBM/Columbia/UNC: IBM/Columbia/UNC: asynchronous digital FIR filterasynchronous digital FIR filter

Several recent startups:Several recent startups: Handshake Solutions, Theseus Logic, Codetronix, Handshake Solutions, Theseus Logic, Codetronix,

Fulcrum, Silistix, …Fulcrum, Silistix, …

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Recent Commercial Interest (2)Recent Commercial Interest (2)Major DARPA program:Major DARPA program:

~$13M~$13M Goals:Goals:

commercial-strength automated CAD tool (=silicon commercial-strength automated CAD tool (=silicon compiler)compiler)

– direct translation from algorithms to chip layoutdirect translation from algorithms to chip layout– capable of producing chips with 50M transistors or morecapable of producing chips with 50M transistors or more– rich suite of analysis and optimization toolsrich suite of analysis and optimization tools

demonstration chipdemonstration chip– Boeing applicationBoeing application– show dramatic improvements in: design time, power show dramatic improvements in: design time, power

consumption, noise pollution, speed (?)consumption, noise pollution, speed (?) Team:Team:

led by Boeingled by Boeingasync startups: Theseus, Handshake Solutions, Codetronixasync startups: Theseus, Handshake Solutions, Codetronixuniversities: UNC, Columbia, UW, OrSUuniversities: UNC, Columbia, UW, OrSU

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A 5-minute Homework ProblemA 5-minute Homework ProblemAliceAlice and and BobBob live on opposite sides of a wide river: live on opposite sides of a wide river:

AliceAlice is supposed to send a message (say, a “Yes”/”No”) is supposed to send a message (say, a “Yes”/”No”) across to across to Bob Bob around midnight. Both have flashlights, around midnight. Both have flashlights, but neither owns a watch. What should they do?but neither owns a watch. What should they do?

Suggest several strategies, and discuss pros and cons of Suggest several strategies, and discuss pros and cons of each.each.

AliceAlice

BobBob

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got it

got it

Solution 1Solution 1AliceAlice uses 2 lamps:uses 2 lamps:

1 to indicate that she is ready with the message, and1 to indicate that she is ready with the message, and 1 for the message itself1 for the message itself

BobBob uses 1 lamp:uses 1 lamp: to indicate that he has received the messageto indicate that he has received the message

AliceAlice

BobBobreadyready

yes/no

yes/no

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Solution 2Solution 2AliceAlice uses 2 lamps:uses 2 lamps:

GreenGreen lamp to indicate “yes” lamp to indicate “yes” Red Red lamp to indicate “no”lamp to indicate “no”

BobBob uses 1 lamp:uses 1 lamp: to indicate that he has received the messageto indicate that he has received the message

got it

got it

AliceAlice

BobBobnono

yesyes

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Solution 3Solution 3What if Alice and Bob could keep time?What if Alice and Bob could keep time?

AliceAlice uses 1 lamp uses 1 lamp for the message:for the message: At 12 midnight: turns on lamp At 12 midnight: turns on lamp if message = “yes”if message = “yes” At 12:01: turns lamp offAt 12:01: turns lamp off

BobBob needs no lamps!needs no lamps! Takes down the message between 12 and 12:01Takes down the message between 12 and 12:01

Pros:Pros: Fewer signals, lesser processing needed Fewer signals, lesser processing needed

Cons:Cons: Alice and Bob must keep their clocks closely Alice and Bob must keep their clocks closely synchronizedsynchronized If Bob’s watch is off by a minute, incorrect communication If Bob’s watch is off by a minute, incorrect communication

possiblepossible