common-centroid capacitor layout generation considering device matching and parasitic minimization

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 7, JULY 2013 991

Common-Centroid Capacitor Layout GenerationConsidering Device Matching and

Parasitic MinimizationMark Po-Hung Lin, Member, IEEE, Yi-Ting He, Vincent Wei-Hao Hsiao, Rong-Guey Chang, and

Shuenn-Yuh Lee, Member, IEEE

Abstract—In analog layout design, the accuracy of capacitanceratios correlates closely with both the matching propertiesamong the ratioed capacitors and the induced parasitics dueto interconnecting wires. However, most of the previous worksonly emphasized the matching properties of a common-centroidplacement, but ignored the induced parasitics after it is routed.This paper addresses the parasitic issue in addition to devicematching during common-centroid capacitor layout generation.To effectively minimize the routing-induced parasitics, a novelcommon-centroid placement style, distributed connected unitcapacitors, is presented. Based on the placement style, theratioed capacitor layout generation flow and algorithms areproposed to simultaneously optimize the matching properties of acommon-centroid placement and minimize the induced parasitics.Experimental results show that the proposed approach cangreatly reduce area, wirelength, and routing-induced parasitics,and guarantee the best matching quality after routing.

Index Terms—Analog layout, capacitor matching, common-centroid constraint, parasitic minimization, placement, routing.

I. Introduction

RATIOED capacitors are frequently applied to many ana-log circuit components, such as amplifiers, integrators,

filters, and data converters [3], [4], as seen in Fig. 1. By takingadvantage of the charge ratio among capacitors, these circuitcomponents are designed to be independent of the absolute ca-pacitance values of the capacitors because absolute capacitancevalues are much more sensitive to process variation than therelative capacitance ratio among capacitors. Consequently, theaccuracy of the capacitance ratio among the ratioed capacitorsis the key to circuit performance and robustness. For example,

Manuscript received May 1, 2012; revised July 27, 2012 and September 12,2012; accepted October 5, 2012. Date of current version June 14, 2013. Thiswork was supported in part by the National Science Council (NSC) of Taiwanunder Grant NSC 098-2218-E-194-008-MY3. This paper was recommendedby Associate Editor H. E. Graeb.

M. P.-H. Lin, Y.-T. He, V. W.-H. Hsiao, and S.-Y. Lee are with theDepartment of Electrical Engineering, National Chung Cheng University,Chiayi 621, Taiwan (e-mail: [email protected]; [email protected];[email protected]; [email protected]).

R.-G. Chang is with the Department of Computer Science and Engi-neering, and the Advanced Institute of Manufacturing With High-Tech In-novations, National Chung Cheng University, Chiayi 621, Taiwan (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCAD.2012.2226457

Fig. 1. Ratioed capacitors in analog circuits. (a) Switch-capacitor implemen-tation of a lossy integrator. (b) Charge-scaling DAC using binary weightedcapacitors. [4]

in Fig. 1(a), the output gain of the lossy integrator is equalto the ratio of the capacitors, while in Fig. 1(b), the outputvoltage of the digital-to-analog converter (DAC) is a functionof the voltage division among the binary weighted capacitors.

When designing analog layouts, the accuracy of capacitanceratios correlates closely with the matching properties amongthe ratioed capacitors [5]–[10] and the induced parasitics dueto interconnecting wires [7], [8], [10], [11]. The unwantedparasitics can even shift the design performance as high as90% [12]. To improve the accuracy of capacitance ratios, eachcapacitor is divided into multiple identical square unit capac-itors, as shown in Fig. 2, with the largest practical physicaldimension [13]. The guidelines on the aspect ratio, placement,and routing for a unit capacitor array were presented in [7],[10], and [13], which are summarized as follows.

1) Aspect ratio: Matched capacitors must be arranged toform a rectangular array with equal column and rowspacing, respectively. The aspect ratio of the rectangulararray should be close to 1.0.

2) Placement: Matched capacitors should be placed to sat-isfy the properties of coincidence, symmetry, dispersion,

0278-0070/$31.00 c© 2013 IEEE

992 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 7, JULY 2013

Fig. 2. Two different unit capacitor layout styles, including placement androuting, in an 8 × 8 array for the ratioed capacitors, C1, C2, C3, and C4,where the capacitance ratio is 1 : 2 : 16 : 45. (a) Placement violating thecommon-centroid constraint, but resulting in minimized and matched para-sitics after routing. (b) Placement satisfying the common-centroid constraint,but introducing much longer wirelength and larger unmatched parasitics.

and compactness such that the systematic and randommismatches among the capacitors can be minimized.

3) Routing: The wirelength of each net should be mini-mized and matched with respect to the correspondingcapacitor ratio. The coupling between wires connectingto the top and bottom plates of the ratioed capacitorsshould be avoided. Consequently, both the induced par-asitic resistance and capacitance can be minimized.

We noticed that some of these guidelines may conflict withone another. For example, generating a placement with mini-mized interconnecting wirelength may cause higher degrees ofsystematic and random mismatches among capacitors. On thecontrary, generating a placement with minimized systematicand random mismatches among capacitors may also lead tolonger interconnecting wirelength resulting in more unwantedparasitics. Such dilemma is further illustrated in Fig. 2.

Fig. 2 gives two example layouts of four ratioed capacitors,C1, C2, C3, and C4, based on different placement styles inan 8 × 8 unit capacitor array. Each capacitor consists of 1,2, 16, and 45 unit capacitors, respectively. In Fig. 2(a), theunit capacitors of Ci form a connected placement, which caneasily be wired together without additional routing area. Sucha capacitor array results in the most compact layout area.The induced parasitics of each net is also minimized andmatched. However, such a placement does not satisfy theproperties of coincidence, symmetry, and dispersion, which

leads to higher degrees of systematic and random mismatches.Fig. 2(b) shows an alternative layout, where placement issourced from the most recent work [1], and the routingfollows the guidelines in [7]. Although such a placementsatisfies the properties of coincidence, symmetry, and dis-persion, which leads to minimized systematic and randommismatches, it requires much more routing area and wirelengthto connect all unit capacitors. Such a layout has the followingdisadvantages:

1) long interconnecting wirelength;2) unmatched parasitics among different nets;3) more parasitic capacitance due to close parallel wires;4) worse aspect ratio, incompactness, and increased mis-

matches among capacitors after routing due to morecolumn spacing.

According to Fig. 2, we can hardly find a common-centroidunit capacitor layout, in which the routing-induced parasiticresistance and capacitance are exactly matched. However, itis even more feasible to explore common-centroid placementand routing solutions such that the parasitic resistance andcapacitance are minimized. We observed that minimizingrouting-induced parasitics by reducing the number of longinterconnecting wires in a common-centroid unit capacitorarray, as seen in Fig. 2(b), will not degrade, but improvethe parasitic matching. Therefore, the key problem is how togenerate a common-centroid layout, including placement androuting, for ratioed capacitors, which results in minimized ran-dom or systematic mismatches and routing-induced parasiticsfor better circuit performance.

Most of the previous works emphasized the matching prop-erties of common-centroid placements, but ignored the inducedparasitics after the routing is completed. They proposed differ-ent kinds of algorithms to generate various common-centroidplacements, which include the following approaches.

1) deterministic [14]–[19];2) pattern-based [20];3) randomized [21];4) simulated-annealing (SA) [1], [2], [22]–[24].

During placement optimization, these works only evaluatedthe matching quality of a common-centroid placement withoutmuch consideration of the routing quality and routing-inducedparasitics. Although the routing rules, or guidelines, werebriefed in [7], [10], [15], and [16], none of the previous worksproposed effective routing algorithms to optimize the intercon-nection within the common-centroid unit capacitor array, andintegrated both placement and routing algorithms for parasiticminimization. We noticed that some recent works [25] and[26] proposed exact net matching algorithms by snaking, or de-toured routing. These works tried to match parasitic resistanceamong different nets, and simply ignored parasitic capacitance.Consequently, these approaches are only applicable to busor differential-pair routing, but not practical for routing in acommon-centroid unit capacitor array because of unmatchedparasitic capacitance. In addition, the detoured routing willenlarge the routing space among the unit capacitors, whichresults in a higher degree of systematic or random mismatchdue to process variation.

LIN et al.: CAPACITOR LAYOUT GENERATION CONSIDERING DEVICE MATCHING AND MINIMIZATION 993

Fig. 3. Routing-induced parasitic capacitors within a common-centroid capacitor array. (a) Fraction of the common-centroid capacitor layout of the charge-sharing DAC in Fig. 1(b), where the routing-induced parasitic capacitors are highlighted. (b) Charge-scaling DAC in Fig. 1(b) after including all the routing-induced parasitic capacitors.

The contributions of this paper can be summarized in thefollowing.

1) This is the first work in the literature which addresses theeven more practical and important problem of optimiz-ing routing-induced parasitics within a common-centroidunit capacitor array in addition to device matching.

2) We analyze and categorize various routing-induced par-asitics within a common-centroid unit capacitor arrayusing post-layout parasitic extraction tools.

3) We introduce the common-centroid placement style,distributed connected unit capacitors, for better consid-eration of routing-induced parasitics.

4) We propose a complete common-centroid capacitor lay-out generation flow and algorithms, including automaticplacement and routing, to effectively minimize randomor systematic mismatches and all the routing-inducedparasitics.

5) Our experimental results show that the proposed ap-proach can greatly reduce the parasitics with even bettermatching quality compared with the state of the art [1],[2].

The remainder of this paper is organized as follows. Sec-tion II details the routing-induced parasitics within a common-centroid placement and gives guidelines for parasitic mini-mization. Section III formulates the ratioed capacitor layoutgeneration problem. Section IV investigates the distribution ofunit capacitors and its impact on routing. Section V presentsour layout generation flow and algorithms based on the in-vestigation. Section VI reports the experimental results, andSection VII concludes this paper.

II. Routing-Induced Parasitics

Before proposing our problem formulation for common-centroid capacitor layout generation considering device match-ing and parasitic minimization, we first design the layoutsfor ratioed capacitors based on existing technologies andtools. Once the layout is obtained, we perform post-layoutparasitic extraction and analyze the relationship among thecircuit, layout, and extracted parasitics. Finally, we conclude

the layout guidelines for minimization of the routing-inducedparasitics to derive the new problem formulation.

We analyze the routing-induced parasitics within a common-centroid unit capacitor array with the following steps.

1) Generate the common-centroid placement of ratioed ca-pacitors with the consideration of systematic and randommismatches based on the state-of-the-art technique [1].

2) Connect the unit capacitors based on the routing guide-lines in [7].

3) Perform parasitic extraction and analysis using the in-dustry’s sign-off tool [27].

According to the parasitic extraction results, there are twokinds of routing-induced parasitics, including parasitic resis-tors and parasitic capacitors. The value of a parasitic resistoris proportional to the length of the corresponding wire, whilethat of a parasitic capacitor is proportional to the parallelwirelength between two close wires or proportional to theoverlapped area between two wires belonging to differentmetal layers. The routing-induced parasitic capacitors withina common-centroid capacitor array, as seen in Fig. 3, canbe further classified into three categories according to theirinterconnection relationship among the terminals of the ratioedcapacitors and the substrate.

1) Top Plate to Bottom Plate, CTBi : A parasitic capacitor

appears when a via or wire segment connecting to a topplate of a ratioed capacitor is close to another via orwire segment connecting to a bottom plate of the sameor a different ratioed capacitor.

2) Top Plate (Bottom) to Top (Bottom) Plate, CTTij (CBB

ij ): Aparasitic appears when a via or wire segment connectingto a top (bottom) plate of a ratioed capacitor is close toanother via or wire segment connecting to a top (bottom)plate of a different ratioed capacitor.

3) Top (Bottom) Plate to Substrate, CTSi (CBS

i ): A parasiticcapacitor exists between any wire connecting a top(bottom) plate of a ratioed capacitor and the substrate.

According to the analyzed routing-induced parasitics in acommon-centroid unit capacitor array, we summarize the lay-out guidelines to minimize these unwanted parasitic resistorsand capacitors, as seen in Table I.


TABLE I

Layout Guidelines for the Minimization of the Routing-Induced Parasitics in a Unit Capacitor Array

Parasitic Type Layout GuidelinesParasitic resistors Minimize total wirelength of the nets in the unit capacitor array.Parasitic capacitors from top (bottom) plates to the substrate Minimize total wirelength of the nets in the unit capacitor array.Parasitic capacitors from top plates to bottom plates Minimize close parallel wirelength of two nets that connect the top and

bottom plates of the unit capacitors, respectively.Parasitic capacitors from top (bottom) plates to top (bottom) plates Minimize close parallel wirelength of two nets that connect different sets of

top (bottom) plates of the unit capacitors.

III. Problem Formulation

Based on the layout guidelines for a common-centroidunit capacitor array, as illustrated in Section I, and thosefor routing-induced parasitic minimization, as demonstratedin Section II, we propose the new problem formulation forcommon-centroid capacitor layout generation considering bothdevice matching and parasitic minimization.

We are given the following inputs:1) a set of m capacitors, C, where each capacitor, Ci ∈ C,

consists of ki identical unit capacitors;2) the dimension of a unit capacitor;3) the parameters related to random and systematic mis-

matches [1], [14], [16];4) available routing layers and their preferred directions;5) the corresponding design rules;6) the design netlist.

The ratioed capacitor layout generation problem is to producean optimized 2-D common-centroid unit capacitor array, Ar×s,with r rows and s columns in which:

1) oxide-gradient induced mismatch [1], [16] is minimized;2) overall correlation coefficients [1], [9] are maximized;3) total interconnecting wirelength and capacitive coupling

between close parallel wires are minimized;4) the targeted aspect ratio, 1.0, with compact layout area

after routing is achieved.

IV. Distribution of Unit Capacitors

Before proposing the placement and routing algorithms tosolve the addressed problem, we will first investigate theplacement and distribution of unit capacitors in Ar×s and itsimpact on the corresponding routing topologies because therouting-induced parasitics closely correlate with the routingtopologies. The more routing tracks required within Ar×s, themore parasitics induced in Ar×s.

We elaborate and compare three different placement stylesaccording to the unit capacitor distribution of a capacitor, Ci.All these placement styles satisfy the properties of coincidenceand symmetry, so they are all common-centroid.

1) Disconnected Unit Capacitors: The ki unit capacitors ofCi are dispersively placed throughout Ar×s. Such place-ment requires � r

2� (� s2�) horizontal (vertical) routing

tracks [i.e., one routing track in every other horizontal(vertical) channel between adjacent rows (columns)] toconnect all unit capacitors of Ci.

2) Connected Unit Capacitors: The ki unit capacitors ofCi are equally divided into two groups that contain � ki

2 �

Fig. 4. Different placement styles for the capacitor, C5, and the correspond-ing routing topologies. (a) Disconnected unit capacitors. (b) Connected unitcapacitors. (c) Distributed connected unit capacitors.

and � ki

2 � unit capacitors, respectively. The unit capacitorsin each group form a connected placement, and those indifferent groups are not necessary to be connected. Suchplacement requires at most two routing tracks [i.e., eachone in the symmetric horizontal (vertical) channels] toconnect all unit capacitors of Ci when the two groupsare disjointed.

3) Distributed Connected Unit Capacitors: The ki unitcapacitors of Ci are unequally divided into a numberof groups in which all unit capacitors form a con-nected placement. The connected placements of differ-ent groups are dispersively distributed all over Ar×s.Although such placement requires at most � r

2� (� s2�)

horizontal (vertical) routing tracks to connect all unitcapacitors of Ci, it may only require as less routingtracks as the placement type of connected unit capacitorswhen the connected unit capacitors in each group arewell arranged in Ar×s.

Fig. 4 demonstrates the aforementioned three differentplacement styles of the capacitor, C5, which consists of eightunit capacitors in an 8 × 8 unit capacitor array, and theircorresponding routing topologies. The placement style ofdisconnected unit capacitors in Fig. 4(a) requires four routingtracks, while those of connected unit capacitors and distributedconnected unit capacitors in Fig. 4(b) and (c) require only tworouting tracks. Consequently, the placement style of distributedconnected unit capacitors has much shorter interconnectingwirelength and smaller capacitive coupling between wires thanthat of disconnected unit capacitors. It also has much bettermatching properties than that of connected unit capacitors.

V. Flow and Algorithms

Based on the concept of the distributed connected unitcapacitors, we propose our ratioed capacitor layout generation


Fig. 5. Proposed ratioed capacitor layout generation flow.

flow and algorithms to simultaneously minimize systematicand random mismatches, total interconnecting wirelength, andtotal capacitive coupling between wires. The flow of ouralgorithms is illustrated in Fig. 5. First, the dimensions ofthe unit capacitor array, Ar×s, should be determined (seeSection V-A). For each alternative of the array dimensions, wethen perform the simultaneous placement and global routing(see Section V-B) based on the SA algorithm [28] and the pair-sequence representation [1], which are the gray area in Fig. 5.Finally, the detailed routing algorithm (see Section V-C) isexecuted to complete the layout.

A. Array Size Calculation

To achieve the targeted aspect ratio, 1.0, with compactlayout area after routing, we consider two alternatives of the2-D unit capacitor arrays, Ar1×s1 and Ar2×s2 , with differentdimensions. For m capacitors, which consists of k1, k2, . . . ,km unit capacitors, respectively, the array dimensions, r1 × s1

and r2 × s2, can be calculated based on

r1 =⌈√∑m

i=1 ki

⌉s1 =

⌈∑mi=1 ki

r1

⌉(1)

r2 = r1 + 1 s2 =

⌈∑mi=1 ki

r2

⌉. (2)

B. Simultaneous Placement and Global Routing

Once the array dimensions are determined, the placementand global routing algorithms are simultaneously performedfor each unit capacitor array of the specific dimensions. Inthis subsection, we will first review the pair-sequence repre-sentation, and then propose novel algorithms to analyze theroutability for a given placement and assign routing tracks foreach net during placement iterations. The cost functions forthe simulated annealing algorithm will be detailed finally.

1) Pair-Sequence Representation: Since our work is basedon the pair-sequence representation [1], we will first give abrief review over the representation. A pair sequence, Pr×s,is an ordered sequence of unit capacitor pairs. It representsa common-centroid placement of a 2-D unit capacitor array,Ar×s. The unit capacitors in each pair, (ui, uj), of the pairsequence are symmetrically placed with respect to the center

Fig. 6. (a) Common-centroid placement in A3×3 that is converted fromthe pair sequence, P3×3 = [(u1, ), (u2, u3), (u4, u5), (u6, u7), (u8, u9)].(b) Common-centroid placement in A3×4 that is converted from the pairsequence, P3×4 = [(u1, u2), (u3, u4), (u5, u6), (u7, u8), (u9, u10), (u11, u12)].

of Ar×s. The first pair in Pr×s corresponds to the placementlocations that are the closest to the center of Ar×s. Each ofthe following pairs corresponds to the placement locations thatare farther to the center of Ar×s than the preceding placementlocations. If the distance from several placement locations tothe center of Ar×s is the same, these placement locations areordered in the counter-clockwise direction starting from theone that is located at the 12-o’clock direction.

Given a pair sequence, we can easily convert the pairsequence into its corresponding common-centroid placementby placing the unit capacitors in each pair at their correspond-ing locations in the unit capacitor array. Fig. 6 shows twodifferent common-centroid placements in A3×3 and A3×4 thatare converted from the corresponding pair sequences P3×3 =[(u1, ), (u2, u3), (u4, u5), (u6, u7), (u8, u9)] and P3×4 =[(u1, u2), (u3, u4), (u5, u6), (u7, u8), (u9, u10), (u11, u12)].We can further perturb a pair sequence to generate a differentcommon-centroid placement with the same array dimensions.

2) Routability Analysis: As discussed in Section I, thenumber of required routing tracks of each net in a common-centroid unit capacitor array will have great impact on match-ing properties among unit capacitors, total interconnectingwirelength, and capacitive coupling between nets. Based onthe proposed placement style of distributed connected unitcapacitors, as illustrated in Section IV and Fig. 4(c), we wantto minimize the number of required horizontal (vertical) rout-ing tracks in horizontal (vertical) channels for each net whilesimultaneously optimizing the matching properties amongcapacitors during placement. We consider the minimum-trackroutability of a net in a common-centroid unit capacitor array,which is defined as follows.

Definition 1 (Minimum-Track Routability): A net, ni, in acommon-centroid unit capacitor array, Ar×s, is minimum-trackroutable if it requires at most two horizontal (vertical) routingtracks in different horizontal (vertical) channels such that allits associate unit capacitors can directly be connected.

Given a common-centroid placement in Ar×s and a setof nets, N, we will check if all ni ∈ N, is minimum-trackroutable so that the total interconnecting wirelength in Ar×s

can be minimized. By taking the advantage of the symmetryproperty in a common-centroid placement, we only need tocheck one-track routability of a net, which is further definedin the following.

Definition 2 (One-Track Routability): A net, ni, on the top(left) half of a common-centroid unit capacitor array, A� r

2 �×s


Algorithm 1 One-Track-Routability Analysis

Input: ni, Uni, A� r

2 �×s (Ar×� s2 �)

Output: Lhni

(Lvni

)1: Lh

ni(Lv

ni) ← ∅;

2: Qni← ∅; // Qni

is a set of connected unit capacitorgroups.

3: for all uk ∈ Unido

4: q ← MakeSet (uk);5: UpdateChannelSpan (q);6: Qni

← Qni∪ {q};

7: end for8: for all uk ∈ Uni

do9: for all u′

k ∈ Neighbor (uk) do10: q ← FindSet (uk);11: q′ ← FindSet (u′

k);12: if u′

k ∈ Uni∩ q �= q′ then

13: q ← Union (q, q′);14: UpdateChannelSpan (q, q′);15: end if16: end for17: end for18: Lh

ni(Lv

ni) ← ComputeOverlappingChannelSpans (Qni

);19: return Lh

ni(Lv

ni)

(Ar×� s2 �), is one-track routable if it requires exactly one hori-

zontal (vertical) routing track in a horizontal (vertical) channelsuch that all its associate unit capacitors in A� r

2 �×s (Ar×� s2 �)

can directly be connected.Based on the definition of one-track routability, we pro-

pose the one-track-routability analysis algorithm, as seen inAlgorithm 1, to examine if ni in A� r

2 �×s (Ar×� s2 �) is one-

track routable or not. Inputting ni, a set of its associate unitcapacitors, Uni

, and A� r2 �×s (Ar×� s

2 �), the algorithm finds a setof connected unit capacitor groups, Qni

, in Uni. To determine

connected unit capacitor groups efficiently, the disjoint-setdata structure [29] is applied. First, each unit capacitor, uk,in Uni

forms a disjoint set that denotes a connected unitcapacitor group. Second, two of the disjoint sets are iterativelycombined if a unit capacitor belonging to one disjoint setis adjacent to another unit capacitor belonging to the otherdisjoint set, and both unit capacitors are connected by ni.After each uk in Uni

and its adjacent unit capacitors aretraversed, the set of connected unit capacitor groups is finallyobtained.

During the disjoint set operations, we dynamically updatethe horizontal (vertical) channel span for the connected unitcapacitor group in each set, q ∈ Qni

. Once all the connectedunit capacitor groups are obtained, we then find the commonhorizontal (vertical) channels according to the overlappedchannel spans among different connected unit capacitor groupsin Qni

. The algorithm returns the horizontal (vertical) channelset, Lh

ni(Lv

ni), in which all the channels are feasible for ni

to satisfy the one-track routability. To connect Uniin A� r

2 �×s

(Ar×� s2 �), we only need to assign a horizontal (vertical) routing

track for ni to one of the channels in Lhni

(Lvni

), which will befurther discussed in the next subsection. If Lh

ni(Lv

ni) is empty,

Fig. 7. (a) Connected unit capacitor groups, where the feasible verticalchannels of each net in A8×4 are Lv

n1={lv5}, Lv

n2={lv3, lv4}, Lv

n3={lv4}, and

Lvn4

={lv1, lv2, lv3, lv4}. (b) Bipartite graph for the routing track assignmentproblem in (a). (c) Resulting assignment after finding the minimum-costbipartite matching.

ni must be one-track unroutable. Empirically, we can easilyfind a common-centroid placement that makes all nets one-track routable, as demonstrated in our experimental results.However, if such a placement does not exist, we would allowa minimum number of nets that can apply the routing topologyof disconnected unit capacitors in Fig. 4(a).

The time complexity of Algorithm 1 is O(k), where k isthe number of unit capacitors, which can be analyzed in thefollowing. According to [29], the operations of the disjointset data structure, including MakeSet, FindSet, and Union,take constant time. The procedure UpdateChannelSpan alsotakes a constant time because it is performed only when aunit capacitor group, q, contains one unit capacitor, or whentwo unit capacitor groups are combined. The inner loop fromLines 9 to 16 also takes constant time because uk has atmost four neighbors (i.e., four adjacent unit capacitors). Theprocedure ComputeOverlappingChannelSpans takes O(k) timebecause there are at most k connected unit capacitor groupsin Qni

. To sum up, the overall algorithm takes O(k) time.Fig. 7(a) illustrates the connected unit capacitor groups and

the feasible vertical channels of the nets {n1, n2, n3, n4} inA8×4 after performing Algorithm 1 for each net. It shouldbe noted that the unit capacitors connected by n1 and n4 inFig. 7(a) are not fully common-centroid because of the oddnumbers of unit capacitors. To perform Algorithm 1 for n1

(n4), the right (left) half of A8×8, which contains more unitcapacitors connected by n1 (n4), should be selected as theinput to Algorithm 1. After obtaining Lv

n1(Lv

n4), the feasibility

of the channels in Lvn1

(Lvn4

) must be verified in the symmetriccounterpart. For example, Lv

n4corresponding to the left half of

A8×8 contains the channels, lv1, lv2, lv3, lv4, and lv5. The feasibilityof their symmetric channels, lv9, lv8, lv7, lv6, and lv5, in the righthalf of A8×8 should be considered. In this case, we only needto verify the feasibility of lv6 and lv5, which are adjacent to theunsymmetrical unit capacitor located at a55. Since n4 is notone-track routable in lv5 for the right half of A8×8, lv5 shouldbe removed from Lv

n4.

3) Routing Track Assignment: After obtaining the feasiblehorizontal (vertical) channels of each net from Algorithm 1, weassign a routing track for each net in one of its feasible chan-


Fig. 8. Routing topology of the net, n3, consisting of two vertical trunkwires, one horizontal bridge wire, and many horizontal or vertical branchwires.

nels. The objective of the routing track assignment problem isto minimize the maximum number of required routing tracks ina horizontal (vertical) channel such that both the unwanted par-asitic capacitance due to parallel wires and the row (column)spacing of Ar×s can be minimized. Moreover, we simultane-ously reduce total wirelength during routing track assignment.

We construct a weighted bipartite graph, GB(V = VN ∪ VT ,E), and formulate the routing track assignment problemas a minimum-weighed bipartite-matching (MWBM) [30]problem. In GB, VN and VT are two disjoint vertex subsets.Each vertex in VN denotes a net, and each vertex in VT

corresponds to a routing track in a horizontal (vertical)channel in A� r

2 �×s (Ar×� s2 �). The track number of different

channels must be the same because of equal row (column)spacing in Ar×s. The number of vertices in VT must be largerthan that in VN to ensure routing completeness. For a vertexvN

i ∈ VN and a vertex vTj ∈ VT , an edge, (vN

i , vTj ) ∈ E, exists

if and only if the net represented by vNi is one-track routable

in the channel that contains the routing track denoted byvT

j . Fig. 7(b) shows the bipartite graph for the routing trackassignment problem in Fig. 7(a).

In order to minimize total wirelength, we associate eachedge, (vN

i , vTj ), in GB with a weight, w(vN

i , vTj ), which

indicates the estimated wirelength of the net, ni, after it isassigned to the track, tj . It can be calculated by the summationof the trunk distance, dtrunks(i, j), bridge distance, dbridge(i, j),and branch distance, dbranches(i, j), as seen in (3). The trunkdistance includes the wirelength of ni in tj and that of itssymmetric counterpart. The bridge distance is the wirelengthof ni that connects the two trunks in the symmetric channels inAr×s. The branch distance is the rest wirelength of ni that con-nects all its associate unit capacitors in Ar×s. Fig. 8 shows therouting topology of the net, n3, consisting of two vertical trunkwires, one horizontal bridge wire, and many horizontal orvertical branch wires. The trunk, bridge, and branch distance ofeach net can easily be estimated based on the routing topology

w(vNi , vT

j ) = dtrunks(i, j) + dbridge(i, j) + dbranches(i, j). (3)

Based on the MWBM formulation, all the net trunks canbe evenly distributed among different channels with minimumwirelength, as shown in Fig. 7(c). Consequently, the row (col-umn) spacing of Ar×s, total layout area, parasitic resistance,

and parasitic capacitance due to parallel trunk wires are alsominimized.

4) Cost Evaluation: Different from the previous work [1],which only minimizes the oxide-gradient induced mismatch,M, [16] and maximizes the overall correlation coefficients,ρ, [9] in their objective function during placement, we furtherevaluate the routing quality of a common-centroid placementby calculating the total wirelength, W , in Ar×s, and totalparallel wirelength, WP , for those adjacent parallel wiresat the closest proximity. We minimize the cost function, �,as seen in (4), during simultaneous placement and globalrouting, where α, β, and γ are user-specified parameters,0 ≤ α, β, γ ≤ 1. During SA, we maintain the average valuesfor M, ρ, W , and WP , which are denoted by Mavg, ρavg,Wavg, and WP

avg, respectively

� =

⎛⎝ α × M−Mavg

Mavg+ β × ρavg−ρ

ρavg

+γ × W−Wavg

Wavg+ (1 − α − β − γ) × WP−WP

avg

WPavg

⎞⎠ . (4)

C. Detailed Routing

We perform detail routing for the common-centroid place-ment with minimum �. The trunk wires are first routed ineach horizontal (vertical) channel. When a channel containsmultiple trunk wires of different nets, they should be orderedfrom left to right in the channel to minimize the total wire-length of the corresponding branch wires of the nets in thesame channel. To reduce the parasitic capacitance betweena top plate and a bottom plate, we separate the trunk wiresconnected to the top and bottom plates of a capacitor intodifferent horizontal (vertical) routing layers based on the three-layer HVH routing model [31].

After all the trunk wires are routed, we route the branchwires of each net based on the breadth-first-search algo-rithm [29]. Starting from the trunk wires of a net, we itera-tively search and connect the neighboring unit capacitors withbranch wires until all the corresponding unit capacitors areconnected. Once the top (bottom) plates of all unit capacitorsare connected with branch wires, the bridge wires are finallyrouted to connect the trunk wires of the same net in thesymmetric channels. The spacing between bridge wires shouldbe enlarged to avoid the unwanted parasitic capacitance.

VI. Experimental Results

We implemented our ratioed capacitor layout generationalgorithms in the C++ programming language and executedon a 2.26 GHz Intel Xeon machine under the Linux operatingsystem. Our benchmark circuits are based on those in [1], asseen in Table II, where the circuits, SCF 1–3, were sourcedfrom [16], SAR 8–10b were designed by [1], and SAR 6–7b were extended by us. Table II also lists the numberof capacitors (“# of Cap.”), the capacitor ratio (“CapacitorRatio”), and the total number of unit capacitors (“# of UnitCap.”) of each circuit.

We compared our approach based on the placement styleof distributed connected unit capacitors with Lin et al.’s


TABLE II

Benchmark Circuits in [1]

Circuit # of Capacitor Ratio # ofCap. Unit Cap.

SCF 1 5 2 : 6 : 7 : 7 : 8 30SCF 2 5 1 : 2 : 2 : 10 : 17 32SCF 3 4 1 : 2 : 16 : 45 64SAR 6b 7 1: 1 : 2 : 4 : 8 : 16 : 32 64SAR 7b 8 1: 1 : 2 : 4 : 8 : 16 : 32: 64 128SAR 8b 9 1 : 1 : 2 : 4 : 8 : 16 : 32 : 64 : 128 256SAR 9b 10 1 : 1 : 2 : 4 : 8 : 16 : 32 : 64 : 128 : 256 512SAR 10b 11 1 : 1 : 2 : 4 : 8 : 16 : 32 : 64 : 128 : 256 : 512 1024

TABLE III

Comparisons of Array Dimensions (‘‘Ar×s ’’), Oxide-Gradient-Induced Mismatches (‘‘M ’’), Overall Correlation Coefficient (ρ),

Total Wirelength (‘‘W ’’), Total Parallel Wirelength (‘‘Ar×s ’’), Aspect Ratios (‘‘AR’’), Total Layout Area (‘‘Area’’) and Runtime

(‘‘Time’’) for Lin et al.’s Approaches [1], [2] and Ours

Lin et al.’s Approaches [1], [2] OursCircuit Ar×s M ρ W WP AR Area Time Ar×s M ρ W WP AR Area Time

(%) (μm) (μm) (μm2) (s) (%) (μm) (μm) (μm2) (s)SCF 1 6×5 0.08 9.63 2687 1811 1.16 33 429 0.46 6×5 0.08 9.52 2590 1418 1.09 26 449 0.61SCF 2 7×5 0.02 9.36 3001 1965 1.12 36 946 0.47 7×5 0.02 9.36 2578 809 1.28 30 960 3.96SCF 3 8×8 0.52 5.52 4282 605 1.13 66 366 1.14 8×8 0.52 5.55 2738 373 1.02 53 037 4.02SAR 6b 8×8 1.08 18.94 3329 1103 1.13 58 897 1.49 8×8 0.73 19.46 2419 228 1.08 55 942 3.99SAR 7b 12×11 0.73 25.04 7505 2395 1.07 131 335 2.44 12×11 0.73 25.61 4536 448 1.00 118 494 4.26SAR 8b 16×16 0.76 31.65 17 185 6916 1.18 248 906 4.98 16×16 0.74 31.82 7662 467 1.08 228 712 5.76SAR 9b 24×22 1.17 37.64 37 845 15 890 1.06 517 593 12.06 24×22 0.83 38.60 14 523 825 1.00 477 992 11.24SAR 10b 32×32 1.44 43.10 85 414 35 166 1.23 1 047 779 54.31 32×32 1.12 44.97 26 059 2644 1.08 924 813 24.18Comp. 1.16 0.99 1.80 7.86 1.06 1.15 0.78 1.00 1.00 1.00 1.00 1.08 1.00 1.00

approaches [1], [2] based on the placement style of discon-nected unit capacitors. Since [1] only proposed the placementalgorithm, we additionally implemented the heuristic routingapproach described in [2]. We implemented the cost functionaccording to [2], as shown in (5). The first two terms in (5)are the same as those in (4). The last term in (5) is to make theadjacent rows (columns) of the resulting placement have theleast number of different capacitors, where X is the summationof the number of different capacitors in each adjacent row(column), and Xavg denotes the average of X during SA

�′ =

(α × M−Mavg

Mavg+ β × ρavg−ρ

ρavg

+(1 − α − β) × X−Xavg

Xavg

). (5)

For a fair comparison, the experimental setups, including theoxide thickness, oxide gradient, correlation coefficient of a unitcapacitor, and coefficients in (4) and (5), for both approacheswere all the same. The oxide thickness, oxide gradient, andcorrelation coefficient of a unit capacitor are 40 nm, 10 ppm,and 0.9, respectively. The coefficients, α, β, and γ , in (4),and α and β in (5) are all 0.25. Each unit capacitor hasthe square dimensions of 25 μm × 25 μm. Table III showsthe comparisons of array dimensions (“Ar×s”), oxide-gradientinduced mismatches (“M”), overall correlation coefficient (ρ),total wirelength (“W”), total parallel wirelength (“WP”), as-pect ratios (“AR”), total layout area (“Area”) and runtime(“Time”) for Lin et al.’s approaches [1], [2] and our approach.

The results in Table III show that the aspect ratios of thelayouts generated by our approach are closer to 1.0, which

is the targeted aspect ratio of the layout of a common-centroid capacitor array. Compared with [1] and [2], ourapproach results in 1.80X total wirelength and 7.86X to-tal parallel wirelength improvements based on the proposedplacement style of distributed connected unit capacitors, one-track routability analysis, and MWBM formulation for routingtrack assignment. In addition to wirelength reduction, ourapproach also achieves 1.16X smaller oxide-gradient inducedmismatches, 1% better overall correlation, and 14% total areareduction because the required track number of each horizontal(vertical) channel is minimized. The runtime of our approach is22% longer because we additionally performed the routabilityanalysis and MWBM algorithms during placement iterations.It should be noted that our approach may converge fasterduring SA for larger designs, such as SAR 10b.

We further compared the routing-induced parasitic capac-itance based on Lin et al.’s approaches [1], [2] and oursby generating the resulting layouts based on the TSMC0.18-μm process technology [32], and performing design rulechecks, layout versus schematic verification, and parasiticextraction using the commercial tool [27]. Table IV showsthe total parasitic capacitance of different types, as describedin Section II, including “Top Plate to Top Plate (

∑ ∑CTT

ij ),”“Bottom Plate to Bottom Plate (

∑ ∑CBB

ij ),” “Top Plate toSubstrate (

∑CTS

i ),” and “Bottom Plate to Substrate (∑

CBSi ),

for each circuit. Since the parasitic capacitance of “Top Plateto Bottom Plate,” CTB

i , as shown in Fig. 3(b), may affect thecapacitance ratio of the capacitors in C, instead of comparing


Fig. 9. Stick diagram of the resulting common-centroid placement and routing of the ratioed capacitors in SAR 8b based on (a) Lin et al.’s approaches [1],[2] with disconnected unit capacitors, which requires four routing tracks in each vertical channel, and (b) our approach with distributed connected unitcapacitors, which requires only one routing track in each vertical channel.

the amount of∑

CTBi , we compared the accuracy, σ̄, of the

capacitance ratio, as seen in Table IV.Assuming that the ideal capacitance ratio of the n capacitors

in C is RatioI1 : RatioI

2 : · · · : RatioIm, and the capacitance

of a unit capacitor is denoted by Cunit , the ideal and the realcapacitance, CI

i and CRi , of Ci ∈ C can be calculated by

(6) and (7), respectively. The real capacitance ratio of them capacitors in C, RatioR

1j : RatioR2j : · · · : RatioR

mj , can beobtained by normalization with respective to CR

j , as seen in(8). When i is equal to j, RatioR

jj is equal to RatioIj

CIi = Cunit × RatioI

i (6)

CRi = CI

i + CTBi (7)

RatioRij = RatioI

j × CRi

CRj

. (8)

We evaluated the accuracy of the capacitance ratio withrespect to CR

j , which is denoted by σj , by summing up thenormalized capacitance ratio difference of each capacitor inC, as seen in (9). The average accuracy of the capacitanceratio with respect to different capacitors in C can be obtainedby (10). A smaller value of σ̄ indicates higher accuracy of


TABLE IV

Comparisons of the Routing-Induced Parasitic Capacitance, Including Total Top-Plate-to-Top-Plate Capacitance (‘‘

∑∑CTT

ij ’’),

Total Bottom-Plate-to-Bottom-Plate Capacitance (‘‘

∑∑CBB

ij ’’), Total Top-Plate-to-Substrate Capacitance (‘‘

∑∑CBB

ij ’’), and

Total Bottom-Plate-to-Substrate Capacitance (‘‘

∑CBS

i ’’), and the Circuit Accuracy (‘‘σ̄ ’’) in Terms of Total Normalized

Capacitance Ratio Difference for Lin et al.’s Approaches [1], [2] and Ours

Lin et al.’s Approaches [1], [2] Ours

Circuit∑∑

CTTij

∑∑CBB

ij

∑CTS

i

∑CBS

i σ̄∑∑

CTTij

∑∑CBB

ij

∑CTS

i

∑CBS

i σ̄

(fF ) (fF ) (fF ) (fF ) (%) (fF ) (fF ) (fF ) (fF ) (%)SCF 1 9.734 2.848 72.837 121.491 0.083 5.075 1.406 59.300 108.706 0.139SCF 2 6.785 1.794 60.667 111.953 0.110 3.478 0.594 56.560 109.643 0.398SCF 3 12.794 2.201 75.832 188.224 0.047 4.154 0.635 51.641 157.983 0.126SAR 6b 0 2.572 11.714 210.789 3.650 0 1.019 10.878 165.293 0.404SAR 7b 0 6.782 22.227 432.683 0.321 0 1.766 21.683 317.868 0.296SAR 8b 0 12.252 46.604 912.793 0.838 0 2.345 43.024 579.317 0.687SAR 9b 0 27.843 88.545 1823.283 2.048 0 5.455 86.040 1121.507 0.712SAR 10b 0 48.487 181.483 3670.183 3.205 0 9.752 170.399 2136.713 2.891Comp. 2.307 6.510 1.126 1.593 1.822 1 1 1 1 1

Fig. 10. (a) and (b) Final layouts of the ratioed capacitors in Fig. 9.

the capacitance ratio with the consideration of routing-inducedparasitic capacitance after post-layout parasitic extraction

σj =m∑i=1

|RatioRij − RatioI

i |RatioI

i

× 100% (9)

σ̄ =1

m

m∑j=1

σj. (10)

The results in Table IV show that, compared with Lin et al.’sapproaches [1], [2], our approach results in great parasiticreduction in all aspects and better accuracy of the capacitanceratios after considering the routing-induced parasitic capaci-tance, especially for the SAR circuits. For the SCF circuits,the σ̄ value representing the circuit accuracy based on our ap-proach is at most 0.288% larger than that based on Lin et al.’sapproaches [1], [2], which is a relatively small difference.

Fig. 9(a) and (b) shows the resulting placements of theratioed capacitors in the circuit, SAR 8b, based on theplacement styles of disconnected unit capacitors [1] and the

proposed distributed connected unit capacitors, respectively.Fig. 10(a) and (b) further shows the final layouts for bothplacements in Fig. 9. The placement style of disconnectedunit capacitors requires four routing tracks in each verticalchannel, while that of distributed connected unit capacitorsrequires only one routing track. Consequently, the layout inFig. 10(b) has much smaller area and routing-induced parasiticresistance/capacitance.

VII. Conclusion

In this paper, we presented a new problem formulation forratioed capacitor layout generation considering both devicematching and parasitic minimization. We introduced our lay-out generation flow and algorithms, which consists of arraysize calculation, simultaneous placement and global routing,and detail routing, based on the proposed common-centroidplacement style, distributed connected unit capacitors. Theexperimental results showed that the proposed approach canreduce area, wirelength, and routing-induced parasitics, andguarantee the best matching quality after routing.


Acknowledgment

The authors would like to thank Prof. J.-M. Lin and Prof.S.-J. Chang’s Group from National Cheng Kung University,Tainan, Taiwan, for providing the benchmark circuits in [1]and technical consulting corresponding to their works [1] and[2].

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Mark Po-Hung Lin (S’07–M’09) received the B.S.and M.S. degrees in electronics engineering fromNational Chiao Tung University, Hsinchu, Taiwan,in 1998 and 2000, respectively, and the Ph.D. degreefrom the Graduate Institute of Electronics Engineer-ing, National Taiwan University, Taipei, Taiwan, in2009.

He was with Springsoft, Inc., Hsinchu, from 2000to 2007. In 2008, he was a Visiting Scholar with theDepartment of Electrical and Computer Engineering,University of Illinois at Urbana-Champaign, Urbana.

He has been an Assistant Professor with the Department of ElectricalEngineering, National Chung Cheng University, Chiayi, Taiwan, since 2009.His current research interests include analog design automation and very largescale integration physical synthesis.

Yi-Ting He received the M.S. degree from the De-partment of Electrical Engineering, National ChungCheng University, Chiayi, Taiwan, in 2012.

Her current research interests include electronicdesign automation with an emphasis on analog lay-out design automation.

Vincent Wei-Hao Hsiao is currently a Graduate Stu-dent with the Department of Electrical Engineering,National Chung Cheng University, Chiayi, Taiwan.His current research interests include analog layoutautomation.


Rong-Guey Chang received the B.S. and M.S. de-grees in applied mathematics from National ChungHsing University, Taichung, Taiwan, in 1991 and1993, respectively, and the Ph.D. degree in com-puter science from National Tsing Hua University,Beijing, China, in 2000.

He was with Faraday Technology Corporation,Hsinchu, Taiwan, from 2000 to 2002. He was anAssistant Professor with the Department of Com-puter Science and Information Engineering, NationalChung Cheng University, Chiayi, Taiwan, in 2002,

and has been an Associate Professor with the Department of Electrical Engi-neering since August 2009. His current research interests include embeddedsoftware, compiler design, and integrated circuits and systems.

Shuenn-Yuh Lee (M’98) received the B.S. degreefrom National Taiwan Ocean University, Chilung,Taiwan, in 1988, and the M.S. and Ph.D. degreesfrom National Cheng Kung University, Tainan, Tai-wan, in 1994 and 1999, respectively.

Since 2002 and 2006, he has been an AssistantProfessor and Associate Professor, respectively, withthe Department of Electrical Engineering, NationalChung Cheng University, Chia-Yi, Taiwan, wherehe is currently a Full Professor. He served as theChairman of the Heterogeneous Integration Con-

sortium sponsored by the Ministry of Education, Taiwan, from 2009 to2011. His current research interests include design of analog and mixed-signal integrated circuits, including filters, high-speed analog-to-digital con-verter (ADC)/digital-to-analog convertor (DAC), and sigmaVdelta ADC/DAC,biomedical circuits and systems, low-power and low-voltage analog circuits,and radio-frequency front-end integrated circuits for wireless communica-tions.

Dr. Lee is currently a member of the Engineering in Medicine and BiologySociety, the Circuits and Systems Society, the Microwave Theory and Tech-niques Society, and the Solid-State Circuits Society of the IEEE. He is alsoa member of the Institute of Electronics, Information, and CommunicationEngineers and the Chinese Institute of Electrical Engineering.

common-centroid capacitor layout generation considering device matching and parasitic minimization

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