combinational_logic1-1

8/12/2019 Combinational_Logic1-1

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COMBINATIONAL CIRCUITS

LOGIC CIRCUITS:

1. Combinational

2. Sequential

Combinational logic circuits (circuits without a memory):

Combinational switching networks whose outputs depend only

on the current inputs.

Sequential logic circuits (circuits with memory):

In this kind of network, the outputs depend on the current inputs

and the previous inputs. These networks employ storage elements

and logic gates. [Chapters 5 and 9]

COMBINATIONAL CIRCUITS

Most important standard combinational circuits are:

Adders

Subtractors Comparators

Decoders

Encoders

Multiplexers

Available in ICs as MSI and used as

standard cells in complex VLSI (ASIC)


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ANALYSIS OF COMBINATIONAL LOGIC

CA ++=

ABC=

BCACAB ++=

12 'TF=

23 TT +=


ABCCABCBABCA

ABCCBBCACABCBA

ABCCBACBCABA

ABCCBABCACAB

ABCTFTTF

+++=

+++++=

++++++=

+++++=

+=+=

''''''

)'''')('''(

))('')('')(''(

)()'(

'12231

BCACABF ++=2


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Inputs Outputs

A B C F 1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

INPUTS OUTPUTS


From the truth table can you tell the function of the circuit?

//Example 4-10//------------------------------------------

//Gate-level description of combinational circuitmodule analysis (A,B,C,F1,F2);

input A,B,C;output F1,F2;wire T1,T2,T3,F2not,E1,E2,E3;

or g1 (T1,A,B,C);and g2 (T2,A,B,C);

and g3 (E1,A,B);and g4 (E2,A,C);and g5 (E3,B,C);

or g6 (F2,E1,E2,E3);not g7 (F2not,F2);

and g8 (T3,T1,F2not);or g9 (F1,T2,T3);

endmodule

COMBINATIONAL LOGIC - Verilog CODE


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COMBINATIONAL LOGIC - Verilog CODE//Stimulus to analyze the circuit

module test_circuit;

reg [2:0]D; *input specified with a 3-bi treg vector D: 0 2wire F1,F2; *outputs

analysis circuit(D[2],D[1],D[0],F1,F2); *D[2]=A, D[1]=B, D[0]=Cinitial

begin

D = 3'b000; *D is a 3-bit vector initialized to 000repeat(7) *The repeat loop gives the 7 binary numbers after 000

#10 D = D + 1'b1 ; *D is incremented by 1 after 10 nsend

initial

$monitor ("ABC = %b F1 = %b F2 =%b ",D, F1, F2); *Display truth tableendmodule

Simulation Log:

ABC = 000 F1 = 0 F2 = 0ABC = 001 F1 = 1 F2 = 0

ABC = 010 F1 = 1 F2 = 0

DESIGN OF COMBINATIONAL LOGIC

1. From the specifications of the circuit, determine the number

of inputs and outputs

2. Derive the truth table that defines the relationship between the

input and the output.

3. Obtain the simplified Boolean function usingx-variable K-Map.

4. Draw the logic diagram and verify the correctness of the design.


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DESIGN OF COMBINATIONAL LOGIC

Example:Design a combinational circuit with three inputs and one

output. The output is a 1 when the binary value is less than three.

The output is 0 otherwise.

01110011

0101

0001

0110

1010

1100

1000

Fzyx

111

00 01 11 10

0

1

y

x

'''' zyF +=

x

y

z

F

z

y z

ARITHMETIC LOGIC UNIT (ALU)

ACC

CPU

Store

Path

Load Path

4

4

4

EN

4

4

Memory Cell

Select Lines

2Read/Write

Control BusPC

M

U

X

4

4

ACC to Data Bus

Load

ACC

ALU

Control

Inputs

4

4

Load MAR

Use PC

Memory

Address

Address

Bus

16

Data

Bus

Instruction Path

Data

Bus

Load

IR

MAR

Control

Unit

(FSM)

IR

Decoder

External

MemoryEN2

EN1Y

ALU

B A

BufferEN

4

Legend

A, B ALU Inputs

ACC Accumulator

ALU Arithmetic and Logic Unit

MAR Memory Address Register

CPU Central Processing Unit

FSM Finite State MachineIR Instruct ion Register

PC Program Counter

Control Signal

Bus

+ Devices with Reset/Clock

Inputs

+

+

+

+

+

Copyright: Tylavsky , Arizona State University


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BINARY ADDER Half Adder

A B O C

0 0 0 0

1 0 1 0

0 1 1 0

1 1 0 1

Inputs Outputs

A B C F 1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

INPUTS OUTPUTS

BINARY ADDER - Full Adder

C


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CASCADE 4-BIT FULL ADDER

Ci+11100

Si0111

Bi1100

Ai1101

Ci0110

3 2 1 0 i

//Gate-level hierarchical description of 4-bit adder

// Description of half adder (see Fig 4-5b)

module halfadder (S,C,x,y);input x,y;output S,C;

//Instantiate primitive gatesxor (S,x,y);

and (C,x,y);endmodule

//Description of full adder (see Fig 4-8)module fulladder (S,C,x,y,z);

input x,y,z;

output S,C;wire S1,D1,D2; //Outputs of first XOR and two AND gates//Instantiate the halfadder

halfadder HA1 (S1,D1,x,y),

HA2 (S,D2,S1,z);or g1(C,D2,D1);

endmodule

CASCADE 4-BIT FULL ADDER - HDL CODE 1


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//Description of 4-bit adder (see Fig 4-9)

module_4bit_adder (S,C4,A,B,C0);

input [3:0] A,B;

input C0;

output [3:0] S;

output C4;

wire C1,C2,C3; //Intermediate carries

//Instantiate the fulladder

fulladder FA0 (S[0],C1,A[0],B[0],C0),

FA1 (S[1],C2,A[1],B[1],C1),

FA2 (S[2],C3,A[2],B[2],C2),

FA3 (S[3],C4,A[3],B[3],C3);

endmodule

CASCADE 4-BIT FULL ADDER - HDL CODE 2

combinational_logic1-1

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