combinational logic design practices. zdocumentation ztiming zdecoders zencoders zthree-state...
TRANSCRIPT
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COMBINATIONAL LOGIC DESIGN PRACTICES
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COMBINATIONAL LOGIC DESIGN PRACTICES
DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
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DOCUMENTATION
WHAT? SPECIFICATION: INTERFACE, FUNCTION
HOW? BLOCK DIAGRAM SCHEMATIC DIAGRAM TIMING DIAGRAM STRUCTURED LOGIC DEVICE DESCRIPTION CIRCUIT DESCRIPTION
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BLOCK DIAGRAMS
INPUTS, OUTPUTSFUNCTIONAL MODULESDATA PATHSCONTROL SIGNALS
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BLOCK DIAGRAMS
PROCESSOR
DECODINGLOGIC
MEMORY
16
816
CS~
R/W
DATA
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BUS
COLLECTION OF TWO OR MORE RELATED SIGNALS
SLASH AND NUMBER: NUMBER OF SIGNALS
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SIGNAL NAMES
WELL CHOSEN NAMES CONVEY INFORMATION
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SIGNAL ACTIVE LEVELS
ACTIVE HIGHACTIVE LOWASSERTED WHEN AT THE ACTIVE
LEVELDEASSERTED (NEGATED) WHEN NOT
AT THE ACTIVE LEVEL
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NAMING CONVENTION
ACTIVE HIGH: GO, PAUSE, READYACTIVE LOW: GO~, PAUSE.L, /READY,
ETC.
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ACTIVE LEVELS FOR PINS
INVERSION BUBBLE: ACTIVE LOWNO INVERSION BUBBLE: ACTIVE
HIGH
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COMBINATIONAL LOGIC DESIGN PRACTICES
DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
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CIRCUIT TIMING
TIMING DIAGRAM RELATIONSHIPS AMONG INTERNAL SIGNALS REQUIREMENTS ON EXTERNAL SIGNALS
CAUSALITYDELAY TIMING TABLEDELAYS RANGE: MINIMUM, MAXIMUM,
TYPICALPROPAGATION DELAY (tHL, tLH,…)
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TIMING SPECIFICATIONS
MAXIMUM: HOW DID THEY MEASURE IT? TEMPERATURE (25 °C, 40 °C, …) CAPACITIVE LOAD (0 pF, 50 pF, …) VCC (3.3V, 5V, …)
TYPICAL IDEAL?
MINIMUM WORK FOR ZERO DELAY? TEMPERATURE, LOAD, VCC, …
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TIMING ANALYSIS
COMPLEX FOR LARGE CIRCUITSCAD TOOLS HELP, BUT:
NEED TO UNDERSTAND WHAT THE RESULTS ARE
OFTEN MANY CONTROLS NEED TO KNOW HOW TO TEST
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COMBINATIONAL LOGIC DESIGN PRACTICES
DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
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DECODERS
MULTIPLE INPUT, MULTIPLE OUTPUT CIRCUIT THAT CONVERTS CODED INPUTS TO CODED OUTPUTS
INPUT AND OUTPUT CODES ARE DIFFERENT
ONE-TO-ONE MAPPING
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DECODERS
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BINARY DECODERS
n-TO-2n DECODERSACTIVATE EXACTLY ONE OF 2n
OUTPUTS BASED ON n-BIT INPUTS
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2-TO-4 BINARY DECODER
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LOGIC SYMBOLS
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ONE-HALF OF 74x139 DECODER
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ONE-HALF OF 74x139 DECODER
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74x138 3-TO-8 DECODER
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CASCADING BINARY DECODERS
74x138 HAS BOTH ACTIVE HIGH AND ACTIVE LOW ENABLE INPUTS
WITH TWO 138s WE CAN ENABLE OR THE OTHER USING THE MSB
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SEVEN-SEGMENT DECODER
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COMBINATIONAL LOGIC DESIGN PRACTICES
DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
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ENCODERS
MULTIPLE INPUT, MULTIPLE OUTPUT CIRCUIT THAT CONVERTS CODED INPUTS TO CODED OUTPUTS
OUTPUT CODE HAS FEWER BITSONE-TO-ONE MAPPING
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BINARY ENCODER
2n-TO-n ENCODERINPUT: 1-OUT-OF-2n CODEOUTPUT: n-BIT BINARY CODE
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BINARY ENCODER
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BINARY ENCODER
Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7
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PRIORITY ENCODERS
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8-INPUT PRIORITY ENCODER
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74x148 PRIORITY ENCODER
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COMBINATIONAL LOGIC DESIGN PRACTICES
DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
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THREE-STATE DEVICES
ENABLE - DEVICE “FLOATS”FLOATS = HIGH IMPEDANCE STATE = = HI-Z STATE = DISCONNECTED
STATE
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MULTIPLE SOURCES ON THREE-STATE PARTY LINE
MULTIPLE THREE-STATE DEVICES CAN SHARE SINGLE LINE
FIGHTINGDEAD TIME
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MULTIPLE SOURCES ON THREE-STATE PARTY LINE
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STANDARD THREE-STATE BUFFERS
HYSTERESIS?BUFFERSTRANSCEIVERS
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COMBINATIONAL LOGIC DESIGN PRACTICES
DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
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MULTIPLEXERS
DIGITAL SWITCH
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MULTIPLEXERS
1
0
n
jj iDjMENiY
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74x151, 74x157
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74x153
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THREE-STATE MUXES
DISABLED OUTPUT HI-Z INSTEAD OF 0: 74x151 74x251 74x153 74x253 74x157 74x257
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EXPANDING MUXES
EXPAND THE NUMBER OF BITS MULTIPLE 74x151s…
FANOUTEXPAND THE NUMBER OF SOURCES
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MUXES, DEMUXES, BUSES
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MUXES, DEMUXES, BUSES
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DECODERS AS DEMUXES
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DECODERS AS DEMUXES
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DESIGN EXAMPLE
CREATE A MUX-DEMUX SYSTEM FOR A 2-BIT BUS
4 2-BIT INPUTS TO 4 2-BIT OUTPUTSUSE STANDARD TTL CHIPS FROM
BOOK
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COMBINATIONAL LOGIC DESIGN PRACTICES
DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
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XOR FUNCTION
XY=X’Y + XY’
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XOR MULTIGATE DESIGN
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XOR MULTIGATE DESIGN
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XOR GATES
ANY TWO SIGNALS MAY BE COMPLEMENTED
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PARITY
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COMBINATIONAL LOGIC DESIGN PRACTICES
DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS
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COMPARATORS
EQUALITY - COMPARATORSARITHMETIC RELATIONSHIP -
MAGNITUDE COMPARATORS
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4-BIT COMPARATOR
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ITERATION?
n. THE ACTION OR A PROCESS OF REPEATING AS: A PROCEDURE IN WHICH REPETITION OF A
SEQUENCE OF OPERATIONS YIELDS A RESULT SUCCESSIVELY CLOSER TO A DESIRED RESULT
THE REPETITION OF A SEQUENCE OF COMPUTER INSTRUCTIONS A SPECIFIED NUMBER OF TIMES OR UNTIL A CONDITION IS MET
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ITERATIVE CIRCUITS
ITERATIVE ALGORITHM:1. SET C0 TO INITIAL VALUE, SET i TO 0
2. USE Ci AND PIi TO TO GET POi AND Ci+1
3. INCREMENT i 4. IF i<n GO TO STEP 2
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ITERATIVE COMPARATOR
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74x85 COMPARATOR
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ARITHMETIC CONDITIONS