colourtelevision trainingmanual a3-achassis a3...
TRANSCRIPT
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COLOURTELEVISIONTRAININGMANUAL A3-ACHASSIS
A3-ACHASSISCIRCUITANALYSISCPU’Band SwitchSystem” switchVIF/ChromaVertical Out
:M34300N4-622SP:LA791O:LA791O:LA7681:LA7837
Power Supply Circuit
0
REFERENCENO.WM-5200S2
... ..,,
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< Contents>
Part 1 CPU and V/S Tuning Page1.1-11-2
2.
3.3-13-2
4.
5.
6,6-16-26-3
7.
8.
9,
10.
System Outiine -................. ...................................!.. ............................ ., . . . ..0......4
CPU and Main lCS.............................................................................................. 4
Features ........................... ................................................................................ 4
Key Input Circuit .............. ................................................................................ 10
Key Functions ..................................................................................................... 11
Main Switch ................................................................0.... .,, ,,. ,!.,..0,... ... ,,*......#o#.. 11
Remote Control of the Main Power Supply..................................................... 12
CPU Clock Oscillation ......................................................................................... 14
CRT Display Clock. oscillation ............................................................................ 14
Band Switching and Tuning............. ................................................................ 14Band Switching ,,, ,..........0.. ............................................................,, ,,.,, ,,0...,, .,, ,0
14
Tuning ............................... ................................................................................ 16
Fine Tuning ....................................................................................................... 17
System Switching .............. ................................................................................ 17
Analogue Control ................................................................................................ 18
Linear AFT......................... ................................................................................ 19
TV/AV Switching ................................................................................................ 19
10-I. SCART 21 pin Switching ................................................................................... 1910-2.Remote Control Switching ................................................................................. 19
11.
11-111-211-311-411-511-611-7
12.
13.
Other CPU Functions ...................................................................................... 21
Memory ............................................................................................................. 21
OFF-Timer-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal ...............................................................................................................Sound Mute ., ........0... .........0................................................................................Skew Output ............................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Load Protector ...................................................................... . . . . . . . . . . ...0 . ...,
Teletext Control ................................................................................................
Special Functions ...............................................................................................
CPU Repair......................... ................................................................................
Part 2 VIF/Chroma/DEF One Chip IC1. VIF/SIF/AGC ......................................................................................................1-1 FM Detector Output(Pin-l) ...............................................................................1-2 FM Discriminate &.Mute(Pin.2) .......................................................................1-3 Negative Feedback(Pin.3) ..................................................................................!-4 Audio Frequency Input(Pin-4) ...............................,...,..,,.,.,,,, ,,, ,.,,,,,..,,,, ,,, ,,, ,,, ,,1-5 Audio Output(Pin-5) ......... ................................................................................
L1
2121-212222
23
26
272929303031
-1-
B
1-61-71-81-91-101-111-121-131-14
2.2-12-22-32-42-52-62-72-82-92-1o
3.3-13-23-33-43-53-63-73-83-93-1o3-113-123-133-143-153-163-173-18
Part 31.2.2-12-2
Part1.
2.
3.
4.
PageVIF Amp lnput(Pin-7 and 8) ............................................................................31RF AGC Volume(Pin-9) ....................................................................................... 32AGC Filter(Pin-l O).........................................O................................................... 33Video Output(Pin-42) ........ ................................................................................ 33AFT Coil(Pin-43) .................................................................................4.............. 34AFT Output(Pin-44) ........... ................................................................................ 34SIF Input and D.C. Attenuater(Pin-45) . ........................................................... 35RF AGC Output(Pin-46) .....................................................................................35Video Detector Coil(Pin-47 and 48) . ................................................................ 36
Video/Chroma ......................................................................................,,...,.!.. ,.. , 37Chroma Input and Color Control(Pin-40) ......................................................... 37ACC/Killer Filter(Pin-39 and 41) ...................................................................... 37Contrast Control/Burst Cleaning Coil(Pin-12) . ................................................ 38Chroma Output(Pin-14) .................................. ................................................... 38ldent Filter(Pin-15) ..............,$......,..,.. ............................................................... 39X’tal OSC(Pin-16) ............................................................................................... 39APC Filter,Pin-17 ......................................... ................................................... 39Tint Control(Pin-19) ...................................... ................................................... 39B-Y R-Y lnput(Pin-18 and 20) ................... ................................................... 40R-Y/G-Y/B-Y Difference Output(Pin-21,22 and 23) ........................................ 41
Video out and Deflection ................................................................................. 42Video Output and Fly-back Pulse lnput(Pin-24) ............................................. 42Power Supply(Pin-25) ....................................................................................... 42Fly-back Pulse input, Burst Gate Pulse Output(Pin-26) . ................................. 43Horizontal Output(Pin-27) . ........................................... ,.. .$...,.. ......................... 44Ceramic Resonator(Pin-28) .............. . . . . . . . . . . . . . . . . . . . . . . ...!.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44AFC Filter(Pin-29) ............................................................................................. 44Filter for Horizontal Sync(Pin-30) ...................... ............................................ 45Vertical Output (Pill.31 ).................................................................................. 45Vertical Output Sensitivity Setting(Pin-32) ....) ........0..... ................................ 46Vertical Deflection Circuit .............................................................................. 47Vertical Synchronization Signal Separation Sensitivity Setting,.,, ............... 50Sync Separation(Pin-33) .................................. ................................................. 51AFC Operation ............................................... .................................................. 52Brightness Control,(Pin-35) .............................................................................. 53Pedestal Clamping Filter(Pin-36) .................... .................................................. 54Video Tone Control(Pin-37) ............................................................................... 54Video Signal Input(Pin-38) ............................. .................................................. 55Contrast Control ................................................................................................ 55
Power Supply Circuit .................................................................................... 56Operation Outline .............................................................................................. 56Explanation of Circuit Operation ......................................................................, 56Starting Operation ...........................................................................................56Oscillation Circuit ..............................................................................................56
4 Vertical Deflection OutputOverview ................................................. .......................................................... 60
0
Features .................................................. .......................................................... 60
Block Diagram and External Connection .......................................................... 61
Pin Description ................................................................................................. 62
-2-
0
,., ,,.
Page5. Function Description ........ ................................................................................ 635-1 Vertical Trigger Input .... ................................................................................ 635-2 Ramp Generator ............... ................................................................................635-3 One-Shot Circuit .............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ..,,..,.,,,0, . . . . . . . . . . . . . . ,, ...,0...,,0. . . . . . . . . . 645-4 Constant Amplitude and Feed Back 0,, ,, .,, . 0, .,,...,. .,, ,,, .,, , ,0.,,,.,! ,,, ,,, ,,, ,,, ,,, ,,, , ,,, ,,, . 655-5 Driver Circuit .............................0.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ?.! 655-6 DC Bias Control ................O.$..c..i....i. ...........!10!$.I.**4..$*I6O..*4..**.*.$4C.$6....!.0.....$$....665-7 Linearity Correction Circuit ............................................................................ 67
-3-
[Part 1 CPU and V/S Tuning]
1. System Outline
The system employs a CPU dcvclopcd for the A3 chassis (VIF/SIF/CHROMA/DEF-ONECHIP lC) with the following functions.
1-1 CPU and Main ICS
CPU : M34300N4-622SP MITSUBISHICMOSROM 4K bytesCRT character display (16 characters x 2 rows)EEPROM (128 x 8 bits)Dual in line -42s
Band switching : LA791O SANYOSystcm switching :LA791O SANYO
‘ 1-2 Features(1) 32-programme function (AV position x 3)(2) Tuning band switching (3 bands or UHF only )(3) Manual tuning preset(4) Fine tuning(5) Teletext control(6) Analoguc control (colour,volume, brightncss,contrast, mcrnory)(7) TV/AV switching(8) Mute(9) Off-timer(10) 48-function remote control(11) On-screen display
(Programme number, AV,analoguc control data, off-timcr,ctc.)(12) Special functions
,., .. .,’ .’,. ,. ........
,, ... ., .,’ ‘..,..’,. . . .. ’.,
Fig. 1 shows a block diagram of CPU peripheral circuits
OEEEl--
Band switching1C71O ~LA791O
V-LBV-HB
wV-UB
TunerI
IC701M34300N4-622SP
n
CPU
❑EEPROM
128x8bits
II
RAM
128x8bits
~
ROM4086x9bits
r+Vcc +5V
--rEEE1
WA:l’’’LL’
~ Analogue ~ IClolcontrol VIF/CHROMA
LA7681
i
Fig. 1 CPU peripheral circuits
-5-
o
[i
RIW22C+I
——
t
[
lC.J51 LA7910
12349678
5,6!(
U795cml
!+?.!527K
r!R715mJ,m(
I
mv 31 UNO
3 mm
3 SKEu
14 x IN
!
35 x Wr
7713 ,70,Iw CXJX:~o 36 TCXT
W%22K TEXT
I I %71 I.
““w2-fri@y#
$CJa .7A,!76Iw
w.
-%:jb 1
I.u(L1.0. 9
AFT-IN 0
RESE1 7
k-W
1 I I
In&
1
1 1 I I I
II
I076 t293114(R, S,l, U1 II
7F2-*c106
77J7 ~’
n?mO.dl
0711253936
IEE3
:?;; R71647K
---l-m-
-L+R741220
55
:7JS
ml
—
R764
-W
—
—
1 L [ i
I I
#
Fig.2 Schematic diagram of CPU
-6-
I IBlanking output l! llOut
aCreen character output 2 B0
aBlanking output 2 3 G
r-lLine out mute output 4 R
TV/AV-switch & SCART input
I
5 P4
V-sync in(vert location) 6 P62
aReset input 7 RESET
~AFT input 8 P51
Time base signal inputl 9]P50
aVolume control signal 10 VDPO
aColour control signal 11 VDP1
l-lBrightness control signal 12 VDP2
dContrast control signal 13 VDP3
uRemote control input 14 P53
1---1Power protector signal 15 P60
aAFT switch output 16 P70
uPower switch output 17 P71
A/V switch output [181P72
aCround 19 TEST
I-1Tuning voltage output 20 D/A
~
Ground 21 Vss
Vcc
OSC2
Oscl
[Isync
Vsync
P21
P20
Xout
Xin
P61
P12
Pll
Plo
P03
P02
Pol
Poo
P33
P32
P31
P30
(Top view)
Fig.3 CPU M34300N4-622SP
—421Power source (+5V)—
--l41 CRT display OSC output
401CRT display OSC input-—391H-sync input-—381V-sync input
371Text data output-—
J36 Text clock output
~CPU clock output
341CPU clock input
33\Skew output
.321Band output-—
J31 Band output
3010ption switch output-
—
-J28
-271-
1-l26-
124
123
322
Key scan output
Key scan input
pin allotment
-7-
CPU pin descriptions
‘in’40. Function Description Note
1 CRT display blanking-out-1 H:activc H:>2.4Voutput L:<O.4V
2 CRT display f;rccn character H:active H:}2,4Vsignal output L:<O.4V
3 CRT display blanking-out-2 H:active H:)2.4Voutput L:<O.4V
4 Line out mute output H:mutc ON H:)2.4VL:mute OFF L:<O.4V
5 TV/AV switch & Out H:TV,AV2 mode In H:SCART in, no H>2.4V or 0,7VDDSCART input L:AV1 mode L:SCART in, ycs L(O.4V or 0.4VDD
6 Vertical sync H:>O.7VDDsignal input L:(O.4V~~
7 Reset input L:active H:)0.9VDDL:<0.4VDD
8 AFT signal input H:)0.7VDDL:<0.4V~D
9 Time base signal H: Time base signal: ycs H:>0.9VDDL: Time base signal: no L:<0.4VDD
10 Volume control H:activc L{O.4Voutput
11 Colour control H:active L<0,4Voutput
12 Brightness control H:active L(O.4V
output
13 Contrast control Hactive L(O.4V
output
14 Remote control L:active H:)0.7VDD
input L:(0.4VDD
15 Abnormal power source H:abnormal H:)O.7Vrmsignal input L:normal (Note 1) L:<0.4VDD
16 AFT switch signal H:AFT ON H:)0.7VDDoutput L:AFT OFF L:<0.4VDD
17 Power switch output Out H:Power OFF In H:R/C H:)2.4V& R/C switch input L:Power ON L:without R/C L:(O.4V or 0,4VDD
18 AV switch 1n H:AV-1 Out H:TV,AV-1 mode H:>2.4VL:AV-2 L:AV-2 mode b.(0.4V or 0.4VDD
19 Test terminal Connected to GND
20 Tuning voltage out L: active 14 bits PWM output H:)2.4V, L:O.4V
2 1 Vss Ground
Note 1: When “L” is maintained for 1.2 seconds, power is switched off.
-8-
I
PinNot Function Description Note
22
23 Key switch input L:active H>O.7V ~
24L(0.4fDD
25
26 Key switch scan out & L:active
27 system switch out System switch : See Note 2L(3V
28 Key switch scan out L:active
29
30 Option switch output L:active L<3V
31 Tuning band output See Note 3
32
33 Skew output H OFF L<0.4VDDL:ON
34 CPU clock input 4 MHz
35 CPU clock outputceramicOsc
36 Text control output Clock output?%.::
37 Text control output Data output H:)2.4VL:(0,4V
38 CRTmdisplayvertical sync signal H:}2.4V
L: active39 CRT display
L<O.4V
horizontal sync signal
40 CRT display OSC input5 MHz OSC
41 CRT display OSC output
42 v~~ 4,5V-5,5V
( Note 2 : System switching ) (Note 3 : Band switching output)
System French systems 4-system
L’ L B/C 1 3-systcm
Switch s-1 s-1 s-2 s-3 s-l s-2 s-3 s-4
Pin 26 L L H H L L H H
Pin 2 L H L H L H L H
t-VL
Pin 31 L
Pin 32 L
Band
--1-VH UHF
-J-LH
HL1
-9-
m
Z. Key Input Cirouit
This circuit sends the timing signal output from pins 26 to 29 of the CPU topins 22 to pin 25. Fig.4 shows the key input circuit.When a key is pressed, key scan signals are sent toThe CPU decodes the input key scan signal, judgesthen performs the operation that corresponds to that keyAs shown in Fig.5, an option switch is also included in
either of pins 22 to pin 25.which key was pressed, and
scan signal.this system.
22CPU
H
Preset
23Tuning+
24Prog.(+)
P25
Analoguecontrol
26 (+)
27P
d Mcrnory
TTV’AV-Disp’ay&selectcontrol
(-)
29
Pil 29‘1
Pil 301
?
S1 Pin
I I
S9 S2 Pin
S5 S3 Pin
-wP’i”
—lystcm switch
Fig.4 key matrix
Diode
[Sw. Connected OpenI [
25 S 1 IUHF only 13 Bands i
\S2 I4 systems I3 systems I
IS3 ISystem display:no ISystem display: yes I-424 1 1
S4 ISystem L/L’ ISystem B/G,l/I’ 1
S5 AV mode system AV mode systcmmemory : no
23memory : yes
S6 Text : yes Text: no
1S9 IDigital AFT : no IDigital AFT : yes I
22 1S8
Is’
CPU pin 18:ground=AV-2, off=AV-1 ICPU pin 17:ground=R/C, off=no R/C I
1 I J#
Fig.5 Option switch matrix+=+
-Io-
,,,,,, ,,’,.. .’,”’. :., ,.,.,,..’,,‘,,’,’.,’,,.,.,,,. .
,.,.,...,.,,.,,,. ., ....,,. :, ”.. ., I,,, ,,.,.,,.,,. .. . . .
The TV receiver can be designed to allow selection of desired modes by connect-ing diode to the option switch instead of the keys mentioned above. The signalat this circuit is taken one time only, at the time of initialization, which iswhen the main switch is turned on.
The CPU then decodes this according to the program, and enters the switchcondition in the memory of the necessary RAM. The data of this RAM are read and
#executed during the execution of the main program.
3.Key Functions
3–1 Main SwitchWhen the TV power cord is connected and the main switch is turned on, the CPU
terminals operate as shown in the timing chart of Fig.6.First, the power supply for CPU peripheral circuits rises to +5 V. The terminalat pin 17 then rises temporarily to 5 V and immediately drops to O V. At thecut-off of Q792, the base of Q552 goes high, energizing Q552 and grounding R565and D562. This energizes Q551 and Q554 and supplies B4-24 V and B6-12 V to theset. During this time, the CPU reads and starts to output tuning data frominternal memory.
Audio mute also goes active to mute the audio signal. The CRT starts operationabout 600 ms after the main switch is turned on, and displays text on-screen.
All OFF Main switch ONN
CPU power
i!
CPU pin 17
TV oweri I
l!V & 24V ----- -------------- --------------------------- -------end-by160 430ms _ 675ms
condition!!ii Ims ;
AFT output(PIN 16)
UN
OFF— 1.
AFT OFF AFT ON
II I
CRT display~!!?!!7!!?!!:!!__K____._L
Stand-by conditionFig.6 Timing chart for power ON
As described later, the CPU is equipped with a variety of special functions.When the main switch is turned on and the CPU is placed in stand-by condition toallow operation using the power button of the remote control transmitter,the timing for the voltage of each terminal is as shown by the dotted lineabove. The +12 V and 24 V power supplies for the TV then remain OFF awaitingthe input of the remote control transmitter’s power button.
-11-
ii
3-2 Remote Control of the Main Power SupplyThere are two methods used for remote control of the main Dower, and the
control system differs slightly from the stand-by condition described above.
15$1AEO ! 92
Q
C562 R557160ET : :J
1s1835 !005532SC536
i J# J [ 11552 r
lK- A .... m
,, 12Y . . . . r, -&&+ C?J63 L
I
Fig.7-A
. ...!.....
-Q-?7R7Q7’2G[
..470 2SJ?7
m;L?J,.0!
Lo!..,..
/
.,3
b I L 1 1 1 1 m., 1 I 1 w
LTo Q716
Fig.7-B
With the control system shown in Fig.7-A, when CPU power control pin 17 is at5 V (high), Q792 (POW. OFF) is ON, the base of Q552 is turned OFF by groundpotential, and Q551 (B4-24V) and Q554 (B6-12V) are cut-off, stopping the 24V and12V supply to the TV. The power switching circuit, however, refiiains operatingto supply +130V, 15V, etc. Considerable power is thus consumed by this circuitduring stand-by.
This iS improved in the power control circuit shown ill Fig.7_B, ill which thephotocoupler which is inserted in series with the base of Q315 in the switchingcircuit goes ON when Q716 is energized, thus sending base current to Q315. Q315goes ON, grounding the base of the power switching transistor Q313 and stoppingthe oscillation of Q312. The power switching circuit does not operate, the~secondary side outputs of the converter transformer all become zero, andvirtually the only power consumed during stand- by is that of the CPU. Thisextremely small power consumption differs considerably from that of Fig. 7-A.
Fig. 8 shows the timing chart for when the power button of the remote controltransmitter is used to turn on the power from the stand-by condition.
-12-
CPU powersource
~Set 12V(24V)
AFT SWoutput
Mute
tch
5v–
Ov
12V
ov–-B
5v—
Ov
5V
ov–
ON–
OFF
‘cIwer ON
160ms -
[24V)
PowerOFF
Fig.8
130ms —
1-
‘ower ON
I
575ms~
AFT ON
LOFF
-13-
4. CPU Clock Oscillation
Clock oscillation for CPU operation is via a ceramic oscillator conncctccl topins 34 and 35. The oscillation frequency is 4 MHz.
5. CRT Display Clook Oscillation
(lock oscillation for the CRT display is viaconnected to pins 40 and 41. TH71O SDT-35 iscompensation with an oscillation frequency of 5VR71O(3K) to compensate the position of text on
an L/C oscillating circuita thermistor for temperatureMHz, which is adjusted bythe CRT. For text display
(size, type, position, etc.), the blanking signal from pin 1 of the CPU and thetext signal arc synchronized and output to Q641 of the CRT PCB via Q741 and Q742buffers, and the text symbol is displayed. The reference signal for textposition is made up of the vertical and horizontal sync signals input to CPU pin39, together with the clock oscillation circuits connected to pins 40 and 41.
To position the text vertically, display begins from the trailing edge of thevertical sync signal to the nth line of the horizontal sync signal. The valueof n is determined by the CPU program.Left/right positioning begins from the trailing edge of the horizontal syncsignal to the nth oscillation pulse (pins 40, 41). Here also, the value of n isdetermined by the CPU program.
6.Band Switching and Tuning
6– 1 Band SwitchingThe band switching signal is output to CPU pins 31 and 32, Band switching
operates only when the preset button is pressed to set the preset mode. It doesnot operate outside the preset mode.
Each time the preset button is pressed, the levels of pins 31 and 32 change asshown in the table below, cycling through VL-VH-UHF-VL.
The output of pins 31 and 32 alters the output voltage of pins 1, 2, and 7 ofband switching IC LA791O, to switch the tuner’s receiving band.
I CPU IBand Pin 31 Pin 32
VL L L
VH L H
UHF H L
-14-
,/”....,,”:,:. ,...”
,,.‘., ‘,’
... .,., ...,,,,.. .
,.,.. .
0 (’LA7!210
Fig.9 Band switch IC
There isindividually
1I
Input from CPU
Pin No.3
L
H
L
H
Pin No.4
L
L
H
H
1-
Output from LA7910
TVL(NO.1) VH(NO.2)
H
H
I L: less than 0.8V \ -: High impedance\ H: more than 3V I H: 12V
JHF(No.7)
H
also an A2 chassisconnected transistors
LA791O in/out level
infor
which band switching IC LA7910 is replacedeach band (VL, VH, UHF). See Fig. 10.
LL-1-%- r
To T“ UHF
To T“ VH
To T“ VL
CPU UHF VH VL
32 31 30 QI Q2 Q3
L H H H-12V L:OFF L:OFF
H L H L:OFF H-12V L:OFF
H H L L:OFF L:OFF H-12V
.
-15-
The timing of band switching operations is shown in the figure below,
When the band voltage is switched, tuning voltage pin 20 is completely loweredand the tuningminimum level.circuit is muted
Band data
Mute
AFT output(pin 16)
Tuningvoltage
voltage of the tuner connected to Q785 starts operation from theLinear AFT is also turned off at the same time, and the audioto cut pulse noise generated during switching.
c?”-1 I
l----+””tc“---l1
II
AFT OFF—
+Tu~g voltagc=minimum
I
Fig.11 Timing chart for band switching
6-2 TuningWhen the preset button on the set is pressed to place it into the preset mode
and onc of the tuning keys is pressed, the tuning voltage of the tuner goes upor down. The tuning voltage is output to CPU pin 20, from which it passesthrough the low pass filter of C789, R790, and R789, and is applied to the tunertuning pin via Q785. Muting operates while the tuning kcy is pressed. Theentire tuning voltage range is divided into 16,383 steps. When the button ispressed, the values change for the first 300 ms as follows: VL=l5 steps, VH=8Steps, and UHF=4 Steps. Following this, the tuning voltages change inproportions of 64 steps/80ms, 64 steps/32rns, and 64 steps/l 6ms respectively.
For VL to go from minimum to maximum voltage, it takes 20 seconds to change16,383 steps at the rate of 8 steps/10 ms (16383/8 x 0.01s); for VH it takes 40seconds, and for UHF it takes 80 seconds.
The output of CPU pin 20 is the same as that described in the next section,6-3 Fine Tuning, in which the waveform is output with the pulse modulatedaccording to 14-bit digital data for 122Hz with a 500-ns minimum pulse width.
However, the rate of change for output amount differs from that for finetuning, with 64 steps/80ms for VL tuning as compared to 4 steps/100ms for VLfine tuning.
-16-
6-3
Thefrom
#
,..’, .,,.
.,.,,.
,,... ., ... .,.,. ,,,
Fine Tuning
fine tuning key of the remote control changes the tuning voltage outputCPU pin 20 and applies it to the tuner as shown in the table below,
Band Step changes/100ms Min-max time Total steps : 16,383
VL 4 410 sec
VH 2 820 sec
UHF 1 1,640 sec
When the tuning key is pressed, linear AFT goes OFF (CPU pin 16 goes high).Fine tuning does not operate in the AV mode. In the preset mode, the bar displayon the CRT changes according to the tuning voltage.
In the actual output waveform of the CPU tuning voltage, voltage changes arerepeatedly modulated withinpulse width of 500ns.
[500ns-minimum
a pulse width of 122 Hz and output with a minimum
pulse width
1-122Hz(8.2ms) 4
This output passes through the low pass filter C790, C789, and R790 to controltuning voltage transistor Q785 and change the voltage at the TU pin of thetuner. The output waveform changes as shown by the broken lines in Fig.12.
7. System Switching
When the system switching keylevels of CPU pins 26 and 27
The table shows the conditionsOPEN, S4 OPEN (no diode connected).
connected to CPU pins 25 to 29 is pressed, thechange sequentially as shown in the table below.
when the key input option switch is set to S2
CPU LA791O
Pin 26 Pin 27 Pin 2 Pin 7
S1 L L
S2 L H H
S3 H L H
- : High impedanceH: 12V
-17-
The output from pins 26 and 27 is input to pins 3 and 4 of systcm switching351 LA7910. This input changes the levels of LA791O pins 2 and 7 as shownthe table. When pin 2 is high, Q357 is ON, and AN3565N(SECAM decoder lC) pinis high, the systcm is PAL. When pin 7 is high, Q351 is ON, and AN3565N pin 8grounded, the system is SECAM.
When pins 2 and 7 are both open, AN3565N pin 8 opens and the systcm (PALSECAM) is automatically judged by the lC according to the input signal.
The output waveforms of pins 26 and 27 described above are as shown below.
t-20nls ———————
Pin 26,27= Low level 5V n n
ICin8is
or
Ov
Pin 26,27 =High lCVC1 5V
Ov
~-2oop Fig,13
8. Analogue Control(Volume, colour, brightness, contrast control)
These controls are adjusted by pressing the select key for the desired controlitem, then using the -/+ keys.
CPU pin 10 :CPU pin 11 :CPU pin 12 :CPU pin 13 :
The output that resultsappropriate pin with theaccord ing to 7-bit data.is 16 W.
Volume control outputColour control outputBrightness control outputContrast control output
from pressing the -/+ keys sends a waveform , to thewave form pulse width modulated in up to 65 stepsThe frequency is 1 kHz, and the minimum pulse width
—
I
<Control min. ) <Control max. )
The 65 steps that bring this data from minimum to maximum value take abwtseven seconds. The pulse output that reaches pins 10 to 13 passes through thelow pass filter that is connected to each pin, after which the volume controloutput applies DC control to the audio lC, and the colour, brightness, andcontrast control outputs apply DC control to the chroma IC. The controlindications shown below are displayed on the CRT in accordance with the outputlevel.
La GIFig”’5.0The control items are switched by pressing the CPU select key, which cycles
through COLOUR---BR1GHTNESS---CONTWST---VOLUME--repeatedly, and the level ofcontrol is adjusted for whichever control item is displayed on-screen.
,,.,,. .;,,.. . ‘, ’:,..:.,.,.,.. ‘, :’, .,,, ,, 1.,’;.,,’ ,. ,’. ”;.,.’
.,.,,;. ‘., ,,
9. Linear AFT
The AFT circuit and its operation have not changed from previous chassis. Inthe A3 chassis, AFT operation is performed by the tuning circuit connected to
)in 43 of IC101 LA7680 and consisting of T131, C131, C132, C133, C134, and L131,Because the tuner voltage holding accuracy of the voltage synthesizer used in
this chassis is not as high as that of a frequency synthesizer, AFT must beconstantly applied after tuning. However, since errors may occur with AFTapplied when the tuning voltage is changed by changing channels or switchingtuning bands, AFT must be turned off during these operations. Thus for bandswitching, the AFT ON/OFF signal is sent to CPU pin 16.
When pin 16 goes high, Q751 goes ON, and AFT operation is stopped by forcefullygrounding the L/C of the AFT tuning circuit at VIF CPU pin 16.
Conversely, when pin 16 is low (0.4 V or less), Q751 goes OFF, and the AFTcircuit of 1C101 operates normally to apply the AFT voltage output (1C101 pin44) to the tuner AFT pin.
Note The digital AFT circuit is not used in the A3 chassis (CPU pin 8).
10. TV/AV Switching
10– 1 SCART 2 I–Pin SwitchingWhen an external control signal is connected to pin 8 of the 21-pin socket, the
video circuit can be remotely switched using the switching TR or IC.
10– 2 Remote Control or TV/AV Key SwitchingAddition of the option switch (see Key inputs) allows switching between AV1 and
TV or between AV2 and TV. Either switching cycle can be controlled by remotecontrol key or a key on the set to cycle TV-AV1-TV-AV1... or TV-AV1-AV2-TV...
i
CPU pin 18
OFF ON
> Fim16 sT+-”
<Option switch S8>
The output of CPU pin 5 turnsWhen CPU pin 5 is low (SCARTgoes ON. At the same time,to the external AV input is
(Option switch S8 : ON)
the switching TRpin 8 is high),
the TV pin of
ON/OFF.TV/AV switch Q732 goes OFF and Q810switching IC801 (LC 4066B) connected
opened, the pin connected to the external AV isclosed, the audio signal is input- to audio output lC pin 2, and the video signalis input to pins 38 and 33 of video signal processing lCIO1 via Q802.
When the option switch is OFF (CPU pin 18 is OFF), two AV inputs are possible.Switching is then done according to the changes in CPU pin levels that are madeby pressing the TV/AV key on the set, as shown in the table below.
-19-
CPU Pin 5 CPU Pin 18
TV H (5V) H (5V)
AV 1 L (OV) H (5V)
AV 2 H (5V) L (OV)
(Option switch OFF>
in eith~r case, the muteis pressed to switch modes,
Key 011
signal is output for about 600 ms after the TV/AV keyin order to prevent noise during switching.
-160ms 430nls
1z
TV(or AV mode) I AV (or TV mode)
Mute ON
Mute OFF ~ IFig.17
-20-
11. Other CPU Functions
11-1 Memory(1) The memory function
.,..’.
is used to store the control values for volume, colour,brightness, and contrast during ordinary TV
#from memory and reproduced during laternormal key of the remote control transmitter.
(2) The tuning voltage, band voltage, and systemduring preset.
11– 2 off– Timer
reception, so they can be readTV reception by pressing the
data are also stored in memory
I
When the off-timer key is pressed, “-00” is displayed on the CRT. Then eachtime the key is pressed, this display cycles through “-30” “-60” “-90” “- 120”“-00’’... The first time the off-timer key is pressed, the time remaining on thetimer is shown. Each subsequent press of the key increases the time by 30minutes. This timer setting is cancelled when the power is turned off.
11– 3 NormalWhen the normal key is pressed, the control values which have been stored for
volume, colour, brightness, and contrast are read from memory and set
accordingly.
11– 4 Sound Mute
11- 4– 1 During Channel SwitchingWhen the sync signal from VIF lC pin 30 is input to CPU time base signal pin 9,
it is applied simultaneously to audio output lC pin 3 via Q 181. Then as soonas the sync signal stops, muting is applied to the audio circuit.This prevents popping noise when changing channels or switching bands.
VIF lC pin 30 is high when the horizontal sync signal is normal, and low whenthe phase of the horizontal sync signal shifts. Thus pin 30 goes low in theabsence of a sync signal or when horizontal sync deteriorates, mutingtransistor Q181 goes OFF, and pin 3 of audio 1C171 AN5265 goes high (12 V), toset the audio lC volume at minimum and prevent audio output.
11- 4– 2 During Remote ControlWhen the mute button of the remote control transmitter is pressed, the signal
is decoded by the remote control receptor and the audio control signal which isoutput to CPU pin 10 is set to the minimum level in order to cut audio output.
11– 5 Skew OutputWhen the programme number for VCR1, 2, 3 or the AV mode is selected, CPU pin 33
goes low. This cuts off skew signal switching transistor Q733, then passesthrough D731 and is applied to VIF/DEF IC1OI pin 32, where it shortens (by 1/2)the normal time constant of the AFC (automatic frequency control) for thehorizontal sync signal within the IC in order to quickly trace unstable input inthe horizontal sync of playback from sources such as a VCR, and pt%vefit jitterin the horizontal direction of the image.
-21-
I
11–6 Overload ProteotorWhen an abnormality during TV reception causes CPU pin 15 to go continually
(less than 0,8V) for approximately one second, the overload protector shiftsTV into stand-by condition. In the actual circuit design, pin 15 is connectedthe 9V power supply of the set in order to protect the set from being damagedoperation when a malfunction in a component along the 9V line, or along theline, has caused an extreme drop in voltage.
11-7 Teletext ControlA clock frequency of 14 kHz output from pin 36 and 7 bits of data from pin
lowthe
toby
12V
37are input to the Teletext decoder CPU to control the Teletext CPU. A partiallist of the text control signals that are derived from the 7-bit signal of pin37 is shown in the table below.
5VPin 36 clock output Fig.18
. u – Ov14kHz
_ Pin 37 output Bit o 1 2 3 4 5 Fig.19
Bit O=I:Text mode, Bit O=O:TV mode
Bit123456
p:;”;;001110
1111”10
RedGreenYellowStatus
SiziupDown
Tex~
-22-
i
12. Special Function
This CPU is equipped with special functions that allow the set’s initialcondition and subsequent operating conditions to be set. This is not possible,however, in preset, AV, text, and text-TV-n~ix modes. The descriptions and
setting procedures for these special functions are given below.You can set the special functions to input the special codes using the special
key and the programme selector of the remote control transmitter.
The codes and functions are as follows.
Code Function
I 01 IReset all special functions I
\ 70 ISearch for channel scanning I71 Memory delete for channel scanning
(Used to delete a programme position from the channel scanningposit ions. )
72 Memory add for channel scanning(Used to add a programme position to the channel scanning positions.)
90 Private position (Set and reset)(Used to restrict the viewing of some programme positions. )
NOTE Special functions are not cancelled when the power is turned off or whenthe AC power plug is disconnected from the mains.
Setting the Private Position (Special code 90)
. The private position is used to restrict the viewing of programme positionsthat you do not want others to watch.
o Any positions can be set as private positions.
ExampleSetting Programme Position 15 as a Private Position m1.
2.
?. .
4.
Select programme position “ 15“ using the programme selector.I
s-1I
Press and hold the special key of the remote controltransmitter for more than 2.5 seconds. “SP--” will bedisplayed on the screen.
nsP––
]nput special code 90 using the programmc selectorof the remote control transmitter.
Press the memory button in the front control sectionof the TV set. ‘The picture will then disappear, and“X 15“ will be displayed on the screen. u
The private position setting is now completed.When position 15 is selected using the programme selectorafter the private position setting has been completed, onlythe characters “X 15“ will appear. &
Fig.20
-23-
Watching a Programme in the Private Position :1. Select the private position (position 15) using the
programme selector .2. Press and hold the special key of the remote control
transmitter for more than 2.5 seconds. ‘ SP--’ will bc n
displayed on the screen.3. ]nput special cndc 90 using t hc programme selector
of the rcmo! e control transmitter.The programnlc in the private position will then tiappear. Next, press the special key, and “SP90”will dicappcar.
NOTE: If you watch a programmc on the private position, thenE
SP90
select another programmc position, you will have to repeatthe above procedures before you can watch a programmc in Fig.21the private position again.As many private positions as you want can be set.
Resetting the Private Position#This is done in the same manner as the private position setting.
—
For example, to reset programme position 15 in the private position:1. Select programme position “15“ (private position) using the programme
selector. (“X 15“ will be displayed on the screen. )2. Press and hold the special key of the remote control transmitter for more
than 2.5 seconds. (“SP--” will be displayed on the screen. )3. input special code 90 using the programmc selector of the remote control
transmitter.4. Press the memory button of the front control section of the TV set.
Position 15 is now reset in the private position.
Channel Search (special code 70)# When special code 70 is input, all the programme positions are automatically
scanned, and the active programmc positions arc stored in memory.Once this programming is complctcd, the TV receiver will select only thestored programmc positions when the channel scanning key is pressed.
Inputting special code 701. Press and hold the special kcy of the remote control
transmitter for more than 2.5 seconds.(“sP--” will bc displayed on the screen, )
2, input special code 70 using the programmc selectorof the remote control transmitter.
3. Press the memory button. The programmc positions arcthen automatically scanned, and the active programmepositions are stored in memory, The channel scanningwill then stop at the position where it started scanning.The channel scanning is now completed.
ElsP-–
El
SP70
Fig.22●
-24-
,,,. .’, .,,
,.,,,.’ i
Memory Delete for Channel Scanning (Special Code 71)This function is used to delete a programme position from the channel scanning
positions, so it will not be scanned when the channel scanning key is pressed.
-For example, to delete position 2 from the channel scanning positions:r
1.
2.
3.
Select programme position 2 usingthe programme selector.Press and hold the special key formore than 2.5 seconds, and inputcode 71 using the programme selectorof the remote control transmitter. DC
Press the memory button of the front Fig,23control section of the TV set.Position 2 is now deleted from the channel scanning positions,Position 2 will be passed over when the channel scanning key is pressed.
Channel Scanning Memory Add (Special code 72)This function is used to add a programme position to the channel scanning
positions, so it will be scanned when the channel scanning key is pressed.
For example, to add position 2 to the channel scanning positions:1.
2.
3.
Select programme position 2 using the programme selector.
~~Press and hold the special key for morethan 2.5 seconds, and input special code
72 using the programme selecter of theremote control transmitter. Uu
Fig.24Press the memory button, of the front control section of the TV set.Position 2 is ‘nowPosition 2 will be
Resetting All SpecialWhen special code 01 is
added to the channel scanning positions.scanned when the channel scanning key is pressed.
Functions (Special code 01)input, all the special functions are reset.
How To Input Special Code:1. Press and hold the special key for more than
2.5 seconds, and input special code 01 usingthe programme selector.
2. Press the memory button of the front controln
SPO1section of the TV set.All the special functions are now re-set. Fig.25
NOTE: The special functions can also be cancelled by inputting code ()(). Whenspecial functions are cancelled using code 00, the start condition for TVpower is changed to the standby start condition, meaning that the picturewill not appear even when the mains ON/OFF switch is set to the onposition. To turn on the TV set from the standby mode,press power on(offbutton of the remote control, Code 00 is input in the same mafiner as code01.
-25-
Other Special FunctionsThe start condition for TV power can be changed by inputting code 50 or 51,
When code 50 is input:Even if the mains bN/OFF Switch is set to the on position, the picture
will not appear. (The TV set remains in the standby mode). To turn on the TVset from the standby mode, press the power ON/OFF button of the remote control.
Inputting Code 50 :1.Press and hold the special key for more than 2,5 seconds, and input code 50
using the programrnc selector.2.Press the memory button on the front control section of the TV set,
NOTE: To return the TV’S power starting condition to its original condition,input code 51. Code 51 is input in the same manner as that for specialkeys.
13. CPU Repair
When installing a ncw CPU, keep in mind that the data of the EEPROM inside theCPU must be initialized the first time it is used.to initialize.(1)(2)(3)(4)
(5)
(6)
(7)(8)
(9)
Connect the antenna to the TV.install the new CPU.Turn on the power switch.Select position 1 using the direct access of theremote control.
Select the special function mode by pressing andholding the recall key for more than 2.5 seconds.(“SP--” will be displayed on the screen.)
Use the numeric keys to input 00 or 01 (see notebelow).
Press the memory key,Press the preset button, then select a channel andstore it in an appropriate position.
Press the preset button again to return to the normalreception mode.
Usc the following procedure
EsP–—
El
SPOO
Fig.26
This completes the initializing procedure, lf you should make athis initializing, turn off the power and repeat the procedure
Note: Inputting 00 will set the stand-by starting condition, so
mistake duringfrom step (3).
that when themain switch is pressed the set will enter stand-by condition and wait forthe power key of the remote control transmitter to be pressed.inputting 01 will start the TU in whatever condition it was in when thepower was last turned off.
-26-
,,,,, ,.,‘,,’.
[ Part 2 VIF/CHROMA/DEF ONE CHIP IC LA7680]
This part describes the functions of SANYO LA7680 PAL/SECAM
processing one chip IC ,according to the pin allotment respectively.]ig. 1 and Fig.2 show the block diagram and the pin allotment.
tI
colour TV signal
>:co
>az
I f \ I
Fig. 1 Pin allotment
-27-
ii
o ?.3(2SC5.J6
-+2_4 2SC536
kC155KZ
0.01
!?;;7II
z
!7137270KR138270K
J31000
I 22K
252 ~25 ,J,k CJ68R
T
i-
J
U161L164*Z R163 C121
8?0 0 (7 4,7K wCd
~ r’ *i16~~>.i 15xF
RIAO
$‘ill
IK
2C1621 161 .,.,. ! r,. 16EMI0
4 m
clb316EM10&
R748[J245))74,s 1555
220
R745 R746180 [K
—
ClooKZ
1 T2iPiIlToT mF “k” ‘m’;<
O1OI
0.01
w‘i’T102sTll133xv
Will
x 47 yiCIO.9 rpc. I47R il
v---%0117>WJduo T %-L,,
Rl[o{I J. I., F )
11]DJ 0110270
wFOA02- IOA
4
r1
C760-.
I10
r
if
C.X5 ’28KZ 2.70,01
R284680
R2.93680 z1?OR
C?21 222
Volz l%’ -
C271FK0,01
r
t-R26322QK X?o I
R?(,4
t
n}R262 R26 112K
390K4,7K _ +
& ~ ~~:~
C272KZ0,01
M.
1. ‘n
,CEo
14
1 111111
IilrvR28 I1-
B-IK0 ;033
Pm
&L-Jm
IK EM4.7 VR~IIB-20K
t431 R412
130I /213J2,7K
0411::A;CI-10 ~%::
1C28
J
KZ0.0
R28390
..R420I /2DJI,2KI * 100
r
1
“’o’ ~ ILA7680 CWWM4J OEF J.W4E
TFig.2 1C101 LA7680 peripheral circuit
-28-
,’..,,’,,
,,..,
l. VIF/SIF/AGC
1-1 FM Detector output (Pin 1)The l-pin output is based on the emitter follower circuit. Therefore, its output
impedance is rather low. The capacitor of 1000PF sl~ould be inserted for carrier‘filtration between this pin and the GND. In sound multiplex system, the capacitor
value should be changed to 560pF (-3dB at 60kHz).The “de-emphasis” circuit would require a series resistance of 5.6k0 and a
capacitance of 0.01 UF between that resistance and the GND.
Vcc
::200 From FM DET.
300 5k 30k Bias
FM DET o 5V
OUT <I
I-2 FM Discriminate & Mute (Pin
L.NDFig.3
2)The FM detector is based on a “quadrature detection circuit”. This detector uses
two signals: one with limited amplitude from the limiter AMP and the other with90” of phase difference from the phase shifter. These two signals are used by themultiplier for FM detection. The output level and the bandwidth can be determinedby the two damping resistors (R1 and R2) for the coil and the ceramicdiscriminate.
The MUTE function for the FM detector can be activated by lowering the DC pinvoltage across the damping resistance to less than 1V.
Example ceramicdiscriminate circuit
Mute
30k* P
Vcc10k
Mute
15/JH
‘CDA 5.5ME21
MURATA
h & Limiter amp
Fig.4
-29-
i
1-3 Negative Feed Back of AF Amp (Pin 3)This pin is for audio pre amp Negative Feed Back (N.F.B).
The output signal from pin 1 enters the A.F, amp circuit through the D,C. att,circuit and then amplified. The gain can be determined by the RI value. If it islk~, the gain would be about 20dB. The pin 3 D.C. voltage is about 4,2V.The output signals from pin 3 and pin 5 (audio output) are in phase with each
other. Therefore, the output signals from pin 5 arc inverted and then fceded backto pin 3 as AC signals.
If external AC feedback to pin 3 is not used, incrcasc the RI value in orderfor the pin 5 output not to reach saturation region (for example, Rl=l 2kfl ).
..
1-4The
This
Vcc
Fig,5
ll~di~ F~Q~u61~~y Input (Pin 4)input impedance is set to 30k Q.pin circuit is internally DC-based. Therefore, the input signals should be
accepted via a coupling capacitor. If the internal signals from pin 1 arc rc-ccivcd, the polarities of the capacitor should be set as shown below.
FM DETOUT
DcVR +
5V
Fig.6
-30-
,,, , . ..“,..,.,,,.
,,, .,, ,,, i
1-5 Audio Output(Pin 5)This pin is for A.F.amp output. The pin outPut is based on crnittcr-follower
circuit and has a series resistance of IOOQ, Some driving conditions would
require lower output irnpedancc. in these cases connect an external resistor RI as~hown below. The sound output power can be determined by the ratio of R2 and R3.The DC output voltage at pin 5 is about 4V.
I
IFzyqR2
NFB
-F 3
R3 -+
1-
Y
/
/
Z% *7?%
Fig.7
h
Vcc
.-
1-6 VIF Amp Input (Pins 7 and 8)These pins are for VIF amp input. The signal input to this pin uses the balanced
transmission circuit. The capacitor should be used for DC shutout. Its capacitanceshould be 0.01 UF or more. The input impedance Ri is about 1.8k0 and the input
capacitance, about 4pF. The IC pin wiring should usc the Cl and crossed on aprinted circuit board. This may improve the electrical field characteristics.
In case of High impedance SAW In case of Low impedance SAW
HI imp. SAW LOimp. SAW
Fig.8
-31-
1-7 RF AGC Volume (Pin 9)The AGC voltage smoothed by pin 10 (first AGC filter) is again smoothed by the
Cl of the pin 9. The gain control is carried out by this double smoothing.Cl is used for determining the AGC time constant and should be a polyester filmcapacitor. By applying DC current externally to pin 9, the operating point of theKF AGC AMP can be changed and the RF AGC out signal from pin 46 can be adjusted,
The operating range of the RF AGC amp can vary depending on the value of aresistor R1 in series with pin 9, However, it should be 100kO. The Cl capacitor(polyester film capacitor) should be placed as C1OSC as possible to pin 9.
10k
VR
Vcc
?
b-i” :‘L‘~lOOk 10k
9 alR1
c1
J
VIF0.01/.s , AMP/
For
For
charging
charging
RF AGC
OUT RF AGC
AMP L
J//
Fig.9
-32-
,, ,,, .,,.,, ,,, . ..... ;., .,,,.,.,,
1-8 AGC Filter (Pin 10)The peak signal detected by the AGC detector is smoothed by the Cl capacitor,
an external capacitance to pin 10 and then generates the AGC voltage.To determine the AGC time constant, add a capacitor between 0.22 and 0.47uF
externally. Note that the external capacitor with small leakage current should0 be used. Fo~ twnpla: OS txp~citor, tantalum electrolytic capacitor, etc. (for
limiting the ringing of synchronization signal leading edge at rather a lowtemperature. )
By lowering the pin 10 voltage to less than 1V, the mute function can beactivated for the FM detector and the video output circuits at the same time.
This terminal isconnected to thebase terminal ofthe 01 transistorshown on the
previous page.
10k
10k*)
Bias
VIDEO&AUDIO
VIDEOSIG,
MUTE t--l%
Fig.10
1-9 Video Output (Pin 42)This pin is for video output and based on emitter-follower circuit, The value of
the biasing resistor R1 should be 1kQ or more. Changing the R2 value would affectpeaking and f characteristics. Video output voltage at no signal= 4,5V, Voltage ofa synchronization signal leading edge= 2.3V. Video amplitude= 2Vp-p.
~ ‘cc Tvcc
330
lk RI ‘2
i“!l!i ‘
VIDEO500 OUTPUT
// / /
Fig.11
-33-
1-10 AFT Coil (Pin 43)The AFT circuit is based on “quadrature detection circuit”. This circuit uses
two signals: one is the CW signal from the video detector and the other is thesignal with a 9~ of phase difference from the pin 43 phase shifter. These twosignals are input to the multiplier for phase detection.To activate the AFT defeat function, connect the pin to the GND through the RIresistor, Note that the R1 resistance should bc less than 20kil. The AFT improvesas the Cl value increases. The recommended Cl value should be in the range between68pF and 10OpF.
The AFT irnprovcs as the Q of the L1 increases. The recommended QO is 90.C2 is needed to form a sound trap circuit. This circuit prevents the AFT circuitfrom muifunctioning. Cl :C2=5: 1 is desired. lf the AFT defeat switch is not used,RI and C3 arc not required.
I T VccI
Bias 115k \
> {b ‘
-x‘ 1.5pF4,
AFT
DEFEAT
Cw
(From VIDEODET COIL)
Fig.12
C2 +(-3 J_
-r I
1-11 AFT Out (Pin 44)The AFT circuit uses the collector of the current mirror circuit for output
and includes an on-chip load resistance.The direct voltage of pin 44 at no signal is about 4.5V (typical), The AFTsensitivity can be changed by the value of external resistors RI and R2.The recommended ratio of R1 and R2 is 1:1 to maintain good tcmpcraturccharacteristics.
c1closetime
is a capacitor for carrier filtration, This capacitor should bc placed asas possible to the pin. The values of R3 and C2 can determine the AFT loop
constant.
-4300
-F%
1300
— Vcc -
67 k
.-
%
67 k
- Vcc
RI
*;””R2 1000p
H / /
Carrier
Filter
-34-
0
Fig.13
ii
1–12 SIF Input and D.C. Att. (Pin 45)Pin 45 is an unbalanced SIF input pin. Its input impedance is about 3kQ. This
pin serves as the D.C.att. input pin alternat ivcl y. The input is controlled bya PNP type transistor and its input impedance is very high.If external components are added as shown below, the buzz characteristics can
‘be improved. The c) circuit shows the best high pass filter characteristics.
Vcc
Bias ~DcATT
5k5k
5op21 Q Bias
II~ t
5k
-T- ‘cc
Fig.14
I I
J%7)%0”0”h
1-13 RF AGC Out (Pin 46)This pin output is based on emitter-follower circuit. The time constant can bc
determined by external components, R and C. The maximum direct voltage of this pinis 8V, Select the values of RI and R2 with tuner specification in mind, tocieterrninc the direct voltage.
Cl is used as a carrier leakage filter capacitor for preventing unpredictableoscillation. The values of R1, R2 and C2 can determine the RF AGC loop timeconstant.
T ‘cc200 RI
> To Fig,1530k TUNER
Tcl R2
-35-
1-14 Video Detector Coil (Pins 47 and 48)The best value for the QO of the video detector coil is about 60. If the value of
damping resistor RI “is incrcascd, better 1.07MHz beating is irnprovcd. At the sanletime,the video output is degraded quickly in distortion.The recommended value for damping resistor RI is about 3k0 to 4.7kfl.
?/4
Fig.16
2. Video/Chroma
2-1 Chroma Input
0
and Color Control --alternative pin (Pin 40)
..... ...... .. ... ... ......... .. .. . .... .... .. ..... ..... .... ...............
1st B.P.A.3op
ColR02 %3 :
‘ : ‘*
C3
“v
40 01 Q2R3
@l
z%2 : Iok
/./
Rol ~ R1
2.2k ~ 16k
1= < ‘v
/ / J /
R2 15kColor ~ To color
control –%4 ~ c1 control
Jlop ~ J?:p
/
O.O’lLI :.--.-—-—--— ..... . . ...... .. . . ..... ........
Fig.18Chroma input and color control circuit(Pin 40 receives a chroma signal with color control voltage superimposed on. )
2-1-1 Chroma InputCO1, LO1 and C02 form a band-pass filter. RO1 and R02 are damping resistors for
the band-pass filtration. Note that the input impedance of pin 40 is about 7k!l.C3 is a capacitor for DC shutout and used for cutting color control voltage.
The standard input to pin 40 is 100mVp-p at burst signal level. If the signallevel is too high, divide damping resistor RO1 and then connect the dividingpoint with the pin.
2-1-2 Color ControlThe input voltage (chrorna signal + DC voltage) to pin 40 goes to the low-pass
filter circuit (Rl, Cl, R2 and C2) and its output is used as the color controlvoltage. The low-pass filter circuit eliminates the chroma signal from the inputvoltage to the pin and finally picks up the DC voltage only. This DC voltage isused as the color control voltage. The
2-2 ACC/Killer Filter (Pins 39 and 41)Pins 39
~~~ol,, circuit
detectionFig.19
control neutral voltage is 1/2 Vcc.
and 41 filter pins for smoothing burstoutput voltage. The ACC and the Killer
are operated by differential voltage
~c,~ between these pins. Note that pin 41 can be used
zfor white balance adjustment.
O.01/,IF
Pin 41 holds the burst detection voltage during burst ON. In other cases, pin39 holds the burst detection voltage. As the amplitude of the burst signal goes upfrom O, the differential voltage between pin 39 and pin 41 goes up from O to somehundreds nlV. In this case, the voltage of pin 41 gets higher. Capacitor C3 betweenpin 39 and pin 41 is needed for removing ACC vertical sag. The standard values forCl, C2 and C3 are shown in the above example circuit.
To adjust white balance, set the pin 41 pin voltage level t~ less than L5V(VCC=9V, Normally ground level) and the pin 32 vertical out to high level.
-37-
2-3 Contrast Control/Burst Cleaning Coil (Pin 12)
Fig,20 Contrast control/burst cleaning circuit
[—~ TO ACC, Killer. etc.
[: ii “& +--Ezl
Q +;fll R2
68p9k 9k
~LI j Buff. Color Contrast%: Control
Contrast R3 2op 2opControl C2 C3
.— J$,,
%LkO’d.zOO1~; 4’to Contrast Control
.. .. ... ..... . . .. . .. .. . . . .. .. ....... . . .... ......
* Burst cleaning coil -- Mitsumi MA8051
Pin 12 is for rccciving (video/color) contrast control voltage (DC) and a burstcleaning pin.
2-3-1 Contrast ControlThe contrast control voltage is input to pin 12 through R3 and L1. It is then
divided into the Video contrast control signal and the color contrast controlsignal by the buffer circuit. The color contrast control signal is DC voltagewithout burst signal. The burst signal is removed by the low-pass filter circuit(RI, R2, C2 and C3), The video control control signal is DC voltage without burstsignal. The burst signal is also eliminated by the low-pass filter circuit.
2-3-2 Burst CleaningThe tank circuit (L1 and C4) is added to pin 12 for burst cleaning, R3 for
contrast control and burst cleaning coil LI are connected as shown in the abovediagram. lts junction is connected to the ground through the 0.01 pF capacitor Theresonance level of the tank circuit is determined by LI and C4. lts resonancefrequency (f) is calculated as follows:
f = l/2RjE
To adjust the rcsonancc level, input ACC allowable signal to the chroma inputpin, and change the L1 value while monitoring the pin 14 chroma output. When theresonance frequency is detected, the amplitude of the chroma output signal isrcduccd to a minimum level. At this time, the amplitude of the burst signal hasincrcascd to a maximum lCVC1. I 1
2-4 Chroma Out (PinPin 14 is for outputting
signals and its output ison open emitter circuit.
(1)PAL standard: The
“’on)achrOma+u--based
& O.OlpF//,
DC voltage level at pin 14 is about 6Vdc (VCC 9V),irrespective of contrast and color
. .control voltages. The chrorna signal is
superimposed on the DC level output signal. Since the maximum supply current of Q1is 10mA, select the RI value with chroma signal in mind.
-38-
,,, ,.,.,,,.,. ,.. ,..,,. ., ,,,..’,, ,. .,,,,,,
i
(2)NTSC standard: The DC voltage level is about OV and no chroma signal is output.The standard R1 value is lkfl.
2–5 Ident Filter (Pin 15) n
#
(1)
(2)
PAL standard:The phases of the PAL signal R-Y signal component and burst signal changeevery lH. The signal detected and then outputthis pin and smoothed by external capacitor Cl.the phase of burst signal.As the value of Cl is increased, noise immunitythe judgment of burst signal phase takes longeris 0.0047pF as shown in the above circuit.NTSC standard:
by idcnt circuit is input tolt is finally used for judging
is improved as much. However,time. The standard value of Cl
NTSC standard requires no ident circuit. Set the pin voltage level to lessthan 3V for IC switching from PAL to NTSC. Connect this pin to the groundthrough a 1k~ of protection resistance.
2-6 X-tal Pin (Pin 16)Use a crystal (X’tal) oscillator in series with chroma subcarrier frequency line
for resonance.Example:
?
16
Fig.23-L~ 1 Crystal resonance I
0 series with subcarrier—
J_ in series with subcarrier J_ Crystal re~nance in
T4 frequent y I ine
?kz(a)
2-7 APC Filter (Pin 17)
Vcc
I/(b
PinThe9V).6V.
frequency line
(b) typex 4.433619 MHz - Kinseki EXOC043.579 S45MHZ - Kinseki EXO017
7 is an APC filter pin. ..
internal APC reference voltage is about 6V (VccThe DC voltage of this pin is about the same asSince the ripple rate of the APC reference
voltage is is about- - 57%, the best ratio of R1/R2 is4C2 ‘11
+
c1 0.47/.LF R2 0.75. If both of the RI and R2 values arc increased,
TO.olp pull-in rangem , the pull-in range
Fig.242-8 Tint Control (Pin 19)(1) NTSC standard:
By applying DC voltage to this pin, TINTreference voltage is 1/2vcc, set this
(2) PAL standard:The PAL standard stops the internal TINTapplied to this pin, TINT cannot be controlled, DC voltage apply to thi~ pinwould not affect internal function blocks such as the TINT at all.
is widened. If they arc decreased,is narrowed.
can be controlled. Since the internalpin voltage level to the 1/2vcc.
circuit operation. Even if voltage is
-39-
i
2-9 B-Y-In/R-Y-In (Pins 18 and 20)Pins 18 and 20 are pins for receiving chroma
14). This applies only to the PAL standard.The output signal from pin 14 is divided intodelay line. The B-Y component is input to pin20.
I
LA7680
signal from the chroma out pin (pin
B-Y and R-Y components by the 1H18 while the R-Y component to pin
I ‘‘ o,ol/1 IIR(32 Fig.25
1 6804Y—
Ro3
680
O.olu -’- %3
J /
The input impedance of both pins is about 16k0. The DC voltage is about 3V DC forPAL and about 2. 3V DC for NTSC, with the pins left open. The B-Y and R-Y componentshould be input to the pins according to this DC voltage.CO1, C02 and C03 are capacitors for DC shutout. The connecting point between R02and R03 is connected to the ground through capacitor C03 for reducing noise andripple. If noise or ripple is active, demodulator balance is degraded, causinglarge carrier leakage.RO1, R02, R03, and LO1 are needed for 1H delay line matching, The output signalfrom pin 14 is divided into two signal components: B-Y and R-Y, VR1 is used forreducing the original signal by the combined loss of the lH delay line and TO1.
The demodulation output rat io can be changed by modifying R-Y or B-Y signalcomponent, as shown below.
LA7680 ‘‘O.oljl
IL
R(32660
4
C(33I
&
Fig.26
-40-
,,.
2-10 R-Y/G-Y/B-Y Colour Difference Output (Pin 21,22 and 23)(1) Pins 21 and 23 are for R-Y and B-Y color difference output, respectively. Pin
22 is for G-Y color difference on the LA7680,
(2) Generally, the low-pass filter●
difference pinsSuch an external
--i
for subcarrierfilter has good
,.6F+T’”+
(270Q and 390pF) is connected to the colorfiltration. However, it is not always required.
effect on spark.
TI
Z%:*
Fig.28Applicable to pills 22 and 23The above example circuit includes a low-pass filter for spark.
-.
ii
-41-
3, Video Out and Defltw~ion
3-1 Video output (Pin 24)Pin 24 is for video output and for FBP input.
Fig,29
7.25V
V.BLK
,-.+02-Y
i m FBP(BLK)
The video signal is output to pin 19 through Q3, and D3. By inputting FBP to pin- 24 through DO1 and RO1, horizontal banking of the video output signal can be
controlled. The FBP signal from pin 24 is taken into the IC by Q1 and Q2(threshold voltage 7.25V) and used as horizontal banking pulse for chroma signal.Resistor ROI is used to restrict to less than 10mA the peak current flowing intopin 24 at the FBP input. Note that FBP is clipped by Q4 at Vcc + VBE point.The FBP ringing may be superimposed on the video signal (-Y) and cause screenoutput distortion. DO1 is a diode used for preventing such a problcm.The horizontal banking is carried out automatically through D2. At this time, the24-pin output voltage is about 7.2V (17.5H for NTSC and 21.5H for PAL).
3-2 Power Supply (Pin 25)Pin 25 is power supply pin for
Fig.30lcc=13mA
+
+tiigh B .
horizontal deflection.
... . .. . .. . .
7.5V
RI r I+ I
I
Her. OSCZener AFC
DriverI
h ??$?........... ...... ......
Select the R1 value in order for the current flowing into pin 25 not to reach13n~A.
+B-7.5V #Rl=
13nlA
-42-
i
3-3 Fly Back Pulse Input, Burst Gate Pulse Output (Pin 26)Pin 26 serves as a three-functional pin: flyback pulse input, burst gate pulse
output and VCR switch.
..........
Fig.31 Vcc
FBPVcc
cl
VCR SW
2.4-3.4V *
v~~ + Zvf ...........>
318 x Vcc + 2vf -->
pulse
3-3-1 Flyback pulse inputThe flyback pulse at about 100V is input to this pin through resistors RI and R2.
The threshold voltage for flyback pulse input to the lC is 3/8 x Vcc + Vf.Resistors RI and R2 are used for limitting to less than 5mA the peak currentflowing into the internal IC (Q4). input flyback pulses enter the AFC loop circuitfor absorbing horizontal output and storage time. However, since the screencentering was offset in advance, change the R1-C1 integral value to carry out thescreen centering.
3-3-2 Burst gate pulse outputFlyback pulses input to the pin through resistors RI and R2 are limited by Q4 and
Q5 at 3/8 x Vcc + 2Vf. The flyback pulse voltage rises up to Vcc + 2Vf only duringburst gate pulse output. Because of this, the burst gate pulse is not output ifscreen phase adjustment is not complete.
3-3-3 VCR switchPin 26 serves as the VCR switch by superimposing 2.4V to 3.4V DC voltage on input
signal to this pin. This DC voltage causes Q3 to be always active.If the VCR switch turns on, the normal AFC 1 (pin 29) control current is doubled.However, the VCR switch cannot function if vertical free-run operation like nochannel has been started.
-43-
i
3-4 HorizontalPin 27 serves as
Output (Pin 27)a horizontal output with push-pull specification.
Fig.32 Horizontal driver Tr.
.... . . ... ... ..........
3-!5Pin
3-6Pin
C$3;i3n&lRx30xmtor (Pin 28)used as the pin for connecting a ccrarnic resonator to the ]C.
AFC Filter (Pin 29)29 is an AFC1 filter pin.
Since the DC bias for AFC output is determined by 3xVfAFC filter should be placed close to the power supplycharacteristics.In the circuit diagram below, Cl is a capacitor for
from the power supply, thefor improving power ripple
eliminating vertical ripple.Resistor R1 is for producing voltage from control current.used as a smoothing capacitor.When the AFC control current is converted to voltage byinternally limits the voltage at ~ 1.5V.
Fig,33
..- —-;::
7.5k
25k
tic-l
And Capacitor C2
resistor Rl, pin
is
25
3-’7 Filter for Horizontal Sync (Pin 30)Pin 30 is used as a filter pin for detecting horizontal synchronization signal.
When horizontal screen image phase adjustment is complete, the voltage at pin 30gets high. Otherwise, its voltage gets low.
H
3k
Q3Q4
2.7k
""""""-"""-"--""""":""-" fl:""""""-""""""'"""""""""""""-"~
~ Channel select signal
Fig.34
Q3 and Q4 forms a comparator using the 1/2 Vcc voltage as the reference voltage.If the voltage at pin 30 gets below I~ VCC, horizontal synchronization isconsidered incomplete. In this case, virtual count-down mode is switched tononstandard mode and at the same time horizontal AFC1 control current is doubled,Therefore, if the external time constant for Din 30 is small. the Dull-in time at4-channel selection is shortened.
However, if the external time constant isgets low due to electric field effect andstability than the nonstandard modeTherefore, the external time constant forelectric field effect, noise characteristics,
.-
too small, the voltage at pin 30 easilynoise. The standard mode shows better
in electric field effect and noise.pin 30 should be deterrninated, withand synchronization troll-in speed in
mind. Pin 30 can be used as input pin for channei select signal through transistor.
TR1 .
3-8 Vertical Output (Pin 31)Pin 31 is connected with such vertical output lCS as the LA7835/36/37/38 (SANYO).
The LA7680 has the automatic select circuit for vertical synchronization signal ‘-cycle from 50Hz and 60 Hz. It outputs the result to pin 31. If the LA7680 selects60 Hz, it outputs high to the pin. Otherwise, it outputs low to the pin.
Fig.35
~ “ p~=--- i ~‘“””.”..”.’”-.........””..-..31 ........................................................................ ................................~
u
If the cycle of the verticalconnect pin 31 to the GND or
synchronization signal is fixed to 50Hz or 60 Hz,the Vcc.
-45-
i
1)To use the internal 50/60HZ cycle select circuit:
7-~ Vertical trigger accept period ~
60Hz select periods
-t-
50Hz select periods255H CyCIC 288.5H cycle <Cle
2)T0 set the pin 31 voltage at higher than 8.7V:
7~Vcrtical trigger~
accept period225H CyCIC r 297H CyCIC
3)T0 set the pin 31 voltage at lower thari 0, 15V:
~Vcrtical trigger~accept period
269H cycle 357H cycle
3-0 vertical Output, Sensitivit y Setting (Pin 32)Pin 32 serves as multi-functional pin: Vertical output, sensitivity setting for
horizontal synchronization separation, external vertical triggermode release switch, and V-HOLD.
input, autotrigger
A2xvf—.. . .. . ,.—.,-. - w +- ~Q5 Q8#aensltlvlcy ur pulse
7Q2SZ II-J>
,,
r Input to vertical driver
Rol (to pin 2 of the LA7835)
4
Fig.36
-46-
...,.,
,’ .(,, ‘,,, .,.,
.,, . ,,, ., .,,,...’., 4 .’ .,,, .,,,. ,, ,,,,,, ,., ,, ,,. i
3-10 Vrtical Deflection CircuitThis system has a divider circuit using 2fH as the clock.
3-10-1 lSO/60Hz Automatic select1 Ver G 288.5 : Select50Hz
0 1 Ver < 288.5 : Select60HzThe pull-in period right after synchronization signal input is in the cycle
period between 225 and 357, as shown below.
As stated above,circuit selects
-Vertical synchronization pull-in period~— - Select 60H2
-t-Se’ect ‘OHz—225H cycle 288.5H cycle 375H cycle
if the vertical cycle is 1 Ver > 288.5H, the automatic select50 Hz. lt then narrows the pull-in period as shown below.
~357Hcyclelf the automatic select circuit selects 60 Hz, it sets the pull-in period as shownbelow.
=297Hcycle
3-10-2 60/60 Fixed FunctionTo start the 60Hz fixed mode, apply the voltage higher than 8.7V (VCC=9V) to pin
31. in this mode, the vertical synchronization pull-in period is set as shownbelow.
I225H cycle
To start the 50Hz fixed mode, applythis mode, the vertical synchronization
I
I‘297H cycle
the voltage lower than O.15V to the pin. Inpull- in period is set as shown below,
—
~, 269H cycle1357H cycle
-47-
i
3-10-3 Standard/Nonstandard Judge CirouitThe standard/nonstandard judge circuit k provided for telling standard signals
(1 Ver=262,5H for NTSC or 1 Ver=312.5H for PAL) from nonstandard signals(1 Ver= 262.5H or 312.5 H).This circuit consists of a base-8 (octal) counter and base-4 (nibble) counter.lt counts up for each Ver cycle.
If the standard signal counter advances to’’8”, this system resets the systemusing a pulse signal generated by the system divider. (Standard mode)This counter operate at 1 Vcr=262.5H cycle (60Hz NTSC) and at 1 Vcr=312.5H (50 HzPAL). (Auto-trigger mode)
If the nonstandard signal counter advances to’’4”, the systcm is reset by thetrigger pulse generated within the vertical synchronization pull-in period.(Nonstandard mode) This function works together with the horizontal synchro-
nization signal detect function of pin 30.The nonstandard mode is started up when the horizontal synchronization is notcomplete and the voltage at pin 30 gets below 1.2VCC.
3-10-4 Vertical Blanking Pulse Generation60Hz (NTSC) 50Hz (PAL)
.-o~ of-I
-?).5 H 17H ~ -O(5H [ 21H
3-10-5 Horizontal AFC Defeat Pulse Generation60Hz (NTSC) 50Hz (PAL)
I2:8H OH AH
I~308H OH i 8H
The horizontal AFC defeat period is an period of the above pulse period and thevertical synchronization signal period. Therefore, if the vertical synchro-nization signal period is longer than 8H, the horizontal AFC defeat period becomeslonger as much.
3-10-6 Free-Run ModeIf vertical and horizontal synchronization signals are not input, this system
enters into free-run operation mode at 1 Ver 262.5H or 1 Ver 312.5H period.In this case, whether 1 Ver is 262.5H or 312.4H depends on 60Hz or 50Hz at eachmoment.
That is, when the system receiving 60Hz signals (NTSC) enters a no-signal state,the system is forced into free-run operation mode at 1 Ver 262.5H.If the system receiving 50Hz signals (PAL) enters a no-signal state, the systemis forced into free-run operation mode at 1 Ver 3 12.5H period.The system can be operated at 1 Ver 262.5H by applying the voltage higher than8.7V to pin 31. To start the system operation at 1 Vcr 312.5H, apply the voltagelower than O.15V to the pin.
-48-
.,4...,’:., .“. .,. ,’,,,,..,.’
. ,,,
.,, ./ ,,:,. .,
3-10-7 External Trigger InputTo output an external trigger pulse to an lC, supply the current greater than
1.7mA from pin 32 to the ground.The synchronizable frequencies by the external trigger pulse is from 1/225H tol/356.5H.
0
“L
i....... .......... 32 ....... .. .. ....Fig.37
R(M2.4k
n External trigger pulse
,
3-10-8 Auto- Trigger Mode Release Switch
H~------ 32 ------”~
R03
Fig.38Rol
24k R04
/ /
To release the auto-trigger mode, add the clamp circuit in order for the 32 pinvoltage not to get below L7V.The auto-trigger mode can be released by setting 31 pin voltage level at lowerthan 1/2Vcc, as shown below.
Fig.39Q~------ 30 -----”””~
lkChannel select signal
The channel selection by this system requires 4 Ver periods so that the verticalimage adjustment can be completed by the above three functions, To improve thesynchronization signal pull-in speed, pin 30 or pin 32 should be used in theabove-mentioned manner if the channel selection signal is used for this purpose.
That is, both of pin 30 and pin 32 can be used as the release pins for theauto-trigger mode. ln this case, there will be no problem if voltage is alwaysapplied to pin 32. However, the voltage level at pin 30 should not always be setto lower than 1/2VCC because the primary function of this pin is to detect ahorizontal synchronization signal. For more information on the pin 30 timeconstants, refer to the item dealing with pin 30.
-.
-49-
3-11 Vertical Synchronization Signal Separation
Output signal waveform of pin 32 for standard signal
-<”””””””’’’”CCJ
OH
Sf3nsitivity EkWing
r112 “cc
\ ~--- 0“
310.5 H 312H 8H
Fig.40
The vertical synchronization signal scparati9r4 sensitivity can be set by changingthe external RO1 resistor value of pin 32. The sensitivity of the verticalsynchronization separation has a high level period and a low level period, The32-pin output signal waveform peak voltage during the high level period is 2/3Vcc.If the value of resistor RO1 is set to 24kll, the minimum synchronization signalpulse width for vertical synchronization is 14FS during the high level sensitivityperiod and 23.5ps during the low level sensitivity period. This is not affectedby change of the RO1 value.
In addition, this system is designed to synchronize with the copy guard signalshown below, with ROl=22k0.
(1Op
r
d - - —
“-”-~ 0.5 H [email protected]
< Vertical synchronization signal s.
Fig.41
#
-50-
3-12 Sync Separation Input (Pin 33)Pin 33 k used as a synchronization separation input pin.
# M15k
Q2
-JLn~ f $, +R1
1 4 I ( ~
Composite video
— 7VC2 R~
Tsignal input
!T* u /........................”.” . . . . . . . .
Fig.42
Set the Cl value to 0.22 to 1uF, and adjust R2 to produce the potentialdifference across R1 so that it becomes equal to about 30% of the synchronizationsignal. RI is a resistor to supply the driving current for synchronization signalseparation. The value of resistor R1 should be set to supply 300uA when thepotential difference across RI gets to 30% of a synchronization signal.C2 is used as a high-frequency filter for feeble electric field. The filtercharacteristics are determined by R1 and C2. Pin 33 is used to keep the blackscreen, for example, if no signal is input to video input pin after the TV set isswitched to the video signal input mode ,
i
-51-
i
3-13 AFC OperationThe horizontal defection circuit of the LA7680 is based on double AFC technique,
The operational blocks and the waveforms of each block are shown below.
=+’4=32fH
Fig.44
Jr E
Sync A AFC 8 Hor Phase Hor J
Sep I C.D.F @
Shifter Driver
I h
L$=l--l”
“ .............-.-. . . ............................
H ... .. ..._ ! .__ ----- - ._._.-..: .-. _.-----
- -
0
-52-
ii
(1) The AFC1 controls the horizontal OSC block so that the B pulse falls at themiddle of the A pulse signal.
A: Vertical synchronization signalB: fH (Pulse generated by dividing the horizontal OSC output by 32)
(2) The AFCII controls the phase shifter so that the D pulse falls at the middle*
of the G pulse signal.D: Pulse delayed 2 clocks (about 4ps ) after B.G: FBP pulse delayed by RO1 and CO1.H AFCI1 output voltage (As H voltage increases, the phase of
signal J is delayed. Otherwise, it is advanced. )J: Horizontal driver output pulse
3-14 Brightness Control (Pin 35)Pin 35 is a brightness control pin. The neutral voltage for brightness control
is about 4.5V. At this voltage level, the output voltage of pin 24 (-Y out) isabout 3V.The relationship between the 24-pin output voltage and the brightness controlvoltage (V-brightness) is show below. Note that the V-brightness can be changed byusing VRI,
AV.y. out =-6
7R01 ~. AVB:ight
‘1+ 3ok
0
+
“---””-..24 -———–—— 35 .." . ... . ... . .. ... .. .................... . .. ........-
-y.out Rol
i
VR1R~z @Z
JI,
‘cm ‘
h
Fig.45
The DC restoration rate can be changed by usinghighest if the R02 value is set to “infinite”,will be lowest.
\ V Bright
R02 and COI,If the R02
The rate will be theis shorted, the rate
—
-53-
3-15 Pedestal Clamping Filter (Pin 36)Pin 36 is a filter pin for pedestal clamping.
Fig.46
-? Vcc3.3k A
~z’ c1lk lk (lpf)
,+
‘t C2(2.2pF)
/
The output voltage of pin 36 is about 3.3V at brightness control neutral level.For transition response during power ON and OFF, two capacitors should be addedexternally as shown in the above figure. The ratio of Cl (connected with powersupply)/C2 (connected with the GND) should be 1/2.
3-16 Video Tone Control (PinPin 37 k used as the second
f Rot (S.zk)
37)differential input and the video tone control pin.
R3> Video controi circuit
C2 J- 10k
~ R2
15k zz
J< T 1
?l’: ‘i’=’h L O.olgA Cal
Fig.47/, (22pF)
o
J /
Icll”’”1
The SCGOUd differential signal is generated from an input Signal t9 pin 37 whichk first differentiated by RO1 and CO1,The DC voltage from the video tone volume
and again internally by Cl and RI.control VRI is transmitted to the video
tone control circuit through RO1, pin 37, R2 and R3.The neutral level of the video control is about 4V. By changing this voltagev~ue, the second differential signal can be controlled.
,!..
$!,;-54-
,,. ,,., ,.. ,.,,,,. ,
,..ii
Fig.48#
VR’!YG...............
37
m ~. .
ft + 38
/ /....... .......
If the video tone is set to “sharp” and the-Y output waveform (pin 24) are not equal tothe circuit as shown above. Then, adjust thethe undershoot can be equal to each other.If the video tone is set to “soft”, connect R02 to
3-17 Video Signal Input (Pin 38)Pin 38 is an input pin for video signal.
Flat
pre-shoot and the undershoot of theeach other, connect the coil (LO1) to
RO1 value so that the pre-shoot and
the circuit.
signal Soft signal
Fig.49
‘r f’Rot D.L
w
z
5k
, R02 RIa7,
R133 10pF j 5k5k c1
alz
2op/
#z
RO1, R02 and R03 are matching resistors for delay line.The standard input level at pin 38 is 0.5Vp-p to 0.8 VP-P. To adjust the inputlevel, use R02 and R03.The soft video tone signal is generated by removing high frequency component fromthe video signal of pin 38 with the low pass filter (Rl and Cl). The softening can –be controlled by changing the composition of the flat signal of Q1 and the softsignal of Q2 with the video tone control voltage from pin
3-18 Contrast Control (Pin 12)The contrast control is carried out at about 22dB.
2/3 VCC.
37.
Its control neutral voltage is
2kBuffer v A., v <,
213VCC
Fig.50 \ 2op
......................
-55-
[Part 3 Power Supply Circuit]
1. Operation Outline
As shown in Fig,l the power-supply circuit of an A3 chassis is composed of therectification smoothing circuit, tllc oscillation circuit, the control circuit andthe output rectification circuit.
Fig.2 shows the voltage and current of each point in the normal operation of thepower circuit. The AC input voltage is rectified in full-wave in the rectificationsmoothing circuit, and unstable DC voltage is smoothed by the smoothing capacitorC507. This unstable DC voltage is input to the oscillation circuit. In theoscillation circuit, the blocking oscillation circuit is used for the switchingtransistor Q513 to gcncratc (in the input coil) the square-wave pulses and theoscillation frcqucncics corresponding to the operation of the control circuit.The square-wave pulses obtained in the output coil have a dimension corresponding tothe ratio of the input coil to the output coil; these pulses are rectified at theoutput rectification circuit, thus the desired DC voltage is obtained.
2. Explanation of Circuit Operation
--2-1 Starting OperationWhen the power is switched ON, a trickle current flows through the starting
resistors R520 and R521 toward the switching transistor Q513 base, and a greateramount of collector current flows through the input coil (3)-(7) of the convertertransformer, As a result, electromotive force is generated in the input coil(3)-(7), and voltage is also gcncratcd in the feedback coil (1)-(2).
This voltage is, through (R5 19, C514, R524), applied as positive feedback to thetransistor Q513 base, thus the transistor is turned ON.
The above operations are performed in an instant, and enough base current is inputinto Q513 to maintain the ON state.
The collector current of Q513 amplified linearly as time passes according to thei=V~*t relationship. (Note; that L is the inductance value of the input coil)
2-2 Oscillation CircuitEach operation of the switching transistor Q513 is explaihcd below.
2-2-1 Switch Off Operation(A) When the control circuit k not in operation.
The collector current is amplified Iincarly as time passes. When the collectorcurrent becomes hfe times as large as the base current, Q513 can no longerremain ON, and switches OFF immediately.
(B) When the control circuit is in operation .When Q513 is ON , the positive pulses are generated in the feedbackcoil(l)-(2), and are integrated to make the sawtooth-wave pulses.The composite voltage is made from these pulses and the fluctuation of theoutput voltage, and is applied to the base-emitter of Q512. When thisbase-emitter voltage reaches the a sufficient value (approx. 0.6 V-O.7V), thetransistor Q512 is turned ON. Then the base current of Q513 is bypassed to the 0collector-emitter of Q512, and Q513 is immediately switched OFF, Thefluctuation of voltage, mentioned previously, is dctectcd on the second sideof T511.
-56-
,.’ .,.,
When Q513 is switched OFF, the energy stored in the input coil (3)-(7) during theON period is supplied to the load side from the outputrectification circuit.
At this time, the current flowing in the output coil attenuatesRefer to Fig. 2(f).
‘ 2-2-2 Switch On Operation
coil through the output
as time passes.
The current flowing - in the output coil attenuates as time passes, and when it .finally reaches zero, the T1 period ends and the T2 period start.At this time, resonance is caused by the inductance of the coil (3)-(7) of theconverter transformer, T5 11, and the distribution capacity is inserted equivalentlyin parallel with T5 11.
The resonant current flows toward terminal (3) from terminal (7) in the inputcoil, and as a result, because the generated current flows toward the terminal (2)from the terminal (1) in the feedback coil, Q513 remains OFF.
The resonant current becomes maximum at the end of the T2 period, and thedifferential coefficient of the current becomes zero.
After that, the polarity of the differential coefficient of the current isinverted. As a result the current directed toward the terminal (1) from terminal(2) is generated in the feedback coil, and applied to the base of Q513,
Thus, Q513 is switched ON momentarily by the positive feedback action in thefeedback coil, even if there is only a slight base current.
-57-
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Converter transformer T511Voltage between (3) and (7)
Converter transformer T511Current flowing in (3)-(7)
VCE of Q513
Converter transformer T511Voltage between (2) and (1)
Converter transformer T511Voltage between (9) and (10)
Converter transformer T511Current flowing in (9)-(
(g) VC=ofQ512
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Fig.2 Operation voltage and current waveforms
-59-
[Part 4 Vertical Deflection Output IC LA7837]
1. Overview
The LA7837 is the vertical deflection output device designed for usc with colourtelevisions monitors and displays. It incorporate a builtin ramp generator circuit,constant vertical amplitude function for 50/60 Hz operation, thermal protectioncircuit and pump-up circuit. The LA7837 provides deflection current up to 1,8 Ap-p.
This device offer a number of improvements over previous vertical deflection ICs,resulting in simplified circuit and board design with enhanced performance,This include:
* Newly dcvclopcd driver functions on-chip which allow the AC/DC feedback loop tobe implemented with a single IC, thus reducing problems with cross talk from thehorizontal signals affecting interlace characteristics, Earlier dcviccs includedthe previous stage small-signal processing lC in the AC/DC feedback loop.Interlacing and vertical jitter problems occurred frequently since the feedbackloop had to physically span two separate devices.
* lrnprovcd noise immunity by treating the vertical trigger input as a pulse signalrather than as a Iincar signal. This limits the Cffccts of noise, andparticularly horizontal signal noise, even if the noise is induced onto the
-- connection lines from the previous stage lC.* Built-in driver amplifier so that the gain of the vertical output amplifier is
determined by one device, whereas previously the total gain of the verticaloutput stage was the product of the previous stage small-signal processing lCgain and the gain of the vertical output section. This improvement results in amajor reduction in instability and gain variation problems when different devicesare combined.
* Improved cross-over distortion performance, making these devices particularlysuitable for high-picture quality, large-screen equipment.
* The LA7837 is available in 13-pin SIPS, which include a built-in heat sink.
2. Features* Low power consumption* Minimum external parts count* Stable interlacing and vertical jitter characteristics* Constant vertical amplitude for both 50 Hz and 60 Hz operation* Built-in ramp generator, driver circuit and pump-up circuit* Vertical output circuit with thermal protection* Low linearity fluctuation with vertical screen size* Limited output DC bias fluctuation with vertical frequency
-60-
0
3. Block Diagram and External Connections
.’, .,,
.,.
Vccl &12V
2
7
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5of60Hz
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Fig. 1
12.2 to 4.7
z0.1 pF
-61-
4, Pin Description
Pin
umber
12345678910111213
—
Name
Vcc,lNTC~RAMP
50/60c RAMPFBVCC7
c 1>uMPc FILTGNDoutvCC13
Function
]nput and driver stages positive power supply inputVertical trigger inputOne-shot time constantRamp waveform control current50/60 vertical amplitude control inputRamp waveform integration capacitorVertical output negative feedback inputPump-up circuit positive power supply inputPump-up capacitorHigh-frequency stability filter capacitorPower supply groundVertical deflection outputOutput stage positive power supply input
-t-t--1 I
*!P16k
200
lW
. — —— —
) 00 U1 23 45
+
200
200
)6 7
J1
—
8 9
Fig,2 Pin internal circuit
-62-
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—
—
o10 11 12 13
5. Functional Description
.’..’,.
5-1 Vertical Trigger InputThe vertical trigger input circuit shown in Fig.3 k driven by the negative
~olarity vertical sync pulse from the previous stage small-signal processing lC,The falling edge of the input pulse is inverted by the differential amplifier and
drives the ramp generator. This pulse is differentiated and only the leading edgeused by the ramp generator, ensuring that fluctuations in the input pulse width willnot affect circuit operation.
The input threshold level of the trigger circuit is approximately Vcc/4. The inputtrigger waveform is shown in Fig.4.
01
2
03 04
110
Fig.3 Vertical trigger input circuit
Fig.4. Vertical trigger input pulse
5-2 Ramp GeneratorThe ramp generator circuit shown in Fig. 1I generates the vertical deflection
sawtooth waveform. The circuit consists of the one-shot circuit, a current sourceand a limiter. The sawtooth wave is generated by charging and discharging the I ~Ftantalum capacitor connected to pin 6. The charging current of this capacitor isgenerated by a Miller circuit constant current source controlled by the curreptdrawn from pin 4. The voltage on pin 4 is held constant at approximately Vccl /2,hence the peak value of the sawtooth wave can be changed by varying the pin 4external resistance,
-63-
The current at pin 4 withtantalum capacitor on pin 6, and
Q=CV=IT
IIF X 1.5VP_P =“ * = T = l/6oHz,,
For a vertical frequency of 50 Hz,
1-lIF X 1.5VP_P
‘- ~ = l/50Hz
i5-3 One-ShotThe one-shot circuit clamps
value of 5/12 Vccl. The one-shotBy clamping the start of
the recommended peak sawtooth voltage of 1.5V,11F60 Hz vertical frequency is given by
901 A
the current is:
= 75pA
the sawtooth voltage following trigger input, to aperiod is set by the time constant on pin 3.
the sawtooth at this voltage, fluctuation of thesawtooth start voltage by the horizontal components is prevented. This measureremoves the major source of interlace problems, giving the LA7837 excellentinterlace characteristics.
=-6-3-1 One-shot Time ConstantThe one-shot period must be shorter than the vertical retrace period. lf it exceeds
this period, the sawtooth waveform will still be clamped when the scan line starts.It is suggested that the clamp period, Tc, be set to approximately half the verticalretrace time, TR, ensuring that Tr will bc lCSS than Tc even if vertical size ischanged.
lntcrlace characteristics do not change with Tc, provided Tc is less the TR andgreater than approximately 200Ls.
5-3-2 Time Constant CalculationThe time constant on pin 3 is formed by a capacitor CO=O.O1~F and a resistor RO,
where the clamp time T= O.7COR0.For a vertical retrace period of 1 msi setting RO to 68kll gives Tr= 0,7 X0.01X10–6X68X103= 0.476ms.
.
Fig.5 Clamp Waveforms
-64-
.,,.. .
5-4 Constant Amplitude and Feedback CircuitThe LA7837 lC incorporate circuitry to keep the sawtooth amplitude constant for
vertical frequencies of both 50Hz and 60 Hz. This ensures a constant screen size forboth 50Hz and 60FIz operation whel~ used in dualmodc 50 Hz/60Hz PAL/NT’SC televisionreceivers. This function is controlled by pin 5, the 50 Hz/60Hz amplitude control
# Pin.* Dual mode
For 50Hz vertical frequency, pin 5 is grounded. For 60Hz vertical frequency, pin5 is either connected to pin 1 or to a DC voltage of 3V or more to increase thesawtooth generation current by 20%, thus giving the same screen size as for 50Hzoperation.
* 50Hz or 60Hz single modePin 5 is permanently grounded since it is not needed. Note that it should not beleft open, in order to prevent possible damage due to static discharge.
5-5 Driver CircuitThe driver circuit shown in Fig.6 has a differential input stage driven by the
sawtooth waveform (waveform (b) in Fig.7). The negative feedback waveform at pin 7(waveform (a) in Fig.7) derived from the vertical deflection output is applied t[the other input of the differential amplifier.
The feedback waveform is created by summing the parabollc waveform generated by thevertical output coupling capacitor C3 and the sawtooth waveform produced by the ACfeedback resistor R6 in Fig. 11. The feedback operates so that the DC base voltagesof the differential amplifier transistors Q7 and Q8 are balanced.
As well as the feedback loop to the differential amplifier, a second loop isformed by feeding the sawtooth amplitude control current from the AC feedbackresistor R6 through a fixed resistor and a variable resistor (R1 and VerticalHeight in Fig. 11). Thus, the sawtooth voltage across resistor R6 modulates thecurrent into pinwhole feedbacknegative feedbackcoupling capacitor
4. Since this current is integrated by the capacitor on pin 6, theloop effectively cancels the parabolic component of the pin 7waveform due to the waveform component from the vertical output
C3.
i
Fig.6 Driver Circuit
-65-
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Printed in Japan