coe 202: digital logic design combinational circuits part 2
DESCRIPTION
Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324. COE 202: Digital Logic Design Combinational Circuits Part 2. Objectives. Arithmetic Circuits Adder Subtractor Carry Look Ahead Adder BCD Adder Multiplier. Adder. Design an Adder for 1-bit numbers?. Adder. - PowerPoint PPT PresentationTRANSCRIPT
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COE 202: Digital Logic DesignCombinational Circuits
Part 2
Dr. Ahmad AlmulhemEmail: ahmadsm AT kfupm
Phone: 860-7554Office: 22-324
Ahmad Almulhem, KFUPM 2010
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Objectives
• Arithmetic Circuits• Adder
• Subtractor
• Carry Look Ahead Adder
• BCD Adder
• Multiplier
Ahmad Almulhem, KFUPM 2010
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Adder
Design an Adder for 1-bit numbers?
Ahmad Almulhem, KFUPM 2010
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Adder
Design an Adder for 1-bit numbers?1. Specification:
2 inputs (X,Y)2 outputs (C,S)
Ahmad Almulhem, KFUPM 2010
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Adder
Design an Adder for 1-bit numbers?1. Specification:
2 inputs (X,Y)2 outputs (C,S)
2. Formulation:
Ahmad Almulhem, KFUPM 2010
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
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Adder
Design an Adder for 1-bit numbers?1. Specification: 3. Optimization/Circuit
2 inputs (X,Y)2 outputs (C,S)
2. Formulation:
Ahmad Almulhem, KFUPM 2010
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
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Half Adder
This adder is called a Half AdderQ: Why?
Ahmad Almulhem, KFUPM 2010
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
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Full Adder
A combinational circuit that adds 3 input bits to generate a Sum bit and a Carry bit
Ahmad Almulhem, KFUPM 2010
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Full Adder
A combinational circuit that adds 3 input bits to generate a Sum bit and a Carry bit
Ahmad Almulhem, KFUPM 2010
X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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Full Adder
A combinational circuit that adds 3 input bits to generate a Sum bit and a Carry bit
Ahmad Almulhem, KFUPM 2010
X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
XYZ
0
1
00 01 11 100 1 0 1
1 0 1 0
XYZ
0
1
00 01 11 100 0 1 0
0 1 1 1
Sum
Carry
S = X’Y’Z + X’YZ’ + XY’Z’ +XYZ
= X Y Z
C = XY + YZ + XZ
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Full Adder = 2 Half Adders
Manipulating the Equations:
S = X Y Z
C = XY + XZ + YZ
Ahmad Almulhem, KFUPM 2010
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Full Adder = 2 Half Adders
Manipulating the Equations:
S = ( X Y ) Z
C = XY + XZ + YZ
= XY + XYZ + XY’Z + X’YZ + XYZ
= XY( 1 + Z) + Z(XY’ + X’Y)
= XY + Z(X Y )
Ahmad Almulhem, KFUPM 2010
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Full Adder = 2 Half Adders
Manipulating the Equations:
S = ( X Y ) Z
C = XY + XZ + YZ = XY + Z(X Y )
Ahmad Almulhem, KFUPM 2010
Src: Mano’s Book
Think of Z as a carry in
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Bigger Adders
• How to build an adder for n-bit numbers?• Example: 4-Bit Adder
• Inputs ?
• Outputs ?
• What is the size of the truth table?
• How many functions to optimize?
Ahmad Almulhem, KFUPM 2010
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Bigger Adders
• How to build an adder for n-bit numbers?• Example: 4-Bit Adder
• Inputs ? 9 inputs
• Outputs ? 5 outputs
• What is the size of the truth table? 512 rows!
• How many functions to optimize? 5 functions
Ahmad Almulhem, KFUPM 2010
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Binary Parallel Adder
1 0 0 0
0 1 0 1 + 0 1 1 0 1 0 1 1
To add n-bit numbers:• Use n Full-Adders in parallel• The carries propagates as in addition by hand• This is an example of a hierarchical design
• The circuit is broken into small blocks
Ahmad Almulhem, KFUPM 2010
Carry in
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Binary Parallel Adder
To add n-bit numbers:
• Use n Full-Adders in parallel
• The carries propagates as in addition by hand
Ahmad Almulhem, KFUPM 2010
This adder is called ripple carry adder
Src: Mano’s Book
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Ripple Adder Delay
• Assume gate delay = T
• 8 T to compute the last carry
• Total delay = 8 + 1 = 9T
• 1 delay form first half adder
• Delay = (2n+1)T
Ahmad Almulhem, KFUPM 2010
Src: Course CD
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Subtraction (2’s Complement)
How to build a subtractor using 2’s complement?
Ahmad Almulhem, KFUPM 2010
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Subtraction (2’s Complement)
How to build a subtractor using 2’s complement?
Ahmad Almulhem, KFUPM 2010
1
S = A + ( -B)Src: Mano’s Book
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Adder/Subtractor
How to build a circuit that performs both addition and subtraction?
Ahmad Almulhem, KFUPM 2010
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Adder/Subtractor
Ahmad Almulhem, KFUPM 2010
Src: Mano’s Book
Using full adders and XOR we can build an Adder/Subtractor!
0 : Add1: subtract
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Binary Parallel Adder (Again)
To add n-bit numbers:
• Use n Full-Adders in parallel
• The carries propagates as in addition by hand
Ahmad Almulhem, KFUPM 2010
This adder is called ripple carry adder
Src: Mano’s Book
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Ripple Adder Delay
• Assume gate delay = T
• 8 T to compute the last carry
• Total delay = 8 + 1 = 9T
• 1 delay form first half adder
• Delay = (2n+1)T
Ahmad Almulhem, KFUPM 2010
Src: Course CD
How to improve?
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Carry Look Ahead Adder
• How to reduce propagation delay of ripple carry adders?
• Carry look ahead adder: All carries are computed as a function of C0 (independent of n !)
• It works on the following standard principles:• A carry bit is generated when both input bits Ai and Bi are 1, or
• When one of input bits is 1, and a carry in bit exists
Cn Cn-1…….Ci……….C2C1C0
An-1…….Ai……….A2A1A0
Bn-1…….Bi……….B2B1B0
Sn Sn-1…….Si……….S2S1S0
Carry Out
Carry bits
Ahmad Almulhem, KFUPM 2010
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Carry Look Ahead AdderAi
Bi Si
Ci+1
Ci
Pi
Gi
The internal signals are given by:
Pi = Ai Bi
Gi = Ai.Bi
Carry Generate Gi : Ci+1 = 1 when Gi = 1, regardless of the input carry Ci
Carry Propagate Pi : Propagates Ci to Ci+1
Note: Pi and Gi depend only on Ai and Bi !
Ahmad Almulhem, KFUPM 2010
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Carry Look Ahead Adder
The internal signals are given by:
Pi = Ai Bi
Gi = Ai.Bi
The output signals are given by:
Si = Pi Ci
Ci+1 = Gi + PiCi
Ai
Bi
Ci+1
Ci
Pi
Gi
Si
Ahmad Almulhem, KFUPM 2010
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Carry Look Ahead Adder
The carry outputs for various stages can be written as:
C1 = Go + PoCo
C2 = G1 + P1C1 = G1 + P1(Go + PoCo) = G1 + P1Go + P1PoCo
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
Ai
Bi
Ci+1
Ci
Pi
Gi
Si
Ahmad Almulhem, KFUPM 2010
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Carry Look Ahead Adder
Conclusion: Each carry bit can be expressed in terms of the input carry Co, and not based on its preceding carry bit
Each carry bit can be expressed as a SOP, and can be implemented using a two-level circuit, i.e. a gate delay of 2T
Ahmad Almulhem, KFUPM 2010
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Carry Look Ahead AdderA0
B0
A1
B1
A2
B2
A3
B3
P0
G0
P1
P2
G2
G3
G1
C0
C1
C2
C3P3
C4 C4
S0
S1
S2
S3
Carry Look Ahead Block
Ahmad Almulhem, KFUPM 2010
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Carry Look Ahead AdderSteps of operation:- All P and G signals are initially generated. Since both
XOR and AND can be executed in parallel. Total delay = 1T
- The Carry Look Ahead block will generate the four carry signals C4, C3, C2, C1. Total delay = 2T
- The four XOR gates will generate the Sums. Total delay = 1T
Total delay before the output can be seen = 4TCompared with the Ripple Adder delay of 9T, this is an
improvement of more than 100%CLA adders are implemented as 4-bit modules, that can
together be used for implementing larger circuits
Ahmad Almulhem, KFUPM 2010
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BCD Adder
BCD digits are valid for decimal numbers 0-9Addition of two BCD numbers will generate an output,
that may be greater than 1001 (9).In such cases, the BCD number 0110 is added to the
result as a correction stepWhen adding two BCD numbers, the maximum result
that can be obtained is:9 + 9 = 18 If we include a carry in bit, then the maximum result that can
be obtained is: 19 (10011)Both numbers 18 and 19 are invalid BCD digits. Therefore, a 6
needs to be added to bring them to correct BCD format.
Ahmad Almulhem, KFUPM 2010
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Adding two BCD numbers – Truth Table
The truth table defines the outputs when two BCD numbers are added
The function F is 1 for all invalid BCD digits, and therefore acts as a BCD verifier
To minimize the expression, a 5 variable can be used, or:
-A 4 variable k map can be used to minimize the function F, and
-The result is ORed with CO, since the function is always 1 whenever CO is 1
* From course CD Ahmad Almulhem, KFUPM 2010
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Adding two BCD numbers – Minimization
Z3Z200
01
11
10
00 01 11 100 0 0 0
0 0 0 0
1 1 1 1
0 0 1 1
Z1Z0F
F = Z3Z2 + Z3Z1 + CO
Ahmad Almulhem, KFUPM 2010
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Adding two BCD numbers – Circuit
B3 B2B1B0 A3A2A1A0
Carry In
Z3 Z2 Z1 Z0
0
S3 S2 S1 S0
Cout 4-bit Binary Adder
4-bit Binary Adder
Correction Step
Ahmad Almulhem, KFUPM 2010
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Adding two BCD numbers - Steps
The two 4-bit BCD inputs are added by the 4-bit binary adder to produce the sum Z3Z2Z1Z0 and a Carry Out (Cout)
When Cout =0, the correction step executes by adding 0000 to Z3Z2Z1Z0, and the output remains the same
When Cout =1, the correction step adds 0110 to Z3Z2Z1Z0 to generate the corrected output
The output carry is the same as Cout
If additional decimal digits need to be added, the BCD adder can be cascaded, with the output carry of one phase connected to the input of the other
Ahmad Almulhem, KFUPM 2010
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Binary Multiplication
Similar to decimal multiplication
Multiplying 2 bits will generate a 1 if both bits are equal to 1, and will be 0 otherwise. Resembles an AND operation
Multiplying two 2-bit numbers is done as follows:
B1 B0
x A1 A0
----------------
A0B1 A0B0
A1B1 A1B0 +
----------------------------------
C3 C2 C1 C0
This operation is an addition, requires an
ADDER
Ahmad Almulhem, KFUPM 2010
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Binary Multiplication
Therefore, for multiplying two 2-bit numbers, AND gates and ADDERS will be sufficient
Half Adders
Ahmad Almulhem, KFUPM 2010