code generation is a constraint problem · packing local vs. global 3/35. problems in traditional...
TRANSCRIPT
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Code Generation is a Constraint Problem
Roberto Castaneda Lozano – SICS
Mats Carlsson – SICS
Frej Drejhammar – SICS
Christian Schulte – KTH, SICS
SweConsNet’12
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Outline
1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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Compilers, Code Generation, Register Allocation
Traditional compiler:
front-endinstructionselector
instructionscheduler
registerallocator
sourceprogram
assemblyprogram
code generator
Key code generation task: register allocation
assignmentspillingcoalescingpackinglocal vs. global
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Problems in Traditional Code Generation
All tasks are interdependent
staging is sub-optimal
Each task is NP-hard: solved by heuristic algorithms
fast but sub-optimal and complex
“Lord knows how GCC does register allocationright now”. (Anonymous, GCC Wiki)
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Can We Do Better?
1 Potentially optimal code:
task integrationcombinatorial optimization
2 Simpler design: separation of modeling and solving
. . . sounds like something for CP
previous CP approaches:
scheduling only (Malik et al., 2008)integrated code generation
scheduling, assignment (Kuchcinski, 2003)selection, scheduling, allocation (Leupers et al., 1997)
→ limitation: local (cannot handle control-flow)
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Our Approach
Constraint model unifying
global register allocation with all its essential aspectsinstruction scheduling
Based on a novel program representation
Robust code generator based on a problem decomposition
Current code quality: on par with LLVM (state of the art)
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1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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Running Example: Factorial
int factorial(int n) {
int f = 1;
while (n > 0) {
f = f * n;
n--;
}
return f;
}
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Low-Level Program Representation
After instruction selection
Control-flow graph:
vertices: blocks of instructions without control-flowarcs: jumps and branches
Instruction: defined temps, operation, used temps
t7 ← mul t6, t5
A temp is live while it might still be used
Two temps interfere if they are live simultaneously
non-interfering temps can share registers
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Linear Static Single Assignment (LSSA)
How to model interference of global temps?
start from Static Single Assignment (SSA)decompose global temps into multiple local temps
New invariant: in LSSA all temps are local
→ simple interference model
Input form to the register allocation model
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Linear Static Single Assignment: Factorial
t1, t2 ←t3 ← lit4 ← slti t2← bne t4← t1, t2, t3
t5, t6, t7 ←t8 ← mul t7, t6t9 ← subiu t6← bgtz t9← t5, t8, t9
t10, t11 ←← jr t10← t11
t1 ≡ t5t2 ≡ t6t3 ≡ t7
t1 ≡ t10t3 ≡ t11
t10 ≡ t5t11 ≡ t8
t6 ≡ t9t7 ≡ t8
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1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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Register Assignment
to which register do we assign each temporary t?
rt?
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Register Assignment: Geometric Viewcycle
0
1
2
3
$v0$v1$a0$a1
. . .
. . . $ra
processor registers...
...
...
t
issue of definer(t)
last issue of users(t)
Interfering temps cannot share registers: disjoint2
Global: congruent temps share the same register
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Register Assignment: Example
$v0$v1$a0$a1
. . .
. . . $ra
cycle
0
1
2
3
4
5
in
li
slti
bne
nop
out
t1t2t3
t4
rt1 7→ $ra, rt2 7→ $a0, rt3 7→ $v0, rt4 7→ $v1
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1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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Spilling and Coalescing: Copies
Spilling requires copying temps from/to memory
introduce copy instructions
Copy operations:
register to memory (sw)memory to register (lw)register to register (move)nothing (null)
Copies can be implemented by different operations:
t6 ← {sw, move, null} t3
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Spilling and Coalescing: Factorial with Copies
t1, t2 ←t3 ← lit4 ← slti t2t5 ← {move, sw, null} t2t6 ← {move, sw, null} t3← bne t4← t1, t5, t6 t7, t8, t9 ←
t10 ← {move, lw, null} t8t11 ← {move, lw, null} t9t12 ← mul t11, t10t13 ← subiu t10t14 ← {move, sw, null} t12t15 ← {move, sw, null} t13← bgtz t13← t7, t14, t15t16, t17 ←
t18 ← {move, lw, null} t17← jr t16← t18
t1 ≡ t7t5 ≡ t8t6 ≡ t9t1 ≡ t16
t6 ≡ t17
t16 ≡ t7t17 ≡ t14
t8 ≡ t15t9 ≡ t14
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Spilling and Coalescing: Unified Register File
cycle
0
1
2
3
$v0$v1$a0$a1
. . .
. . . $ra m1 m2 . . .
. . .
...
processor space memory space
. . .
. . .
...
... . . .
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Spilling and Coalescing: Operation Variables
which operation implements each copy instruction i?
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Spilling and Coalescing: Constraints
Operation selection:
The register spaces to which copy temps are allocated aredetermined by the selected operation.
if t6 ← t3 is implemented by sw:
t3 must be assigned to processor registerst6 must be assigned to memory registers
Coalescing:
A copy is implemented by null iff its temps are assignedto the same register.
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Spilling and Coalescing: Example
Block with two copies:
t5 ← null t2t6 ← sw t3
$v0$v1$a0$a1
. . .
. . . $ra m1 m2 . . .
. . .cycle
0
1
2
3
4
5
6
in
li
sw
slti, null
bne
nop
out
t1
t2t3
t4
t5t6
null
sw
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1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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Register Packing
AX BX CXAH AL BH BL CH CL
. . .
. . .
cycle 0
1
t1t2
t3
t4
No model changes required
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1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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Instruction Scheduling
in which cycle is each instruction i issued?
Classic scheduling model:
dependencies among instructions
resource constraints
Connection to register allocation: live ranges
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1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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LSSA Decomposition
Key: congruences are the only link between blocks
rt1 = rt7rt5 = rt8rt6 = rt9rt1 = rt16
rt6 = rt17
rt16 = rt7rt17 = rt14
rt8 = rt15rt9 = rt14
rt1 rt2 rt3
rt4 rt5 rt6
rt7 rt8 rt9
rt10 rt11 rt12
rt13 rt14 rt15
rt16 rt17 rt18
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Solving Strategy
modeler global solver local solver
SSAfunction
LSSAfunction
local problems
local solutions
assemblycode
1 Convert to LSSA form
2 Solve satisfaction problem for global register assignment
3 Solve local optimization problems for each block
minimize makespan
4 Combine local solutions to form a global one
5 Iterate until optimality (or time-out)
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1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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Experiment Setup
86 functions from bzip2 (SPECint 2006 suite)
Selected MIPS32 instructions with LLVM 3.0
Implementation with Gecode 3.7.3
Sequential search on standard desktop machine
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Quality of Generated Code vs. LLVM
1001011021031041051061071081091010
1001011021031041051061071081091010
estimated
cycles
(codegenerator)
estimated cycles (LLVM)
b
b
b
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Solving Time
101
102
103
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105
106
101 102 103 104
averagesolvingtime(m
s)
instructions
b
b
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b b
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1 Introduction
2 Program Representation
3 Constraint ModelRegister AssignmentSpilling and CoalescingRegister PackingInstruction Scheduling
4 Decomposition Solver
5 Results
6 Conclusion
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Conclusion
1 Model unifying:
essential aspects of register allocationinstruction scheduling
→ state-of-the-art code quality
2 Problem decomposition
→ robust generator for thousands of instructions
Key: tailored problem representation (LSSA form)
Lots of future work:
search heuristics, symmetry breaking . . .integration with instruction selectionevaluate for other processors and benchmarks
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