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©Copyright 2005 Cirrus Logic, Inc. SEP 2005EV-2MAN21http://www.cirrus.com
CobraNet™ EV-2
Digital Audio Networking Processor
CobraNet EV-2 Development System Manual
TM
CobraNet™ EV-2
Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, theinformation is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers areadvised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current andcomplete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information,including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under anypatents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization withrespect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for generaldistribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, CobraNet, and DSP Conductor are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a registered trademark of Motorola, Inc.
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CobraNet™ EV-2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Required Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Included: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Not Supplied: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Setup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Switch and Connector Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
J300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8J401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8J700 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8P450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8P501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8P504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8SW200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9SW201-SW204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9SW500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Detailed Description of EV-2 Components . . . . . . . . . . . . . . . . . . . . . . . . . . 11The Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Microcontroller Memory Space: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Microcontroller Port Connections: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Interfacing the Microcontroller to the CM . . . . . . . . . . . . . . . . . . . . . . . . .13Programming the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Interfacing Serial Audio to the CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Functional Discussion of FPGA Operation . . . . . . . . . . . . . . . . . . . . . . . .18
Hex Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21EV-2 Schematics, Page-by-Page Description . . . . . . . . . . . . . . . . . . . . . . . .22
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Microcontroller and Hex Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Connectors and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Optional VCXO and clock buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22AES3 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Power Supply Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Appendix A: Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Appendix B: EV-2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Appendix C: Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Appendix D: EV-2 Schematic Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Appendix E: EV-2 Command Line Interface. . . . . . . . . . . . . . . . . . . . . . . . . . 38
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CobraNet™ EV-2
IntroductionThe EV-2 provides a means of evaluating the CM-1 or CM-2 CobraNet™ Modules and the CirrusLogic CobraNet Silicon Series of devices. In addition to evaluating the CM-1 or CM-2 (hereaftercollectively referred to as the CM except where differences between the CM-1 and CM-2 exist),the user may also use the EV-2 as a development platform and as an example interface for CMs,the Cobranet Silicon Series, and other CobraNet related projects. The EV-2 connects to the CMvia the module's host interface. An 8051-type microcontroller interfaces to the CM's host port,and a simple audio router on the EV-2 allows multiple audio inputs and outputs to connect to theCM's serial audio interface. The EV-2 software provides a simple interface for audio routing onthe EV-2, as well as development support.
Features*:
• Analog audio I/O: Two channels of analog audio input converted to high quality, 24-bit, 48 kHz or 96 kHz digital audio. Two channels of 24-bit, 48 kHz or 96 kHz digital audio con-verted to high quality, analog audio output. Refer to Appendix B for audio I/O specifica-tions.
• Digital audio I/O: One stream of AES3 input and one stream of AES3 output. An AES3 stream is two channels of digital audio. The AES3 input stream is sample rate converted.
• 8051-type microcontroller: 64kB on-chip Flash Program Memory, 1kB internal SRAM, 32kB external SRAM and in-system programmability.
• Field programmability: The supplied EV-2 software provides a means to reprogram EV-2 microcontroller firmware for field upgrades or user development.
• RS232 Interfaces: Two RS232 interfaces, one direct to the CM and another to the micro-controller.
Figure 1. EV-2 Block Diagram
AnalogInput
AnalogOutput
CM
MODULE INTERFACE
VCXO ADC
DAC
AES
LEDs
SRAM
HexSwitches
RS232Interfaces
FPGA
8051
Output Input
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CobraNet™ EV-2
• Routing flexibility: Route from any audio source to any audio sink using the supplied EV-2 software. Route to and from the CM as well as within the EV-2.
• Sine wave generation: A sine wave test tone may be used as an alternate audio source. Minimal frequency and gain control is provided.
• Hex switches: Four hex formatted switches may be used for network identification of the CobraNet module and/or user development.
• Command line interface: The 8051, via its RS232 serial interface, can be used to configure the CM using a command line interface.Cobranet HMI variables can be viewed and modified using this interface. Refer to Appendix E for a description of the Command line interface.
• LED display: Three LED indicators are provided and may be used for user development.
• Power supply: Uses standard computer ATX power supply (not included).
*The EV-2 has gone through a hardware revision to incorporate state-of-the-art A/D and D/Aconverters from Cirrus logic. The new revision board is identified by a “Rev. E” designator.Most of the changes in this document relate to the new converters and their functionality. Anyother changes which differ from the Rev. D board will be identified as such.
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CobraNet™ EV-2
Getting Started
Required Materials
Included:The CobraNet EV-2 Development Package ships with the following materials:
• EV-2 module w/ CM CobraNet PCB Qty. (2)
• 3’ CAT5 crossover cable Qty. (1)
• 6 - Pin Phoenix-style audio connectors Qty. (6)
NOTE: In order to provide you with the latest versions of our firmware and softwaredevelopment kit (SDK), we use web-based distribution for our updates. To obtainthe latest versions of documentation and software, please go towww.cirrus.com/cobranetsoftware.
Not Supplied:• Two (2) ATX computer power supplies with cables are required, one for each EV-2
module. These devices are commonly available at computer retail stores.
• Audio cables.
• RS232 cables. (Not required to pass audio.)
Setup Procedure
• Using the supplied Phoenix connectors, build audio input and output cables and two AES3 cables (if desired). These will be used to connect your audio input and output devices to the EV-2 modules. For analog audio pin assignments, see Figure 2 or Figure 3 below. For AES3 pin assignments, see Figure 4 below.
• Connect a power supply to the ATX Power Connector at P450 on each EV-2 module.
• Connect the CAT5 crossover cable between the Ethernet jacks at J5 on each CM board.
• Connect a stereo audio source to the analog inputs at J300.
• Connect a stereo audio monitor to the analog outputs at J401.
• Apply power to both EV-2 modules.
• Verify that you have established a proper connection. See Table 1 on page 7 for Ethernet connector LED status The LED CR710, if on, indicates that the AES3 receiver does not detect a valid AES3 data input stream. If AES3 I/O is not being used, this can be disre-garded. Otherwise, connect a proper AES3 signal to J700. Note that there must be a valid AES3 input for the AES3 output to work.
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CobraNet™ EV-2
• CR300, when on, indicates an overflow condition detected on the A/D converter.
• The units are now ready to pass audio. The audio input at J300 on one board should now appear at J401 on the other board and vice versa.
Module
CM-1 CM-2
Condition Left LED Right LED Left LED Right LED
Conductor Flashing Green Solid Orange Flashing Orange Flashing Green
Performer Flashing Green Solid Green Solid Orange Flashing Green
Fault Flashing Red Flashing Red Flashing Orange Flashing Orange
Table 1: Ethernet Jack Indicator Legend.
Figure 2. Connector, Switch and Jack Locations
J401Audio Outputs
J300Audio Inputs
P450
ATX Power Connector P504 Serial Bridging
Connector
(+-gnd) (+-gnd)
J5 J6
Ethernet Jacks
Serial MCU Connector
P501
System Reset Switch
SW508
SW200
Programming Switch
J700 AES I/O
gnd - + gnd - + Input Output
CR710 AES LED
Hex SwitchesSW201-4
Power StatuAs
(+-gnd) (+-gnd)
CR300
CobraNet module CM-1 or CM-2
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Switch and Connector Functionality
J300Audio Input Connector: Phoenix-style connector for two-channel balanced audio input,+14.4 dBu maximum (0 dBFS). Refer to Figure 3 for the signal connection.
J401Audio Output Connector: Phoenix-style connector for two-channel balanced audio output,+8.3 dBu maximum (0 dBFS). Refer to Figure 3 for the signal connection.
J700AES3 I/O Connector: Phoenix-style connector for an AES3 stream. Refer to Figure 4 for thesignal connection. For the AES3 tranceiver to operate properly a vailid AES3 signal must beprovided at the AES3 input.
P450ATX power supply connector: ATX power supply is not included with this kit.
P5019-Pin, D-Type Connector: RS232 connection for communicating with the EV-2 microcontrollerusing the supplied routing software or a command line interface ( see Appendix E ). Dataformat is 19200, e, 8, 1.
P5049-Pin, D-Type Connector: RS232 connection to the CM for serial bridging. The default dataformat is 19200 baud, 9-bit format for the CM-1. 9-bit format supports any 8 bit format withparity such as 19200, e, 8, 1. The default data format for the CM-2 is 19200 baud, 8-bitformat.
+ - gnd + - gndRightLeft
Figure 3. Analog Audio Input and Output Phoenix-style Connectors
+ - gndOutput
+ - gndInput
Figure 4. AES3 I/O Phoenix-style Connector
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CobraNet™ EV-2
SW200Programming switch: The EV-2 microcontroller can be programmed via its serial port,connector P501. The supplied software can be used to perform field updates to the board'scode and firmware. This programming capability is initially disabled, but can be enabled bysetting the hex switches to FFF8H and then clicking on the "Hex Switches" display (seeFigure 6 ). For more information about the programming mode, please refer to theProgramming the Microcontroller section.
SW201-SW204Hex switches: SW201-SW204 may be used to uniquely identify the unit on a network. Validsettings fall within the range 0000-FFEF (values FFF0-FFFF are reserved). Changing thesevalues updates the value of the CobraNet module's SNMP variable, sysName, to the currenthex switch value. Through SNMP, the user may query this variable. The SNMP response is ofthe form "PEAK_AUDIO_EVAL-SWwxyz", where the wxyz represents the hex values of theswitches in ASCII format.
SW500System reset switch: This momentary switch resets the EV-2 and attached CM, and initiatescalibration operations for the analog-to-digital converter (ADC) and digital-to-analogconverter (DAC).
SoftwareThe EV-2 is supplied with the CNEval.exe application, which may be used to setup audio routeson the EV-2 (this should not be confused with routing audio over the CobraNet network). TheEV-2 has seven sources of audio input, with each source consisting of a stereo pair of audiochannels. The sources are:
• Four Synchronous Serial Interface (SSI) audio streams from the CM
• An AES3 audio input stream.
• One audio stream from the ADC (Rev. D boards had two audio streams from the ADC)
• A sine wave generator, a stream of two identical 24-bit resolution sine waves.
Using CNEval.exe, the user can route any of these seven source streams to any of the six outputstreams. The available output streams are:
• The four SSI audio streams going to the CM
• One going to the DAC
• One to the AES3 transmitter.
CNEval.exe communicates with the EV-2 via an RS-232 serial connection. CNEval.exe cancommunicate using either COM1 or COM2 of the PC on which it is running. The connection fromcomputer to EV-2 must be made as follows:
• Connect a straight-through, male-to-female, 9-pin RS232 cable to EV-2 connector P501.
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CobraNet™ EV-2
• Select the appropriate PC serial port. The software will attempt to make contact with the EV-2.
• Once communication is established, the routing can then be configured. (See Figure 5 below for an example of a routing scheme.)
The default on power up state of the EV-2 is for the ADC and DAC to be the source and sinkrespectively, using the CM’s SSI #0 I/O stream. The audio is then transmitted/received via aCobraNet Bundle to/from the other CM. This allows evaluation of the CobraNet module in theanalog domain without any configuration.
The EV-2 software also has a programming mode that may be used to perform field updates ofthe EV-2 microcontroller code. For more information about the programming mode, please referto the section Programming the Microcontroller below.
Besides the Route panel, the HMI panel under the Panels menu allows the user to configuresome HMI variables for evaluation purposes. From the HMI panel the user can set receiver andtransmitter bundle assignments as well as changes latency, data format, and sample rate.
The Peek menu provides a means to view HMI variables. In the various panels under Peek,items that are in an indented text field are ones which are read/write. These can not be changedfrom the Peek panels but are there to alert the user that these are variables that could bechanged via SNMP or the Host port.
Figure 5. Screen Shot of EV-2 Software - Audio Routing Interface
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CobraNet™ EV-2
Detailed Description of EV-2 Components
The MicrocontrollerThe microcontroller on the EV-2 is a Philips Semiconductor P89C51RD2. This microcontrollerhas 64 kByte of internal Flash Program Memory and 1 kByte of Static RAM. The microcontrolleris field programmable using the provided CNEval.exe software. The microcontroller's clock rateis 33Mhz. Philips P89C51RD2 preliminary specification for programming information and partusage may be found on the Philips Semiconductor website:http://www.semiconductors.philips.com.
Microcontroller Memory Space:Besides the internal program and data memory space the microcontroller also has anexternal 64k data memory space. The microcontroller is hard-wired to execute from internalFlash Program Memory only. The Flash Program Memory has been segmented to store bothProgram and FPGA configuration data. The Program Memory map is shown in Table 2 onpage 11 and the data memory map is shown in Table 3 on page 11:
*After reset, the FPGA is the only device in the upper 32k of the data memory space. Themicrocontroller is then able to configure the FPGA and once configured the FPGA performsmore sophisticated address decoding of the upper data memory space. Refer to the FPGAsection of this document for a detailed description of the configuration process and a listing ofthe current EV-2 FPGA firmware memory map.
Memory Location Description
0x0000-0xBFFF Program Memory
0xC000-0xFFFF FPGA Configuration Data
Table 2: Flash Program Memory Map
Memory Location Description
0x0000- 0x02FF Internal Static RAM
0x0300-0x7FFF External Static RAM
0x8000-0x87FF Unused
0x8800 FPGA express mode con-figuration*
0x8801-0xFFFF Unused
Table 3: Microcontroller Data Memory Map After Reset but Before FPGA Configuration
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CobraNet™ EV-2
Microcontroller Port Connections:Port 0: used for the address/data (AD) bus. Once configured, the FPGA latches the loweraddress byte from the AD lines.
Port 1: used for several purposes as shown in Table 4 on page 12.
Port 2: upper address bus. Port 2 is output only.
Bit # Name of Signal I/O Description
0 INIT_IO# I Used when configuring the FPGA. Refer to Xilinx Spartan datasheet for more detail.
1 PROGRAM# O Used to initiate the FPGA configu-ration. Refer to Xilinx Spartan datasheet for more detail.
2 MUTE# I Mute signal from the CM module
3 HEX_DATA_IN O Not used. May be used to concat-enate settings from other hex switches.
4 HEX_CLOCK O Used to latch the hex switch val-ues into a serial shift register.
5 HEX_SHIFT O Used to shift the hex switch values from the serial shift register.
6 HEX_DATA_OUT O The hex switch value from the serial shift register appears at this input.
7 MCU_P17 O This is used for communication between the FPGA and MCU.
Table 4: Port 1 Signal Descriptions
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CobraNet™ EV-2
Port 3: See Table 5 on page 13.
Interfacing the Microcontroller to the CMPlease refer to the EV-2 schematic, found in Appendix D for information regarding interfacingto the CM.
The CM has a host interface that allows a host processor (such as an 8051 microcontroller)to interface to the DSP on the CM. From a hardware perspective the interface to the CM-1and CM-2 is almost the same,. The host interface signals are a data strobe signal, HDS#; aread/write line, HRW, an 8-bit bi-directional data bus, HD0-HD7, and three address lines,HA0-HA2 on the CM-1 and four address lines, HA0-HA3 on the CM-2. The HEN# line hasbeen configured by the CobraNet software to be ignored or seen as a logic low. Given thishost configuration, the interface of the microcontroller to the CM host port is straightforward.In addition to the above signals there are two more, HACK# and HREQ# which can be usedas flags to indicate a state change on the CM.
With regard to the CM-1 which uses a Motorola DSP56303, care must be taken with thetiming of HDS# and HWR. Motorola's timing specifications for the DSP56303 host port in anon-multiplexed, single data strobe mode requires a set up time from the falling edge ofHWR# to the falling edge of HDS# of 4.7ns and the hold time from the rising edge of HDS# tothe rising edge of HWR# of 3.3ns. The pulse of the HDS# signal must be wholly within thepulse of the HWR# signal with the constraints stated above. Please refer to Motorola'sDSP56303 Technical Data sheet for complete information regarding timing and interfaceissues. This is available for download from the Motorola web site athttp://www.freescale.com.
Bit # Name of Signal I/O Description
0 RXD I RS232 serial port receive signal.
1 TXD O RS232 serial port transmit signal
2 HREQ# O Connected to the CM module host request signal. See CobraNet Technical Datasheet for a com-plete description of this signal.
3 HACK# I Connected to the CM module host acknowledge signal. See Cobra-Net Technical Datasheet for a complete description of this signal. May be used as an interrupt request on the microcontroller.
4 Watchdog I Watchdog signal from the CM
5 MCU_P35 I/O Connected to SCI_CLK via the FPGA. Also used to detect sample rate.
6 WR# O Microcontroller write signal.
7 RD# O Microcontroller read signal.
Table 5: Port 3 Signal Descriptions
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CobraNet™ EV-2
In the EV-2 application, the host address lines are generated by the address latch in theFPGA (see Table 6 on page 16) and the host data bus is connected directly to the data bus ofthe microcontroller. The HREQ# and HACK# signals are connected to the two interrupt inputsof the microcontroller. These signals may be used for data handshaking and asynchronusnotification respectively.
The final host signal, HRESET#, resets the CM when asserted low. Setting a bit in the hostreset register (see Table 6 on page 16) controls this signal. See the discussion of the FPGAbelow for more information about this signal.
Supplemental information regarding the CM Host interface may by found in the section titled"Host Management Interface" in the CS1810xx data sheet available on the Cirrus Logicwebsite: www. cirrus.com.
Programming the MicrocontrollerThe EV-2 is designed so that field updates of both the microcontroller firmware and the FPGAfirmware are possible. If only the efficacy and performance of the CobraNet paradigm isbeing evaluated, reprogramming of the microcontroller is not required. However, use of thefield program capability may aid in the design of a CobraNet based product.
Modifying the Flash Program Memory of the microcontroller constitutes the update.
The programming instructions that follow pertain to the supplied EV-2 routing/programmingsoftware, CNEval.exe. Programming the microcontroller is a multi-stage process:
1. Install the EV-2 CNEval.exe software on your Windows-based computer.
2. Install an RS232 cable from port 1 or 2 on your PC to P501, the 9-pin D-type connec-tor closest to the center of the board.
3. Run CNEval.exe
4. Change the hex switches (SW201-SW204) to FFF8 (as viewed when looking at the hex switches). You may, as an alternative, click in the narrow recessed panel on the left of the upper status bar.
5. Select "Program" from the Utility menu in CNEval.exe.
6. From the “Serial” drop-down menu select a serial connection, either port COM1 or COM2 based on which is connected.
7. Located near the two serial RS232 connectors is a switch, SW200. This switch must be set to the program mode position. The program position is indicated by silk screen on the EV-2 board.
8. Push switch SW508, the momentary reset switch. SW508 is located just behind the hex switches.
9. Select which firmware to update, either the FPGA or the 8051.
10. Wait for programming to complete. Do not interrupt the programming process!
11. Once programming has completed for the microcontroller or the FPGA firmware, return the programming switch, SW200, to the normal operation position and press the reset switch, SW508.
12. Click OK to return to the main window in CNEval.exe.
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CobraNet™ EV-2
Interfacing Serial Audio to the CMIn general, interfacing to most off-the-shelf A/D and D/A converters is straightforward and the CMis no exception. Most signals for a direct connection to these as well as other audio ICs such asthe CS8420 AES3 transceiver, are available on the CM module interface connector. Mostconverters provide for a choice of bit clock and sample (frame) clock polarity, as well as audiodata formats such as SPI™ or I2S.
The A/D converter, a Cirrus Logic CS5381 is configured for slave operation, which means that itrequires a bit clock and a sample (frame) clock input. The master, bit and sample clocks aredirect connections from FS512, SCK and FS1 respectively, as is the data stream which comesfrom one of the SSI ports. The CM can be configured to clock data from either edge of the bitclock, as well as allowing for specifying the polarity of the sample clock. (See the CobraNetwebsite and the CobraNet Technology Datasheet for more information.) This is important sincethe CS5396 works with sample pairs which need to be phase aligned. The polarity of the sampleclock specifies this alignment. For the EV-2 application, the SSI ports of the CM have beenprogrammed to send two channels per port. This allows a straightforward connection without anydemultiplexing.
The connection to the Cirrus Logic CS4398 D/A converter is similarly straightforward. Like theSCS5381, it uses the FS512, bit clock and sample clock directly from the CM. Data to the DACand from the ADC are also direct except that they pass through a selector circuit in the FPGA. Ifa particular design does not include multiple sources of audio, then the connection can be directto the CM interface connector.
FPGAThe Field Programmable Logic Array is a Xilinx Spartan(tm) XCS10XLVQ100-4. It is mapped intothe microcontroller's memory space. The microcontroller must configure the FPGA after poweron or reset. Express mode configuration is used for this part. Refer to the Xilinx Spartan(tm) XLfamily data sheet for more information on the Express mode configuration operation. This datasheet can be found at the Xilinx web site, http://www.xilinx.com/. The address for configuration is0x8800. Once configured, the FPGA's two main functions are to decode the microcontroller'saddress signals and to route audio from a user selected source to a user selected destination.Secondary functions are to generate a sine wave signal and implement registers whose functionare mostly of a control nature. A discussion of the memory decoding, routing, sine wavegeneration and other functions follow.
The memory map of the upper 32k of the microcontroller space after configuration, is shown inTable 6 on page 16. Most bit-defined locations use the least significant microcontroller data bussignal AD0 as the controlling bit. Other data bits are ignored on these registers. Power on andreset default for all registers is 0 unless specified otherwise.
15 Rev. 2.1
CobraNet™ EV-2
Memory Location R/W Description
0x8000 W Bit register for green LED, CR903. 0=LED on, 1=LED off. Refer to Table 10 on page 20 for this and other LED regis-ters.
0x8001 W Bit register for red LED, CR904. 0=LED on, 1=LED off.
0x8002 W Bit register for yellow LED, CR905. 0=LED on, 1=LED off.
0x8004 W Bit register for green LED blink control. 0=blink off, 1=blink on.
0x8005 W Bit register for green LED blink control. 0=blink off, 1=blink on.
0x8006 W Bit register for green LED blink control. 0=blink off, 1=blink on.
0x8008 W DAC audio routing address (see Table 7 on page 18).
0x8009 W Bit register for DAC mute signal. 0=mute on, 1=mute off.
0x800A W Bit register for sample rate mode. 0=48k, 1=96k. Note: use AD1 instead of AD0
0x800B W Bit register for DAC reset signal. 0=reset on, 1=reset off.
0x8010 R Audio Calibration Status. 1=Calibrating, 0=Ready. See the Calibrating Audio section for details.
0x8010 W Manual ADC Calibration. 0=Normal, 1=Calibrate. See the Calibrating the ADC section for details. (Rev. D applicable only)
0x8011 W Bit register for ADC slave/master control. 0=Slave, 1=Mas-ter. (Rev. D applicable only)
0x8012 W ADC high pass filter (HPF) select. 0=Enabled, 1=Disabled.
0x8018 W AES3 audio routing address (see Table 7 on page 18).
0x8019 W Bit register for AES3 mute signal. 0=AES output muted, 1=Unmuted.
0x8020 W SSI 0 audio routing address (see Table 7 on page 18).
0x8021 W Bit register for SSI 0 mute signal. 0=Muted, 1=Unmuted.
0x8028 W SSI 1 audio routing address (see Table 7 on page 18).
0x8029 W Bit register for SSI 1 mute signal. 0=Muted, 1=Unmuted.
Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration
Rev. 2.1 16
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Note 1: The FPGA only decodes this address. The actual register is located on the CM. See theMotorola DSP56303 users manual or the CS18101 manual for a discussion of each of these hostport registers.
0x8030 W SSI 2 audio routing address (Table 7 on page 18).
0x8031 W Bit register for SSI 2 mute signal. 0=Muted, 1=Unmuted.
0x8038 W SSI 3 audio routing address (Table 7 on page 18).
0x8039 W Bit register for SSI 3 mute signal. 0=Muted, 1=Unmuted.
0x8040 Note 1 CM-1 Host Port ICR register. CM-2 Message-A register.
0x8041 Note 1 CM-1 Host Port CVR register. CM-2 Message-B register.
0x8042 Note 1 CM-1 Host Port ISR register. CM-2 Message-C register.
0x8043 Note 1 CM-1 Host Port IVR register. CM-2 Message-D register.
0x8044 Note 1 CM-1: Unused. CM-2 Data-A register.
0x8045 Note 1 CM-1 Host Port Data register high. CM-2 Data-B register.
0x8046 Note 1 CM-1 Host Port Data register middle. CM-2 Data-C register.
0x8047 Note 1 CM-1 Host Port Data register low. CM-2 Data-D register.
0x8048 Note 1 CM-2 Host Control Register.
0x8049 Note1 CM-2 Host Status Register.
0x8051 W Bit register for Host reset signal. 0=Asserted, 1=Deas-serted.
0x8052 W Bit register for Host interface mode. 0=Motorola, 1=Intel
0x8054 W Signal MCU_P35 is either SCI_CLK from the CM or FS1 from the CM. 0=SCI_CLK, 1=FS1.
0x8058 R/W Auxiliary lines. Not used, for test purposes only.
0x8060 R FPGA configuration major version.
0x8061 R FPGA configuration minor version.
0x8062 R FPGA configuration revision number.
0x8070 R/W Sinewave Gain register. See Table 9 on page 19.
0x8078 R/W Sinewave Frequency register. See Table 8 on page 19.
Memory Location R/W Description
Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration
17 Rev. 2.1
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Configuring the FPGAThe FPGA is configured from data that is stored in the upper 16kbytes (0xC000-0xFFFF) ofthe microcontroller’s Flash Program Memory. The microncontroller code for configuring theFPGA uses express mode which writes byte-wide data to the FPGA. Refer to the XilinxSpartan XL family data sheet for more information on the express mode configurationoperation. The address used for writing configuration data is 0x8800.
Functional Discussion of FPGA Operation
Routing of Audio Data
The routing of audio data is achieved by a simple 8 to 1 multiplexing operation; for each audio destination three data bits in an a register in the FPGA select the source. For example, the three data bits in the D/A audio routing register determine which audio source is selected to appear at the analog outputs (J401). Table 7 on page 18 shows the definition of the data bits and the respective audio source.
microcontroller data bitAD2 AD1 AD0 Audio Source
0 0 0 CM SSI 0
0 0 1 CM SSI 1
0 1 0 CM SSI 2
0 1 1 CM SSI 3
1 0 0 ADC
1 0 1 AES3 Input
1 1 0 ADC (low latency, Rev D only)Otherwise same as ADC above.
1 1 1 Sine wave
Table 7: Definition of Audio Routing Register Bits
Rev. 2.1 18
CobraNet™ EV-2
Sine Wave Generator
The FPGA contains a 32-sample, 24-bit, sine table. The table is stepped through at the sample clock rate so the resulting fundamental frequency is 48kHz / 32 samples = 1500Hz and 3000Hz at 96kHz. Limited control over frequency and gain is provided. Listed below are the values to write to the frequency and gain registers in the FPGA.
Frequency register data bits
AD3 AD2 AD1 AD0
Frequency48kHz sample rate
(96kHz sample rate)
0 0 0 1 1.5 kHz (3.0 kHz)
0 0 1 0 3.0 kHz (6.0 kHz)
0 0 1 1 4.5 kHz (9.0 kHz)
0 1 0 0 6.0 kHz (12.0 kHz)
0 1 0 1 7.5 kHz (15.0 kHz)
0 1 1 0 9.0 kHz (18.0 kHz)
0 1 1 1 10.5 kHz (21.0 kHz)
1 0 0 0 12.0 kHz (24.0 kHz)
Table 8: Sine Wave Frequency Register Bit Definitions
Gain register data bitsAD1 AD0 Gain
0 0 0dB
0 1 -6dB
1 0 -12dB
1 1 -18dB
Table 9: Sine Wave Gain Register Bit Definitions
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CobraNet™ EV-2
LED Control
There are two bit registers to control the state of each of three LEDs. The mapping of control bits to LED behavior is described in Table 10 on page 20. The data bit is always AD0. Note that blink overrides on/off but when blink is turned off the LED will go to the state designated by the On/Off bit.
Calibrating the ADC
There is a ten-second warm-up time to allow both the ADC and DAC to settle. All audio is muted during this 10-second warm-up. This warm-up cycle only takes place on system reset which is initiated by either power-up or a user pushing the reset button (SW508).
Version Control
The FPGA contains three hardwired eight-bit registers that contain an ASCII version number of the FPGA configuration file. The microcontroller reads these registers for version control and reporting purposes.
Mute Control
Muting comes from three different sources 1) the microcontroller can mute or unmute audio by writing to a bit control register. There is one mute bit control register for each output audio path, 2) the CM asserts its mute signal, and 3) all audio is unconditionally muted during a power on/reset warm-up cycle.
On/Off Blink Status
0 0 off
1 0 on
0 1 blink
1 1 blink
Table 10: LED Status
Rev. 2.1 20
CobraNet™ EV-2
Hex SwitchesFour pins on the 8051 allow the hex switches to be read. The EV-2 circuitry associated with thehex switches serves as an example implementing this common CobraNet feature (seeRecommended User Interface Practices section in the CobraNet Programmer’s Manual for adiscussion of use of this scheme). Requirements include a physical (hardware) mapping of thehex switches to a code (software) within the CM. Some of the requirements to achieve this arelisted below:
1. Two of the four signals will be control signals: a Shift/Load# signal where Shift is high and Load is Low. The Load allows for parallel, asynchronous loading of the hex switch data into a shift register and the Shift allows for serial shifting of data out of that regis-ter. A clock signal to perform the shifting operation where data changes on the rising end of the clock. The 74HC165 IC is an example of a part that supports this protocol.
2. The other two signals are the shifted data output and an input that will be shifted seri-ally into the shift register concatenating it with the hex data. The intent of this latter signal is to allow for the possibility of concatenating other data, additonal hex switches or otherwise, for application specific enhancements.
3. The software will convert the serial hex data stream to a four-byte ASCII value that represents the switch settings.
As shown in Figure 6, viewing hex switches from the front, the given switch positions would readas "CA30" in a software query of the hex switch setting. On the EV-2, the microcontoller isresponsible for reading the switches through the hardware serial interface and converting thosereadings to an ASCII representation. This representation is then written to the CM through thehost port. Specifically, the EV-2 microcontroller updates the CM's HMI variable, sysName. UsingSNMP, the user may query this variable. The SNMP response is of the form"PEAK_AUDIO_EVAL-SWwxyz", where the wxyz represents the hex values of the switches inASCII format. In the example shown in Figure 6, a query of sysName would return"PEAK_AUDIO_EVAL_SWCA30".
Figure 6. Example Switch Setting
21 Rev. 2.1
CobraNet™ EV-2
EV-2 Schematics, Page-by-Page DescriptionThe following sections provide detailed descriptions of the EV-2 schematic drawings contained inAppendix D.
Block DiagramThis page is a hierarchical block diagram showing an overview of all schematic pages andinterconnects between pages.
Microcontroller and Hex SwitchesThis page shows an 8051-type microcontroller, its connections, and peripherals. Peripheralsinclude 32kbytes of SRAM, hex switch interface, clock oscillator and programming switch.
A/D ConverterThis circuit is based on the Cirrus Logic CS5381 reference design. See the Cirrus Logicwebsite, http://www.cirrus.com, for a detailed description of the CS5381, its developmentsystem, the CDB5381, and reference design, the CRD5381.
D/A ConverterThis circuit is based on the Cirrus Logic CS4398 reference design. See the Cirrus Logicwebsite, http://www.cirrus.com, for a detailed description of the CS4398 and its developmentsystem, CDB4398. The CS4398 in the EV-2 design runs in stand-alone mode.
Connectors and InterfacesThis page shows the CM interface connectors, P510 and P511, as well as the RS232interface. The reset switch circuit, SW508 and associated components are also included onthis page.
Optional VCXO and clock buffersAlthough the CM produces a high quality master clock, in some applications, the masterclock my be compromised by long or noisy signal paths (i.e. ribbon cable connection). Anoptional VCXO circuit is included as an example of re-clocking the master clock (FS512) toattenuate jitter. The VCXO is not installed on the current EV-2 board. Clock buffers are usedto recondition the clock from the CM.
AES3 TransceiverThis circuit uses the Cirrus Logic CS8420 AES3 Transceiver. See the Cirrus Logic website,http://www.cirrus.com, for a detailed description of the CS8420 as well as the evaluationboard, the CDB8420. The CS8420 runs in AES3 transceiver mode with input sample rateconversion. For the AES3 tranceiver to operate properly, a valid AES3 signal must beprovided at the AES3 input.
Power Supply ConditioningThe main power connector is a standard ATX connector. The voltage mains are conditioned,as well as protected with transient voltage suppressor diodes. Numerous voltage regulatorsare used to filter and condition the power supplied to the analog audio section.
FPGAThis page shows the connections to the FPGA, which is a Xilinx XCS10XL-4VQ100 IC. Seethe FPGA discussion above for a detailed description of its functionality.
Rev. 2.1 22
CobraNet™ EV-2
Appendix A: Definition of TermsThis Appendix contains brief definitions of many of the terms used in the discussion of CobraNetand CobraNet networks.
Audio ChannelA single audio signal. Audio channels on CobraNet have a 48KHz sampling rate and may be16, 20 or 24 bit resolution. Multiple audio channels may be carried in a Bundle.
Audio StreamTwo audio signals, i..e. a stereo pair. Audio on the EV-2 is routed in streams. This isequivalent to the SSI data of the CM when in 16 channel mode, i.e. two channels per SSI.
Broadcast Addressing Broadcasting is a special case of Multicasting (see multicast below). Whereas it is possible,in some cases, to indicate intended recipients of multicast data, broadcast data isunconditionally received by all DTEs within a network domain.
BundleThe basic network transmission unit under CobraNet. Up to 8 audio channels may be carriedin a Bundle.
Category 5 Cable (CAT5)CAT5 is inexpensive unshielded twisted pair (UTP) data grade cable. It is very similar toubiquitous telephone cable but the pairs are more tightly twisted. CAT5 cable runs forEthernet are limited to 100 meters due to signal radiation and attenuation considerations. ACAT5 run in excess of 100 meters may be overly sensitive to electromagnetic interference(EMI). It should be noted that not all CAT5 cable is UTP. Shielded CAT5 also exists but is raredue to its greater cost and a much shorter distance limitations than UTP CAT5.
CobraNetCobraNet is a combination of hardware, software and protocol allowing distribution of manychannels of digital audio over Fast Ethernet. CobraNet supports switched and repeaterEthernet networks. On a repeater network, CobraNet eliminates collisions and allows fullbandwidth utilization of the network. CobraNet uses standard Ethernet packet structure andnetwork infrastructure.
CobraNet DeviceA device in compliance with the CobraNet specification for transmission and/or reception ofdigital audio and associated sample clock.
ConductorCobraNet Device on the network supplying master clock. A conductor arbitration procedureinsures that, at any time, there is one and only one conductor per network.
Crossover CableA crossover cable can be used to directly connect two network devices.
DTEShort for Data Terminal Equipment, a DTE is any network device that produces or consumesdata. A CobraNet Device is a DTE.
23 Rev. 2.1
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EthernetA Local Area Network (LAN) technology that allows transmission of information betweencomputers. Ethernet is, by far, the most widely deployed LAN standard worldwide.
Fast EthernetA newer version of Ethernet, also known as 100BASE-T. It supports data transfer rates of100Mbps. CobraNet operates on a Fast Ethernet network.
Full DuplexData can be transmitted and received simultaneously.
Half DuplexData can only be transmitted in one direction at a time.
HubHub is not a technically concise term. The term can be used to refer to either a Repeater Hubor a Switching Hub.
MbpsShort for megabits per second, it is a measure of data transfer speed.
Multicast AddressingData which is Multicast is addressed to a group of, or all DTEs on a network. All DTEs receivemulticast addressed data and decide individually whether the data is relevant to them. ASwitched Hub is typically not able to determine appropriate destination port or ports formulticast data and thus must send the data out all ports simultaneously just as a RepeaterHub does. Multicast addressing is to be avoided when possible since it uses bandwidthnetwork wide and since all DTEs are burdened with having to decide whether multicast datais relevant to them.
Multicast BundleA multicast Bundle supports a one-to-many routing of audio on the network. Ethernetmulticast addressing is used to deliver a multicast Bundle. Because a multicast bundleconsumes bandwidth network-wide, use of this delivery service must be rationed on aswitched network.
Network TopologyThe physical and logical relationship of nodes in a network; i.e., a star, ring, tree, bus, etc.
NodeA processing location. A node can be a computer, a switch, a CobraNet device, or any otherdevice that has a unique network address.
Repeater HubAn Ethernet multi-port repeater. A data signal arriving in any port is electrically regeneratedand reproduced out all other ports on the hub. An Ethernet network is typically wired in a starconfiguration and the hub is at the center. The use of hubs requires that all devices on thenetwork run in half duplex mode.
Run LengthEach type of media has a limitation in the length of a point-to-point run between two devices.When maximum run length guidelines are exceeded it may not be possible to establish a
Rev. 2.1 24
CobraNet™ EV-2
valid network connection or data may be corrupted. Longer distances can be achieved byupgrading the media or using multiple runs in series.
Switch/Switching HubA Switch examines addressing fields on data arriving at each port and attempts to direct thedata out the port or ports to which the data is addressed. Data may be buffered within theSwitching Hub to avoid the collision condition that may be experienced within a RepeaterHub. A network utilizing Switching Hubs realizes higher overall bandwidth capacity as datamay be received through multiple ports simultaneously without conflict. Switches arefull-duplex devices. A network utilizing switches to connect network segments is referred toas a switched network.
Unicast AddressingData which is unicast is addressed to a specific DTE. A Switching Hub may examine theunicast address field of the data and determine on which port the addressed DTE resides anddirect the data only to that port. Delivery of an e-mail message is an example of unicast dataaddressing.
Unicast BundleA unicast Bundle supports a one-to-one routing of audio on the network. Ethernet unicastaddressing is used to deliver a Unicast Bundle. Because unicast addressing is friendly toEthernet switches, unicast Bundles should be used for audio delivery whenever possible.
Unregulated TrafficRefers to any data transmitted onto a network by non-CobraNet devices. Unregulated trafficis particularly offensive on a repeater network as it interferes with CobraNet's collisionavoidance mechanism and can result in audio dropouts. On a switched network, unregulatedtraffic is only a problem if it appears in such copious quantity as to overload the network.
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Appendix B: EV-2 SpecificationsA/D: Cirrus Logic CS5381
AUDIO SPECIFICATIONS:
• Two input channels.
• Frequency Response (-1 dB from a full-scale 1 kHz sine wave input):
20 Hz to 20 kHz, +-0.1 dB, 48kHz sample rate20 Hz to 40 kHz, +0.1, -4 dB, 96kHz sample rate
• Total Harmonic Distortion plus noise ( full-scale 1k Hz sine wave input ):
< -114 dB, 48kHz sample rate< -110 dB, 96kHz sample rate
• Dynamic Range (-60 dB from a full-scale 1kHz sine wave input, unweighted):
> 115 dB, 48kHz sample rate> 110 dB, 96kHz sample rate
• Maximum Input Level: +8.3dBu, balanced differential.
• Input Impedance: 20 k Ohms balanced.
DIGITAL SPECIFICATIONS
• A/D quantization: 24-bit resolution.
• Audio Sampling Rate: 48kHz or 96kHz
CONNECTOR: 6-Pin Phoenix-type connector.
Digital I/O: Cirrus Logic CS8420-CS
• AES3 input and output. Input is sample rate converted.
CONNECTOR: 6-Pin Phoenix-type connector.
OTHER SPECIFICATIONS
• Power Consumption: <10 W (includes CM)
• Power Connector: Uses standard ATX power supply connector (ATX power supply not included).
• RS232 Connection: Non-standard (RX/TX only) EIA-RS232C connection with auto loop back. Connectors are 9-pin D-types.
Rev. 2.1 26
CobraNet™ EV-2
D/A: Cirrus Logic CS4398
AUDIO SPECIFICATIONS:
• Two output channels.
• Frequency Response (-1 dB from a full-scale 1 kHz sine wave input):
20 Hz to 20 kHz, +-0.1 dB, 48kHz sample rate20 Hz to 40 kHz, +0.1dB, -10 dB, 96k sample rate
• Total Harmonic Distortion plus noise ( full-scale 1k Hz sine wave input ):
< -106 dB, 48kHz and 96k sample rates
• Dynamic Range (-60 dB from a full-scale 1kHz sine wave input, unweighted):
> 112 dB, 48kHz and 96k sample rates
• Maximum Output Level: +9.75 dBu balanced differential.
• Output Impedance: 200 Ohms
DIGITAL SPECIFICATIONS
• D/A quantization: 24-bit resolution
• Audio Sampling Rate: 48kHz and 96kHz
CONNECTOR: 6-Pin Phoenix-type connector.
27 Rev. 2.1
CobraNet™ EV-2
Appendix C: Other ResourcesA comprehensive array of CobraNet information can be accessed at the Cirrus Logic publicwebsite. Among the resources available are: FAQs, white papers, datasheets, programmer’sguides, network design guidelines, common network terminology, a listing of recommended andtested Ethernet equipment and set-up information for selected Ethernet switches.
The main URL for this site is: http://www.cirrus.com.
A developer’s website containing more in-depth technical information is also maintained whichtargets primarily CobraNet manufacturers and those considering integrating CobraNet into theirproducts.
Access to the developer’s website is granted subject to execution of a Non-disclosure Agreement(NDA). Please contact your local Cirrus Logic sales office or distributor for further details.
The public CobraNet website can be found at: http://www.cirrus.com/en/products/pro/areas/netaudio.html.
The latest documentation and software for CobraNet products can be found at:http://www.cirrus.com/cobranetsoftware.
Rev. 2.1 28
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SE
T#
AE
S_D
OU
TA
ES
_B
CL
KA
ES
_W
CL
K
AE
S_D
IN
EN
_96K
#E
N_96K
FS
512_O
UT
AE
S I
/OE
V2_A
ES
.Sch
MR
ES
ET
#
EN
_96K
#
AE
S_D
IN
AE
S_D
INA
ES
_D
OU
T
AE
S_D
OU
T
AU
X_P
OW
ER
[0..3]
SC
I_C
LK
Pow
erE
V2_pw
r.sc
h
AE
S_F
S1
AE
S_B
CL
K
AE
S_F
S1
AE
S_B
CL
K
EN
_96K
AD
[0..7]
WR
#P
RO
GR
AM
#IN
IT_IO
#
HP
F#
AU
X_P
OW
ER
[0..3]
AL
E
SC
I_C
LK
A[8
..15]
RS
VD
[1..4]
SS
I_D
OU
T[0
..3]
SS
I_D
IN[0
..3]
AD
_D
AT
A1
DA
_D
AT
A
AE
S_D
INA
ES
_D
OU
T
MU
TE
#
RD
#
HC
S#
HE
N#
DA
_R
ES
ET
#
HR
ES
ET
#
MC
U_P
35
FS
512_C
LK
FS
1_O
UT
MC
U_C
LK
AE
S_B
CL
K
HW
R#
A[0
..7]
AD
DR
3A
D_R
ES
ET
#
DA
_C
DO
UT
DA
_C
CL
KD
A_C
S#
MC
U_P
17
EN
_96K
EN
_96K
#
CN
EV
_F
PG
AE
V2_F
PG
A.S
chA
D[0
..7]
RX
DT
XD
WR
#
AL
EA
LE
A[8
..15]
RD
#
RD
#
PR
OG
RA
M#
INIT
_IO
#
INIT
_IO
#P
RO
GR
AM
#
A[8
..15]
MU
TE
#
MC
U_P
35
MC
U_P
35
RS
VD
[1..4]
FS
512_C
LK
FS
1_O
UT
MC
U_C
LK
RX
D
AE
S_B
CL
K
HW
R#
A[0
..7]
A[0
..7]
MC
LK
AD
DR
3
AD
DR
3
EN
_96K
AD
_R
ES
ET
#
AD
_R
ES
ET
#
EN
_96K
MC
U_C
LK
MC
LK
FS
512_O
UT
DA
_C
CL
K
DA
_C
DO
UT
DA
_C
S#
DA
_C
CL
KD
A_C
DO
UT
DA
_C
S#
MC
U_P
17
MC
U_P
17
EN
_96K
EN
_96K
#
FS
512_O
UT
SS
I_C
LK
_IN
SS
I_C
LK
_IN
FS
1_IN
FS
1_IN
Appendix D: EV-2 Schematic Drawings
29 Rev. 2.1
CobraNet™ EV-2
12
34
ABCD
43
21
D C B A
Cob
raN
et (
TM
) E
valu
ati
on
Board
- M
PC
, S
RA
M a
nd
Hex
Sw
itch
es E
2500 5
5th
Str
eet
Su
ite
210
Tit
le:
Fil
e:E
V2_8051.S
ch2
919-O
ct-2
004
Dat
e:S
hee
tof
Engin
eer:
Bil
l L
ow
e
ww
w.p
eakau
dio
.com
w
ww
.cir
rus.
com
Siz
e:N
um
ber
:R
evis
ion:
ACir
rus
Lo
gic
, In
c.B
ou
lder
, C
O 8
0301
AD
0A
D1
AD
2A
D3
AD
4A
D5
AD
6A
D7
AL
E
WR
#
RD
#
TX
DR
XD
WA
TC
HD
OG
HR
EQ
#
MR
ES
ET
HA
CK
#
MU
TE
#
MR
ES
ET
MU
TE
#
GN
D
+5V
B200
.1S
C221
10A
20S
Sel
ect
pro
gra
mm
ing m
ode.
SK
T200
SO
CK
ET
40
RX
DT
XD
HR
EQ
#A
D[0
..7]
AD
[0..7]
HA
CK
#W
AT
CH
DO
G
TP
200
TP
S
P1.0
1
P1.1
2
P1.2
3
P1.3
4
P1.4
5
P1.5
6
P1.6
7
P1.7
8
RS
T9
RX
D/P
3.0
10
TX
D/P
3.1
11
INT
R0/P
3.2
12
INT
R1/P
3.3
13
TIM
ER
0/P
3.4
14
TIM
ER
1/P
3.5
15
WR
/P3.6
16
RD
/P3.7
17
XT
AL
218
XT
AL
119
EA
31
AL
E30
PS
EN
29
P0.0
(AD
0)
39
P0.1
(AD
1)
38
P0.2
(AD
2)
37
P0.3
(AD
3)
36
P0.4
(AD
4)
35
P0.5
(AD
5)
34
P0.6
(AD
6)
33
P0.7
(AD
7)
32
P2.0
(A8)
21
P2.1
(A9)
22
P2.2
(A10)
23
P2.3
(A11)
24
P2.4
(A12)
25
P2.5
(A13)
26
P2.6
(A14)
27
P2.7
(A15)
28
U200
MC
U8051
+5V
GN
D
TP
201
TP
G
GN
D
PS
EN
#
PS
EN
#G
ND
A14
10
A13
9A
12
8A
11
7A
10
6A
95
A8
4A
73
A3
25
A2
24
A0
21
A1
23
A6
2
CE
20
OE
22
WE
27
A5
1
D0
11
D1
12
D2
13
D3
15
D4
16
D5
17
D6
18
D7
19
A4
26
U204
7C
199-1
2
AD
0A
D1
AD
2A
D3
AD
4
AD
5A
D6
AD
7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A8
A9
A10
A11
A12
A13
A14
A15 R
200
10K
P1S
+5V
WR
#R
D#
+5V
WR
#
OU
T3
GN
D2
VC
C4
U210
33M
HZ
OS
C
+5V
GN
D
GN
D
+5V
B204
.1S
B210
.1S
INIT
_IO
#IN
IT_IO
#P
RO
GR
AM
#P
RO
GR
AM
#
HE
X_D
AT
A_O
UT
HE
X_D
AT
A_IN
HE
X_C
LO
CK
HE
X_S
HIF
T
C13
B12
D14
SE
R10
A11
CL
K I
NH
15
SH
/LD
1
CL
K2
E3
F4
G5
H6
QH
7
QH
9
U201
74H
C165
C13
B12
D14
SE
R10
A11
CL
K I
NH
15
SH
/LD
1
CL
K2
E3
F4
G5
H6
QH
7
QH
9
U202
74H
C165
GN
D
GN
D
+5V
B201
.1S
GN
D
+5V
B202
.1S
R201
10K
P1S
+5V
AL
E
RD
#
A[8
..15]
A[8
..15]
MC
U_P
35
MC
U_P
35
11
43
22
C5
84
SW
202
BC
H S
W3
11
43
22
C5
84
SW
201
BC
H S
W3
11
43
22
C5
84
SW
204
BC
H S
W3
11
43
22
C5
84
SW
203
BC
H S
W3
10
2345678
1
9
R206
10K
SIP
10
2345678
1
9
R205
10K
SIP
A[0
..7]
A[0
..7]
GN
D
R203
10K
P1S
+5V
MC
U_C
LK
MC
U_C
LK
MC
U_P
17
MC
U_P
17
GN
D
1 234
= O
N
SW
200
DIP
SW
1_S
PD
T
R204
10K
P1S
+5V
R202
51.1
P1S
Rev. 2.1 30
CobraNet™ EV-2
12
34
ABCD
43
21
D C B A
Cob
raN
et (
TM
) E
valu
ati
on
Board
-
AD
C
E
2500 5
5th
Str
eet
Su
ite
210
Tit
le:
Fil
e:E
V2_A
D.S
ch3
919-O
ct-2
004
Dat
e:S
hee
tof
Engin
eer:
Bil
l L
ow
e
ww
w.p
eakau
dio
.com
w
ww
.cir
rus.
com
Siz
e:N
um
ber
:R
evis
ion:
ACir
rus
Lo
gic
, In
c.B
ou
lder
, C
O 8
0301
326
15
7 4
U300
OP
A627
326
15
7 4U
310
OP
A627
B300
.1S
B301
.1S
+9V
A
-9V
A
B310
.1S
B311
.1S
-9V
A
326
15
7 4
U330
OP
A627
326
15
7 4
U320
OP
A627
B330
.1S
B331
.1S
+9V
A
-9V
A
+9V
AB
320
.1S
B321
.1S
-9V
A
+5V
AB
352
.1S
GN
D
B351
.1S
MC
LK
MC
LK
SS
I_C
LK
SS
I_C
LK
FS
1_O
UT
FS
1_O
UT
AD
_D
AT
A1
AD
_D
AT
A1
C350
.01S
8
C353
.01S
8
123456
J300
1X
6P
HN
X
HP
F#
HP
F#
GN
D
TP
300
TP
G
GN
DG
ND
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
FIL
T+
24
RE
F_G
ND
23
HP
F11
LR
CK
3
VQ
22
I2S
/LJ
12
MC
LK
5
SC
LK
4
AIN
L-
17
VA19
RS
T1
MD
IV10
VD6
AGND18
AGND7
OV
FL
15
SD
OU
T9
AIN
R-
20
M1
14
M0
13
AIN
L+
16
VL8
AIN
R+
21
M/S
2
U350
CS
5381
C300
10A
20S
C310
10A
20S
C330
10A
20S
C320
10A
20S
R301
100K
S
R311
100K
S
R331
100K
S
R321
100K
SG
ND
C302
.01S
8G
ND
C332
.01S
8
VQ V
Q
C301
470P
FS
8
R300
90.9
P1S
R303
634P
1S
+9V
A
C311
470P
FS
8
R310
90.9
P1S
R313
634P
1S
R302
10K
P.1
S
R312
10K
P.1
S
R332
10K
P.1
S
R322
10K
P.1
S
C331
470P
FS
8
R330
90.9
P1S
R333
634P
1S
C321
470P
FS
8
R320
90.9
P1S
R323
634P
1S
C306
2700P
FS
8
C326
2700P
FS
8
C307
.01S
8
VQ
R361
5.1
1P
1S
VC
C_+
3
GN
DG
ND
GN
D
EN
_96K
EN
_96K
GN
D
AD
_R
ES
ET
#A
D_R
ES
ET
#
R352
10K
P1S
VC
C_+
3
R305
90.9
P1S
CR
300
LE
D0603R
R360
1K
P1S
C351
47A
16A
ES
+C
352
10A
6S
+C
305
10A
6S
+
C308
10A
6S
GN
D
31 Rev. 2.1
CobraNet™ EV-2
12
34
ABCD
43
21
D C B A
Cob
raN
et (
TM
) E
valu
ati
on
Board
- D
AC
E
2500 5
5th
Str
eet
Su
ite
210
Tit
le:
Fil
e:E
V2_D
A.S
ch4
919-O
ct-2
004
Dat
e:S
hee
tof
Engin
eer:
Bil
l L
ow
e
ww
w.p
eakau
dio
.com
w
ww
.cir
rus.
com
Siz
e:N
um
ber
:R
evis
ion:
ACir
rus
Lo
gic
, In
c.B
ou
lder
, C
O 8
0301
GN
D
+9V
B
-9V
B
B410
.1S
B412
.1S
B411
.1S
B413
.1S
TP
400
TP
G
GN
D
R403
1K
P1S
GN
D
SD
IN3
VR
EF
17
DS
D_B
1
SC
LK
4
RS
T13
DS
D_S
CL
K2
DGND8
M0 (
AD
0/C
S)
12
FIL
T+
15
VL
C14
AO
UT
R-
19
MC
LK
6
M2 (
SC
L/C
CL
K)
10
M3 (
AD
1/C
DIN
)9
VD7
M1 (
SD
A/C
DO
UT
)11
LR
CK
5
AO
UT
R+
20
RE
F_G
ND
16
BM
UT
EC
18
AGND21
VA22
AO
UT
L+
23
AO
UT
L-
24
AM
UT
EC
25
VQ
26
VL
S27
DS
D_A
28
U400
CS
4398
MC
LK
DA
_R
ES
ET
#D
A_R
ES
ET
#
DA
_D
AT
AD
A_D
AT
A
MC
LK
SS
I_C
LK
SS
I_C
LK
FS
1_O
UT
FS
1_O
UT
GN
DE
N_96K
EN
_96K
+5V
B
+C
401
10A
6S
B401
.1S
GN
D+
C400
10A
6S
GN
D
B400
.1S
VC
C_+
3
GN
D
B402
.1S
B403
.1S
+5V
B+
C404
10A
6S
R416
100K
S
R426
100K
SG
ND
GN
D
R436
100K
S
R446
100K
SG
ND
1 2 3 4 5 6
J401
1X
6P
HN
X
3 21
84
U410A
4560
+9V
B
-9V
B
567
U410B
4560
R410
196P
1S
R420
196P
1S
R421
681P
1S
R411
681P
1S
R422
464P
1S
R412
464P
1S
GN
D
GN
D
3 21
84
U430A
4560
+9V
B
-9V
B
567
U430B
4560
R430
196P
1S
R440
196P
1S
R441
681P
1S
R431
681P
1S
R442
464P
1S
R432
464P
1S
GN
D
C421
2200P
FS
C411
2200P
FS
C431
2200P
FS
C441
2200P
FS
C412
47A
16A
ES
C422
47A
16A
ES
C432
47A
16A
ES
C442
47A
16A
ES
C410
0.0
15U
F
C420
0.0
15U
F
C430
0.0
15U
F
C440
0.0
15U
F
C413
0.0
18U
F
C423
0.0
18U
F
C433
0.0
18U
F
C443
0.0
18U
F
B404
.1S
DA
_C
CL
KD
A_C
DO
UT
DA
_C
S#
DA
_C
CL
KD
A_C
DO
UT
DA
_C
S#
GN
DG
ND
GN
D
DA
_C
CL
KD
A_C
DO
UT
EN
_96K
R406
1K
P1S
R407
1K
P1S
R404
1K
P1S
GN
D
DA
_C
S#
R405
1K
P1S
R445
196P
1S
R435
196P
1S
R415
196P
1S
R425
196P
1S
C414
0.0
15U
F
C424
0.0
15U
F
C434
0.0
15U
F
C444
0.0
15U
F
+C
403
100A
E6R
3S
C402
47A
16A
ES
GN
D
Rev. 2.1 32
CobraNet™ EV-2
12
34
ABCD
43
21
D C B A
Cob
raN
et (
TM
) E
valu
ati
on
Board
- C
M &
ser
ial
I/O
, an
d r
eset
cir
cuit
.
E
2500 5
5th
Str
eet
Su
ite
210
Tit
le:
Fil
e:E
V2_co
m.S
ch5
919-O
ct-2
004
Dat
e:S
hee
tof
Engin
eer:
Bil
l L
ow
e
ww
w.p
eakau
dio
.com
w
ww
.cir
rus.
com
Siz
e:N
um
ber
:R
evis
ion:
ACir
rus
Lo
gic
, In
c.B
ou
lder
, C
O 8
0301
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
VC
C_+
3
HR
ES
ET
#
HR
EQ
#
HA
CK
#
HC
S#
SS
I_D
OU
T0
SS
I_D
OU
T1
SS
I_D
OU
T2
SS
I_D
OU
T3
SS
I_D
IN0
SS
I_D
IN1
SS
I_D
IN2
SS
I_D
IN3
FS
512_O
UT
SC
I_R
XD
SC
I_T
XD
SC
I_C
LK
AD
DR
3
RS
VD
1
RS
VD
2
RS
VD
3
RS
VD
4
MU
TE
#
AD
7
A0
A1
A2
AU
X_P
OW
ER
0A
UX
_P
OW
ER
1A
UX
_P
OW
ER
2A
UX
_P
OW
ER
3
WA
TC
HD
OG
HR
W
12
34
56
78
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P510
MM
S_C
ON
N40
12
34
56
78
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P511
MM
S_C
ON
N40
HA
CK
#H
RW
HC
S#
A[0
..2]
A[0
..2]
AD
[0..7]
AD
[0..7]
HR
ES
ET
#
SW
508
SW
2349
CR
508
1N
4148S
R508
10K
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10A
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MR
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ET
MR
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#
VS
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7
C1+
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9
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13
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10
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11
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12
C2-
5
U507
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1 6 2 7 3 8 4 9 5
P504
DB
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RA
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500
TP
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#
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B513
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AU
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Cobra
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Connec
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Res
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RH
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D
33 Rev. 2.1
Rev. 2.1 34
CobraNet™ EV-2
12
34
ABCD
43
21
D C B A
Cob
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TM
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valu
ati
on
Board
- O
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on
al
VC
XO
an
d c
lock
bu
ffer
s.
E
2500 5
5th
Str
eet
Su
ite
210
Tit
le:
Fil
e:E
V2_V
CX
O.S
ch6
919-O
ct-2
004
Dat
e:S
hee
tof
Engin
eer:
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l L
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com
Siz
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B500
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VC
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GN
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Clo
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Opti
onal
VC
XO
The
VC
XO
cir
cuit
pro
vid
es a
n e
xam
ple
of
a ci
rcuit
that
wil
l re
duce
jit
ter
on t
he
mas
ter
clock
. In
the
EV
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ppli
cati
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r is
low
enough w
her
e th
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it d
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tly. T
he
end u
ser,
bec
ause
of
long
tra
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s or
runnin
g t
he
mas
ter
clock
thro
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ther
com
ponen
ts s
uch
as
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PG
As,
may
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im
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men
ting a
jit
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nuat
ion c
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it s
uch
as
this
one.
Wit
hout
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XO
popula
te R
501 a
nd n
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Wit
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CX
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R511
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51.1
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51.1
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R514
51.1
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R502
51.1
P1S
R503
51.1
P1S
R602
51.1
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R501
51.1
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CobraNet™ EV-2
35 Rev. 2.1
12
34
ABCD
43
21
D C B A
Cob
raN
et (
TM
) E
valu
ati
on
Board
- A
ES
Tra
nsc
eiver
E
2500 5
5th
Str
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Su
ite
210
Tit
le:
Fil
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V2_A
ES
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79
19-O
ct-2
004
Dat
e:S
hee
tof
Engin
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l L
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com
Siz
e:N
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20
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DGND22
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24
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27
OR
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U700
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8420
1 2 3 4 5 6
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1 243
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R701
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CR
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3
B506
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GN
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56
4
U501B
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10
U501C
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N_96K
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#
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R709
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90.9
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B672
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R672
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R708
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R507
51.1
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CobraNet™ EV-2
12
34
ABCD
43
21
D C B A
Cob
raN
et (
TM
) E
valu
ati
on
Board
- P
ow
er
E
2500 5
5th
Str
eet
Su
ite
210
Tit
le:
Fil
e:E
V2_pw
r.sc
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919-O
ct-2
004
Dat
e:S
hee
tof
Engin
eer:
Bil
l L
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ww
w.p
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com
Siz
e:N
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ber
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Lo
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lder
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O 8
0301
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A
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CO
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DC
4
CO
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6
CO
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PW
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SB
9
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VD
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DC
12
CO
M13
PS
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N#
14
CO
M15
CO
M16
CO
M17
-5V
DC
18
+5V
DC
19
+5V
DC
20
P450
AT
X_P
OW
ER
VC
C_+
3
GN
D
GN
D
GN
D
GN
D
+5V
GN
D
GN
D
+12V
-12V
+5V
+C
451
470A
E16S
+C
452
470A
E16S
TV
S451
P4S
MB
13A
TV
S452
P4S
MB
13A
TV
S453
P4S
MB
6V
8A
TV
S450
SM
AJ5
V0A
B450
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B451
.1S
B452
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B455
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B453
.1S
B454
.1S
B456
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B461
.1S
GN
DG
ND
+12V
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B
B460
.1S
IN1
GND2
OU
T3
VR
461
78M
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GN
D
C462
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8C
460
.01S
8+
C461
10A
6S
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10A
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+C
450
220A
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+C
453
220A
E10S
+C
454
220A
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IN1
GND2
OU
T3
VR
460
78M
05S
GN
D
AD
J4
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T1
IN3
IN6
IN7
IN2
VR
480
LM
337L
AD
J4
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T2
OU
T3
OU
T6
OU
T7
IN1
VR
470
LM
317L
R480
249P
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R481
1.5
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P1S
C481
10A
20S
-12V
-9V
A
R470
249P
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R471
1.5
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C471
10A
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GN
D
+9V
A+
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B480
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B470
.1S
C470
.01S
8
C480
.01S
8
AD
J4
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T1
IN3
IN6
IN7
IN2
VR
481
LM
337L
AD
J4
OU
T2
OU
T3
OU
T6
OU
T7
IN1
VR
471
LM
317L
R482
249P
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R483
1.5
4K
P1S
C483
10A
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-12V
-9V
B
R473
249P
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R472
1.5
4K
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C473
10A
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GN
D
+9V
B+
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B481
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B471
.1S
C472
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8
C482
.01S
8
+5V
GN
D
CR
504
LE
DP
CG
RN
R513
464P
1S
Rev. 2.1 36
CobraNet™ EV-2
12
34
ABCD
43
21
D C B A
Cob
raN
et (
TM
) E
valu
ati
on
Board
- F
PG
A
E
2500 5
5th
Str
eet
Su
ite
210
Tit
le:
Fil
e:E
V2_F
PG
A.S
ch9
919-O
ct-2
004
Dat
e:S
hee
tof
Engin
eer:
Bil
l L
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ww
w.p
eakau
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.com
w
ww
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rus.
com
Siz
e:N
um
ber
:R
evis
ion:
ACir
rus
Lo
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c.B
ou
lder
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O 8
0301
AD
[0..7]
AD
[0..7] G
ND
B904
.1S
VC
C_+
3
GN
D
B903
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VC
C_+
3
GN
D
B902
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VC
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B901
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VC
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B908
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B907
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VC
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B906
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VC
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GN
D
B905
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VC
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AD
0
AD
1
AD
2
AD
3
AD
4
AD
5
AD
6
AD
7
WR
# WR
#W
R#
PR
OG
RA
M#
PR
OG
RA
M#
INIT_IO#INIT_IO#
A[0
..7]
A[0
..7]
A0
A1
A2
A3
A4
A5
A6
A7
LED0
LED1LED2
AUX_POWER0AUX_POWER1
AUX_POWER2
AUX_POWER3
AU
X_P
OW
ER
[0..3]
AU
X_P
OW
ER
[0..3]
AL
EA
LE
SC
I_C
LK
SC
I_C
LK
A8
A9
A10
A11
A12
A13
A14
A15
AD
DR
3R
SV
D1
RS
VD
2
RS
VD
3
RSVD4
RS
VD
[1..4]
RS
VD
[1..4]
I/O
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MS
6
I/O
3
I/O
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DI
4
I/O
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CK
5
I/O
7
I/O
15
I/O
9
I/O
10
GN
D11
VC
C3
12
I/O
13
I/O
14
I/O
19
M1
22
I/O
16
I/O
20
I/O
, G
CK
221
GN
D23
M0
24
VC
C3
25
PWRDWN26
I/O31
I/O (HDC)28
I/O29
I/O (LDC)30
I/O32
I/O33
I/O39
I/O34
I/O41
I/O (INIT)36
GND49
GND38
I/O40
I/O42
I/O43
I/O44
I/O46
I/O47
I/O, GCK448
DONE50
VC
C3
51
PR
OG
RA
M52
(D7)
I/O
53
I/O
56
(D5)
I/O
57
I/O
58
I/O
59
I/O
60
(D4)
I/O
61
I/O
62
VC
C3
63
(D3)
I/O
65
I/O
66
I/O
67
(D2)
I/O
68
I/O90
(DO
UT
) G
CK
6, I/
O73
I/O
69
I/O78
GC
K5, I/
O54
GND77
GCK7, I/O79
(CS1) I/O80
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
GND88
VCC389
VCC337
I/O92
I/O93
I/O94
I/O95
I/O96
I/O97
I/O98
GCK8, I/O99
I/O
18
GN
D1
I/O
8
I/O
17
I/O, GCK327
I/O35
I/O45
(D6)
I/O
55
GN
D64
I/O
71
I/O81
I/O91
VCC3100
(D1)
I/O
70
(D0, D
IN)
I/O
72
CC
LK
74
VC
C3
75
TDO, O76
I/O
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CK
12
U901
XC
S10X
L-4
VQ
100
SS
I_D
IN0
SS
I_D
IN1
SS
I_D
IN2
SS
I_D
IN3
SS
I_D
IN[0
..3]
SS
I_D
IN[0
..3]
SS
I_D
OU
T[0
..3]
SS
I_D
OU
T[0
..3]
SS
I_D
OU
T0
SS
I_D
OU
T1
SS
I_D
OU
T2
SS
I_D
OU
T3
AD_DATA1AD_DATA1
DA
_D
AT
AD
A_D
AT
A
AES_DINAES_DOUT
AES_DINAES_DOUT
MU
TE
#M
UT
E#
CR
904
LE
DP
CR
ED
CR
903
LE
DP
CG
RN
CR
905
LE
DP
CY
LW
+5V
LE
D0
LE
D1
LE
D2
RD
#R
D#
HC
S#
HC
S#
HE
N#
HE
N#
HR
ES
ET
#
NC
DA_RESET#DA_RESET#
HR
ES
ET
#
MC
U_P
35
MC
U_P
35
FS512_CLK
FS
1_O
UT
FS
1_O
UT
FS512_CLK
MC
U_C
LK
MC
U_C
LK
NC
NC
HWR#NC
NC
AE
S_B
CL
KA
ES
_B
CL
K
HWR#
A[8
..15]
A[8
..15]
GN
D
GN
D
GN
D
GN
D
AD
DR
3
AD_RESET#HPF#
HPF#AD_RESET#
EN_96KEN_96K
NC
DA_CCLK
DA_CDOUT
DA_CS#
DA_CCLK
DA_CDOUT
DA_CS#
MCU_P17MCU_P17
R903
464P
1S
R904
464P
1S
R905
464P
1S
34
U508B
74L
VX
14S
EN
_96K
EN
_96K
#E
N_96K
#
R902
1K
P1S
GN
D
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
GN
D
GN
D
R901
51.1
P1S
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Appendix E: EV-2 Command Line Interface.The EV-2 supports a simple command line interface (CLI). This interface allows the user to eval-uate the CobraNet module (CM) and monitor and control Host Management Interface (HMI) vari-ables. A list and description of commands follow. Please reference the CobraNet Programmer’s Manual for more information about the HMI variables. Please note that there is a significant dif-ference between the CM-1 and CM-2 HMI variable format, i.e. how the raw data is stored in the CM’s memory. Refer to the CobraNet Programmer’s Manual regarding the HMI variable formats.
Command line SyntaxThe CLI is case insensitive, either upper or lower case in any combination may be used. Param-eters enclosed within < > are mandatory with a few exceptions. At least one white space is required between command and parameters. Leading, lagging and multiple white spaces are ignored. A “ctrl-C” or “esc” will abort a command. With exceptions where noted, all numeric val-ues are to be entered or will be displayed in hexadecimal format with a leading “0x”.
This command line interface allows the user to write scripts (i.e Python scripts) that monitor and control HMI variables. Two commands are supported that allow the user to perform these tasks:
Peek <target> [offset]This command will return the value at the given address location or the value of the HMI variable.
<target> – a valid host address. The format of <target> is a hexadecimal number with a “0x” pre-fix.
Example: peek 0xAB12C5
<target> – the user may use an HMI variable. Example: peek sysdescr
In this example the CLI will return the system description in its entirety.
[offset] – optionally used with HMI array variables only. Offset into the HMI array. If not present on an HMI array variable, the peek will return a value for the first location in the array.
Example: peek txBundle 0x1000 The above example will peek location 0x51100 or transmitter #1.Example: peek rxSubMap 0x2005 This example will peek location 0x42005 or receiver #2, channel #5.
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Poke <target> <value> [offset]This command will set the value of the given location in CobraNet memory space to <value>.
<target>– same as peek above.
<value> – a hexadecimal with a “0x” prefix.Example: poke 0x40104 0x1011
[offset] – optionally used with HMI array variables only. Offset into the HMI array. If not present on an HMI array variable the poke will poke the <value> into the first location of the array.
Example: poke txBundle 0x111 0x2000
Please note the difference between the “peek <target = address>” and “<target = HMI>” commands. The “peek <target = address>” command will return the raw value at the specified address location whereas the “peek “<target = HMI>” command will return a properly formatted value. The difference is significant between the CM-1 and CM-2 where the variables are not stored in memory in the same format. An exam-ple is the rxPriority HMI variable.
On the CM-1:peek 0x40104 - command0x101000 - what is returnedpeek rxPriority - command0x1010 - what is returned
On the CM-2:peek 0x40104 - command0x1010 - what is returnedpeek rxPriority - command0x1010 - what is returned
This difference here is that the “peek 0x40104” command returns the raw value as it is stored in memory, the “peek rxPriority” command returns the value as it should be represented. In this example the CM-1 returned a different value than the CM-2 for the “peek 0x40104” command but the same value for the “peek rxPriority” command; this is because the storage format of the variable in memory is different between the CM-1 and CM-2. The main memory architecture difference between the CM-1 and CM-2 is that the CM-1 has a 24-bit wide memory bus whereas the CM-2 has a 32-bit wide memory bus. In the above example the rxPriority HMI variable is an Integer16 data type. On the CM-1 this type of data uses the middle and upper byte of the 24-bit memory location to store the data whereas the CM-2 stores the data in the lower two bytes of the 32-bit wide memory location.
In summary, using the HMI variable name will return data in the proper format. Using the address will return the raw data at the address location.
This also applies to the Poke command. When using the “poke <target = address> <value>” command you must pay attention to how the data (i.e. the <value>) is stored on the respective CM. Where supported, using the “poke <target=HMI> <value> [offset]” command means that the format of <value> is indepen-dent of how the data is stored. This allows for writing a command line interface script that works on either the CM-1 or the CM-2.
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CobraNet™ EV-2
There are a number of commands that control the state of the EV-2 board. Some of these commands should prove useful to the user when evaluating the CM. These commands are:
Route <input> <output>
<input> is the audio source on the EV-2 board, valid sources are:ssi0 – ssi port 0 from the CM.ssi1 – ssi port 1 from the CM.ssi2 – ssi port 2 from the CM.ssi3 – ssi port 3 from the CM.adc1 – digital audio output #1 from the Cirrus Logic ADCadc2 – this is the same as adc1.aes – digital audio output from the Cirrus Logic AES I/O IC.sine – a sinewave generated on the EV-2 board. This makes a useful test tone.mute – sets the digital audio stream to all zeros.
<output> is the audio sink on the EV-2 board, valid outputs are:ssi0 – ssi port 0 to the CM.ssi1 – ssi port 1 to the CM.ssi2 – ssi port 2 to the CM.ssi3 – ssi port 3 to the CM.dac – digital audio input to the Cirrus Logic DAC.aes – digital audio input from the Cirrus Logic AES I/O IC.
Examples:Route ssi0 dac
This will route the CM SSI stream #0 to the DAC.Route sine aes
This will route a sinewave out to the AES output.
Please note that the route command only applies to audio on and from the perspective of the EV-2 board and not between Cobranet devices.
Led <color> <operation>This command controls the state of the three LEDs on the EV-2 board. They may be used for development and debugging if so desired.
<color> = red, yellow, green, all. ‘all’ will perform the <operation> on all three LEDs. <operation> =
on: turn led onoff: turn led offblink+: blink LED, rate is about 2.2Hzblink-: turn blink mode offtoggle: change the state of the LED.
Note: blink mode is independent of the LED state. When blink mode is turned off the state will be returned to the state that the LED was in prior to turning the blink mode on. ‘Off’, ‘On’, and ‘Tog-gle’ have no effect while blink mode is on but will execute while in blink mode, i.e. when blink mode is turned off the LED will assume the state of the last command.
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CobraNet™ EV-2
Example: led green toggle.This will change the state of the green LED. If it was on it will be off. If the LED was in blink mode the LED will continue to blink but will assume the opposite state prior to the toggle command if blinking is stopped.
Query <what>This is a command to return information about the EV-2 and/or CM.
<what> =system: returns information such as MAC address and software/firmware revision levels.hex: returns the value of the hex switches on the EV-2 board.status: Returns the status of the device. Generally the EV-2 and CM will be in one of two states: Ready or Calibrating. The latter indicates that the EV-2 has the ADC and DAC in calibration mode. This latter mode occurs only after power up and lasts for about 10 sec-onds.cnmute: This returns the state of the mute signal coming from the CM. This is not to be confused with the mute choice of the route command. This is a signal on the CM interface that the CM controls. It is in either a muted or unmuted state. Querying this will return the state.mac: The CM Ethernet MAC address is returned.device: This will return the module type, CM-1 or CM-2.hack: Returns the state of the CM HACK# signal, either a “0” or a “1”.hreq: Returns the state of the CM HREQ# signal, either a “0” or a “1”.mute: Returns a list of the outputs paths which are muted .route: Returns a list of the input to output routing information.gain: This parameter returns the gain information for the EV-2 sinewave.frequency: Returns a number from 0x1 to 0x8. See Audio frequency below.
Audio <operation> [value]
<operation> =samplerate
[value] = 48k: changes the CM samplerate to 48k. 96k: changes the CM samplerate to 96k.
calibrate: put the audio converters through a calibration cycle[value] = N/A
gain: sets the gain for the EV-2 test sinewave.[value] = 0dB, -6dB, -12dB, -18dB Default is 0dB.
frequency: sets the frequency for the EV-2 test sinewave.[value] = 0x1-0x8 This value is a multiple of the fundamental frequency which is 1.5kHz for the 48kHz sample rate and 3.0 kHz for the 96kHz sample rate. Default is the fundamental.
hpf: enables (0) or disables (1) the high pass filter in the ADC, see the Cirrus Logic CS5381 data sheet for more details on the operation of the high pass filter.
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TestEV <what>This is used for manufacturing tests of the EV-2 and in general only the ‘resetcn’ will be useful to the user.
<what> =memory – performs an EV-2 memory test, returns either a pass or fail.watchdog – checks the CM watchdog signal to make sure it is in tolerance. Returns pass or fail and measured frequency of CM watchdog signalhost – performs a host test, returns pass or fail.resetcn – resets the CM.
Packet <what> <arg2>This command will perform a packet transfer between CM/EV-2 boards and is used to demonstrate and test the Cobranet packet bridge feature. Two packet types are supported, either command based or text based. The command packet will send an EV-2 line command to the other EV-2 which will return any results (an example would be a query command) as a text based packet. A text based packet will send text to the other EV-2 to be put out its 8051 serial port. This is much like an instant message.
<what> = command: This tells the receiving CM that the following <arg2> is a line command.
<arg2>: this is any valid line command as described in this document.text: this tells the receiving CM that the following <arg2> is text and will output the text to the serial port.
<arg2>: text that may be separated by spaces. Everything that follows the “text” parameter will be considered text.
on: turns packet processing on.off: turns packet processing off.
Examples:packet command query device
This example will return what type of CN module is on the other EV-2.packet text how are you today?
This will send out the 8051 serial port of the other EV-2 the text: how are you today?
Please note that the on and off commands are from the perspective of the EV-2 and not the CM, i.e., the CM will still process commands from other sources if set up to do so.
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CobraNet™ EV-2
Read <register>This command reads the raw value of the host register. Note that the architecture is significantly different between the CM-1 and CM-2.
<register> =(for CM-1, the DSP5303 host register interface.)
icr: read the icr register.cvr: read the cvr register.isr: read the isr register.ivr: read the ivr register.drh: read the drh (rxh) registerdrm: read the drm (rxm) registerdrl: read the drl (rxl) register.
(for CM-2, the CS1810xx host register interface)msg: read the msg register (returns four bytes)data: reads the data register (returns four bytes)msga: returns the value of the message A register.msgb: returns the value of the message B register.msgc: returns the value of the message C register.msgd: returns the value of the message D register.dataa: returns the value of the data A register.datab: returns the value of the data B register.datac: returns the value of the data C register.datad: returns the value of the data D register.control: returns the value of the control register.status: returns the value of the status register.
Write <register> <value>This command writes a value to the host register. Refer to the appropriate documentation regard-ing the host register interface on the CM-1 and CM-2. The architecture is significantly different.
<register> =(for CM-1, the DSP5303 host register interface.) icr: write the icr register.cvr: write the cvr register.isr: write the isr register.ivr: write the ivr register.drh: write the drh (rxh) registerdrm: write the drm (rxm) registerdrl: write the drl (rxl) register.
(for CM-2, the CS1810xx host register interface)msg: write the msg register (writes four bytes)data: write the data register (writes four bytes)msga: write the value to the message A register.msgb: write the value to the message B register.msgc: write the value to the message C register.msgd: write the value to the message D register.dataa: write the value to the data A register.
43 Rev. 2.1
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ting Cirrus Logic, Inc.er information on CobraNet™ products, contact: the Commercial Audio Products Division of Cirrus Logic, Inc.th St. Suite 210 Boulder, CO 80301 (303) 245-5500
peakaudio.comrus.com© 2001-05 Cirrus Logic, Inc. All rights reserved. CobraNet and Peak Audio are trademarks of Cirrus Logic, Inc.
datab: write the value to the data B register.datac: write the value to the data C register.datad: write the value to the data D register.
value> – a hexadecimal with a “0x” prefix. The individual registers are byte wide, a hexadecimal in the <valuarameter greater than a byte will only use the least significant byte.
Example: write msgc 0xb3
te that writing certain registers may trigger CobraNet events. Please refer to the CobraNet Programmer’s Manuormation regarding these registers and the other host interface registers.
target>his command will return the value at the given address location for the EV-2 data memory. Please refer to the eiscussion of the EV-2 memory map.
target> = a valid address in hex format. The address is limited to two bytes.
<target> <value>his command will set the given address location in the EV-2 data memory to the given <value>. Please refer tarlier discussion of the EV-2 memory map.
target> – a valid address in hex format. The address is limited to two bytes.
value> – a byte hexadecimal with a “0x” prefix.