coal-based igfc project phase i fc26-08nt0003894 · 2013-08-22 · coal-based igfc project phase i...
TRANSCRIPT
COAL-BASED IGFC PROJECT
PHASE I FC26-08NT0003894
Praveen Narasimhamurthy – UTC Power
Rick Kerr – Delphi
12th Annual Solid State Energy Conversion Alliance (SECA) Workshop
July 23-25, 2012
Sheraton Station Square Hotel
Pittsburgh, PA
2
OUTLINE
• Summary of stack performance highlights from past year
• Cell and stack fabrication
• Gen 4 stack seal development
• Gen 4 stack voltage variation improvement
• Interconnect and contact material development
• Constant current
• Thermal cycling
3
SUMMARY OF SECA COAL BASED SYSTEM STACK DEVELOPMENT
• Completed scale up of cells from 105 cm2 (active area) cells to 403 cm2 for Gen 4 stacks
• Added additional Gen 4 stack fabrication and testing capabilities
• Fabricated and tested 24 Gen 4 stacks and 55 Gen 3 stacks in past year
• Completed Red X® investigations to improve stack sintering process and decrease stack voltage variation
• Demonstrated 7,000+ hours continuous durability on Gen 3.2 stack; demonstrated 5,000+ hours on Gen 4 stack.
• Completed 70 full thermal cycles on Gen 4 stack, with less than 5% voltage degradation
CELL AND STACK FABRICATION
• Fabricated in past year
– About 2,200 Gen 4-sized
cells
– 24 Gen 4 stacks of varied
configurations (most 30-
cells or greater)
– 55 Gen 3 stacks of varied
configurations (many 30-
cells or greater)
Gen 4 Cell
403cm2
active area
Gen 3 Cell
105cm2
active area
GEN 4 STACK SEAL DEVELOPMENT PROJECT
Inlet Perimeter
CONCENTRATION DIAGRAMS OF POROUS SEAL MICROSTRUCTURES
6
3 0 0 0 2 13
1 25
0 Stack G041 17
0 40-Cell Gen 4 20
1 26
1 35
1 0 0 0 6 34
5 3 5 7 9 12
2 22
0 Stack G035 26
0 40-Cell Gen 4 31
0 33
1 33
1 5 9 11 15 29
STACK SINTERING OPTIMIZATION PROJECT
• Confirmed overheating of the stack seals
– PNNL XRD analyses
– Microstructural analysis
– Coupon confirmation testing at increased sintering
temperatures
• Teardown analyses of previous stacks
• Thermal mapped build stands and stacks during
standard build process
• Developed strategy for investigating build control factors
for improved thermal control during sintering
• Completed stack mapping thermal profiles with varied
build controls
• Confirmation run with new build control parameters
7
8
TEMPERATURE PROFILES PRIOR TO OPTIMIZATION OF SINTERING CYCLE
-200
-150
-100
-50
0
50
100
150
200
10.00 10.50 11.00 11.50 12.00 12.50 13.00 13.50 14.00
Tem
pe
ratu
re D
evia
tio
n f
rom
Sin
teri
ng
Tem
pe
ratu
re, C
els
ius
Time, Hours
Furnace Set Point
Top of Stack
Furnace Air
Stack Internal
TEMPERATURE PROFILES AFTER OPTIMIZATION OF SINTERING CYCLE
9 -100
-80
-60
-40
-20
0
20
40
60
80
100
1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
Tem
pe
ratu
re D
evia
tio
n f
rom
Sin
teri
ng
Tem
pe
ratu
re, C
els
ius
Time, Hours
Furnace Set Point
Furnace Air
Top of Stack
Stack Internal
SEAL STRUCTURAL IMPROVEMENT FROM SINTERING OPTIMIZATION
10
Inlet Perimeter Inlet Perimeter
Stack Perimeter Seal
Prior to Optimization
of Sintering Cycle
Stack Perimeter Seal
After Optimization of
Sintering Cycle
INITIAL GEN 4, 30-CELL STACK PERFORMANCE USING OPTIMIZED
SINTERING PROFILE
11
0
0.2
0.4
0.6
0.8
1
1.2
0.00 50.00 100.00 150.00 200.00 250.00 300.00
RU
Voltage (
V)
Current(A)
Date: 8/19/2011Fuel: 48.5%H2-48.5%N2-3%H20
RED X® STUDY ON MINIMIZING STACK REPEATING UNIT VOLTAGE VARIATION
• Analyzed numerous Gen 4 stacks
– Cross sections
– Repeating unit teardowns
– X-ray and metallographic analyses of repeating units
– Measurement studies of numerous repeating unit
components
– Optical and SEM inspection of components
• Conducted sintering studies
– Component level
– Full stack level
12
MOST RECENT 38-CELL GEN 4 STACK INITIAL POLARIZATION
PERFORMANCE AFTER RED X ® PROJECT
13
0
50
100
150
200
250
300
350
400
450
500
0
5
10
15
20
25
30
35
40
45
0.00 50.00 100.00 150.00 200.00 250.00 300.00
Po
we
r D
en
sity (
mW
/cm
2)
Sta
ck V
olta
ge
(V
)
Current(A)
Date: 06/27/2012Fuel: 48.5%H2-48.5%N2-3%H20
StackGrossVoltage(V) PowerDensity(mW/cm^2)
MOST RECENT 38-CELL GEN 4 STACK INITIAL POLARIZATION VOLTAGE
SPREAD
14
0
0.2
0.4
0.6
0.8
1
1.2
0.00 50.00 100.00 150.00 200.00 250.00 300.00
RU
Voltage (
V)
Current(A)
Date: 06/27/2012Fuel: 48.5%H2-48.5%N2-3%H20
MOST RECENT 38-CELL GEN 4 STACK INITIAL CONSTANT CURRENT
PERFORMANCE (0.35 A/cm2)
15
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
0.00 0.20 0.40 0.60 0.80 1.00 1.20
RU
Voltage (
V)
Time(Hrs)
Date: 06/27/2012Fuel: 48.5%H2-48.5%N2-3%H20
GEN 3.2 STACK DURABILITY TESTING (0.57 A/cm2)
0
50
100
150
200
250
300
350
400
450
500
0
5
10
15
20
25
30
0.00 1000.00 2000.00 3000.00 4000.00 5000.00 6000.00 7000.00 8000.00
Pow
er
Density (
mW
/cm
2)
Sta
ck V
oltage (
V)
Time(Hrs)
Dates: 11/23/2010 to 10/17/2011Fuel: 48.5%H2-48.5%N2-3%H20
StackGrossVoltage(V)
PowerDensity(mW/cm^2)
17
GENERATION 3 30-CELL STACK DURABILITY
30-CELL GEN 4 STACK THERMAL CYCLING
18
THERMAL CYCLING CATHODE CONTACT MATERIALS
19
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0
100
200
300
400
500
600
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
Pow
er
Density (
mW
/cm
2)
Cell
Mean V
oltage (
V)
Thermal Cycle Number
Date: 2/9/2012Fuel: 48.5%H2-48.5%N2-3%H20
Power Density (mW/cm2)Mean Voltage (V)Cathode Contact Material A Mean VoltageCathode Contact Material B Mean Voltage
30-CELL GEN 4 STACK CONSTANT CURRENT DURABILITY (0.27 A/cm2)
20
INTERCONNECT MATERIAL PERFORMANCE
21
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0.00 1000.00 2000.00 3000.00 4000.00 5000.00 6000.00
Ce
ll V
olt
age
, Vo
lts
Time, Hours
Mean Cell Voltage
Interconnect Materials 1
Interconnect Materials 2
Interconnect Materials 3
22
UTC OBJECTIVES FOR PHASE II
• Design and build 15-25kW SOFC breadboard
• Make modifications to SOFC test stand from Phase I to
test breadboard
• Perform extensive verification of test stand and
breadboard on beater stack prior to start of endurance
testing
• Demonstrate 1500 hours endurance on 4-stack module in
a system construct (breadboard)
• Demonstrate thermally self-sustaining operation
• Demonstrate peak power operation
23
• Demonstrated ~1,250 hours durability on Gen 4 stack module.
• Improved test stand reliability by ~3x to complete Phase I
• Completed conceptual and preliminary design for the 25kW breadboard
• Detailed design and breadboard build is ~80% complete
• Test stand modifications for Phase II are ~80% complete
• Software design and bench verification is 90% complete
• Ex-situ verification of breadboard fuel recycle assembly is underway
– Completed ~100 hours of continuous durability at operating temperatures on
an ex-situ test rig
SUMMARY HIGHLIGHTS - SYSTEM
SOFC
Cell
Delphi
Gen 3
Stack
(30 cells)
Delphi
Gen 4
Stack
(40 cells)
Stack Module
in Test Stand
Conceptual SOFC
Breadboard
Gen 4
Stack
Module
Power Plant
Concept
’08 -’10
’10 - current
6.25kW
’10 - current
25kW
’11 -’12
25kW
’11 -’13
25kW
’14-’16
100-200kW
SOFC
Product
>’17
100-400kW
’11 -’12
5kW
Delphi APU
OVERVIEW – SOFC PRODUCT DEVELOPMENT ROADMAP
Stack Module
TASK 6.3 - STACK MODULE ENDURANCE TESTING
25 Delphi Stack Module in the 50 kW capable
test stand at UTC Power
Cathode
Recuperative
Heat Exchanger
Air Inlet
Heater
Stack Module
Hot Box
Gas Inlet/Exit
Fuel Inlet
Heaters
Hot Box
Safety Sensors
Phase I Stack Performance
TASK 6.3 - STACK MODULE ENDURANCE TESTING
26
Endurance Test – System Level Learning
TASK 6.3 - STACK MODULE ENDURANCE TESTING
27
Completed fuel contaminant tests
Completed cathode side chromium sampling
Obtained data on stack manifold temperature distribution
Temperature data used to estimate stack heat loss for
Phase II
Obtained data on stack manifold pressure drop
Currently anode over cathode at stack exit; working with
Delphi
Improved test stand reliability
28
TASK 4.1 - BREADBOARD/SYSTEM DESIGN
NPD Gated Process for System Design and Development
Conceptual Design
Requirements Generation
Trade Studies
Conceptual Models
System Matches
Preliminary Physical Layout
Preliminary Design
Component Requirements
Generation
Component Design
Controls Design
FMEA/FA/HA
Detailed Physical Layout
Detailed Design/Test
• Component Tests
• Hardware
Build/Integration
• Test Plan Review
• Breadboard Checkouts
• Endurance Test
Design Review Design Review Test Report
29
Breadboard Schematic
TASK 4.1 - BREADBOARD/SYSTEM DESIGN
Fuel recycle for maximizing efficiency
HEXs for exhaust heat recovery
Catalytic burner for exhaust management and heat up of cathode inlet air
30
Breadboard Projected Efficiency
TASK 4.1 - BREADBOARD/SYSTEM DESIGN
Breadboard Projections vs. Ideal
Several BOP (recycle blower) over-sized
Heaters included for contingency on breadboard; not required for a product
Air blower for cathode supply not optimized
31
Control Strategy
TASK 4.1 - BREADBOARD/SYSTEM DESIGN
Test stand controller
Controls breadboard startup sequence,
transition to load, on-load operation and
breadboard shutdown for product protection
Host PC & Data Acquisition
GUI-based user interface for controlling test
process, monitoring and data collection
Other Controllers
1. Safety Controller
Hard-wired controls for safety and personnel protection
2. Facility Controller
Provides safety shutoff for all reactant supply system
3. After Burner Controller
Controls test stand afterburner
4. Heater controllers
Maintain test stand controller requested heater set point
TASK 4.1 - BREADBOARD/SYSTEM DESIGN
Breadboard Layout
32
Delphi Stacks
UTCP
Balance of Plant
(BOP)
TASK 4.1 - BREADBOARD/SYSTEM DESIGN
Breadboard Design
33
Fuel System Components
Air System Components
34
Risk Mitigation: Ex-situ Blower Tests
TASK 4.1 - BREADBOARD/SYSTEM DESIGN
Test Rig for Blower Performance
and
Endurance Test
Stack
Module
FUTURE WORK
• Continue cost reduction of stack and
power plant components
• Improve stack durability to meet SECA
goals
• Demonstrate breadboard endurance
• Risk reduce for critical components:
blowers, fuel processing components,
catalytic burners
• Collect system level data for scaled-up
power plant/prototype design in future
phases
Beyond Phase II
35
Breadboard
Power
plant
Prototype
36
ACKNOWLEDGEMENTS
Thanks to Joe Stoffa, Briggs White, and Dan Driscoll of the DOE
for their support and technical guidance