cnrs – inpg – ujf aida wp3 3d industry workshop, may 23 rd, 2011, bergamo 3d-ic prototyping...
TRANSCRIPT
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
3D-IC prototyping service at CMP
Kholdoun [email protected]
CMP
46, Avenue Félix Viallet,
38031 Grenoble, France
http://cmp.imag.fr
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Agenda
• Introduction
• Collaboration for 3D-IC MPW runs service
• Tezzaron Process overview
• 3D-IC Design Platform
• TSV and wafer stacking from austriamicrosystems
• Conclusion
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CMP created in 1981
Offering industrial quality process lines (University process lines cannot offer a stable yield)
Design-kits to link CAD and MPW, to facilitate the design.
Customer base development+ Universities / Research Labs+ Industry+ 1000 Institutions in 70 countries
Non-profit, Non-sponsored
Introduction
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Multi-Project Wafer runs allow to share the price by sharing the reticle area.
Prototype fabrication.
Low volume productions (some hundreds to hundred thousands parts)
Designer C
Chip AChip A
Chip CChip C
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bd e
cc cc
f
Chip BChip B
Designer B cc
c c c
Designer A
Designer C
Chip AChip A
Chip CChip C
a
bd e
cc cca
bd e
cc cc
f
Chip BChip B
Designer B cc
c c ccc
c c c
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Designer A
• Prototypes
• Low volume productionShared cost wafer
Multi-Project Wafer (MPW)
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
IC :
austriamicrosystems
STMicroelectronics
28nm/32nm CMOS40nm CMOS 7LM65nm CMOS 7LM130nm CMOS 6LM
65nm SOI
130nm SOI130nm SiGe BiCMOS
0.35 µ CMOS / CMOS-Opto0.35 µ SiGe0.35 µ HV CMOS0.35 µ HV CMOS EEPROM
0.18 µ CMOS
0.18 µ HV CMOS
MEMS :
CMP/austriamicrosystems
MEMSCAP
0.35 µ CMOS bulk micromachining
PolyMUMPS MetalMUMPS SOI-MUMPS
3D-IC : Tezzaron / GlobalFoundries 2 Tiers 3D-IC / 130nm CMOS
TriQuint Semiconductor 0.15 µ GaAs D-mode pHEMPT
TowerJazz 0.18 µ CMOS
Technology Process Portfolio in 2011
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CMC-CMP-MOSIS Collaboration
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
• Stimulate the activity by sharing the expenses for manufacturing.
• Join forces for the technical support, and dedicate roles for each partner.
• Make easier the tech support for local users respectively by each local center.
• Because there is no standard for the 3D-IC integration, it is urgent to setup an
infrastructure making possible a broad adoption of 3D-ICs. That will have a
beneficial effect on prices, more frequent MPW runs, and more skilled engineers.
Benefits for a global Infrastructure
CMC / CMP / MOSIS partnering for 3D-IC process access
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CMC-CMP-MOSIS partnering on 3D-IC
CMP/CMC/MOSIS partner to introduce a 3D-IC process
Grenoble, France, 22 June 2010, CMP/CMC/MOSIS are partnering to offer a 3D-IC
MPW service based on Tezzaron’s SuperContact technology and GLOBALFOUNDRIES
130nm CMOS.
The first MPW run is scheduled to 31 May 2011:
- 2-tier face-to-face bonded wafers
- 130nm CMOS process for both tiers
- Top tier exposing TSV and backside metal pads for wire bonding.
A design-kit supporting 3D-IC design with standard-cells and IO libraries is available.
Further MPW runs will be scheduled supporting process flavors (multiple tiers beyond
2, different CMOS flavors for different tiers, ...) driven by user requirements.
Potential users are encouraged to contact CMP for details : [email protected]
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CMC - CMP - MOSIS Cooperation• CMC supporting Canadian Customers• CMP supporting European Customers• MOSIS supporting US Customers
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Tezzaron 2-Tier Process (130nm CMOS)
Process Overview
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Source Yole Development
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Tezzaron Process Flow for TSV and DBI (using Via Middle process)
Starting wafer in 130nm (5 Cu metal layers + 6th Cu metal as DBI)
Source Tezzaron
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Tezzaron Process Flow for TSV and DBI (using Via Middle process)
Cu Cu Cu
Cu
Cu
Cu
Cu Cu
Cu
Cu
Cu
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Top Tier(10um thickness)
Bottom Tier(Handle wafer)
Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process)DBIs continuing the stacking
Source Tezzaron
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Top Tier(10um thickness)
Bottom Tier(Handle wafer)
Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process)Bond pad for wire bonding or bump, flip-chip …
Source Tezzaron
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
3D-IC MPW runs
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
3D-IC Potential Users
HEP Labs
3D-IC MPW Initial Infrastructure
First MPW Run organized by FermiLab using an Industrial Process
Clustering Manufacturing
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Source FermiLab (3D Consortium Meeting)
MPW Full Frame
NoticeSymmetryabout verticalcenter line
Test chips:TX, TY2.0 x 6.3 mm
Top tiers Bottom Tiers
Subreticules:A, B, C, D, E, F, G, H, I, J5.5 x 6.3 mm
3D Consortium : 1st MPW run
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
3D-IC Users
3D-IC MPW Infrastructure
CMC-CMP-MOSIS partnering to offer 3D-IC MPW runs
Clustering Manufacturing
Critical mass allow frequent MPW runs and low pricing
In discussion
In place
In place
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CMP/MOSIS/CMC : 1st MPW run
Deadline originally planned for May 31st, 2011
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
3D-IC Design Platform
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Tezzaron / GlobalFoundries Design Platform
• The Design Platform is modular. It has all features for full-custom design or semi-custom automatic generation design.
• PDK : Original PDK from GF + (TSV / DBI) definition from Tezzaron
• Libraries : CORE and IO standard libraries from ARM
• Memory compilers : SPRAM, DPRAM and ROM from ARM
• 3D-IC Utilities : Contributions developments embedded in the platform
• Tutorials, User’s setup.
• All modules inside the platform refer to a unique variable, making it portable to any site. The installation procedure is straightforward.
• Support of CDB and OpenAccess databases.
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
DBI (direct bonding interface) cells library. (FermiLab)
3D Pad template compatible with the ARM IO lib. (IPHC)
Preprocessor for 3D LVS / Calibre (NCSU)
Skill program to generate an array of labels (IPHC)
Calibre 3D DRC (Univ. of Bonn)
Dummies filling generator under Assura (CMP)
Basic logic cells and IO pads (FermiLab)
Floor-planning / automatic Place & Route using DBIs, and TSVs (CMP)
Skill program generating automatically sealrings and scribes (FermiLab)
MicroMagic PDK (Tezzaron/NCSU)
Collaborative Work to the Design Platform
HEP labs contributing with Programs, Libraries, and Utilities. All included in the Design Platform
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Virtuoso Layout Editor with 3D layers and verification
TSV
Back Metal
Back Pad
DBI
Assura
Calibre
Virtuoso from Cadence
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
True 3D Mask Layout Editor
MicroMagic MAX-3D
Technology Files fully supported by Tezzaron
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
- DBIs Placement- TSVs Placement- Obstructions on TSVs
- Std cells Placement- Clock Tree Synthesis
Filler Cells Placement
- Clock routing- Final routing
Automatic P & R Design Flow (From Floor-Plan to Routed Design)
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
assuracalibrecds_cdbcds_oadoceldoherculeshspiceprep3DLVSskillspectrestrmMaptables_ARMstrmMaptables_Encounter
chrt13lprf_DK009_Rev_1D (Version issued in Q1 2011)
calibre:3DDRC3DLVSDRCFILLDRCcalibreSwitchDef
assura:FILLDRCLVSQRC
hercules:DRCLVSSTAR_RCXT
PDK Tezzaron / GlobalFoundries
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Access to the Design-Rules and the Design Platform
CustomerRequest
Signed NDA receptionNDANDA
http://cmp.imag.fr
Foundry’s Agreement
Yes
Design kit &
Design Rules access
NDA Edition
Request to access from CMP Web page or by E-mail to :
The user receive by E-mail the NDA + ARM lirary Addendum.
The user sign and return by post 2 original signed copies
CMP forward to Tezzaron the NDAs.
When Tezzaron is OK, they counter-sign and return one copy to CMP.
CMP return the copy to the user and give the access to the DRM and Design-Platform.
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CPPM, Marseille, FranceIPHC, Strasbourg, FranceLAL, Orsay, FranceLPNHE, Paris, FranceIRFU, CEA Saclay, FranceLAPP, Annecy-Le-Vieux, FranceENSTA PARISTECH, Paris, FranceISEA, Toulouse, FranceENSSAT – Universite Rennes, FranceCEA-DIF, France
University of Bergamo, ItalyUniversity of Bologna, ItalyUniversity of Perugia, ItalyINFN, Roma, ItalyINFN, Pavia, ItalyINFN, Pisa, Italy
University of Bonn, GermanyUniversity of Barcelona, SpainIMSE-CNM-CSIC, Sevilla, SpainTuDelft, The NetherlandsUniversity of Turku, FinlandNorwegian University, Trondheim, Norway
22 Users in Europe
Tezzaron Semiconductor, USA
FermiLab, USA
North Carolina State University, USA
MOSIS, USACMC Microsystems, Canada
University of Sherbrooke, Canada
+ Other centers supported by MOSIS and CMCNot listed here.
Users having access to the Design Platform
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
100µ TSV on 0.35µ CMOS from Austriamicrosystems
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
CNRS – INPG – UJF
AIDA WP3 3D Industry Workshop, May 23rd, 2011, Bergamo
Conclusion
CMC-CMP-MOSIS collaboration to offer services for 3D-IC prototyping and low
volume productions.
Continuous enhancements on the Design Platform offering updates, features, and
design methodologies.
First MPW run deadline : May 31st, 2011