cms/hcal/tridas. mar, 2004 hcal tridas 1 tridas status drew baden university of maryland june 2004
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CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 1
Tridas Status
Drew BadenUniversity of Maryland
June 2004
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 2
Princeton Fanout Board
TTC fiber
Clk80
Input from GLOBAL Fanout
18 Outputs
40MHz
RX_CLK = 40MHz
RX_BC0
INT_BC0
RX_CLK = 40MHz
RX_BC0
QPLL
EXT 80MHz
QPLL can run stand-alone
TTCrx
EXT_BC0
FPGA
Delay
TTC Broadcast
G
G
G
C
C
C
G
QPLL implemented this way allows RX_CLK to be “cleaned” at each board if needed
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 3
HCAL Fanout board
• Final version in operation– CERN, Maryland, FNAL, Wisconsin…– No problems – board is ready for production
• ECAL needs– 4 + 2 spares
• Plus parts for 3 more
• HCAL needs– 16 + 4 spares
• Will build that plus parts for 4 more– 6 more for test stands, etc.
• Total: 33 boards plus parts for 7 more• Time scale:
– Can assemble 6 more on short time scale– Reset needs to wait for an amplifier (14 weeks)
• Proposal– Tell Jeremy and Chris to go ahead with
production now
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 4
TTC_UMD Cards
• Purpose:– Carry TTCrx onto HCAL boards (HTR,
DCC, Fanout)– All boards produced– Vendor put in the LEDs backwards
• Using students to fix it
– Checkout happening now, using students, finished by end of summer
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 5
DCC Status
• DCCv4 boards used in TB03– Being used now in H2 and elsewhere– Testbeam boards have the up to date v5 firmware
• DCCv5 – identical to v4 except for new front panel w/LEDs– LED “boards” are produced– 10 new logic boards ready in Boston– Plan to have “a few” ready by May (E. Hazen)– Can provide new firmware for all existing v4s
• Main firmware change is in the input channel numbering
• Production:– Planning to build 50 DCCs in total
• Another 10 motherboards over what is available now)– Planning to change the 10-pin RJ45 connectors on the LRBs to match the new
variety• New connectors prevent inadvertent insertion of 8-pin RJ45 connectors and bending
the pins
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 6
Changes to HTR for Rev4
• Clocking issues– No earth-shaking changes– No evidence of any difficulties associated with HTR layout/implementation
• “Cosmetic” changes– Moved 2 LC’s down to giver more clearance for fibers– Removed hot swapping circuits
• Worry about noise, decided not to require HTR to be hot swappable
– Front-panel changes– Bias resistors for all differential pair inputs (a powerup issue only…)– Change DCC 10-pin connectors
• Fanout input is 8-pin standard RJ45• Eliminate possibility of plugging Fanout cable into DCC connector, munging pins
– Changes to VME to accommodate software (Big/Little Endian defaults)
• Miscellaneous changes– Fixed what was found to be wrong with Rev3 board, add test points, other
minor stuff
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 7
Changes to HTR for Rev4 (cont)
• Changes necessary for SLB– Optimized critical clock and data lines– HTR 40MHz “LHC” clock to come from TTC
• TPG data and TTC broadcast need to have synchronization
– Added hardware reset circuitry for TTCrx– Deal with SLB startup current– Added separate SLB JTAG chain
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 8
HTR Schematic
SLB
RX_CLK40
SLB
SLB
SLB
SLB
SLB
RX_BC0TTC
TTCrx
CLK80
Crystal
Serial Optical Data
Ref Clk
Deserializers (8)
20Recovered Clk
TPG Path
SY
S4
0 C
lk
TTC Broadcast Async Fifo
PLLTTC 40 Clk x2
XILINX
LC
Fiber Data
Princeton Fanout Card(1/VME crate)
SY
S8
0 C
lk
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 9
HTR TPG Testing
• Testing with latest SLB:– Localbus access of SLB verified easily– JTAG chain working– Link tests between SLB and Wisconsin test receiver board (STC)
• 1.2Gbaud copper link: verified at Maryland• Data verification also passed at Maryland
– Link tests at Madison in May 2004• Data sent from HTR into SLB into Wisconsin trigger receiver board• Some problems found but these were limited to SLB/RCT issues
– Tests underway on TPG cables• Testing various cat6 quad twisted pair
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 10
SLB/Receiver Test Boards
• So far, used Wisconsin STC boards– Very nice for Wisconsin requirements– We need something different for commissioning and production
• Something more flexible and programmable for mass testing– 260 HTRs, 6 SL B/HTR….can’t see plugging each one into a single STC
• Layout underway for an SLB/Vitesse mezzanine transition – Allows use of 6 HTR SLB sites– Run backwards into XILINX
• Board is now under design– Estimate another ~month in the lab for testing.
HTR
SLB site
UW Vitesse receiver mezzanine card
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 11
HTR Production Status
• Production– Preparing fab and assembly contracts
• Will be ~$90k for each. • $90k each, causes Maryland purchasing dept fits
– 3 Rev4’s built and verified, some small changes– 6 Rev4’s at the assembler now – back this week or early
next week• Will verify, then send some to H2 for HO setup
– Will proceed to full production after next batch of Rev4’s are verified
• Integration tests in Madison in May established the TPG patch electrically
– Any changes will be accommodated in firmware
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 12
HTR Rev4 Status
• Current (Rev4) board – 3 in lab now– Testing:
Links/Clocks (same as Rev3, no problems, no mystery at UMD)
DCC path exactly same as Rev3
TPG path
– Just a few layout changes needed, ready for production– Production can begin just as soon as next 6 Rev4’s checkout
• Expect to spend rest of CY04, but maybe sooner depending on how well it goes.
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 13
Fiber Data Links
• What we’ve learned about links this past year:– Dirty fibers – causes mode-dependent reflections and interference
• Persistent cleaning usually helps, sometimes alot
– Reflection at surface of Stratos LC receiver• <12dB reflected light is large – about 5% reflection• We believe reflected light is again reflected by MTP connector and interfering with
primary optical signal– Attenuators between LC and Stratos always cure this
– VCSEL bias current can be varied by I2C to GOL• Installation/commissioning – this will need to be tuned to lowest value
– QPLL really helps• Especially on FE card but also on HTR
– HF layout tweaked, much better results reported
• The proof of the pudding is in the eating– H2 running no longer worries about the fiber data links!!!
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 14
H2 Fiber Link Errors (Anecdotal…)
• Today we are running with 81 fibers sending data to the HTRs– Took a quick 5 minute run (0.5x1012 bits)– All fibers link up nicely and keep their links– 76 show no errors (93.8 ± 2.7% error free)– 2 had 2 errors, 1 had 5, 1 had 9, 1 had 156
• Will investigate these this week• Try more cleaning, and tweak VCSEL current to see what happens• Take 10 minutes worth, see how high an error-free rate we can get
CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 15
Level 1 Latency
• As of this year, we were close– Within 1-2 ticks away from the budget
• The ball’s in Wesley’s court• He has caved from his original 20m down to 10m