cms emu trigger electronicswsmith/cms/padley_feb99.pdf · cms emu trigger electronics b. paul...
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Trigger Layout andResponsibilities
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z Latency: < 3.2 usz Fully pipelined synchronous
architecture, dead time =0z Maximum output rate: <15
kHzz Output to the Global Trigger:
up to 4 highest Pt muons ineach event
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z Put all front end, LCTgeneration and processingelectronics on chambers
z Issues:y Poor accessabilityy Power dissipationy Radiation hardness
New Design(Summer Ô98 UCLA)
z Simple front end boards onchambers
z All digital LCT generation andprocessing logic into 9U crateson periphery
MMMMUUUUOOOONNNN TTTTRRRRIIIIGGGGGGGGEEEERRRR SSSSYYYYSSSSTTTTEEEEMMMM
MMMMOOOODDDDUUUULLLLEEEE CCCCOOOOUUUUNNNNTTTT ((((UUUUCCCCLLLLAAAA,,,,
OOOOSSSSUUUU,,,, RRRRIIIICCCCEEEE,,,, UUUUFFFF))))
4Anode LCT Module - 504
4Cathode LCT Module - 504
4Trigger Motherboard - 264
4DAQ Motherboard - 264
4Port Card - 60
4Clock and Control Board - 126
4Sector Receiver - 24
4Sector Processor - 24
4Sorter - 1
4 Total - 1771
EMU TriggerMotherboard
z One board for two chambersz Receives up to two anode and
two cathode LCTÕsz Matches them in timez Passes them on to Port Cardz 9U VME board with interface
z We have proposal to allow theuse of RPC information toresolve ghosts if needed
MBSchematic(and changes)
From port card
VME Interface(New)
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MMMMOOOOTTTTHHHHEEEERRRRBBBBOOOOAAAARRRRDDDD
INTERFACE ADDRESS24
CLCT2
LB2
CLCT1
CLOCK40DES1, BX0, START COUNT
LUT RAM
RECEIVER
CLCT2
J1
PREPROCESSING
CLCT1
RPC
ALCT2
ALCT1
LB2 PREPROCESSINGCONTROL
BACKPLANECUSTOM
AND
LUT RAM
RECEIVER
ANODE
RECEIVER
RECEIVER
RPC2 LOGIC
RECEIVER
RECEIVER
RECEIVER
ALCT2
RECEIVER
RECEIVER
LB1
MPC
LOGIC
LOGIC
MUON TRIGGER MOTHERBOARD BLOCK DIAGRAM
CSC2
CSC1
RPC
PREPROCESSING
RECEIVER
LOGICPREPROCESSING
PREPROCESSING
PREPROCESSING
ALCT1
FROM
FROM
CATHODE
RECEIVER
LB1
AND
RECEIVER
DATA16
MPC
LOGIC
FROM
VME
LOGIC
ANODE
FROM
RPC1
RECEIVER
CATHODE
LB3
LB3
RECEIVER
CHANNEL
CHANNEL
LINK
LINK
TRANSMITTERS
TRANSMITTERS
TWO MUONS
TWO MUONS
Summer 98TestBeam Prototypes
Engineering "proofs-of-principle"
z Custom analog ASICs(preamps, disc's,comparators)
z Wide use of FPGAs at 40MHz
z High-speed LVDS channellinks
z Clock distribution frommotherboard
z Trigger drives DAQ systemreadout
MotherboardPrototype
z CAMAC boardz Communicate with FE via
LVDSz Send Clock to FE from quartz
or external generatorz Selected LCTÕs stored in FIFO
for reading by CAMACz Board is tested and working at
40 MHz.
It was built,and worked!
By that I mean
z Communicated with LCT cardvia National channel link LVDS
z Distributed clockz Correctly selected ÒbestÓ LCTÕsz We could study BXN matchingy but we could not test the BXN
PLD code¥ Its tough testing this in an
asynchronous beam.
BXN MatchingStudy
Excess
GIF
Turned
OFF
|BXN mismatch| > 1
2% of the time
BXN MatchingStudy
In this case 3.2% excess
GIFTurnedOn
Caveat Emptor
z It must be noted that thoseBXN matching results areusing the worst possible timingyou could get from the Anodes
z There is no way in this testdata to correct the BXN fromthe anode as will be done inreality.
z Thus the results representupper limits.
Trigger MotherboardNew Prototype DesignStatus
z Inputs from LCT modules andoutputs to Port Card arespecified
z PLD design 60% completedz Schematic design in progress
The Port Card
The Port Card
z Serves one sector of 8 or 9chambers
z Receives up to 18 LCTÕs frommotherboards
z Selects the best 3 and sendsto sector receivers on opticalcable
z VME 9U board
Port Card
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DATA16
ADDRESS24
CONTROL
J1
VME
INTERFACE
MUON PORT CARD BLOCK DIAGRAM
CUSTOMBACKPLANE
CLOCK40DES1, BX0, START COUNT
OPTICAL MODULE
OPTICAL MODULE
OPTICAL MODULE
OPTICAL MODULE
OPTICAL MODULE
OPTICAL MODULE
G-LINK
G-LINK
G-LINK
G-LINK
G-LINK
G-LINK
CONNECTOR
THREE MUONS TO
SECTOR RECEIVER
MEZZANINE BOARD
RECEIVERAND
PIPELINE
PIPELINE
RECEIVERAND
RECEIVERAND
PIPELINE
PIPELINE
RECEIVERAND
RECEIVERAND
PIPELINE
PIPELINEAND
RECEIVER
PIPELINE
RECEIVERAND
RECEIVERAND
PIPELINE
PIPELINEAND
RECEIVER
SORTING LOGIC
2 MUONS TMB1
2 MUONS TMB2
2 MUONS TMB3
2 MUONS TMB4
2 MUONS TMB5
2 MUONS TMB6
2 MUONS TMB7
2 MUONS TMB8
2 MUONS TMB9
PORT CARD DESIGNSTATUS
z Inputs from Trigger Motherboardand outputs to Sector Receiver arespecified
z Chipset and Optical Modules forcommunication with SectorReceiver are defined
z Sorting Logic designed and underoptimization now
z Schematic design will start soon
HardwiredLimitations
z Note restrictions of thescheme
z 1 stub per FE cardz 2 stubs per chamberz 3 stubs per 20 or degree
sector
Consequence of descope, mustuse 60 degree sectors instations>1
In station 1 use 20degree sectors tolimit number ofMboards to 9
This used to be 30degrees
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z DISTRIBUTES TTC SIGNALS TO ALLTRIGGER 9U VME MODULES
z UNIFIED DESIGN FOR TRIGGER ANDSECTOR PROCESSOR CRATES
z ABLE TO GENERATE TTC SIGNALS FROMBUILD-IN SIMULATOR
z VME 9U MODULE
ADDRESS
DATA
CONTROL
VMEINTERFACE
BACKPLANE
DIFFERENTIAL
DRIVERS
MUX
MUX
TTCrxBOARDOPTICAL
CABLEFROM TTC
CLOCK
CONTROL
VME 9UMODULE
TTCrxSIMULATOR
MUON CLOCK AND CONTROL BOARD
J1
CUSTOMBACKPLANE
CLOCK40DES1BX ZEROBCR, ECRL1ACC
Clock and ControlBoard Design Status
z Number and list of signals whichshould be distributed from TTC totrigger modules will be finalizedsoon
z Initial proposal on custombackplane is ready
z Schematic design will start soon
MMMMUUUUOOOONNNN SSSSOOOORRRRTTTTEEEERRRR
z RECEIVES 72 MUONS FROM 24 SECTORPROCESSORS (3 MUONS PER SECTORPROCESSOR)
z SELECTS FOUR BEST MUONS AND SENDSTHEM TO GLOBAL MUON TRIGGER
z VME 9U MODULE
CUSTOM
INTERFACE
J1
ADDRESS24
MUON SORTER BLOCK DIAGRAM
VME
CONTROL
DATA16
CLOCK40DES1, BX0, START COUNT
RECEIVER_1
RECEIVER_2
RECEIVER_3
RECEIVER_24
RECEIVER_23
72 MUONSFROM
24 SECTORPROCESSORS
TRANSMITTER
TRANSMITTER
TRANSMITTER
TRANSMITTER
MUON_1
MUON_2
MUON_3
MUON_4
TO GLOBAL MUON TRIGGER
SORTING LOGIC
4 OUT OF 72
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SSSSTTTTAAAATTTTUUUUSSSS
z General requirements (inputsfrom Sector Processors andoutputs to Global Trigger) arespecified
z Basic sorting unit (4 bestpatterns out of 8) initial designis completed
z Optimization and timinganalysis in progress
z Initial specification will beprepared this year
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TTTTRRRRIIIIGGGGGGGGEEEERRRR LLLLAAAATTTTEEEENNNNCCCCYYYY
10
100
1000
10000
100000
1000000
17 BX 27 BX 33 BX 39 BX 80 BX 92 BX
FEB
LCT TMB
MPC
SP
MS
1 BX = 25 ns