cmpe2001 foundations of digital design semester 1,...

Unit study package code: CMPE2001

Mode of study: Internal

Tuition pattern summary: This unit does not have a fieldwork component.

Credit Value: 25.0

Pre-requisite units: 307543 (v.0) Electrical Systems 100 or any previous version OR ELEN1000 (v.0) Electrical Systems or any previous version

Co-requisite units: Nil

Anti-requisite units: Nil

Result type: Grade/Mark

Approved incidental fees: Information about approved incidental fees can be obtained from our website. Visit fees.curtin.edu.au/incidental_fees.cfm for details.

Unit coordinator:

Title: DrName: Wei WongPhone: +61 8 9266 4194Email: [email protected]: Building: 314 - Room: 328

Teaching Staff:

Name: Dr Wei-Juet (Bert) WongPhone: +61 8 9266 4194Email: [email protected]: Building: 314 - Room: 328

Administrative contact:

Name: Ms Michelle CutinhaPhone: +61 8 9266 7428Email: [email protected]: Building: 314 - Room: 340

Learning Management System: Blackboard (lms.curtin.edu.au)

Unit Outline

CMPE2001 Foundations of Digital Design Semester 1, 2017

Faculty of Science and Engineering Department of Electrical and Computer Engineering

CMPE2001 Foundations of Digital Design Bentley Campus 23 Feb 2017 Department of Electrical and Computer Engineering, Faculty of Science and Engineering

Page: 1 of 12CRICOS Provider Code 00301J

The only authoritative version of this Unit Outline is to be found online in OASIS

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Acknowledgement of Country We respectfully acknowledge the Indigenous Elders, custodians, their descendants and kin of this land past and present. The Centre for Aboriginal Studies aspires to contribute to positive social change for Indigenous Australians through higher education and research.

Syllabus This unit focuses on digital design and computer architecture. It provides grounding on the foundations of digital logic design from the perspective of a Microprocessor without Interlocked Pipeline Storage (MIPS) processor architecture. Basic techniques on Boolean algebra and minimisation are covered to design combinational circuits and sequential systems which are building blocks to a MIPS. Using Electronic Design Automation (EDA) tools and Very High Speed Integrated Circuit Hardware Description Language (VHDL) and examining assembly programs, students will be able to gain further understanding in the complex world of computer architecture design.

Introduction In this unit you will be introduced to the fascinating world of Digital Design. We will cover the main concepts and techniques that will allow you to design and understand the function of a small computer.

Unit Learning Outcomes All graduates of Curtin University achieve a set of nine graduate attributes during their course of study. These tell an employer that, through your studies, you have acquired discipline knowledge and a range of other skills and attributes which employers say would be useful in a professional setting. Each unit in your course addresses the graduate attributes through a clearly identified set of learning outcomes. They form a vital part in the process referred to as assurance of learning. The learning outcomes tell you what you are expected to know, understand or be able to do in order to be successful in this unit. Each assessment for this unit is carefully designed to test your achievement of one or more of the unit learning outcomes. On successfully completing all of the assessments you will have achieved all of these learning outcomes.

Your course has been designed so that on graduating we can say you will have achieved all of Curtin's Graduate Attributes through the assurance of learning process in each unit.

Curtin's Graduate Attributes

On successful completion of this unit students can: Graduate Attributes addressed

1 Explain the importance of digital electronics in modern societies

2 Apply common digital techniques to design digital logic systems

3 Distinguish the key parts of the MIPS single-cycle architecture which is valuable for understanding modern computer architectures

4 Examine assembly programs for the MIPS architecture

5 Work in a team to solve digital logic problems

Apply discipline knowledge Thinking skills (use analytical skills to solve problems)

Information skills (confidence to investigate new ideas)

Communication skills Technology skillsLearning how to learn (apply principles learnt to new situations) (confidence to tackle unfamiliar problems)

International perspective (value the perspectives of others)

Cultural understanding (value the perspectives of others)

Professional Skills (work independently and as a team) (plan own work)

Find out more about Curtin's Graduate attributes at the Office of Teaching & Learning website: ctl.curtin.edu.au





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Learning Activities To support your learning of Digital Design and Computer Architecture, you will be exposed to an assortment of learning experiences: Lectures, laboratories, tutorials, and internet resources. It is up to you how much benefit you take from these experiences.

Learning Resources Essential texts

The required textbook(s) for this unit are:

l This textbook is mandatory. You either purchase the Paperback or eBook.

l D. M. Harris and S. L. Harris, Digital Design and Computer Architecture, 2nd ed., Waltham, MA: Morgan Kaufmann, 2012.

l Paperback ISBN: Shown below in () l eBook ISBN: 978-0-12-397816-5

l Always check with your university's bookshop for availability before purchasing elsewhere (further details available in Blackboard Announcements).

(ISBN/ISSN: 978-0-12-394424-5)

Other resources

Below is a list of useful resources.

l S. T. Karris, Digital Circuit Analysis and Design with Simulink Modeling and Introduction to CPLDs and FPGAs, 2nd ed., Fremont, CA: Orchard Publications, 2007.

l M. M. R. Mano, C. R. Kime, and T. Martin, Logic and Computer Design Fundamentals, 5th ed., Hoboken, NJ: Pearson, 2015.

l A. Omondi, Computer Arithmetic Systems: Algorithms, Architecture and Implementation, New York: Prentice Hall, 1994.

l P. Ashenden. (1990, July). The VHDL Cookbook (1st ed.) [Online]. Available: http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf





http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

Assessment Assessment schedule

Detailed information on assessment tasks

1. To solve the eTests you will need to review your lecture notes and additional resources. eTests are an excellent opportunity to review the unit's material and identify possible questions. eTests will be open for approximately 7 days after the corresponding lecture. You may attempt them up to maximum of two times. The marking scheme is detailed in Blabkboard. The intention is that you use eTests to reaffirm some of the most fundamental concepts of the unit.

2. In labs you will put in practice concepts and information you learned in lectures and tutorials. In the lab you will have the opportunity to "play with the toys" to complete a set of tasks involving digital design. You will have to work with a partner and learn how to manage the workload between the two. The lab is the place to give you some hands-on experience. Do the thinking before coming to the lab. It is essential that you complete any pre-lab work before attending the labs.

3. The mid-semester test is your opportunity to obatain an interim feedback on your progress midway through the unit. The test will be an excellent indicator (measure) of your knowledge on the subject matter of digital design and what you need to do to address any issues arising from achieving the required unit learning outcomes.

4. The final exam is your opportunity to demonstrate how well you can apply the knowledge obtained in this unit to solve problems on digital design and computer architecture. It is meant to be challenging to accurately reflect your command of the subject. The final exam will allow the unit coordinator to differentiate students according to how well they attained the unit learning outcomes.

Pass requirements Achieve a grade greater than or equal to 5, or a mark greater than or equal to 50. Attempt at least one Laboratory Rubric Script, one eTest, the Mid-Semester Test and the Final Examination. Obtain a minimum of 40/100 in the Final Examination. The Final Mark will be derived from the weighted-sum of the individual components. Interim results will be available from Blackboard.

Task Value % Date DueUnit Learning Outcome(s)

Assessed

1

eTest x 10 20 percent Week: Starts during Teaching Week 2 Day: Announced in Blackboard/Lectures Time: Typically one week

1,2,3,4

2

Laboratory rubric scripts x 5 20 percent Week: Starts during Teaching Week 2 Day: Depends on enrolment Time: Depends on enrolment

2,3,4,5

3

Mid-semester test 20 percent Week: Mid-semester period Day: TBA Time: TBA

1,2,3

4Final examination 40 percent Week: Exam period

Day: TBA Time: TBA

1,2,3,4





Fair assessment through moderation

Moderation describes a quality assurance process to ensure that assessments are appropriate to the learning outcomes, and that student work is evaluated consistently by assessors. Minimum standards for the moderation of assessment are described in the Assessment and Student Progression Manual, available from policies.curtin.edu.au/policies/teachingandlearning.cfm

Late assessment policy

This ensures that the requirements for submission of assignments and other work to be assessed are fair, transparent, equitable, and that penalties are consistently applied.

1. All assessments students are required to submit will have a due date and time specified on this Unit Outline. 2. Students will be penalised by a deduction of ten percent per calendar day for a late assessment submission

(e.g. a mark equivalent to 10% of the total allocated for the assessment will be deducted from the marked value for every day that the assessment is late). This means that an assessment worth 20 marks will have two marks deducted per calendar day late. Hence if it was handed in three calendar days late and given a mark of 16/20, the student would receive 10/20. An assessment more than seven calendar days overdue will not be marked and will receive a mark of 0.

Assessment extension

A student unable to complete an assessment task by/on the original published date/time (e.g. examinations, tests) or due date/time (e.g. assignments) must apply for an assessment extension using the Assessment Extension form (available from the Forms page at students.curtin.edu.au/administration/) as prescribed by the Academic Registrar. It is the responsibility of the student to demonstrate and provide evidence for exceptional circumstances beyond the student's control that prevent them from completing/submitting the assessment task.

The student will be expected to lodge the form and supporting documentation with the unit coordinator before the assessment date/time or due date/time. An application may be accepted up to five working days after the date or due date of the assessment task where the student is able to provide an acceptable explanation as to why he or she was not able to submit the application prior to the assessment date. An application for an assessment extension will not be accepted after the date of the Board of Examiners' meeting.

Deferred assessments

Supplementary assessments

Supplementary assessments, if granted by the Board of Examiners, will have a due date or be held between 18/07/2017 and 21/07/2017 . Notification to students will be made after the Board of Examiners’ meeting via the Official Communications Channel (OCC) in OASIS.

It is the responsibility of students to be available to complete the requirements of a supplementary assessment. If your results show that you have been granted a supplementary assessment you should immediately check OASIS for details.

If your results show that you have been granted a deferred assessment you should immediately check OASIS for details.

Deferred examinations/tests will be held from 18/07/2017 to 21/07/2017 . Notification to students will be made after the Board of Examiners’ meeting via the Official Communications Channel (OCC) in OASIS.





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Reasonable adjustments for students with disabilities/health circumstances likely to impact on studies

A Curtin Access Plan (CAP) is a document that outlines the type and level of support required by a student with a disability or health condition to have equitable access to their studies at Curtin. This support can include alternative exam or test arrangements, study materials in accessible formats, access to Curtin’s facilities and services or other support as discussed with an advisor from Disability Services (disability.curtin.edu.au). Documentation is required from your treating Health Professional to confirm your health circumstances.

If you think you may be eligible for a CAP, please contact Disability Services. If you already have a CAP please provide it to the Unit Coordinator at the beginning of each study period.

Referencing style

The referencing style for this unit is IEEE.

More information on this referencing style can be obtained at http://libguides.library.curtin.edu.au/c.php?g=202427&p=1332519

Copyright © Curtin University. The course material for this unit is provided to you for your own research and study only. It is subject to copyright. It is a copyright infringement to make this material available on third party websites.

Academic Integrity (including plagiarism and cheating) Any conduct by a student that is dishonest or unfair in connection with any academic work is considered to be academic misconduct. Plagiarism and cheating are serious offences that will be investigated and may result in penalties such as reduced or zero grades, annulled units or even termination from the course. Assessments under investigation will not be given a mark until the matter is concluded. This may result in the unit grade being withheld or a grade of Fail Incomplete (F-IN) until a decision has been made by the Student Disciplinary Panel. This may impact on enrolment in further units/study periods.

Plagiarism occurs when work or property of another person is presented as one's own, without appropriate acknowledgement or referencing. Submitting work which has been produced by someone else (e.g. allowing or contracting another person to do the work for which you claim authorship) is also plagiarism. Submitted work is subjected to a plagiarism detection process, which may include the use of text matching systems or interviews with students to determine authorship.

Cheating includes (but is not limited to) asking or paying someone to complete an assessment task for you or any use of unauthorised materials or assistance during an examination or test.

From Semester 1, 2016, all incoming coursework students are required to complete Curtin’s Academic Integrity Program (AIP). If a student does not pass the program by the end of their first study period of enrolment at Curtin, their marks will be withheld until they pass. More information about the AIP can be found at: https://academicintegrity.curtin.edu.au/students/AIP.cfm

Refer to the Academic Integrity tab in Blackboard or academicintegrity.curtin.edu.au for more information, including student guidelines for avoiding plagiarism.





http://life.curtin.edu.au/health-and-wellbeing/CAP.htm

http://life.curtin.edu.au/health-and-wellbeing/disability_services.htm

http://life.curtin.edu.au/health-and-wellbeing/disablity_services_eligibility.htm#/health-and-wellbeing/10126.htm

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http://libguides.library.curtin.edu.au/c.php?g=202427&p=1332519

http://libguides.library.curtin.edu.au/c.php?g=202427&p=1332519

https://academicintegrity.curtin.edu.au/students/AIP.cfm

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Information and Communications Technology (ICT) Expectations Curtin students are expected to have reliable internet access in order to connect to OASIS email and learning systems such as Blackboard and Library Services.

You may also require a computer or mobile device for preparing and submitting your work.

For general ICT assistance, in the first instance please contact OASIS Student Support: oasisapps.curtin.edu.au/help/general/support.cfm

For specific assistance with any of the items listed below, please contact The Learning Centre: life.curtin.edu.au/learning-support/learning_centre.htm

l Using Blackboard, the I Drive and Back-Up files l Introduction to PowerPoint, Word and Excel





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Additional information

1 ENGINEERS AUSTRALIA Stage 1 competencies and elements of competency assessed in this unit.

1. KNOWLEDGE AND SKILL BASE

1.1 Comprehensive, theory based understanding of the underpinning natural and physical sciences and the engineering fundamentals applicable to the engineering discipline. 1.2 Conceptual understanding of the, mathematics, numerical analysis, statistics, and computer and information sciences which underpin the engineering discipline. 1.3 In-depth understanding of specialist bodies of knowledge within the engineering discipline. 1.4 Discernment of knowledge development and research directions within the engineering discipline. 1.5 Knowledge of contextual factors impacting the engineering discipline. 1.6 Understanding of the scope, principles, norms, accountabilities and bounds of contemporary engineering practice in the specific discipline.

2. ENGINEERING APPLICATION ABILITY

2.1 Application of established engineering methods to complex engineering problem solving. 2.2 Fluent application of engineering techniques, tools and resources. 2.3 Application of systematic engineering synthesis and design processes. 2.4 Application of systematic approaches to the conduct and management of engineering projects.

3. PROFESSIONAL AND PERSONAL ATTRIBUTES

3.1 Ethical conduct and professional accountability. 3.2 Effective oral and written communication in professional and lay domains. 3.3 Creative, innovative and pro-active demeanour. 3.4 Professional use and management of information. 3.5 Orderly management of self, and professional conduct. 3.6 Effective team membership and team leadership.

2 Levels of Learning

Remembering

l Observation and recall of information; knowledge of dates, events, places, materials, objects; knowledge of major processes; mastery of subject matter

Assessment Item Unit Outcome Assessed EA Professional Competencies Assessed1

Levels of Learning2

eTest × 10 1, 2, 3, 4 1.1, 1.2, 2.1, 3.5

Comprehending Applying Analysing

Laboratory Rubric Script × 5 2, 3, 4, 5 1.1, 1.2, 2.1, 2.2, 3.1, 3.2, 3.3, 3.5, 3.6


Mid-Semester Test 1, 2, 3 1.1, 1.2, 2.1


Final Examination 1, 2, 3, 4 1.1, 1.2, 2.1






http://www.engineersaustralia.org.au/sites/default/files/shado/Education/Program%20Accreditation/110318%20Stage%201%20Professional%20Engineer.pdf

http://www.curtin.edu.au/cli/local/docs/TL_Handbook.pdf

Comprehending

l Understand information, grasp meaning; translate knowledge into new contexts; compare and contrast; order, group, infer causes, predict consequences

Applying

l Use information; use methods, concepts, theories in new situations; solve problems using required skills or knowledge; use equipment, tools

Analysing

l Discern patterns; organise parts; recognise hidden meanings; identify components, simplify complex information; metacognition

Evaluating

l Compare and discriminate between ideas; think critically, make judgments about worth (based on stated premises); assess the value of theories, make choices based on reasoned argument; verify or question the value of evidence

Creating

l Combining ideas to develop an original idea or product, engage in creative thinking

Enrolment

It is your responsibility to ensure that your enrolment is correct - you can check your enrolment through the eStudent option on OASIS, where you can also print an Enrolment Advice.

Student Rights and Responsibilities It is the responsibility of every student to be aware of all relevant legislation, policies and procedures relating to their rights and responsibilities as a student. These include:

l the Student Charter l Values and Signature Behaviours l the University's policy and statements on plagiarism and academic integrity l copyright principles and responsibilities l the University's policies on appropriate use of software and computer facilities

Information on all these things is available through the University's "Student Rights and Responsibilities" website at: students.curtin.edu.au/rights.





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Student Equity There are a number of factors that might disadvantage some students from participating in their studies or assessments to the best of their ability, under standard conditions. These factors may include a disability or medical condition (e.g. mental illness, chronic illness, physical or sensory disability, learning disability), significant family responsibilities, pregnancy, religious practices, living in a remote location or another reason. If you believe you may be unfairly disadvantaged on these or other grounds please contact Student Equity at [email protected] or go to http://eesj.curtin.edu.au/student_equity/index.cfm for more information

You can also contact Counselling and Disability services: http://www.disability.curtin.edu.au or the Multi-faith services: http://life.curtin.edu.au/health-and-wellbeing/about_multifaith_services.htm for further information.

It is important to note that the staff of the university may not be able to meet your needs if they are not informed of your individual circumstances so please get in touch with the appropriate service if you require assistance. For general wellbeing concerns or advice please contact Curtin's Student Wellbeing Advisory Service at: http://life.curtin.edu.au/health-and-wellbeing/student_wellbeing_service.htm

Recent unit changes Students are encouraged to provide unit feedback through eVALUate, Curtin's online student feedback system. For more information about eVALUate, please refer to evaluate.curtin.edu.au/info/.

Recent changes to this unit include: In response to comments received from past students through eVALUate, some unit materials and assessments have been revised. A Mid-Semester Test is also introduced into the unit.

To view previous student feedback about this unit, search for the Unit Summary Report at https://evaluate.curtin.edu.au/student/unit_search.cfm. See https://evaluate.curtin.edu.au/info/dates.cfm to find out when you can eVALUate this unit.





mailto:[email protected]

http://eesj.curtin.edu.au/student_equity/index.cfm

http://www.disability.curtin.edu.au/

http://life.curtin.edu.au/health-and-wellbeing/about_multifaith_services.htm

http://life.curtin.edu.au/health-and-wellbeing/student_wellbeing_service.htm

http://evaluate.curtin.edu.au/info/index.cfm

https://evaluate.curtin.edu.au/student/unit_search.cfm

https://evaluate.curtin.edu.au/info/dates.cfm

Program calendar Semester 1 2017

Week Week Begin Date

(Mon)

Lecture Weekly Topic(s) Tutorial Lab

eTest

Assessment Due

Orientation 20 February Orientation Week

1 27 February 1×2-hrs Unit Introduction, Binary Systems & Logic Gates

No Tutorial No Labs

(1 or 2)×1-hr

eTest 1

2 6 March 1×2-hrs Combinational Circuits, Minimisation: Boolean Algebra

1×2-hrs 1×2-hrs

(1 or 2)×1-hr

Lab 1 Prac, eTest 1, eTest 2

3 13 March 1×2-hrs Minimisation: Karnaugh Maps, Decoders & Multiplexers

1×2-hrs 1×2-hrs

(1 or 2)×1-hr

Lab 1 Rubr, eTest 2, eTest 3

4 20 March 1×2-hrs Numeric Systems, Computer Arithmetic

1×2-hrs 1×2-hrs

(1 or 2)×1-hr


5 27 March 1×2-hrs Full-Adders, Arithmetic Logic Unit (ALU)

1×2-hrs 1×2-hrs

(1 or 2)×1-hr


6 3 April 1×2-hrs (*Mid-Semester Test), Latches, Flip-Flops &

State Diagrams, Sequential Systems

1×2-hrs 1×2-hrs

(1 or 2)×1-hr


7 10 April Tuition Free Week eTest 6

8 17 April Tuition Free Week eTest 6

9 24 April 1×2-hrs Counters, Registers, Memories & Programmable Logic

1×2-hrs 1×2-hrs

(1 or 2)×1-hr

Lab 3 Rubr, eTest 7

10 1 May 1×2-hrs Introduction to VHDL: Combinational Circuits,

Sequential Circuits

1×2-hrs 1×2-hrs

(1 or 2)×1-hr


11 8 May 1×2-hrs Processor Architecture, MIPS Architecture &

Instruction Set

1×2-hrs 1×2-hrs

(1 or 2)×1-hr


12 15 May 1×2-hrs MIPS Single-Cycle Processor: Datapath,

Control Unit

1×2-hrs 1×2-hrs

(1 or 2)×1-hr


13 22 May 1×2-hrs Assembly Language, Procedures & Stack

1×2-hrs 1×2-hrs

(1 or 2)×1-hr

Lab 5 Rubr, eTest 10

14 29 May 1×2-hrs Microcontrollers & I/O Devices (TBA),

(Unit Revision)

1×2-hrs 1×2-hrs

Catch-Up Labs





* Details on the Mid-Semester Test will be made available in Blackboard closer to date.

15 5 June Study Week

16 12 June Examinations

17 19 June Examinations





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