cmos topic 7 -_design_methodology

faizah amir/jke/polisas 1

EE603 – CMOS INTEGRATED CIRCUIT DESIGN

Faizah Amir

IC DESIGN METHODOLOGY

At the end of this session, you should be able to:

1. explain the IC design methodology.

2. explain full custom design methodology.

3. explain semi-custom design methodology.

4. explain Programmable Logic Devices (PLD).



DESIGN METHODOLOGY TREE DIAGRAM


STANDARD IC

Standard IC :

• Integrated circuits designed and fabricated for general purpose use.

• Standard IC is available in the market at a very low cost.

• Examples of standard ICs:74 - SERIES TTL, 4000 - SERIES CMOS, OP-AMP, TIMER, INSTRUMENTATION AMPLIFIER, MEMORY, MICROCONTROLLER ,etc.



EXAMPLES OF STANDARD IC

74-series TTL

4000 series CMOS

Op-Amp Timer

Memory

Microcontroller


EXAMPLES OF STANDARD IC



ASICs

• Progress in the fabrication of IC's has enabled the designer to create fast and powerful circuits in smaller and smaller devices.

• This also means that we can pack a lot more of functionality into the same area.

• The biggest application of this ability is found in the design of ASICs .


ASICs

ASICs stands for : Application Specific Integrated Circuits

• ASICs are IC's that are created for specific purposes - each device is created to do a particular job.

• ASICs are produced for only one or a few customers or applications.

• ASICs are devices made for a specific application such as a mobile phone.


EXAMPLES OF ASICs



EXAMPLES OF ASICs

GRAPHIC MEDIA ACCELERATOR

SMART CARD CHIPS



ASICs Advantages

ASICs

COMPARISON BETWEEN ASICs AND STANDARD IC

ASICs STANDARD IC

1. Chip is designed and

manufactured

specifically to meet a

particular function.

2. Each manufacturer

produces a different

chip design.

1. Integrated circuits can

be used by any party or

user.

2. Most manufacturers

produce chips with

similar function.



ADVANTAGES & DISADVANTAGES OF ASICs


ADVANTAGES DISADVANTAGES

� Ability to perform a function that

cannot be done using standard

IC.

� Improve the performance of a

circuit.

� Reduce the volume, weight and

power requirement of a circuit.

� Increase the reliability of a given

system by integrating a large

number of functions on a single

chip / a small number of chips.

� High design security features.

(Piracy prevention)

� High design and processing

cost.

� Complex chip fabrication

equipment is required.

� Advanced computer software

is required in designing the

layout.

� Not economical if market

demand is low.




FULL CUSTOM DESIGN

�All the circuits and mask layouts are

completely designed for the requirements of

a particular IC.

�A microprocessor is an example of a full-

custom design IC—designers spend many

hours squeezing the most out of every last

square micron of microprocessor chip space

by hand.


FULL CUSTOM DESIGN

� It allows designers to include analog

circuits, optimized memory cells.

� Full-custom ICs are the most expensive to

manufacture and to design and only

economic at very high volumes

(millions/year).

�The manufacturing lead time (the time it

takes just to make an IC—not including

design time) is typically eight to ten weeks

for a full-custom IC.


ADVANTAGES & DISADVANTAGES OF FULL CUSTOM DESIGN METHOD


Advantages Disadvantages

1. High component density

per chip.

2. Chip is able to operate

at high frequency.

3. Flexible design.

4. Small chip size.

1. High design and

manufacturing cost.

2. Design is exposed to

errors.

3. Time-consuming design.

4. Advanced computer

software is required in

design process.


SEMI CUSTOM DESIGN

�To make ASICs economic at lower volumes,

the semi-custom concept was introduced

where many applications share the same

basic configuration of logic cells.

�It is only the final interconnect stage that is

different to give the different chips.



SEMI CUSTOM DESIGN

�The mask layers are customized to fulfill the

requirements of a particular IC.

�Often used for speedy design with less effort

compared to full custom design.


SEMI CUSTOM DESIGN

�There are 3 types of semi custom

design:-

1. Gate array

2. Standard Cell

3. Programmable Logic Device (PLD)



Mask set for full custom & semi custom


SEMI CUSTOM IC

GATE ARRAYGATE ARRAYGATE ARRAYGATE ARRAY1. Gate arrays are integrated circuits containing la rge

numbers of digital gates or transistor cells, which can be interconnected in different ways to implement various logic functions.

2. Gate array consists of transistors, usually arran ged in two pairs of PMOS and NMOS.

3. Wafers containing these gate arrays have been processed up to all steps except the metallization layers.


4. Using computer-aided-design tools, only the metallization layer patterns are required to begenerated from the circuit specification, and the fabrication time can be very short.

5. Gate arrays can have several metallization layer s to facilitate interconnection .

6. ASIC vendors offer a selection of gate array cel ls, with a different total numbers of transistors on ea ch cell, for example, gate arrays with 50k-, 75k-, and 100k-gates.


SEMI CUSTOM IC – gate array


SEMI CUSTOM IC

GATE ARRAY FLOOR PLAN




Gate array




ADVANTAGES & DIS ADVANTAGES OF ADVANTAGES & DIS ADVANTAGES OF ADVANTAGES & DIS ADVANTAGES OF ADVANTAGES & DIS ADVANTAGES OF

GATE ARRAY GATE ARRAY GATE ARRAY GATE ARRAY

ADVANTAGES DISADVANTAGES

�Cheaper process

�Speedy design

�Low power dissipation IC

�Advanced CAD software

is required in design.

�Not all of the gates

offered by the vendor are

being used in the design.

�Optimum circuit

performance cannot be

achieved.


GATE ARRAY

IC DESIGN METHODOLOGYSEMI CUSTOM IC

STANDARD CELLSTANDARD CELLSTANDARD CELLSTANDARD CELL

1. Standard cell design involves the use of pre-designed standard cell @ library cell that has been and stored in database.

2. Standard cell @ library cell consists of simple circuit such as inverter or logic gates (AND, OR, XOR, XNOR, flip-flop), and complex circuit such as register, adder, ROM and RAM.



STANDARD CELLSTANDARD CELLSTANDARD CELLSTANDARD CELL

3. Design is carried out by simply using the pre-designed cells from the library and then connect the cells so that certain functions can be implemented.

4. To facilitate placement and routing, the standard cells are designed to have equal height but variable widths, so that the final IC layout will have a regular pattern with rows of cells and interconnect routing running between the rows.

STANDARD CELL FLOOR PLANSTANDARD CELL FLOOR PLANSTANDARD CELL FLOOR PLANSTANDARD CELL FLOOR PLAN


I/O Pads

LOGICBLOCK

BLOCK

Standard Cell

Routing

Standard Cell

Routing

Standard Cell

Routing

Standard Cell

Routing


ADVANTAGES AND DISADVANTAGES ADVANTAGES AND DISADVANTAGES ADVANTAGES AND DISADVANTAGES ADVANTAGES AND DISADVANTAGES

OF STANDARD CELLOF STANDARD CELLOF STANDARD CELLOF STANDARD CELLADVANTAGEADVANTAGEADVANTAGEADVANTAGE DISADVANTAGEDISADVANTAGEDISADVANTAGEDISADVANTAGE

�THE PERCENTAGE OF USING ALL

GATES ARE VERY HIGH.

� PRODUCE HIGH PERFORMANCE

CHIP.

�THE OPTIMUM CHIP SIZE CAN BE

ACHIEVED.

�THE CHIP CAN BE GUARANTEED

TO FUNCTION WELL FOR THE

FIRST TIME IT IS DESIGNED .

�the standard cells MUST BE

designed to have equal height, so

that the final IC layout will have a

regular pattern .

�HIGH DESIGN COST.

� design cannot be done if the

required cell is not available in

the library.


PROGRAMMABLE LOGIC DEVICE PROGRAMMABLE LOGIC DEVICE PROGRAMMABLE LOGIC DEVICE PROGRAMMABLE LOGIC DEVICE

(PLD)(PLD)(PLD)(PLD)

Programmable Logic Device (PLD) is an array of logic gates that can be programmed by the user which contains functions of a small number of logic circuits in a single chip.

IC DESIGN METHODOLOGYDEFINITION


PROGRAMMABLE LOGIC DEVICE (PLD)

PROGRAMMABLE LOGIC DEVICE(PLD)

GENERAL CHARACTERISTICS OF PLD IC

1. PLD does not require a common mask layout in design.

2. The design time is shorter.

3. It consists of a large block of internal connections that can be a programmed.

4. Programming can be done at different stages:

i) at the earliest, it is programmed by the semiconductor

vendor (standard cell, gate array).

ii) by the designer prior to assembly or field deployment.

iii) by the user in circuit.


ADVANTAGES OF PLD COMPARED TO STANDARD IC & ASICs


1. Reduced complexity of circuit boards

• Lower power requirements

• Less board space

• Simpler testing procedures

2. Higher reliability

3. Design flexibility

PLD DESIGNBLOCK DIAGRAM OF PLD LOGIC


PLD DESIGN

PLD DESIGN


PLD DESIGN

TYPES OF PLD


ProgrammableLogic Devices

(PLD)

CPLDSPLD FPGA

•••• PROM

•••• PAL

•••• PLA


TYPES OF PLD

• SPLD – SIMPLE PROGRAMMABLE LOGIC DEVICE

• PROM – PROGRAMMABLE READ ONLY MEMORY

• PAL – PROGRAMMABLE ARRAY LOGIC

• PLA – PROGRAMMABLE LOGIC ARRAY

• FPGA – FIELD PROGRAMMABLE GATE ARRAY

• CPLD – COMPLEX PROGRAMMABLE LOGIC DEVICES


PLD DESIGNDIFFERENCES BETWEEN PROM, PAL, PLA

Summaries of differences between Programmable ROM (PROM), Programmable Array Logic (PAL), and Programmable Array Logic (PLA)

PROM PAL PLA

AND array (hardwired)

AND array (programmable)

AND array (programmable)

OR array(programmable)

OR array (hardwired)

OR array (programmable)


PLD DESIGNPROM ARCHITECTURE

= fixed by manufacturer

= programmed by user

� AND plane = Fixed� OR plane = Programmable

O0 = I0 I1 I2 I3 + I0 I1 I2 I3 + I0 I1 I2_ _ _ _ _ _

O1 = I0 I1 I2 I3__

O3 = I0 I1 I2 I3 + I0 I1I2

_ __ __

O0 O1 O2

O3

I0 I1 I2 I3

PLD DESIGNPAL ARCHITECTURE

• AND plane = programmable• OR plane = fixed

O0 O1 O2 O3

I0 I1 I2 I3

O0 = I0 I1 I2 I3 + I0 I1 I2 I3 + I0 I1 I2


PLD DESIGNPLA ARCHITECTURE

X1 X2 X3

f1 f2 f3

• Both AND & OR plane canbe programmed

f1 = X1 X2 + X1 X3 + X1 X2 X3

_ _ _

• Boolean Expression

• SchematicCapture

• Truth Table

PLD DESIGNPLD PROGRAMMING METHODS


PLD DESIGN

� Three methods of programming PLD:i) Schematic Capture.

ii) Boolean Expression using Hardware Description Language (HDL).

iii) Truth Table / State Diagram.

PLD PROGRAMMING METHODS

PLD PROGRAMMING METHOD

DESIGN LANGUAGE

Types of high level language used in PLD programming :-

•HDL (Hardware Description Language)� VHDL (Very High Speed IC HDL)�Verilog

•CUPL (Universal Compiler for Programmable Logic)•PALASM (PAL Assembler)•ABEL (Advanced Boolean Expression Language)


3 methods of memory storing in PLD:

1) FAMOS - Floating Gate Avalanche Injection Metal Oxide Semiconductor

2) Fuse3) Anti- Fuse

PLD MEMORY STORING METHOD

1. FAMOS TRANSISTORFAMOS - Floating Gate Avalanche Injection Metal Oxide

Semiconductor

FAMOS transistor is the basic building block used to construct the memory cells in non-volatile data storage such as flash, EPROM and

EEPROM memory.

Floating gate in FAMOS will trap and discharge

charges.

P

n+ n+

Gate

Floating Gate

SiO2

Gate

Physical Structure

Symbol



FAMOS TRANSISTOR

The data stored in the memory is non-volatile: data is still exist although the supply is removed.

P

n+ n+

+ + + + + + + +

Vg =0


TRANSISTOR FAMOS+25V

P subs

n+ n+

+16V

Depletion region

n channel

FAMOS in ON state:

High Voltage is supplied between Source and Drain ~ 16-20V.

High voltage is also supplied at the gate (~25V).

n channel exists at the wafer surface due to high voltage at

the gate.

The channel is tapered at the drain due to high voltage

between source-drain.

Source-drain voltage will accelerate electrons (kno wn as hot electrons)through the existing channel. Since the SiO 2 layer is very thin, this will

cause avalanche breakdown of the gate insulating la yer allowing electrons to travel through this SiO 2 layer to the floating gate, giving the floating gat e

electrode an electrical charge.



TRANSISTOR FAMOS


FAMOS in OFF state:

When the floating gate is charged, it modifies the

threshold voltage of the control gate, inhibiting its operation.

Thus, it can be set to lock the transistor in its off state,

distinguishing it from similar transistor which have not bee

charged (programmed).

+25V

P subs

n+ n+

+16V

Depletion region

n channel

The property of FAMOS transistor can be used to provide read-only memory (ROM) function.

The floating gate can be restored to its uncharged state by exposure to strong ultraviolet light which causes the charge to leak away.

Arrays of floating gate transistors in IC are used to provide erasable programmable read-only memory (EPROM). In practice, a programmed EPROM retains its data for about ten to twenty years and can be read an

unlimited number of times.

� Fuse is a two-terminal programmable element that is normally a low resistive element and is programmed or "blown" resulting in an open or high impedance.

2. FUSE



3. ANTI-FUSE

• Anti-fuse is a two-terminal element that is normally a high resistive element and is programmed to a low impedance.


DIFFERENCE BETWEEN FUSE AND ANTI-FUSE

Fuse links Anti-fuse links



LARGE SCALE PLD

CPLD & FPGA

CPLD

CPLDs

� CPLDs evolved from PAL\PLAs - as chip densities increased, it was natural for the PLD manufacturers to evolve their products into larger parts (several tens of thousands of gates).

� Larger sizes of CPLDs allow either more logic equations or more complicated designs to be realised.

LARGE SCALE PLD


CPLD

LARGE SCALE PLD

CPLDs - Applications

GPS Navigation Systems

- Hard disk controller- GPIO interface

- Timing configuration - LCD Timing Control - GPIO Expansion

- Power Management - Level Shifting

PDA



- Keypad scanner

- Logic consolidation

- Controller and interface conversion - Interface expansion

- Simple glue logic

PrinterGSM Phone


P1200 portable handsets (Shenzhen Huayu Communications Technology Company, China )

• Altera MAX II CPLD• Interfaces with:

- Radio Frequency Identification (RFID) reader- Infrared Data (IRDA) sensor

- Bluetooth interface



Robot controller CD/audio controller

FPGA

�This device is similar to the gate array, with the device shipped to the user with general-purpose metallization pre-fabricated, often with variable length segments or routing tracks.

�The device is programmed by turning on switches which make connections between circuit nodes and the metal routing tracks.

�The connection may be made by a transistor switch (which are controlled by a programmable memory element) or by an anti-fuse.

LARGE SCALE PLD


FPGA

LARGE SCALE PLD

FPGA

LARGE SCALE PLD


LARGE SCALE PLD

COMPARISON BETWEEN CPLD & FPGA

CPLD FPGA� Cheaper � More expansive

� Faster operation � Slower

� Contain less gates � Contain more gates

� Use for interfacing purpose � Use for heavy computation purpose

� Include built-in flash memory � Need external memory

Comparison between full custom and semi

custom design

Full Custom Semi customi. Small chip size. i. Large chip size.

ii. Large number of mask. ii. Small number of mask.

iii. Time-consuming design. iii. Faster design time.

iv. High circuit performance. iv. Low circuit performance.



DESIGN METHODOLOGY DIFFERENCES

Design

methodDesign cost Chip size

Operation

speed

Power

dissipation

No. of

mask

Design

time

Full

custom

The most

expensive

The

smallestHighest speed 5x Smaller Numerous

Time-

consuming

Standard

cellAverage Small High-speed 3x smaller Many Average

Gate

arrayCheaper Large Slow 2x Smaller 1@2 piece Fast

PLDThe

CheapestLargest Slowest 1x Smaller None The fastest


DESIGN METHODOLOGY CRITERIA

Criteria of selecting design methodology :

• Operation speed• Components density• Power dissipation• Interface compatibility with other circuit• Design and fabrication cost• Integrated circuit testability



1. Explain briefly these IC design methodologies:i. Full customii. Semi custom (10 marks)

2. State 2 differences between ASICs chip with general chip / standard IC. (4 marks)

3. State 2 advantages and 2 disadvantages of ASICs .(4 marks)

4. i. What is the meaning of gate array?ii. Sketch and label the floor plan of gate array.

(6 marks)5. State 2 advantages of standard cell.

(2 marks)

Example of final exam questions


THE END

cmos topic 7 -_design_methodology

Engineering