cmos scaling on resistive component 2012
DESCRIPTION
This presentation appeared in the internal seminar as opening for the series of study agendas.TRANSCRIPT
Keep Scaling of the CMOS Fabrication Process on Resistive
Componentto Beyond 22nm
James M.M. Chu, PhD
Department of Engineering Science
NCKU
2
Application Oriented IC Performance Needs
Server Desktop
Laptop
Netbook
Tablet
Smart Phone
Mobile Phone
High
Performance☆☆ ☆ ☆☆ ☆ ☆☆ ☆
Low Active
Power☆☆ ☆ ☆☆ ☆☆ ☆ ☆☆ ☆
Low Leakage ☆ ☆ ☆☆ ☆☆ ☆
3
Server / Desktop
Notebook
Netbook
Tablet
Smart Phone
Mobile Phone
Low Power
Standard Performance
High Performance
Leak
age
Pow
er
Operation Frequency
+22%
x10
x10
65nm 45nm 32nm
Product Spectrum of IC Applications22nm
4
Future CMOS Scaling Paths
From INTEL
5
1.00E-11
4.00E-08
8.00E-08
1.20E-07
1.60E-07
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
Contact maximum resistivity for bulk
MPU/ASIC (Ohm-cm2)
Contact maximum resistivity for FDSOI
MPU/ASIC (Ohm-cm2)
22nm
20nm18nm
MPU Physical Gate length
24nm
Co
nta
ct M
ax. R
esis
tivi
ty (Ω
-cm
2)
Production Year
29nm
27nm
ITRS Roadmap - Resistivity
6
Silicon
Source
VS
Drain
LG
Tox
Xj
VG
GateWψ
VD
L
MOSFET device structure
MOSFET Device Structure
VS VG VD
Rc
Rs
VTIdsat
Transistor circuit schematic
7
Rexternal = - RC = Plug contact- RCSD = Silicide, Silicide to S/D contact- RSD = Deep S/D junction- RSDE = S/D Extension- ROV = Accumulation-layer under the gate overlay
RC
RCSD
RS/D
ROVRSDE
ContactPlug
Gate
Rchannel
CMOS Device Resistant Components
8
0
100
200
300
400
500
600
700
800
90nm 65nm 45nm 32nm 22nm
Rchannel Rexternal (Ω-μm)
Rchannel Rexternal
at 32nm node
Technology Node
Res
ista
nce
(Ω
-μm
)
CMOS Resistance Scaling Trend
9
External Resistivity Breakdown - nMOS
RC (Contact Plug Resistance)
RCSD (NiSi / Si Interface)
RS/D (Spreading + Shunt)
RSDE (Spreading + Shunt)
RExternal = 55.5%Rchannel = 44.5%
5 %
16.7 %
6 %
16.7 %
RC (Contact Plug Resistance)
RCSD (NiSi / Si Interface)RS/D (Spreading + Overlay)
RSDE (Spreading + Overlay)
nMOS Rexternal = 44.5%, Rchannel = 55.5%
10
External Resistivity Breakdown - pMOS
RC (Contact Plug Resistance)
RCSD (NiSi / Si Interface)
RS/D (Spreading + Shunt)
RSDE (Spreading + Shunt)
RExternal = 51.9%Rchannel = 49.1%
RC (Contact Plug Resistance)
RCSD (NiSi / Si Interface)
RS/D (Spreading + Overlay)
RSDE (Spreading + Overlay)
22.5 %19.5 %
4.5 %2.6 %
pMOS Rexternal = 49.1%, Rchannel = 51.9%
11
0
10
20
30
40
2009 2010 2011 2012 2013 2014 2015
Year of Production
Dim
en
sio
n (
nm
)
Silicide thickness for bulk MPU/ASIC (nm)
MPU Physical Gate Length (nm)
22nm20nm 18nm
24nm
16.2nm14.7nm 13nm
17.9nm
Proposed450mm Wafer
Insertion
22nm20nm 18nm
24nm
16.2nm14.7nm 13nm
17.9nm21nm
19.5nm
27nm29nm
0
10
20
30
40
Year of Production
Dim
ensi
on
(n
m)
Silicide thickness for bulk MPU/ASIC (nm)
MPU Physical Gate Length (nm)
2009 2010 2011 2012 2013 2014 2015
Silicide Thickness v.s Gate Length
12
22nm
22nm20nm
18nm
24nm
18nm
20nm
MPU Physical Gate length
Co
nta
ct M
ax. R
esis
tivi
ty (Ω
-cm
2)
Co
nta
ct s
ilici
de
shee
t re
sist
ivit
y (Ω
-cm
2)
0
3
6
9
12
15
2009 2010 2011 2012 2013 2014 2015
Production Year
0.00E+00
2.00E-08
4.00E-08
6.00E-08
8.00E-08
1.00E-07
1.20E-07
1.40E-07
1.60E-07
1.80E-07
Contact silicide sheet
Rs for bulk MPU/ASIC
(Ohm/sq)
Contact maximum
resistivity for bulk
MPU/ASIC (Ohm-cm2)
Rcsd v.s Max. Rc Resistivity Scaling
13
Overview of Silicide Characters in Fabrication
Silicide Thermal Stability
Silicide/SiliconInterface
SBH
silicide silicide
Silicide/Silicon
Interface Passivation
Silicide Work
function
Poly Si Substrate
14
Manufacturability
Extendibility
KPI for CMOS Fabrication Process Technology
Summary
• CMOS scaling has three paths and resistive component play bigger role after 32nm node.
• The process of Metal Silicide formation shows room for extension.
• The process development for 22nm and below should fit several KPI for manufacturability and extendibility.