cmos mixed signal circuit design by jacob baker continuation

Data Converter Modeling

In this chapter we continue our discussion of data converters by discussing methods tomodel ideal data converters and their components using SPICE. The main goal of thischapter is to provide tools for evaluating mixed-signal designs with large complexity,which can be used in design evaluation and later in the book. In particular, we willgenerate SPICE models, using behavioral elements, for ideal analog-to-digital converters(ADCs) and digital-to-analog converters (DACs) blocks. This allows us to analyze theperformance of a mixed-signal circuit block in a SPICE simulation within a reasonableamount of time. For example, if we have designed a DAC at the transistor level and wantto use SPICE to simulate its operation, under various temperatures and matchingconditions, we may apply a digital input code generated from our ideal ADC with asinewave input as seen in Fig. 30.1. Similarly, given a digital signal processing (DSP)system, we can drop our ideal DAC into the simulation at any point where there is a digitalword and get an analog waveform output.

Chapter

30

Figure 30.1 Generating the sinewave digital code for DAC simulation with an ideal ADC.

IdealADC

In N-bits DACUnderTest

Out

SPICE transistor level model of a DAC

SPICE behavioral modelof an ideal ADC

Digital code correspondingto the sinewave input.

Clock, f s

Also, in this chapter we look at how the analog-to-digital and digital-to-analogconversion process affects the signals in the system. Figure 30.2 shows the basicconversion process. We will make extensive use of the spectral analysis capability (FastFourier Transform or FFT) available in SPICE to look at the digital data (and analogsignals) in the frequency domain.

30.1 Sampling and Aliasing: A Modeling Approach

In this section we discuss how sampling a signal changes the signal's spectrum. We alsodiscuss how to model the sampling process in SPICE.

30.1.1 Impulse Sampling

Consider the simple sampling gate shown in Figure 30.3a. Let's assume we apply asinewave input, , to this sampling gate of the form, (for the moment, ax(t) Vpsin (2πf in ⋅ t)single frequency input). The output of the sampling gate (a.k.a. sampler), , is they(t)product of the input and a sampling unit impulse signal or

(30.1)y(t) = Σn = −∞

∞Vpsin (2πfin ⋅ nTs) ⋅ δu(t − nTs)

2 Part IV Mixed-Signal Circuits

ADC

t

v

t

v

t

111101011000

RCF

Smoothing or

S/H

Figure 30.2 Signals resulting from A/D and D/A conversion in a mixed-signal system.

Anti-aliasing filter

AAF DSP DACIn Out

Sample and hold

t

v

reconstruction filter

Analog Digital

t

v

Figure 30.3 (a) Simple sampling gate and (b) SPICE implementation of a sampling gate.

t

v

In

Sampling implusest

Sampler output

t

v

In Sampler output

Sampling impluses

(a)(b)

1

x(t) = Vpsin (2πf in ⋅ t)

δu(t − nTs)

y(t) = x(t) ⋅ δu(t − nTs)

Noting that the frequency of the input is fin while the sampling frequency is , thef s(= 1/Ts)spectrum of the input signal is seen in Fig. 30.4a. If we take the Fourier Transform of theinput signal after sampling, that is, we look at the spectrum on the output of the sampler,we get

(30.2)Y( f ) =Vp

Ts⋅ Σ

k =−∞

∞[δ( f − f in + kfs) + δ( f + f in + kfs)]

This is the familiar result that a sampled spectrum is repeated, at intervals of , as seen inf s

Fig. 30.4b (shown is the one-sided spectrum, which is what we will use throughout thebook). Note that if an ideal low pass filter (LPF) is applied to the output spectrum of thesampler (the output of the sampler is connected to an LPF) with a bandwidth greater than

(and lower than [the Nyquist frequency]) then the higher order frequencyf in fn

components can be removed so that only remains (this is our smoothing orf in

reconstruction filter shown in Fig. 30.2)

Example 30.1A sampling gate is strobed with an impulse train running at a frequency of 100MHz ( and the time in between the impulses, Ts, is 10 ns.) Sketchf s = 100 MHzthe resulting output frequency spectrum if a 60 MHz sinewave is applied to thesampler. Also, sketch the time domain input and output of the sampler.

The resulting frequency spectrum is shown in Fig. 30.5. Notice how connectingthe output of the sampler through an LPF, with an ideal abrupt cutoff frequency of

, results in an output sinewave with a frequency of 40 MHz. In order to avoidfn

this situation, that is, to avoid ending up with the wrong, or alias, signal aftersampling and reconstructing, we need to ensure that the signal frequencies appliedto the sampler are less than (the Nyquist frequency, again, ). Reviewingf s/2 fn

Fig. 30.2 we see that this is the purpose of the anti-aliasing filter (AAF). Noticehow, ideally, both the AAF and RCF (ReConstruction Filter) in Figure 30.2 areboth ideal LPFs with a cutoff frequency equal to half the sample frequency (theNyquist frequency). Fig. 30.6 shows the time domain sketch of the sampler'soutput.

Chapter 30 Data Converter Modeling 3

Figure 30.4 One-sided spectrum of a sinewave (a) before and (b) after sampling.

ff

Volts Volts

(a) Input spectrum

(b) Output spectrum after sampling

f in

VpVp

Ts

f in

fn fs 2 f s

(f s + f in)(f s − f in) (2f s + f in)

(2 f s − f in)Y( f )

It should be clear from the preceding discussion that 1) sampling a signal results ina reproduction of the sampled signal's spectrum at DC, fs , 2fs , 3fs , etc., 2) the inputsignal's spectrum should have no significant spectral content above fn in order to avoidaliasing, 3) to avoid aliasing both filtering the input signal using an AAF and increasing thesampling frequency should be used, and 4) to reproduce the sampled signal from theoutput of the sampler (which is nonzero only during the sampling impulse times) an LPF(a reconstruction filter, RCF) should be used.

Note that our discussion illustrates the operation of a sampling gate driven withimpulse signals. As shown in Fig. 30.2; a practical system would have other buildingblocks. We would rarely, if ever, sample a signal and then reconstruct it withoutprocessing it first.

A note concerning the Anti-Aliasing Filter (AAF) and the ReConstruction Filter (RCF)

Before going any further, we should discuss the ideal characteristics of the AAF and theRCF. The ideal characteristics of these filters are shown in Fig. 30.7. Note that both of


Figure 30.5 Spectrum of a 60 MHz sinewave sampled at 100 MHz.

f40 MHz6050 150100 200 250

140 160 240

Original signal,

Aliased signal

f sfn

f inf s − f in f s + f in

2 f s

Time domain input and output for Ex. 30.1.Figure 30.6

25 ns 50 ns 75 ns

Input, 60 MHz Sampler outputs

100 ns

Alias 40 MHz sinewave

these filters must be analog by design. The ideal cutoff frequency for the filters is fn

(assuming the sampling rate on the input of the system is the same as the sampling rate onthe system's output) and the filters should ideally have linear phase. Let's discuss these twoideal characteristics.

The ideal magnitude response, shown in Fig. 30.7a, simply passes all spectralcontent below the Nyquist frequency while removing all signals above this frequency. Theideal phase response, shown in Fig. 30.7b, simply provides a constant delay, to , to allsignals below fn. In other words, the filters remove all unwanted signals while notdistorting the wanted signals.

Example 30.2Discuss why the ideal AAF filter will not introduce distortion into the desiredportion of an input signal.

If our input signal is called and the desired spectral content of this signalvin(t)after filtering is called (that is, contains nonzero spectral content onlyvin(t) vin(t)at frequencies below ), then the output of the AAF, , will be a time shiftedfn vout(t)(with a constant delay of to ) and filtered version of the input, as seen in Fig. 30.8.Note that linear phase is equivalent to saying "constant delay." If our input signalis already bandlimited to , then the output of the AAF is simply a time-shiftedfn

version of the input.


Figure 30.7 (a) Ideal magnitude and (b) phase responses for the AAF and RCF.

f

f0

(a)(b)

H(jω)∠ H(jω)

slope = −2πto

fn = fs/2

fn = f s/2

AAFIn Out

Figure 30.8 Results for Ex. 30.2.

0

In Out

t

vout(t) = vin(t − to)vin(t)

vin(t) vout(t)

to

= 1 for AAF= 1/f s for RCF

Example 30.3Suppose that the circuit, shown in Fig. 30.9, is used as an AAF filter in a dataconversion system. If the inputs to the system are two sinewaves with frequenciesof 4 MHz and 40 MHz determine whether the waveforms coming out of the AAFwill be distorted. Using SPICE show the input and output signals of the AAF.

The amplitude response of the simple RC filter is given by

voutvin

= 1

1 + (2π ⋅RC ⋅ f )2

The 4 MHz input doesn't see any attenuation. The gain, or amplitude response, ofthe filter at 4 MHz is unity (0 dB). The filter attenuates the 40 MHz input by 0.779(−2.17 dB).

The phase response of the simple RC filter is given, in degrees by

∠ vout/vin = θ(f ) = −tan−1(2π ⋅RC ⋅ f )

The phase shift through the filter at 4 MHz is approximately zero (the 4 MHz inputdoesn't see any delay while passing through the filter.) This is the ideal phaseresponse of this filter, i.e. to = 0. Looking at Fig. 30.9 we can conclude that only atfrequencies below approximately 5 MHz will the filter not exhibit phase distortion.The phase shift through the filter at 40 MHz is −39° (the negative sign indicatesthat the output is lagging the input or, in other words, occurs later in time than thecorresponding point on the input.) Since phase is related to delay by

θ(f ) =

% of period, T

to

T⋅ 360 = to ⋅ f ⋅ 360


Figure 30.9 AAF filter for Ex. 30.3.

10 pF

320 50 MHz

20 dB/decade

0

- 90

- 45

5 MHz

500 MHz

0 dBvin(t) vout(t)

vout(t)vin(t)

∠ vout(t)vin(t)

the delay the 40 MHz sinewave sees passing through the filter is 2.7 ns. TheSPICE simulation results are shown in Fig. 30.10 assuming each sinewave input iscentered at ground and has an amplitude of 1V.

Also note that this filter does a poor job attenuating frequencies above 50MHz. For example, the attenuation at 500 MHz (one decade above 50 MHz) isonly −20 dB (0.1). It can be concluded that unless (the Nyquist frequency) isf s/2much larger than the cutoff frequency of the simple RC LPF aliasing will (possibly)still occur in significant amounts. In fact, we could argue that because of theinherent noise present in any electronic circuit, aliasing will always occur whensampling a signal (the wideband noise gets aliased down into the base spectrum[the spectrum below the Nyquist frequency].) The question then becomes "Howmuch aliasing is OK?"

Example 30.4Determine the transfer function of the filter made with a 5 ns long (= to) idealtransmission line shown in Fig. 30.11. Simulate the filters frequency and phaseresponse using SPICE. This filter is called a continuous-time comb filter.

In this analysis we assume that 500-ohm resistors do not load the input or outputof the delay line so that

vout = vin + vin ⋅ ej⋅2πf⋅(−to)

2


Figure 30.10 SPICE simulation results for Ex. 30.3

Input

The transfer function can be written as

voutvin

= 12

(1 + ej⋅2πf⋅(−to)) = 12

Real

1 + cos 2πf ⋅ (−to) +

Imaginary

j ⋅ sin2πf ⋅ (−to)

The magnitude response of this filter is

voutvin

= 12

(1 + cos 2πf ⋅ (−to))2 + (sin2πf ⋅ (−to))2 = 12

2(1 + cos 2πf ⋅ to)

The phase response of this filter is given by

∠ voutvin

= tan−1

sin2πf ⋅ (−to)1 + cos 2πf ⋅ (−to)

Noticing at the phase is which evaluates to . Using f = 1/(2to) tan−1(0/0) ± 90

and cos2x = 1 + cos 2x2

sin2x = 2 sinx cosx

the phase response is given by

for ∠ voutvin

= π(−to) ⋅ f f < 1/(2to)

Notice that the phase response of this filter is linear. The SPICE simulation results,plotted on a linear scale, are shown in Fig. 30.12. The reason this filter is called a"comb filter" should be obvious. Notice how the delay line length is related to thepoints where the magnitude response goes to zero. Also note that this filter couldbe useful to isolate channels in a communication system and easily implemented ona PC board using a microstrip transmission line. The SPICE netlist that generatedthis figure is given below.

* Figure 30.12 CMOS: Circuit Design for Mixed-Signal Systems *.AC LIN 1000 1MEG 1000MEGVin Vin 0 DC 0 AC 1Rtout Vtout 0 50Rt1 Vtout Vout 500Rt2 Vin Vout 500


Figure 30.11 A continuous time comb filter.

500

500

50

vin

vout

vin

vinej2πf (−to)Zo = 50 Ω to = 5 ns

T1 Vin 0 Vtout 0 ZO=50 TD=5n.end

Finally, before leaving this example, consider the dB (magnitude) and phaseresponses of this filter on a log frequency plot, Fig. 30.13. It would appear that themagnitude of the transfer function at 100 MHz, 300MHz, 500 MHz, etc., isnonzero. However, as the equation for the magnitude response shows, this isn't thecase. At these frequencies is zero indicating, in the plots shown in Fig.vout/vin

30.13, that the lower limit is set by step size (number of points per decade) used inAC SPICE simulation. Increasing the number from 1,000, which is what was usedto generate Fig. 30.13 to, say, 10,000 will give more accurate results.

Time domain description of reconstruction

In this section we show why the filter shown in Fig. 30.7, an ideal brick wall low-passfilter with linear phase response, is the ideal reconstruction filter (RCF) on the output ofour impulse sampler. Shown in Fig. 30.14 is a 20 MHz sinewave sampled at 100 MHz.Suppose we want to reconstruct the original input 20 MHz sinewave from the sampleroutput (the weighted impulse functions). After reconstruction the output of thereconstruction filter should be a single tone, 20 MHz, sinewave (it should be an exactreplica of the sampler input). To determine what happens when the output of our sampleris applied to the ideal RCF, we need to determine the time domain response of the filterwhen the Dirac delta function, , is the filter's input signal.δ(t) (δ(0) = ∞, else δ(t) = 0)


100 MHz

Figure 30.12 SPICE simulation results for the comb filter of Ex. 30.4.

We know the transfer function of a system is the Fourier transform of the system'stime domain impulse response (what we are trying to find here). In other words, todetermine the transfer function of the system, we apply the Dirac delta impulse (or inpractice a very large amplitude, very short time duration pulse, see Fig. 30.15) to the inputof the system and we look at the system's output in the time domain. We then take theFourier transform of this output to get the system's transfer function. Therefore, (in thereverse order), to determine the time domain response of the ideal RCF, given the transfer


Figure 30.13 SPICE simulation results, in dB, for the comb filter of Ex. 30.4.

Impulse sampling, at 100 MHz, a sinewave at 20 MHz.Figure 30.14

Sampler input, 20 MHzSampler outputs

10 ns 30 ns 50 ns 70 ns 90 ns

Ts = 1f s

function, we take the inverse Fourier transform of the transfer function. The ideal RCF'stransfer function (Fig. 30.7) can be defined by

(30.3)H( f ) = 1/f s for f < fn else H( f ) = 0

The time domain response is then given, remembering , by2fn = f s

(30.4a)h(t) = ∫−fn

fn

1f s

⋅ ej⋅2π⋅f⋅t ⋅ df = ej⋅2π⋅fn ⋅t − e−j⋅2π⋅fn ⋅t

j ⋅ 2π ⋅f s ⋅ t=

(30.4b)sin 2πfn ⋅ t

πf s ⋅ t=

sinπfs ⋅ tπf s ⋅ t

= Sinc(πf s ⋅ t)

where

(30.5)sin xx ≡ Sinc(x)

The time-domain response of our ideal RCF is shown in Fig. 30.16. Notice that ourimpulse is applied to the system's input at t = 0 and that the output actually anticipates, orstarts, before the application of the input! This indicates the filter is noncausal and can't bebuilt in a practical analog circuit. Before we discuss the implications of this severelimitation (an ideal reconstruction filter can't actually be built), consider Fig. 30.17. Figure


Figure 30.16 (a) Ideal RCF frequency response and (b) impulse response (time).

f

(a)

(b)

0t

1H(jω)

fn = fs/2Ts 2Ts 3Ts− Ts−2Ts−3Ts

sin πf s ⋅ tπf s ⋅ t

= Sinc(πf s ⋅ t)

0.13

Ts

2

0.64 = −3. 9 dB1f s

0.21 = −13.5 dB

Figure 30.15 Time domain impulse response of the ideal RCF.

f

Ideal RCF

time0

Impulseinput toRCF t

1

t=0time

11/f s

fn

30.17 shows the individual response outputs of an ideal RCF with the impulse train of Fig.30.14 as the input. The output of the RCF is the weighted sum of the individual responses,of the form Sinc(x), from each of the weighted impulse inputs into the RCF (usingsuperposition). While this figure is "busy" the basic concept of reconstruction should beobvious.

Practically, we can't make an ideal reconstruction filter, which is a requirement forreconstructing a waveform consisting of frequency components between DC (0) and .fn

For example, sampling a 49 MHz sinewave at 100 MHz (essentially two samples percycle) would require, for reconstruction, a filter with characteristics close to the ideal RCFin order to get a signal out of the system resembling the 49 MHz input. What can we do toease the requirements on the RCF? Here are two possibilities:

1) Increase the sampling rate fs. If we were to sample the 49 MHz signalmentioned above at 500 MHz, we would then have roughly ten samples per cycle. TheRCF used on the output of the system can then have a slower roll-off rate. At the extremeend, taking , eliminates the need for any RCF.f s → ∞

2) Add, after sampling has taken place and using a DSP, additional points inbetween the sampling times. This effectively increases the sampling rate coming out of thesystem. This change (increase) in the effective sampling frequency is known asinterpolation because the values of the additional points are determined by interpolatingbetween the existing data points. The increase in the effective, output, sampling rate easesthe requirements placed on the RCF.

SPICE Modeling the Impulse Sampler

The SPICE model of the impulse sampling gate was shown in Fig. 30.3. A voltage-controlled switch was used to connect the input signal to the sampler's output for verybrief periods of time. In order to make the sampler more ideal, that is, with infinite input


Reconstructing the 20 MHz sinewave of Fig. 30.14.Figure 30.17

Output of the RCF

time

resistance, zero output resistance, etc., the SPICE model shown in Fig. 30.18 will be used.Voltage-controlled voltage sources, with the E prefix, are used to model the idealoperational amplifiers. The switch is modeled with a voltage-controlled switch, an Sdevice. The model is used in the following netlist:

* Figure 30.19 CMOS: Mixed-Signal Circuit Design *.tran .1n 500n 0 .1n UICVin Vin 0 DC 0 Sin 0.75 0.75 5MEGVclock Clock 0 DC 0 Pulse 0 1.5 0 0 0 100p 10nVtrip Vtrip 0 DC .75Ebufin Vinb 0 Vin Vinb 100MEGS1 Vinb Vins CLOCK VTRIP switmodRout Vins 0 10kEbufoutVout 0 Vins Vout 100MEG.model switmod SW.end

In this netlist a 1.5 V, peak-to-peak, 5 MHz sinewave centered at 0.75 V issampled at 100 MHz. The impulses are generated using the pulse statement with zeroesfor both rise and fall times. In the simulation the actual rise and fall times will be limited bythe transient simulation step time (which is set at a maximum of 100 ps using the .transtatement in the netlist above). The impulses have logic amplitude levels of 1.5 V. Theswitch's trip point is set at 0.75 V so that when the impulse goes above 0.75 V the switchis closed. Because the impulse is at 1.5 V for only 100 ps, and the input is slow in relationto this time, the netlist approximates an ideal impulse sampling circuit. Running the netlistabove results in Fig. 30.19.

Using SPICE for Spectral Analysis (Looking at the Spectrum of a Signal.)

Figure 30.19 shows the sampled output of our impulse sampler, in the time domain. It isvery useful, as we've already seen, to be able to look at these data in the frequencydomain. SPICE (actually Nutmeg) has the feature that it can take the Fast FourierTransform (FFT) of a time domain signal. Performing an FFT consists of 1) windowing


Figure 30.18 SPICE model of the ideal impulse sampler.

Sampling impluses

Ebufout

0

Vins

Voutvin

vout

the time domain signal (we will use the Hanning window, a.k.a. von Hann window unlessotherwise indicated), 2) sampling the signal, and 3) taking the Fourier transform of thesignal. Windowing ensures that abrupt transitions do not occur at the beginning and end ofthe signal to be transformed. It's important to realize that taking the FFT of a signal thathas already been sampled results in a spectrum with amplitude errors (more on this in amoment.) To perform an FFT in SPICE we first ensure that the signal to be transformedhas a linear time step. To do this we use

linearize Vout Vin

where Vout and Vin are the signals we are interested in transforming. Using the linearizecommand with no arguments will linearize all of the variables available in the simulation.Next, we use the spec command (spectral analysis command) in SPICE

spec 0 200MEG 2MEG Vout Vin

This command takes the FFT of Vout and Vin over the range of DC to 200 MHz with aresolution of 2 MHz. The minimum resolution allowed when using the spec command(FFT) is set by the transient simulation time, or

(30.6)FFT resolution ≥ 1simulation time

If we simulate a circuit for 500 ns, then our minimum resolution is 2 MHz. We can look atthe spectrum of a signal using the following list of commands:


Figure 30.19 Impulse sampling a 5 MHz sinewave at 100 MHz.

linearize Vout Vin spec 0 200MEG 2MEG Vout Vin* Set noise floor at 120dB by adding 1uVlet voutdb=db(Vout+1e-6)let vindb=db(Vin+1e-6)plot voutdb plot vindb

The spectrums, as an example, on the input and output of an impulse sampler sampling a10 MHz sinewave at 100MHz are shown in Fig. 30.20. Note that 1-µV was added to bothsignals so as to set the noise floor in the display to −120 dB. The DC portion of the inputsignal is 0.75 V while the peak voltage of the 10 MHz sinewave is also 0.75 V (0.75 V =−2.5 dB). Note that in Fig. 30.20b, because of the double sampling mentioned above, theamplitude of the signals in the output is different than that predicted (see Fig. 30.4). Wecan estimate the baseline reduction, resulting from taking the FFT of an impulse sampledsignal (the signal has nonzero values only during the sampling times) using

(30.7)Baseline reduction (or duty cycle) ≈2 ⋅ stepsize

Ts

For Fig. 30.20b the maximum stepsize specified in the transient simulation was 100 ps (foreach cycle of Ts one point is defined as having a total deviation, after being linearized, ofapproximately 200 ps including rise and fall times, hence the factor of two in Eq. 30.7.)The baseline, using Eq. 30.7, is 200 ps/10 ns or 0.02 (−34 dB). The 10 MHz signal in Fig.30.20b is −2.5 dB below the −34 dB baseline. Note how the DC signal is aliased up to thesampling frequency (100 MHz). At DC, with reference to the baseline, the signalamplitude is also −2.5 dB (−36.5 dB). However, when it is aliased up to the 100 MHz(sampling frequency) it is doubled (+6 dB). The doubling comes from adding the images

and and results in an amplitude of −36.5 dB + 6 dB or −30.5 dB.f s + 0 f s − 0

The stepsize used in a transient simulation, as we saw above, is an importantparameter that needs specification when performing a spectral analysis using SPICE. Inthe netlist that generates Figs. 30.19 and 30.20, we used 100 ps but made no comment onwhy this value was selected. Poor selection of the step sizes can give erroneous results ifthe values are too large or cause the simulation to last a long time if the values are toosmall. The transient simulation characteristics in a SPICE netlist are specified using

.tran print-step stop-time delay-time maximum-stepsize <UIC>

The step size, for a general simulation with nonideal components, can be set using

(30.8)stepsize = 1 % ⋅ Ts or with ideal components 10% ⋅ Ts

If our sample frequency, fs , is 100 MHz then we would set our step size to 100 ps using

.tran 100p 2000u 0 100p UIC

The term UIC forces the simulation to start with initial conditions (use initial conditions)such as an initial voltage across a capacitor. The simulation always starts at zero time.However, specifying a delay-time in the simulation will make SPICE start saving data at


the time specified by the delay-time parameter. This parameter is useful in removing, froma spectral response for example, the start-up transients in a simulation or keeping the sizeof a raw output file from getting too large.

Representing the Impulse Sampler's Output in the z-Domain

Consider the output of an impulse sampler, , with an input of shown in Fig. 30.21.y(t) x(t)The sampler output can be written as

(30.9)y(t) = x(t) ⋅ Σk =−∞

∞δu(t − kTs)


−30.5 dB

−34 dB

2.5 dB (0.75V)

Figure 30.20 Spectrum of the signals shown in Fig. 30.19.

2.5 dB (0.75V) below baseline or 36.5 dB

10 MHz Input to the sampler Output of the sampler

Nyquist frequency 90 MHz 110 MHz

10 MHz

(a) (b)

Vol

ts

Vol

ts

Figure 30.21 Output of an impluse sampler.

time

y(t)

Ts

Ts

We can rewrite Eq. 30.9 as

y(t) = x(t)[... + δu(t + Ts) + δu(0) + δu(t − Ts) + δu(t − 2Ts) + δu(t − 3Ts) + ...]

(30.10)

Taking the Fourier transform of this equation results in

Y( f ) = ... + x(−1)e(1)⋅j2π⋅f⋅Ts + x(0)e(0)⋅j2π⋅f⋅Ts + x(1)e(−1)⋅j2π⋅f⋅Ts + x(2)e(−2)⋅j2π⋅f⋅Ts + ...

(30.11)

where the term corresponds to a phase shift of (radians) when the outputej2π⋅f⋅Ts 2π ⋅f ⋅ Ts

of the sampler, , is evaluated at the frequency f. In other words, each consecutiveY( f )sample coming out of the impulse sampler is shifted in the time-domain by Ts (which issimply saying, in words, what Fig. 30.21 shows). If we define

(30.12)z ≡ ej2π⋅f⋅Ts = ej2π⋅ f

fs

then the output of our sampler can be written as

(30.13)Y(z) = ... + x(−1)z1 + x(0)z0 + x(1)z−1 + x(2)z−2 + ...

or

(30.14)Y(z) = Σk= −∞

∞x(k) ⋅ z−k

Example 30.5Determine the output of an impulse sampler in the z-domain if its input, x(t), is aunit step. What is the sampler's impulse response ?H(z) [= Y(z)/X(z)]

The unit step, u(t), is defined by

u(t) = 1 for t ≥ 0

u(t) = 0 for t < 0

The time-domain output of the sampler, with u(t) as an input, is given by

y(t) = Σk = 0

∞u(t − kTs)

or looking at the output in the z-domain

Y(z) = Σk = 0

∞z−k

The time domain signals used in this example are shown in Fig. 30.22. Thesampler's impulse response is simply unity since the z-transform of the input(assuming the input was passed through an ideal impulse sampler so that we cantake the z-transform of the signal) and output of the sampler are identical, that is,

. H(z) = 1


Example 30.6What is the effect of multiplying H(z), in Ex. 30.5 (or any z-domain transferfunction), by z−1?

Multiplying any z-domain transfer function by z−1 is equivalent to shifting thesystem's output later in time by Ts. The result of changing the ideal sampler'stransfer function from unity to z−1 is shown in Fig. 30.23. Multiply by z−L shifts theoutput of the system later in time by L ⋅ Ts

An Important Note

It's important to note that our impulse sampler quantizes1 the input signal in time but notamplitude (unlike an analog to digital converter which quantizes the input in both time andamplitude). The amplitude out of the ideal impulse sampler is exactly the same as theamplitude input to sampler at the sampling impulse time. We'll find that the z-transformcan be used to describe systems using both quantization in time as well as in amplitude. Inother words, whether we are discussing digital words, in a binary format orsampled-analog waveforms with amplitudes of volts, amps, or coulombs, we can use thez-transform to represent the discrete-time systems that process the signals.

1 Quantize: to limit the possible values of a quantity to a discrete set of values. Quantizing in time,for example, means that the output amplitude is only defined at certain discrete times (such as thesampling impulse times for the ideal impulse sampler) or that the amplitude is unchanging duringcertain discrete time intervals (such as seen in the output of the ideal sample-and-hold discussed inthe next section).


Figure 30.22 Sampling the unit-step with an impulse sampler.

Ideal impulsesamplerIn Out

samplingclock time

sampler input

sampler output

1

1

0

0f s

Ts

Figure 30.23 Mulitplying the output of the ideal sampler by .

Ideal impulsesamplerIn

Out

samplingclock time

sampler input

sampler output

1

1

0

0f s

Ts

z−1

z−1

30.1.2 The Sample and Hold

Understanding the operation of the impulse sampler of Sec. 30.1.1 is important inunderstanding the concepts of aliasing and reconstruction. However, as seen in Fig. 30.2,most mixed-signal systems employ a sample and hold (S/H) rather than an impulse samplerso that the sampled waveform is available at times other than the sampling impulse times.Having the samples "held" in between the sampling impulse times is important for properADC operation. The disadvantage of using the S/H, as we shall shortly see, is that it willintroduce distortion into our signal.

SPICE Modeling the Sample and Hold

The block diagram of the SPICE model, for the ideal S/H, is shown in Fig. 30.24. Theinputs are Clock and vin while the output is labeled vout. A SPICE netlist, using the idealS/H, is shown below in which an 8 MHz sinewave is sampled at 100 MHz. The simulationresults, using this netlist, are shown in Fig. 30.25.

* Figure 30.25 CMOS: Mixed-Signal Circuit Design *.tran .1n 500n .1n UICVin Vin 0 DC 0 Sin 0.75 0.75 8MEGVclock Clock 0 DC 0 Pulse 0 1.5 0 0 0 4.9n 10nVtrip Vtrip 0 DC .75VDD VDD 0 DC 1.5Ein Vinbuf 0 Vin Vinbuf 100MEG

S1 Vinbuf VinS VTRIP CLOCK switmodCs1 VinS 0 1e-10S2 VinS Vout1 CLOCK VTRIP switmodCout1 Vout1 0 1e-16

Eout Vout 0 Vout1 Vout 100MEG.model switmod SW .end

The switches S1 and S2 in the netlist above sample the input using the input clock. Notethat both switches can be closed, momentarily in Fig. 30.24, at the same time. The time


Figure 30.24 SPICE model of the ideal sample and hold (S/H).

1e-10

1e-16

Vin

Vout

Clock

Clock

Vinbuf Vins Vout1

that the switches are closed is approximately equal to the transient step time. The charge-sharing between the capacitors is affected by having both switches closed at the sametime. Values given in this figure were selected so that a million-to-one ratio existedbetween the two capacitors (120 dB range.) Because both switches are closed at the sametime, the difference between the two capacitors can be made smaller without affecting thecircuit's operation. Also note that over a time set by GMIN (remember a resistor with avalue of 1/GMIN is placed across every pn-junction in a SPICE simulation and GMIN'sdefault value is 1e-12 or 1 GΩ) and the capacitor values the charge on the capacitors willleak off causing droop. For the 0.1f capacitor the associated RC time because of GMIN is100 µs (increasing this capacitor to 10f won't affect the sampling operation and pushes theRC time up to 10 ms).

The accuracy of the S/H is ultimately limited by the tolerances, that is, RELTOL,ABSTOL, and VNTOL of the simulation. For an accurate simulation we may add

.options RELTOL=1u VNTOL=1u ABSTOL=1p

to the netlist. The accuracy of a simulation will be discussed in greater detail later.

S/H Spectral Response

Consider the application of a sinewave, at a frequency fin , to the ideal S/H shown in Fig.30.26. In order to make the discussion as general as possible assume that the output ofthe S/H can return-to-zero (RZ) as shown in Fig. 30.27 (which shows coarse timequantization for a simpler figure and illustration of the concept of RZ). Note that as T


Figure 30.25 Ideal S/H with an 8 MHz input.

approaches Ts we get the operation of the S/H in Fig. 30.26. The output of the idealsample and hold is given by

(30.15)y(t) = Σn = −∞

∞

vin(t)

Vpsin (2πf in ⋅ nTs) ⋅

h(t)

[u(t − nT) − u(t − (n + 1)T )]

Note that the sine term is only defined at discrete sampling instances so that its spectrumis given by Eq. 30.2. The spectrum of the sampling pulse, , because of the dualityH( f )of the Fourier transform, is given by reviewing Fig. 30.16 or calculated using

(30.16)Fourier[u(t − nT) − u(t − (n + 1)T] = ∫0

Ts

[u(t − nT) − u(t − (n + 1)T]e−j⋅2π⋅f⋅t ⋅ dt

which is evaluated as

(30.17)H( f ) = e−j⋅2π⋅f⋅T − 1−j ⋅ 2π ⋅f

= e−j⋅π⋅f⋅T ⋅ ej⋅π⋅f⋅T − e−j⋅π⋅f⋅T

j ⋅ 2π ⋅f=

phase

e−j⋅π⋅f⋅T ⋅

magnitude

T ⋅ Sinc(π ⋅f ⋅ T)


time

Figure 30.27 Sample-and-hold output with return to zero format.

sinewave in

S/H out

Ts

T

Figure 30.26 Sampling and holding an input sinewave.

Sample andhold (S/H)

clock

In Out

timetime

f in

y(t)

vin

The magnitude of Eq. 30.17, , is plotted in Fig. 30.28. The phase responseH( f )corresponds to a shift in time of T/2 so, to simplify the math below, we will only concernourselves with the magnitude response of H( f ).

Multiplication in the time domain can be evaluated using convolution in thefrequency domain. The frequency spectrum of a sinewave, sampled with an ideal S/H, isgiven by

(30.18)Y( f ) = H( f ) ∗ Vin( f ) = ∫−∞

∞

H(L) ⋅ Vin( f − L) dL

or

(30.19)Y( f ) =

Weighting from S/H, H(f)

T ⋅ Sinc(π ⋅T ⋅ f ) ⋅

Ideal impluse sampler response

Vp

Ts⋅ Σ

k = −∞

∞[δ( f − f in + kfs ) + δ( f + f in + kfs )]

As ( ), the frequency response of the sample-and-hold approaches theT → 0 h(t) → δu(t)ideal impulse sampler of Sec. 30.1.1. Also, note that using an RZ format (making )T < Ts

can reduce the amount of attenuation introduced by the S/H ( doesn't rolloff asH( f )fast.)

For most circuit designs so that, as Eq. 30.19 shows, the sample-and-holdT = Ts

operation weights the amplitude of our ideal impulse sampler's frequency response by

or . Note that at the sampling frequency the output of the ideal S/HSinc

πff s

Sinc

πf2fn

goes to zero. Let's illustrate the frequency response of an ideal S/H using an example.

Example 30.7Using the ideal S/H SPICE model show and discuss the spectrum resulting fromsampling a 3 MHz sinewave at 100 Msamples/s.


Figure 30.28 (a) Sampling pulse and (b) its spectrum.

time

0f

1

(a)

(b)

u(t − nT) − u(t − (n + 1)T)

T

T

2T

1T

3T

Ts

H( f )h(t)

The results of passing a 0.75 V (peak) sinewave centered at 0.75 V(−2.5 dB)through the ideal S/H are shown in Fig. 30.29. We have also plotted the responseof the S/H, in this figure. The attenuation the 97 MHz image sees isH( f )

attenuation = Sincπ ⋅97100

= 0.031 = −30.2 dB

The amplitude of the 97 MHz image is −2.5 dB below the attenuation resultingfrom using a S/H or −32.7 dB. Note how, at the Nyquist frequency of 50 MHz, thesignal is attenuated by −3.9 dB. Also note how the DC image at is attenuatedf s

by the S/H instead of being doubled as in the impulse sampler (Fig. 30.20.)

Two additional notes: first, the S/H cannot be used as an AAF since anyaliasing that occurred using the impulse sampler still occurs using the S/H. Forexample, sampling a 60 MHz sinewave at 100 MHz still results in a 40 MHz aliassignal in the base spectrum (the spectrum from DC to fn ) as shown in Fig. 30.5.Now, however, the signal is attenuated by the S/H (the attenuation is −2.4 dB at40 MHz when sampling at 100 Msamples/s.) In other words, the S/H can bethought of as an ideal impulse sampler followed by a Sinc response filter. Second,


Figure 30.29 Output of a S/H after sampling a 3 MHz sinewave at 100 MHz.

DC, 0.75 V

50 MHz

S/H response

Noise floor

Vol

ts, p

eak

fn

−3.9 dB−13.5 dB

3 MHz, 0.75V peak (−2.5 dB)

97 MHz, −32.7 dB

fs

repetitively sampling and holding a signal results in only one S/H attenuation hit(assuming the timing is such that a sampling operation is not occurring when theprevious S/H stage's output is changing). This means that topologies that useseveral S/H operations on an input signal, such as a pipeline ADC, only attenuatethe signal by once. Sinc(πf/f s)

The output of the S/H (assuming ) should be passed through a two-stageT = Ts

reconstruction filter, to recover the input signal. One of the stages will have the frequencyresponse of the ideal RCF of Fig. 30.16. The other stage will have a frequency responsegiven by

(30.20)HRCFSH( f ) = 1

Sinc

πf

fs

=πf

2fnsin

πf

2fn

to compensate for the attenuation of the S/H Sinc response. The shape of the idealreconstruction filter is shown in Fig. 30.30. Again, increasing the sampling frequency,relative to the input frequency will ease the requirements placed on the reconstructionfilter. Note how using the RZ format modifies the requirements placed on thereconstruction filter to the point, when using impulse sampling, of having the brick-wallideal RCF of Fig. 30.7.

Before we leave this section let's answer the question: "What sets the value of thenoise floor in SPICE (Fig. 30.29)?" We can limit the noise floor, in Fig. 30.29 forexample, by adding 1 µV to voltages in the circuit. However, the SPICE-simulatedspectrum's noise floor, which is set by simulation variations is limited by the RELTOLparameter. Also, the length of the simulation can be important. ABSTOL, which defaultsto 1 pA, and VNTOL, which defaults to 1 µV, signify when a current or voltage hasconverged in a SPICE simulation. If the step change in the simulation, for all currents andvoltages at a given time, is within ABSTOL (for currents) or VNTOL (for voltages) thenSPICE moves on to the next step in time (for a transient simulation). The parameterRELTOL was added to SPICE so that simulations involving large currents and voltages


Figure 30.30 Ideal reconstruction filter response for a S/H.

1

f

1

f

3.9 dB (1.56)0 dB

Overall response of RCFfor a S/H

f s 2f s

HRCFSH (f )

fn

were not forced to use ABSTOL and VNTOL to signify convergence. In other words, if acurrent is approximately 10 A we won't force the SPICE number for the current to be10.000000000001. Instead we use 10.01 (the product of RELTOL [assuming = 0.001]and 10 A) to signify convergence. To signify that a current has converged we use thelarger of

or (30.21)ABSTOL RELTOL ⋅ Isimulated

while for a voltage we use the larger of

or (30.22)VNTOL RELTOL ⋅ Vsimulated

For the simulation shown in Fig. 30.29 we set RELTOL to so that our 1 V level10−6

signals simulate to within 1 µV of their "actual" values. This keeps the simulation noisefrom setting our noise floor. The practical problem of reducing RELTOL is convergencewhen non-ideal components (e.g. MOSFETs) are added to the simulation. Trade-offs mustbe made between simulation noise and convergence when using both ideal and non-idealcomponents in a simulation.

Circuit Concerns for Implementing an S/H

Figure 30.31 shows a single-ended input and output S/H implementation using either anop-amp or an OTA (operational transconductance amplifier.) At the time t0 , the and φ1 φ2

switches are closed while the switches are open. During this time, that is the timeφ3

between t1 and t2, the input charges the hold capacitor CH . The input is connected to theleft side, or bottom plate (the plate closest to the substrate), of CH while, because of theop-amp, the right side (top plate) is connected to ground (or a common mode voltage,VCM). At t1 the switch opens and for a very short time (set by ) the op-ampφ1 t3 − t1

operates open loop (no feedback). As the top plate is always at ground (or VCM) at t1 , thecharge injection and capacitive feedthrough resulting from the switches turning off areφ3

independent of the input signal. When the switch turns off, the charge injection will,φ2

ideally, flow into the low-impedance input vin since the impedance looking into the right ofthe switch is large. This, again ideally, leaves the voltage across the hold capacitorφ2

unaffected by the charge injection resulting from turning off the switches. This sequence of


Single-ended S/H operation. Figure 30.31

Bottom plate

vin

vout

CHφ2

φ3

φ3

φ1 φ1

t3t2t1to

φ2

φ3

turning off the switch to the right of CH followed by turning off the switch connecting vin

to CH is often, confusingly, called bottom plate sampling. Bottom plate sampling isillustrated in its simplest form in Fig. 30.32. In this figure the switch connected to thebottom plate of the capacitor is turned off first. When the switch turns off, the chargeφ2

can be injected into the low-impedance node, the input vin , or into the series combinationof CH and the off switch. The charge takes the lowest impedance path to ground and thusmost of the charge injection resulting from the switch turning off flows through vin ,φ2

leaving the voltage across the hold capacitor unaffected. We should see why the name"bottom plate sampling" is confusing. Reviewing Fig. 30.31 we see the top plate of thehold capacitor is connected to the switch while, in Fig. 30.32, the bottom plate of theφ1

hold capacitor is connected to the switch.φ1

Returning to the discussion of the operation of the S/H of Fig. 30.31 we see that att3 the switches turn on and the op-amp behaves as a voltage follower holding theφ3

sampled input voltage. The sampling instant occurs between t1 and t3 (which should beshort to keep the op-amp output from drifting towards VDD or ground.)

30.2 SPICE Models for DACs and ADCs

In this section we develop SPICE models for ideal digital-to-analog converters (DACs)and analog-to-digital converters (ADCs). Our goal is to have SPICE code, or subcircuits,that we can place in a mixed-signal simulation to either: 1) generate a digital word basedon an analog input (using the ideal ADC) or 2) look at the spectrum of a digital signal(using the ideal DAC and the spectral analysis capability in SPICE [using the discreteFourier Transform].)

30.2.1 The Ideal DAC

While there are an infinite number of ways to implement an ideal DAC in SPICE, we use amethod that results in a computationally efficient model for a DAC. Before we discuss theimplementation, let's review some fundamental characteristics of a DAC.


Figure 30.32 Bottom plate sampling.

Turns off first

Turns off lastφ2

φ1

vin

CH

Consider the ideal transfer characteristics of a 3-bit DAC shown in Fig. 30.33. (Fora detailed review of general DAC characteristics see Ch. 28.) Notice in this figure that wehave drawn two reference voltages, and , and are assuming thatVREF+ VREF−

When a digital input of 000 is applied to the DAC, the output voltageVREF+ > VREF−.becomes . When the input code is increased to 001, the output of the DAC (anVREF−analog voltage defined at discrete amplitude levels) increases by one Least Significant Bit(LSB). If the DAC has an input code with a number of bits, N, then we can define an LSBas

(30.23)1 LSB = VREF+ − VREF−

2N= VLSB

If, for example, and and , then our LSB, the verticalVREF+ = 1.25V VREF− = 0.25 N = 3distance between adjacent points in Fig. 30.33, is 0.125V. Note that in our discussion of


000 001 010 011 100 101 110 111Digital

input code, 0

1/8

2/8

3/8

4/8

5/8

6/8

7/8

8/8

Figure 30.33 An ideal 3-bit DAC.

Ideal

3-bit DAC

VOUT − VREF−

VREF+ − VREF−

VOUT

VREF+

b2

b1

b0

VREF−

b2b1b0

1 LSB

VREF+

VREF−

VREF+ − 1LSB

an ideal DAC we are assuming that the output of the DAC ranges from up toVREF−. We could just as easily have assumed that the output ranged fromVREF+ − 1LSB up to . The important thing to notice is that the DAC output range isVREF− + 1LSB VREF+

smaller than the difference between the positive and negative reference voltages.1LSBFor the DAC developed in this chapter we will assume andVREF+ = VDD = 1.5 V

. In Ch. 33 we discuss a submicron CMOS process using these powerVREF− = VSS = 0 Vsupply voltages, 1.5 V and 0 V. Selection of the power supply rails, which are noise free ina SPICE simulation, allow the maximum output range for the DAC (assuming thereference voltages are indeed the maximum and minimum voltages in the system, i.e., nocharge pumps or external, larger, power supply voltages.) If we need more resolutionwhen using our ideal DAC we will simply increase the number of bits, N, used and hencedecrease the value of the DAC's LSB.

SPICE Modeling Approach

We can write the output of the ideal DAC in terms of the reference voltages and digitalinput codes (which are logic "0" or "1"), and assuming that an input code of all zeroesbN

results in an output voltage of , asVREF−

(30.24)VOUT = (VREF+ − VREF−) ⋅

bN−1

21+ bN−2

22+ ... + b1

2N−1+ b0

2N + VREF−

or

(30.25)VOUT = (VREF+ − VREF−) ⋅ 12N

⋅ (bN−12N−1 + bN−22N−2 + ... + b1 ⋅ 21 + b0) + VREF−

We can implement this equation, in SPICE, using a non-linear dependent source (a Bsource). For a 3-bit, ideal DAC, the statement that implements this equation may look like

*Non-linear dependent source, B, for generating the DAC outputBout Vout 0 V=((v(vrefp)-v(vrefm))/8)*(v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm)

The terms BXL correspond to logic signals that have a value of 1 V or 0 V.

Example 30.8Write the non-linear dependent source statement for an ideal 12-bit DAC.

The statement follows:

Bout Vout 0 V=((v(vrefp)-v(vrefm))/4096)*+(v(B11L)*2048)+v(B10L)*1024+v(B9L)*512+v(B8L)*256+v(B7L)*128+v(B6L)*64+v(B5L)*32+v(B4L)*16+v(B3L)*8++v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm)

remembering that a "+" in the first column of a line indicates that the text on theremainder of the line behaves as if it were typed at the end of the previous line. Itdoesn't indicate addition.

The next thing we need to concern ourselves with is the digital logic levels. Wewant to use our ideal DAC with non-ideal (real) circuits where the logic voltage levelsmay not be well defined. We need to determine and use a switching point voltage based on


the power supply voltage VDD. We will assume the input logic code is a valid logic "1" ifits amplitude is greater than VDD/2 and a logic "0" if its amplitude is less than VDD/2. Wecan implement the VDD/2 switching point, or trip voltage, using the following SPICE lines

*Generate Logic switching point, or trip, voltageR1 VDD trip 100MEGR2 trip 0 100MEG

The solid logic levels can be generated using the following subcircuit SPICE code. Theswitch implementation is shown in Fig. 30.34.

.subckt Bitlogic trip BX BXL Vone one 0 DC 1SH one BXL BX trip SwitmodSL 0 BXL trip BX Switmod.model switmod SW.ends

Using the above code, the subcircuit definition for an ideal 8-bit DAC can bewritten, as shown in Fig. 30.35. Using this subcircuit in the following netlist, we can showthe operation of an ideal 8-bit DAC:

VDD VDD 0 DC 1.5VREFP VREFP 0 DC 1.5VREFM VREFM 0 DC 0.0

VB7 B7 0 DC 0 pulse 1.5 0 0 200p 200p 1279.8n 2560nVB6 B6 0 DC 0 pulse 1.5 0 0 200p 200p 639.8n 1280nVB5 B5 0 DC 0 pulse 1.5 0 0 200p 200p 319.8n 640nVB4 B4 0 DC 0 pulse 1.5 0 0 200p 200p 159.8n 320nVB3 B3 0 DC 0 pulse 1.5 0 0 200p 200p 79.8n 160nVB2 B2 0 DC 0 pulse 1.5 0 0 200p 200p 39.8n 80nVB1 B1 0 DC 0 pulse 1.5 0 0 200p 200p 19.8n 40nVB0 B0 0 DC 0 pulse 1.5 0 0 200p 200p 9.8n 20n

X1 VDD VREFP VREFM Vout B7 B6 B5 B4 B3 B2 B1 B0 DAC8bit


Figure 30.34 Generating logic levels using voltage controlled switches.

1 V

BXLClosed when BX > trip

Closed when BX < trip

BX is the logic input witha, possibly, poorly definedamplitude.

In this netlist we are assuming and . The pulse sources step theVREF+ = 1.5V VREF− = 0DAC through all possible codes, i.e. from 00000000 (= 0V) all the way up to 11111111 (=1.5V − 1 LSB) in increments of 1.5/256 or 5.859 mV (= 1 LSB.) The simulation results areshown in Fig. 30.36. It should be very easy to see how to implement any resolution idealDAC at this point using SPICE.

Before leaving the ideal DAC let's discuss how to shift the ideal outputcharacteristics up by 1 LSB. The DAC in Fig. 30.35 has an output range of 0V to(VREF−)VDD − 1 LSB . We can re-write Eqn. 30.25 as(VREF+ − 1LSB)

VOUT =

1LSB

(VREF+ − VREF−) ⋅ 12N

⋅(bN−12N−1 + bN−22N−2 + ... + b1 ⋅ 21 + b0) + VREF−

(30.26)


*** Start Ideal 8-bit DAC Subcircuit *************************

.subckt DAC8bit VDD VREFP VREFM Vout B7 B6 B5 B4 B3 B2 B1 B0

*Generate Logic switching point, or trip, voltageR1 VDD trip 100MEGR2 trip 0 100MEG

*Change input logic signals into logic 0s or 1sX7 trip B7 B7L BitlogicX6 trip B6 B6L BitlogicX5 trip B5 B5L BitlogicX4 trip B4 B4L BitlogicX3 trip B3 B3L BitlogicX2 trip B2 B2L BitlogicX1 trip B1 B1L BitlogicX0 trip B0 B0L Bitlogic

*Non-linear dependent source, B, for generating the DAC outputBout Vout 0 V=((v(vrefp)-v(vrefm))/256)*(v(B7L)*128+v(B6L)*64++v(B5L)*32+v(B4L)*16+v(B3L)*8+v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm)

.ends

.subckt Bitlogic trip BX BXL Vone one 0 DC 1SH one BXL BX trip SwitmodSL 0 BXL trip BX Switmod.model switmod SW.ends

*** END DAC Subcircuit *************************************

Figure 30.35 SPICE subcircuit netlist for an ideal 8-bit DAC.


Figure 30.36 Simulating an ideal 8-bit DAC.

DA

C in

puts

(le

vel s

hift

ed f

or e

asy

view

ing)

DAC Output

DAC Inputs

b0

b7

To shift the output up by 1 LSB (so the output of the ideal DAC ranges from 1 LSB above to ) we simply add one to the binary-weighted term in the parentheses orVREF− VREF+

VOUT =

1LSB

(VREF+ − VREF−) ⋅ 12N

⋅(bN−12N−1 + bN−22N−2 + ... + b1 ⋅ 21 + b0 + 1) + VREF−

(30.27)

This equation is trivial to implement in our ideal DAC by adding two characters to ournon-linear dependent source, i.e. "+1".

30.2.2 The Ideal ADC

The characteristics of our ideal analog-to-digital converter (ADC) are shown in Fig.30.37. (Again, a complete discussion of ADC characteristics was given in Ch. 28.) Noticehow in this figure the transfer curve is shifted to the left. If we were to flip the curve on it'sside and mark, with black dots, the intersection of the analog input voltage with the ADCtransfer curve, we would have the DAC transfer curve of Fig. 30.33. Again 1 LSB is givenby Eq. 30.23. Notice how converting a (normalized) input voltage of 0.1 V will result in anoutput code of 000 which is the same output code resulting from converting 0 V. Unlikethe ideal DAC, the ideal ADC quantizes its input with the practical result of adding noiseto the input signal. This noise is often called quantization noise.

The implementation of the ideal ADC consists of an ideal S/H followed by passingthe output of the S/H (the held signal) through an algorithm to generate the output bits.The algorithm we use is based on a pipeline ADC and follows:

1. The input signal is sampled and held.

2. This held signal is input to a comparator that compares the input value to areference voltage.

3. If the input signal is greater than the reference voltage, the output bit is set to ahigh, and the reference signal is subtracted from the input. The difference is multiplied bytwo and passed to the output of stage.

4. If the input signal is less than the reference voltage, the output bit is set low.The input signal is multiplied by two and passed to the output of the stage.

5. This output is used as the input to the next stage and steps 2, 3, and 4 above arerepeated. This continues for N stages (where N is the number of bits in the ADC).

The reference voltage, or common mode voltage VCM , can be determined bycalculating the midpoint between and followed by subtracting so thatVREF+ VREF− VREF−the is referenced to 0V. This can be written asVCM

(30.28)VCM = VREF+ + VREF−

2→ VCM0 = VREF+ + VREF−

2− VREF− = VREF+ − VREF−

2

We also want to level shift the input signal so that it is referenced to 0V. In addition, wewant to shift the transfer curves to the left by 1/2 LSB as seen in Fig. 30.37. To do this we


use the following SPICE statement (for an 8-bit ADC where V(OUTSH) is the outputvoltage of the ideal S/H [the input to the pipeline algorithm above])

* Level shift by VREFM and 1/2LSBBPIP PIPIN 0 V=V(OUTSH)-V(VREFM)+((V(VREFP)-V(VREFM))/2^9)

The last term in this statement is 1/2 LSB, which is given by

assuming (30.29)1/2 LSB = VREF+ − VREF−

2N+1VREF+ > VREF− ≥ 0

We are level-shifting the input and common-mode voltage because we want to make themodel as flexible as possible. For example, we want the ADC model to function if =VREF+0.5V and . Note that if and , the model can beVREF− = 0.25V VREF− = 0 VREF+ = VDDsimplified.


000

001

010

011

100

101

110

111

Digitaloutput code,

0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 8/8

Analog input

Ideal

3-bit ADC

Figure 30.37 An ideal 3-bit ADC.

Analog input voltage

b2b1b0

VIN − VREF−

VREF+ − VREF−

VREF−VREF+ − 1LSB

VREF−

VREF+

VIN

b2

b1

b0

1LSB

fclk


*** START IDEAL 8-BIT ADC Subcircuit ******************************.subckt ADC8bit VDD VREFP VREFM Vin B7 B6 B5 B4 B3 B2 B1 B0 CLOCK

* Set up common mode voltageBCM VCM 0 V=(V(VREFP)-V(VREFM))/2

* Set up logic switching pointR3 VDD VTRIP 100MEGR4 VTRIP 0 100MEG

* Ideal input sample and hold XSH VDD VTRIP VIN OUTSH CLOCK SAMPHOLD


* 8-bit pipeline ADCX7 VDD VTRIP VCM PIPIN B7 VOUT7 ADCBITX6 VDD VTRIP VCM VOUT7 B6 VOUT6 ADCBITX5 VDD VTRIP VCM VOUT6 B5 VOUT5 ADCBITX4 VDD VTRIP VCM VOUT5 B4 VOUT4 ADCBITX3 VDD VTRIP VCM VOUT4 B3 VOUT3 ADCBITX2 VDD VTRIP VCM VOUT3 B2 VOUT2 ADCBITX1 VDD VTRIP VCM VOUT2 B1 VOUT1 ADCBITX0 VDD VTRIP VCM VOUT1 B0 VOUT0 ADCBIT.ends

* Ideal Sample and Hold subcircuit.SUBCKT SAMPHOLD VDD VTRIP Vin Vout CLOCKEin Vinbuf 0 Vin Vinbuf 100MEGS1 Vinbuf VinS VTRIP CLOCK switmodCs1 VinS 0 1e-10S2 VinS Vout1 CLOCK VTRIP switmodCout1 Vout1 0 1e-16Eout Vout 0 Vout1 0 1.model switmod SW .ends

* Pipeline stage.SUBCKT ADCBIT VDD VTRIP VCM VIN BITOUT VOUTS1 VDD BITOUT VIN VCM switmodS2 0 BITOUT VCM VIN switmodEouth Vinh 0 VIN VCM 2Eoutl Vinl 0 VIN 0 2S3 Vinh VOUT BITOUT VTRIP switmodS4 Vinl VOUT VTRIP BITOUT switmod.model switmod SW .ends*** END ADC Subcircuit *************************************

Figure 30.38 SPICE subcircuit netlist for an ideal 8-bit ADC.

Example 30.9Modify the SPICE code of Fig. 30.38 so that the subcircuit simulates an ideal12-bit ADC.

We can change the level shift statement (change 9 to 13) to


and add to the pipeline algorithm

* 12-bit pipeline ADCX11 VDD VTRIP VCM PIPIN B11 VOUT11 ADCBITX10 VDD VTRIP VCM VOUT11 B10 VOUT10 ADCBITX9 VDD VTRIP VCM VOUT10 B9 VOUT9 ADCBITX8 VDD VTRIP VCM VOUT9 B8 VOUT8 ADCBITX7 VDD VTRIP VCM VOUT8 B7 VOUT7 ADCBIT

where the last statement is a modification of the existing, in the 8-bit ideal ADC,statement for X7.

We can simulate the operation of our ideal 8-bit ADC in several ways. Let's beginby simply applying a ramp from to (0 to 1.5V) to the ADC while clocking theVREF− VREF+ADC at 100 MHz. The results are shown in Fig. 30.39. Additional simulations using theideal ADC will be left as an exercise for the reader. We are now in a position to put ourideal ADC and DAC together so that we can look at the spectral response and limitationsresulting from quantization noise.

Summary

It's important to realize the usefulness of the simulation models we have just developed. Inany mixed-signal simulation using SPICE we can use our ideal ADC to generate a digitalsignal, most often a sinewave, as an input source. We can use the DAC to convert a digitalword into an analog waveform. We can then take the Discrete Fourier Transform of theresulting analog waveform, using the SPICE "spec" command, and view the digital data'sspectrum.

Note that in this chapter we are only discussing the use of the offset binary format(see Ch. 29) for our digital words (0000... corresponds to and 1111... correspondsVREF−to ). It should be clear that we can modify our ideal data converters to workVREF+ − 1LSBwith any data format. We could also add digital logic to our converter subcircuit for theformat conversion and continue to use the ideal ADC/DAC developed in this chapter.

30.3 Quantization Noise

At this point we should understand the sampling process and understand the operation ofthe ideal ADC and DAC. What we want to do in this section is understand quantizationnoise (the effective noise added to a signal after passing through an ADC) and how itaffects the spectrum of a signal.



Figure 30.39 Simulating an ideal 8-bit ADC.

ADC Outputs and clock

ADC Input

ADC input andS/H output

b0

b7

Clock

30.3.1 Viewing the Quantization Noise Spectrum Using Simulations

Consider the simple connection of an ideal 8-bit ADC to an ideal 8-bit DAC as shown inFig. 30.40. If we put an 7 MHz sinewave into the ADC with an amplitude of 0.75 V andan offset of 0.75 V (so the sinewave swings from to ])VREF− [= 0 V here] VREF+ [= 1.5 Vand clock the ADC at 100 MHz the waveforms of Fig. 30.41 result. Note how the outputof the DAC looks very similar to the output of an ideal S/H (see Fig. 30.25.) Now,however, the amplitude of the DAC output signal is quantized, that is, within 1 LSB (=1.5/256 or 5.859 mV for the present simulation) of the ADC input. This quantization isnot obvious after looking at Fig. 30.41 (the time domain response). However, looking atthe spectrums of the ADC input and the DAC output reveal the difference in the noisefloor between the two (Fig. 30.42.) The inherent noise floor in the simulation, that isassociated with the input signal, is approximately −140 dB (0.1 µV.) The noise floorassociated with the DAC's output (the signal + quantization noise) is approximately −60dB (1 mV). It is desirable to determine what sets this value and its spectral content. Againnote that the ADC quantizes the signal, which results in the quantization noise.


Ideal8-bit ADC

8Ideal

8-bit DAC

VDD = 1.5 VDD = 1.5

Figure 30.40 Passing a signal through an ADC and then through a DAC.

Analog Digital Analog

VIN VOUT

fclk

Figure 30.41 7 MHz ADC input and the corresponding DAC output.

fclk = f s = 100MHz

To characterize the spectral characteristics of the quantization noise let's make thefollowing assumptions (Bennett's criteria) concerning the signal we are converting:

1) The input (to the ADC) signal's amplitude variation falls between andVREF+ so that no saturation of the digital output code occurs. Exceeding the normalVREF−

operating range of the ADC affects the quantization noise spectrum by adding spurs orspikes to the output spectrum.

2) The ADCs LSB is much smaller than the input signal amplitude. When this isn'tthe case, the output of the ADC can appear squarewave (when converted back into ananalog waveform) like and result in a spectrum, once again, that contains spikes or spurs.We'll see later in the book that adding or subtracting a fed-back signal (from the outputbased on the expected or past quantization noise) to the input modifies this requirement.

3) The input signal is busy (not DC or a low frequency input.) We define busy, forthe moment, as meaning that no two consecutive outputs of the ADC have the samedigital code. For the ideal ADC of Fig. 30.41 and so that the1LSB = 5.86 mV Ts = 10 nsinput must change at least 5.86 mV every 10 ns. We'll see that adding a high-frequencydither or pusedo-random noise signal to the input, which can be filtered out later (eitherusing a digital filter or when we pass the output through the reconstruction filter), canmake the requirement on the input of being busy practical in an actual circuit.


DAC Output,

ADC Input

Figure 30.42 Spectrums of the signals shown in Fig. 30.41.

Sign

al p

lus

Noi

se, S

+N

, Vol

ts p

eak

fn fclk = f s

7 MHz, 0.75V peak (−2.5 dB)

VFFT( f )

We use these assumptions (Bennett's criteria) in the following discussion unless otherwiseindicated.

An Important Note

It's important to note that simply sampling an input waveform, using an S/H, does notresult in quantization noise, as seen in Fig. 30.29. The amplitude into the ideal S/H, at thesampling instant, is exactly the same as the amplitude out of the ideal S/H. To understandwhy this is important, consider the test setup shown in Fig. 30.43. If we input the 3 MHzsinewave of Ex. 30.7 into this circuit, we get the outputs shown in Fig. 30.44. Clearlythere is a difference between the S/H's input and its output. However, this difference hasnothing to do with noise, an unwanted signal, since passing the output of the S/H, VOUTSH ,


Figure 30.43 Taking the difference between the S/H input and output.

IdealS/H

VINVOUT

fclk

VOUTSH

Figure 30.44 (a) Time domain difference between S/H input and output and (b) spectrum.

Difference output

Input spectrum

Difference spectrum

Vol

ts, p

eak

VOUT

through the ideal reconstruction filter of Fig. 30.30 results in an exact replica of the S/Hinput VIN .

RMS Quantization Noise Voltage

If we were to set up a test configuration similar to that shown in Fig. 30.43 (see Fig.30.45) where the input to the ADC is subtracted from the DAC output, the resultingoutput waveform would have little to do, in every case, with the quantization noise. Thisis especially true when the input to the ADC contains a broad frequency spectrumextending from DC to the Nyquist frequency, . However, if we simply apply afn = f s/2slow linear ramp to the input of this test setup (to limit the input frequency spectrum), seeFig. 30.45, we can 1) see the resulting quantization noise over a wide frequency spectrumand 2) observe the transfer curve, in the time domain, similar to Fig. 30.37. Note that thisinput violates Bennett's criteria (which, as we'll see, means the noise power spectraldensity is flat from DC to the Nyquist frequency.)

A section of the input and output, using the test setup of Fig. 30.45, is shown inFig. 30.46a. It's important to understand the input/output relationship between the idealADC and DAC shown in this figure. (Note that clocking the ADC too slow or putting in aramp that rises too quickly will distort this waveform.) As an example, when the ADCinput is slightly above 758.79 mV, in this figure, the ADC output code (input to the DAC)changes. The ADC output code can be calculated as 755.9 mV/1 LSB ( 1 LSB = 1.5/256 =5.86 mV for the present simulation) or 129 when the input is slightly below 758.79 mVand 130 when the input is slightly above 758.79 mV. Looking at the transfer curves in thisfigure it appears as though the output changes when the ADC code is 129.5 or 758.79mV/1 LSB. This, as seen in Fig. 30.46b and discussed below, results in centering thequantization error around the input (and is the reason we shifted the ADC transfer curvesby 1/2 LSB when we developed our ideal ADC model).

The difference output, between the two signals of Fig. 30.46a, is shown in Fig.30.46b. Some points to note about this sawtooth waveform 1) its average value is zero, 2)the waveform contains an abrupt transition (and so we expect a wideband output spectrumsimilar to that which occurs after sampling a waveform), and 3) its peak-to-peakamplitude is 1 LSB. Like a sinewave, which also has zero average value, we cancharacterize this quantization error waveform by looking at its root-mean-square (RMS)


Figure 30.45 Taking the difference an ADC input and the DAC output.

IdealADC

IdealDAC

Slow RampVIN

VOUTDfclk

VOUT


ADC Input

DAC Output

Figure 30.46 (a) ADC input and DAC output.

764.65 mV

758.79 mV

1 LSB = 5.86 mV

Figure 30.46 (b) Difference between ADC input and DAC output.

Difference between ADC input and DAC outputwhen the ADC input is a slow ramp.

Note the frequency of this waveform is 10 MHz.

1/2 LSB

−1/2 LSB

value. This value can be calculated using

(30.30)VQe,RMS = 1T ∫

0

T

(0.5LSB − 1LSBT

⋅ t)2dt = 1 LSB12

= VLSB

12

This value is the RMS Quantization Noise Voltage for a specific data converter. Note thatthe value of the period for this sawtooth waveform, T , doesn't appear in the evaluatedresult of this equation. Also note that the sampling frequency, fs , isn't present in thisequation. For our present discussion where 1 LSB is 5.86 mV orVQe,RMS = 1.69 mV−55.43 dB.

Treating Quantization Noise as a Random Variable

If Bennett's criteria holds, then the quantization noise voltage can be thought of as arandom variable falling in the range of , as seen in Fig. 30.47. The probability±0.5 LSBthat the quantization error is −0.2 LSB is the same as the probability that the error is 0.4LSB. In other words, there is no reason why the quantization error should have one valuemore often than another value.

The quantization error noise power is the variance of the probability densityfunction. The RMS quantization error voltage is the square root of the quantization noisepower. The variance of the probability density function (the quantization noise power, PQe)is given, knowing the average of the quantization error, , is zero, byQe

(30.31)PQe = ∫−1/2LSB

1/2LSB

ρ ⋅ (Qe)2 ⋅ dQe = VLSB2

12

so that, once again, the RMS quantization noise voltage is

(30.32)VQe,RMS = VLSB

12

Again, if our LSB voltage is 5.86 mV, then, once again, (−55.4 dB.) IfVQe,RMS = 1.69 mVwe look at Fig. 30.42 we see that the peak noise voltage, at a given frequency, variesessentially over the entire spectrum (white noise) and has a value ranging from −60 dBdown to less than −80 dB. Note that although the entire spectrum contains quantization


Figure 30.47 Probability density function for the quantization error in an ADCassuming Bennett's criteria holds.

1/2 LSB−1/2 LSB

Probability density function, ρ

1VLSB

∫−1/2LSB

1/2LSB

ρ ⋅ dQe = 1

Qe

1 LSB = VLSB

noise it is not because of the sampling process used in the ADC (and so quantization noisedoesn't experience aliasing.) Quantization noise is added to the signal after the samplingprocess during the analog-to-digital conversion process. To qualitatively understand whythe quantization error spectrum is white, in Fig. 30.42, we remember that there are abrupttransitions in the DAC output, and if the quantization error is truly random, the timesbetween the changes have varying periods. We might speculate that by simulating a longertime or using a multiple frequency input so as to "exercise" the ADC, the resultingquantization errors are further randomized and the resulting error spectrum will be flat.

Calculating RMS Quantization Noise Voltage from a Spectrum

The voltage spectrums for the quantization noise and the input signal (Figs. 30.46a and b)are shown in Fig. 30.48. Note that the harmonics of the noise are, as we would expect,spaced by 10 MHz (= 1/T ). Also note, the sampling frequency doesn't affect the value ofthe RMS quantization noise voltage. The peak voltage of the fundamental tone in thequantization noise voltage spectrum is approximately −55 dB or −58 dB RMS (peakvoltages [magnitudes] are used in the spectrum plots shown in this chapter unlessotherwise indicated). To relate the RMS noise voltage calculated above, i.e., −55.4 dB, tothe values shown in Fig. 30.48 we would: 1) convert the peak voltages to RMS values bysubtracting 3 dB from each value, 2) square each result to get the mean-squared voltage,3) sum the mean squared values, and 4) take the square root of this sum to get the RMSquantization noise voltage. Looking at the peak values of the first three tones in the


Figure 30.48 Input and quantization noise spectrums for the signals of Fig. 30.46.

Input Ramp Spectrum

Quantization Noise Spectrum

Vol

tage

, pea

k

quantization noise spectrum, −55 dB, −60 dB, and −65 dB we convert these values toRMS voltages, 1.26 mV, 0.708 mV, and 0.398 mV. The quantization noise, calculated

using only the first three tones, is then = 1.5 mV, RMS or(1.26)2 + (0.708)2 + (0.398)2

−56.5 dB. Clearly, increasing the number of tones used in this calculation will cause theresult to approach Eq. (30.30) (1.69 mV).

To calculate the RMS quantization noise voltage from a DAC output spectrum wesum the mean-squared contribution from each component (after removing the desiredtones from the spectrum) and then take the square root of the result (as mentioned above.)See VFFT( f ) in Fig. 30.42 as an example. If the resolution of the FFT is fRES , then we canwrite this as

where (30.33)VQe,RMS = 12

⋅ Σk=0

M−1

VFFT2 ( k ⋅ fRES ) M = #FFTpoints

The factor of root two comes from changing the peak values in a spectrum to RMSquantities. Note that the term "bin" is often used to describe the fact that the output of theFast Fourier transform is only valid at discrete frequencies (the bins.) The number of binsis also known as the number of points in an FFT output vector (labeled #FFTpoints or Min Eq. [30.33]). This is seen in Fig. 30.48 (also shown in Fig. 30.48 is an FFT problemknown as the "picket fence" effect which will be discussed in a moment). If the FFTresolution in a simulation is 1 MHz then the FFT output, assuming the starting frequencyis DC (0), will have nonzero values at DC, 1 MHz, 2 MHz, and so forth. If the stopfrequency is 200 MHz, then the total number of points in an FFT output vector is 201.

Note that if Bennett's criteria holds, Eq. (30.33) will equal . If it doesn'tVLSB/ 12hold, then the calculated using Eq. (30.33) will be different from . AnVQe,RMS VLSB/ 12input high-frequency sinewave violates Bennett's criteria. For example, consider samplinga 25 MHz sinewave at 100 MHz. If the sample points occur at the zero crossing points onthe sinewave and at the peak/valley points, the resulting DAC output will be a rectangularwaveform with a well-defined spectrum.

After a simulation we can determine the length of the FFT output vectors using the

display

command or for a specific vector, say voutd, we can use

print length(voutd)

These commands show, in the WinSPICE command window, the length of the vectors andthe type, e.g., complex, real, db, etc. (for the display command) or the length of aparticular vector (for the "print length" command).

If we want to set a component of the FFT to a value, say zero, we may want to usea command sequence like

let m=mag(voutd)let m[7]=0


This sequence of commands sets the ninth element of a vector to zero (since we start atelement zero.) This is often done to remove a tone in an output spectrum resulting fromthe input signal or some other distortion.

Example 30.10Using WinSPICE calculate the RMS Quantization Noise Voltage from thespectrum of Fig. 30.48.

We begin by running the simulation that generates this figure (running the netlistfile Fig30_48.cir). After the simulation is completed we type, in the WinSPICEcommand window,

display

and the following appears:

frequency : frequency, real, 401 long [default scale]vin : voltage, complex, 401 longvindb : decibel, real, 401 longvoutd : voltage, complex, 401 longvoutdb : decibel, real, 401 long

We see from this that the length of the FFT is 401. Note that we could have usedthe length command, as we'll do below, to determine the length of the FFT insteadof the display command.

To calculate the RMS Quantization Noise Voltage we can use the following:

let m=mag(voutd)let qnoise=0.707*sqrt(mean(m*m)*length(m))print qnoise

which gives a result of 2.08 mV, a value larger than the 1.69 mV calculated for earlier. Before we discuss the discrepancy between the two RMS voltages,VQe,RMS

notice that we took the average (mean) of the mean-squared value of voutd andthen multiplied the result by its length to sum the mean-squared voltages asspecified by Eq. (30.33).

Now we need to discuss the difference between the SPICE simulated and thecalculated RMS Quantization Noise Voltages above. While the implementation of a FastFourier Transform is outside the subject matter of this book, we can comment here on twoFFT problems and how to reduce their effects; namely, the picket-fence effect and spectralleakage.

The picket fence effect, and the visual reason for its name, is shown in the insertfigure in Fig. 30.48. Coherent sampling (synchronizing the quantization error, Fig. 30.46,with the sampling clock) was used to magnify the effect. In our discussion above weassumed, for the first tone at 10 MHz, that the contribution to was − 55 dB. OnVQe,RMS

closer inspection, we see that there are also contributions, − 61 dB, to the quantizationnoise at 9.5 MHz and 10.5 MHz. At these two side frequencies, the amplitude


contribution is one-half of the main contribution (− 6 dB below the main contribution.)Figure 30.49 shows that if one over the simulation time is equal to the FFT resolution thenthe boundaries between the adjacent FFT output points, spaced by the reciprocal of thesimulation time, are coincident. This results in averaging adjacent contributions when theFFT output is generated. To reduce the effects of this averaging, we can increase thelength of the simulation (having the effect of decreasing the window width used with theFFT). We can modify Eq. 30.6 to reduce the picket-fence effects by requiring

(30.34)Simulation time, Tstop ≥ 2FFT resolution

= 2f res

Example 30.11Repeat Example 30.10 if Eq. 30.34 is used to set the FFT resolution andsimulation length.

In Example 30.10 the simulation time was 2,000 ns. We could increase thesimulation time to 4,000 ns or reduce the FFT resolution from 500 kHz to 1 MHz.In order to keep the simulation time reasonably short (and to avoid spectralleakage discussed next) we will decrease the FFT resolution and leave thesimulation time at 2,000 ns. Figure 30.50 shows the resulting output spectrum withthe decreased FFT resolution (now 1 MHz.) The RMS Quantization NoiseVoltage calculated by SPICE, from this spectrum, is 1.71 mV RMS.

To understand what is meant by "spectral leakage," consider the sinewave withinfinite duration shown in Fig. 30.51a. When an FFT is performed on a time domainwaveform, the first step is to "window" the waveform. The simplest window is therectangular window. In a simulation the duration of the sinewave is finite and set by thesimulation time or transient stop time, Tstop . We can think of taking the infinite durationsinewave of Fig. 30.51a and multiplying it by the rectangular waveform of Fig. 30.51b toobtain the waveform used in the simulation, Fig. 30.51c. This multiplication means theresulting waveform is the convolution of the original sinewave spectral response (animpulse) and the frequency domain transform of the squarewave (a Sinc waveform) in the


Figure 30.49 Showing the origins of the picket-fence effect.

FFT Points 0 1 2

FFT resolution

1/(simulation time)

Plotting

0

11

0.5 0.5

0 1 2

= 1/Tstop


Figure 30.51 Showing how spectral leakage, resulting from an FFT, affects a waveform.

t

(a)

t

(b)

t

(c)

11

1

f

(d)

1

Frequency spectrum of (a)

f

(e) Frequency spectrum of (c)

f

(f), von Hann (Hanning) window

Linear amplitude

Log amplitude

Tstop

Tstop

Tstop

1/Tstop

f in

f in

f in

f in1/Tstop

Figure 30.50 Eliminating the picket-fence effect from the simulation in Fig. 30.48.

Qua

ntiz

atio

n N

oise

Vol

tage

, pea

k

frequency domain. The result is that instead of the sinewave spectral response being animpulse function, as seen in Fig. 30.51d, it is a weighted Sinc waveform, Fig. 30.51e. Notehow the FFT spectral response of the sinewave, Fig. 30.51e, is spread out or "leaks" intothe frequencies around the actual, or continuous time response. The large ratio of the peakvalue of the Sinc pulse to its first sidelobe is usually undesirable. Rather, to minimize thesesidelobes, other windowing functions are used. The one we are using in this chapter is thevon Hann (a.k.a. Hanning or Cosine) window shown, without the sidelobes, in Fig. 30.51f.The response is shown on both linear and log amplitude scales and the width of thewindow is 2/Tstop at its base (= 1 MHz if Tstop = 2,000 ns.)

Example 30.12Using SPICE show the spectrum of a 1-V (peak) sinewave at 10 MHz over aspectral range of DC to 200 MHz with an FFT resolution of 1 MHz and asimulation time of 2,000 ns (windowed frequency spread of 1 MHz, Fig. 30.51e.)

The results are shown in Fig. 30.52. Note how the only point in these figures thathas a nonzero value occurs at 10 MHz. The plotting lines are used to connect thefive FFT output points shown in each of these figures.

We were careful, in the previous example, to select the sinewave frequency to

coincide exactly with one of the points were the FFT is calculated (10 MHz.) We know inthe previous example that the FFT points are calculated at DC, 1 MHz, 2 MHz, ..., 200MHz. An error in the FFT output response occurs if spectral content doesn't fall on one ofthese frequencies. Consider the following example.

Example 30.13Repeat Ex. 30.12 if the sinewave frequency is changed to 10.4 MHz.

The FFT output is shown in Fig. 30.53. Note that although the input frequency isat 10.4 MHz the peak in the FFT response still occurs at 10 MHz (an FFT outputpoint.) Also notice how the spectrum of the sinewave is effectively wider than thesinewave of Ex. 30.12. The 10.4 MHz sinewave is within the FFT resolution ofboth the 10 MHz and 11 MHz points. The result is effective spectral content atthese frequencies. Sinewaves that do not fall exactly at the FFT calculation pointsare smeared in the FFT output spectrum. This smearing can spread across the


Figure 30.52 Output spectrum of 10 MHz sinewave showing the window's effect.

spectrum and affect spectral content at other frequencies. Consider the followingexample.

Example 30.14Using SPICE plot the output spectrum resulting from adding the 10 MHz and 10.4MHz sinewaves from the previous two examples.

The results are shown in Fig. 30.54. Note how, even though the 10 MHz sinewavehas an amplitude of 1 V, the resulting output spectrum reports an amplitude ofapproximately 600 mV at 10 MHz. This is a result of contributions from the 10.4MHz signal, after windowing, subtracting from the 10 MHz signal calculationpoint.

It's important to understand that by increasing the simulation time, the windowlength increases causing the width of the Sinc spectrum, see Fig. 30.51e, to decrease.However, increasing the simulation time without making a corresponding change in theFFT resolution can actually be harmful to the results. For example, if 1/Tstop is 100 kHz(simulation time of 10,000 ns) and the FFT resolution is 1 MHz then an input sinewave at10.5 MHz will have no effect on the resulting output spectrum. In general, it's importantto make

(30.35)Simulation time, Tstop = 2FFT resolution

= 2fres


Figure 30.54 Magnitude and spectral response for the sum of the 10 and 10.4 MHz sinewaves.

Figure 30.53 Magnitude and spectral response for the 10.4 MHz sinewave of Ex. 30.13.

Also note that in a general simulation, which includes MOSFETs, we can set the step sizeused in a transient simulation with Eq. (30.8). However when using ideal components, asin this chapter, the step size can be increased to speed up the simulation time.

Example 30.15Determine the RMS Quantization Noise Voltage from the DAC output spectrumshown in Fig. 30.42.

Figure 30.42 was generated with an FFT resolution of 1 MHz and a simulationtime of 1,000 ns. We will increase the simulation time to 2,000 ns. The resimulatedspectrum of the DAC output noise is shown in Fig. 30.55. Notice in this spectrumthat there is a signal at DC and 7 MHz (from the input signal.) Also, the aliasedsignals are present in the output spectrum at 93 MHz, 107 MHz, and 193 MHz.To calculate the quantization noise we would have to first zero these componentsout. We can use the following WinSPICE commands to calculate the quantizationnoise:

let m=mag(vout)let m[0]=0let m[7]=0let m[93]=0let m[107]=0let m[193]=0let qnoise=0.707*sqrt(mean(m*m)*length(m))print qnoise

The resulting RMS Quantization Noise Voltage is 1.72 mV.


Figure 30.55 Simulating the circuit shown in Fig. 30.40 for 2,000 ns.

Sign

al p

lus

Noi

se, S

+N

, Vol

ts p

eak

Note that the simulations we have shown in this chapter generate spectralresponses out to twice the clocking frequency or 200 MHz when using a 100 MHz clock.To reduce simulation time we may limit the spectral response to the Nyquist frequency.Also, an important component of the simulations can be the addition of

.options RELTOL=1u

to a netlist. Not including this statement or one similar (e.g. RELTOL = 10u) in a netlistmay limit the simulated noise floor to a significant voltage.

WinSPICE can also be useful if measured data is available. The data from aspectrum analyzer can be written to a text file and loaded into a WinSPICE vector usingthe load command. See the WinSPICE online manual.

The FFTs Relationship to the Continuous Time Fourier Transform

Before we leave this section, let's comment on how the Discrete Fourier Transform(implemented using a Fast Fourier Transform algorithm) is related to the Continuous TimeFourier Transform. We can write the Continuous Time Fourier Transform of a timevarying function, v(t), using

(30.36)V( f ) = ∫−∞

∞

v(t) ⋅ e−j2πf⋅t ⋅ dt

or if we assume a finite simulation time

(30.37)V( f ) = ∫0

Tstop

v(t) ⋅ e−2πf⋅t ⋅ dt

To approximate this Continuous Time Fourier Transform with discrete variables we willuse the following

where (30.38)dt = ∆t and t = k ⋅ ∆t k = 0, 1, ... N

The variable is the transient step time (the time difference between points in the FFT∆talgorithm) and N is the number of time steps used in the algorithm . The(Tstop = N ⋅ ∆t)frequencies where the FFT is calculated, assuming Eq. 30.35 is valid, is given by

(30.39)f = n ⋅ f res = 2nTstop

where n = 0, 1, ... M − 1

The variable M is the number of points in the FFT output vector (the number offrequencies the FFT is calculated at.) Finally, we can relate the Continuous Time FourierTransform, evaluated at discrete frequencies, to the Discrete Fourier Transform with

(30.40)V( f ) f=n⋅fres ≈

Discrete Fourier transform, VFFT(n)

Σk=0

N

v(k ⋅ ∆t) ⋅ e−j(4π/N)nk ⋅∆t

(noting that is used in the exponent because our FFT resolution was twice the4πreciprocal of the simulation time) or


(30.41)V( f ) f = n⋅fres ≈ ∆t ⋅ VFFT(n )

In general, an FFT output is scaled, divided by , so that it approximates the continuous∆ttime Fourier Transform when it is plotted. This is usually transparent to the user of theFFT routine.

30.3.2 Quantization Noise Voltage Spectral Density

If the quantization noise voltage spectrum is truly flat (Bennett's criteria holds) we candetermine the noise power spectral density of , with units of , or theVQe,RMS VQe

2 ( f ) V2/Hz

noise voltage spectral density, with units of by solvingVQe( f ) V/ Hz

(30.42)

VLSB2

12= 2 ∫

0

fs/2

VQe2 ( f ) ⋅ df

where the factor of two accounts for the power in the negative frequencies of thespectrum. (See Ch. 7 for a discussion of noise spectral densities) We are assuming that thenoise power is bandlimited to the Nyquist frequency (the output of the DAC is passedthrough an ideal RCF). Solving Eq. 30.42 yields

(30.43)VQe( f ) = VLSB

12f s

= VREF+ − VREF−

2N 12f s

with units of . The Quantization Noise Spectral Density is inversely proportional toV/ Hzthe sampling frequency. Figure 30.56 shows that we can model the ADC as a summingblock with added to the input signal. VQe( f )

After looking at Eq. 30.43 we might think that by simply increasing the samplingfrequency we can reduce the amount of quantization noise an ADC introduces into ananalog input signal. While increasing the sampling frequency spreads the quantizationnoise spectral density out over a wider range of frequencies, see Fig. 30.57, with acorresponding reduction in amplitude, the sampling frequency doesn't affect the total RMSQuantization Noise Voltage. However, bandlimiting the spectrum using a filter reduces theamount of quantization noise introduced into an input signal. In the simplest case a lowpass filter, which we will think of as an averager, can be applied to the ADC output, which


Ideal8-bit ADC

AnalogDigital

Figure 30.56 Modeling ADC quantization noise.

Digital AnalogVIN

fclk

VIN

VQe( f )

is digital, to reduce the amount of quantization noise introduced into the signal. We canwrite the amount of noise introduced into an input signal over a range of frequencies using

where (30.44)VQe,RMS2 = 2 ∫

fL

fH

VQe2 ( f ) ⋅ df fL < fH ≤ f s/2

Again the factor of two is used to account for the contributions to in the negativeVQe,RMS

frequency spectrum (the FFT routine, discussed in the previous section, uses a one-sidedspectrum so the factor of two is not necessary when making calculations using the SPICEsimulation output data.) Because the output of the ADC is a digital word, we wouldrequire a digital filter to bandlimit the output spectrum of the ADC. We will discuss digitalfiltering in the next chapter. For now let's show that the sampling frequency indeed doesn'taffect the quantization noise, assuming Bennett's criteria are valid, and then let's discussthe concept of averaging to reduce quantization noise.

Example 30.16Repeat Ex. 30.11 if the sampling frequency is increased from 100 MHz to 200MHz.

Doubling the sampling frequency has no effect on the output quantization noise. Itremains at 1.69 mV RMS.

Example 30.17Repeat Ex. 30.15 if the sampling frequency is increased from 100 MHz to 200MHz.

Again, the RMS Quantization Noise Voltage remains essentially unchanged, i.e.,1.68 mV RMS. Recall that the circuit shown in Fig. 30.40 is used in this exampleand Ex. 30.15 with an 7 MHz input. It's instructive to show the time domainoutput of Fig. 30.40 when clocked at 200 MHz, Fig. 30.58, and compare it to Fig.30.41 (the output of the circuit of Fig. 30.40 clocked at 100 MHz). Note how theDAC output voltage step size has decreased in Fig. 30.58 when compared to Fig.30.41, yet the quantization noise remains unchanged. This shows, once again, thatwe must look at the spectrum of a signal to determine the quantization noisevoltage and that the "coarseness" of an output signal has nothing to do withquantization noise.


Figure 30.57 Quantization Noise Spectral Density.

f fn = f s/2

VQe( f )

VLSB

12fs

Reducing Quantization Noise Using Averaging

Consider the parallel combination of ADCs and DACs shown in Fig. 30.59. The top ADCand DAC are essentially the path we had back in Fig. 30.40 clocked at 100 MHz. Thebottom path is a mirror image of the top except that its clock signal is inverted (delayed by5 ns.) The two resistors are used to average the output of the DACs, or

(30.45)VOUT = VOUTA + VOUTB

2


Figure 30.59 Using two paths to average the quantization noise.

Ideal8-bit ADC

8Ideal

8-bit DAC

Analog

Digital

Analog

Ideal8-bit ADC

8Ideal

8-bit DAC

VIN

VOUT

fclk = 100 MHz

VOUTA

VOUTB

Figure 30.58 Output of the circuit shown in Fig. 30.40 with 7 MHz input and 200 MHzsampling clock. This figure should be compared to Fig. 30.41.

Note that this configuration effectively samples the input at 200 MHz (200 Msamples/s) as was accomplished in Fig. 30.58 except that now we are averaging consecutive[2 ⋅ f s]

samples. If we input an 7 MHz sinewave into this configuration, the same signal used inFig. 30.41 or Fig. 30.58, we get the output shown in Fig. 30.60. Note the resemblance toFig. 30.58. Also note the additional phase shift. The RMS Quantization Noise Voltagenow, however, has dropped from 1.68 mV to approximately 1.18 mV.

The Noise Spectral Density View of Averaging

In Fig. 30.59 we effectively doubled the sampling frequency. We can redraw Fig. 30.57, toshow the effects of averaging, by changing the amplitude in this figure from VLSB/ 12( f s)to and by increasing the frequency spectrum range as seen in Fig. 30.61.VLSB/ 12 ⋅ (2f s)Assuming that we are still interested in the spectrum up to , the RMS Quantizationf s/2Noise can be calculated using

(30.46)VQe,RMS2 = 2 ∫

0

fs/212

⋅VLSB

2

12f s⋅ df

or

(30.47)VQe,RMS = 1

2⋅ VLSB

12


Figure 30.60 Output of the circuit of Fig. 30.59 with an 7 MHz input sinewave.

In general, averaging K samples results in an RMS Quantization Noise Voltage of

(30.47)VQe,RMS = 1

K⋅ VLSB

12

The non-averaged noise, , is reduced by the root of the averaging factor K. WeVLSB/ 12know that the simulated in Ex. 30.17 was 1.68 mV. We simulated this circuit,VQe,RMS

again, using an averaging of two (Figs. 30.59 and 30.60) which resulted in a simulated of 1.18 mV. We could have estimated this RMS Quantization Noise beforehandVQe,RMS

using Eq. 30.47 as , which is, of course, the simulated result.(1.68 mV)/ 2 = 1.18 mV

An Important Note

For averaging to effectively reduce the RMS Quantization Noise, the ADC and DAC mustbe linear (how linear will be answered in the next chapter.) Examine Fig. 30.62. In theideal situation, two adjacent codes are averaged to give an output that falls exactly inbetween the outputs of the data converter. In the case where the data converter has anonlinearity, the averaged point doesn't necessarily provide an output that is muchdifferent from the data converter outputs themselves. If the data converter contains a


f

Original SpectrumNew Spectrum

Figure 30.61 Quantization Noise Spectral Density with two-sample averaging.The sampling rate is effectively doubled.

fn = f s/2

VQe( f ), V/ Hz

VLSB

12fs

1

2⋅ VLSB

12f s

f s

Figure 30.62 Showing how ADC or DAC linearity affects averaging.

Input signal

Idea

l dat

a co

nver

ter

switc

hing

leve

ls

Averaged

Points

Input signal

Averaged Points

Ideal situation Nonlinearity in transfer characteristics

Ideal code level

Actual code level

Indicates output of the data converter

missing code (an input difference between two inputs at consecutive sampling times of1-LSB results in the same output) then the averaging does nothing. If the data converter isnonmonotonic (an increase in the data converters input doesn't result in an increase in itsoutput) then the averaged value is meaningless. Finally, note that an input DC value (adigital code that isn't changing for the DAC or an analog voltage that isn't changing for theADC) or a value that isn't "busy" (not changing by at least 1 LSB in between samplinginstances) will not benefit from averaging. These topics are discussed further in the nextchapter.

Practical Implementation of Averaging in ADCs

The averaging topology shown in Fig. 30.59 is not practical in most situations. The siliconarea required to implement the extra ADC and DAC generally costs more than is gainedby the reduction in quantization noise. Also, as we'll see later, there are other techniquesfor averaging that provide a more efficient way to reduce quantization noise. Having saidthis and knowing that there are better ways, we will answer the question "How do weimplement an ADC using averaging?"

Figure 30.63 shows how we can add a digital averaging filter to the output of theADC to reduce quantization noise. The ADC and digital averaging filter are clocked at arate of fclk . If K = 2, for example, then the filter will sum its previous two inputs andoutput the result at a rate of fclk . This filter could be implemented with a register and anadder. Note that the output word size increases when using the digital filter (it had betterif we are reducing the quantization noise!) For example, if the output of the ADC is an8-bit word, then the running sum coming out of the filter, again assuming K = 2, will be9-bits.

We might, at this point, assume that we can use a low-resolution ADC, say 6-bits,with a significant amount of averaging to attain large resolutions (again the ADC must belinear.) Assuming the input to the ADC is busy and we place restrictions on the bandwidthof the signals coming into the ADC then we can increase the resolution by averaging. Wehave to place restrictions on the bandwidth of the signal coming into the ADC because,unlike Fig. 30.59, we haven't increased the sampling rate of the signals. Therefore, theamplitude of the spectral density remains unchanged. For an averaging of two, we wouldhave to limit our input signal bandwidth to fs /4. If this wasn't the case, then an inputsinewave at fs /2 would average to zero. Again, these topics will be discussed in greaterdetail in Ch. 31.


IdealADC

Figure 30.63 Using a digital averaging filter to reduce quantization noise.

Analog Digital Digital

DigitalAveraging

Filter

VIN

fclk

REFERENCES

[1] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS: Circuit Design, Layout, andSimulation, IEEE Press, 1998. ISBN 0-7803-3416-7

[2] L. W. Couch, Modern Communication Systems: Principles and Applications,Prentice-Hall, 1995. ISBN 0-02325286-3

[3] S. Haykin, An Introduction to Analog and Digital Communications, John Wiley andSons, 1989. ISBN 0-471-85978-8

[4] P. A. Lynn, and W. Fuerst, Introductory Digital Signal Processing, Second Edition,John Wiley and Sons, 1998. ISBN 0-471-97631-8

[5] E. P. Cunningham, Digital Filtering: An Introduction, John Wiley and Sons, 1995.ISBN 0-471-12475-3

[6] R. K. Hester, Introduction to Oversampled Data Conversion, Notes from a tutorial atthe 1995 International Solid-State Circuits Conference (ISSCC-95).

[7] W. R. Bennett, "Spectra of Quantized Signals," Bell System Technical Journal, Vol.27, pp. 446-472, July 1948.

[8] J. C. Candy, and G. C. Temes (eds.), Oversampling Delta-Sigma Data Converters,IEEE Press, 1992. ISBN 0-87942-285-8

[9] S. R. Norsworthy, R. Schreier, and G. C. Temes (eds.), Delta-Sigma DataConverters: Theory, Design, and Simulation, IEEE Press, 1996. ISBN 0-7803-1045-4

LIST OF SYMBOLS/ACRONYMS

AAF - Anti-Aliasing Filter

ADC - Analog-to-Digital Converter

- Hold capacitor in a S/HCH

DAC - Digital-to-Analog Converter

DSP - Digital Signal Processing

- Time difference between points used in an FFT∆t

- Clock signalφ

FFT - Fast Fourier Transform

fclk - Frequency of the input clock signal

- Input sinewave frequencyf in

- Nyquist frequency which is 50 MHz in this chapter. Sometimes also calledfn ( fn = f s/2)the folding frequency.

- Resolution of an FFTf res


- Sampling frequency which is 100 MHz in this chapter. Sometimes alsof s (Ts = 1/f s)called the Nyquist rate.

- Transfer functionH(jω)

Portion of the ideal S/H reconstruction filterHRCFSH( f ) =

k - Counting index

K - Averaging factor or oversampling ratio

LPF - Low Pass Filter

= Least Significant BitLSB = VLSB = VREF+ − VREF−

2N

n - Counting index

N - Number of bits in a data converter or the number of time steps in an FFT

M - Number of points in the output of an FFT (or order of modulator, see Ch. 32)

OTA - Operational Transconductance Amplifier

- Quantization errorQe

RCF - ReConstruction Filter

RZ - Return-to-Zero format

S/H - Sample and Hold

SPICE - Simulation Program with Integrated Circuit Emphasis

- Probability density functionρ

Sinc(x) = Sin(x)/x

- Phase of a functionθ

T - period of a periodic waveform

to - A time delay

- Sampling interval Ts (Ts = 1/f s)

- Final simulation timeTstop

- Spectral density, V( f ) V/ Hz

- Common-mode voltage, which is 0.75 V in this bookVCM

VDD - positive power supply voltage which is 1.5 V in this chapter

- Discrete Fourier Transform of V implemented using an FFTVFFT(n)

VOUTD - Difference between an analog input and a digitized output, see Fig. 30.45.


VOUTdB - Output signal in decibels

VINdB - Input signal in decibels

- Output voltage of a S/HVOUTSH

- Quantization Error Spectral Density, VQe( f ) V/ Hz

- Time domain input voltagevin(t)

- Input signal after bufferingVinbuf

- Input signal after samplingVins

- See LSBVLSB

Vout - Output voltage

- Peak sinewave amplitudeVp

- RMS Quantization Noise VoltageVQe,RMS

- Positive reference used in an ADC or DAC, which is 1.5 V in this chapterVREF+

- Negative reference used in an ADC or DAC which is ground in this chapterVREF−

VSS - negative power supply voltage which is 0 V in this chapter

= z ej2π⋅f⋅Ts = ej2π f

fs

QUESTIONS

30.1 Qualitatively, using figures, show how impulse sampling a sinewave can result inan alias of the sampled sinewave at a different frequency.

30.2 What does linear phase indicate?

30.3 What does multiplying a signal by indicate? How does the magnitude ofej⋅2πf⋅(−td)

the resulting signal change? How does the phase change?

30.4 Show, in the time-domain, the input, output of the transmission line, and output ofthe comb filter in Fig. 30.11 if the input signal is a sinewave with a peak amplitudeof 1 V and a frequency of 100 MHz. Show the two 500 Ω resistors average theinput signal and the output signal of the delay line (transmission line).

30.5 Regenerate Fig. 30.19 if the switches are closed for 5 ns instead of 100 ps.

30.6 What sets the minimum resolution of an FFT in a SPICE spectral analysis.

30.7 Explain why the sinewave in Fig. 30.19 is "double sampled".

30.8 Explain why z is used in signal processing. What does multiplying a signal by z−1 doto the signal.

30.9 Sketch the implementation of a circuit that will multiply a digital signal by z−1.


30.10 Sketch the time-domain representation of the five signals shown in Fig. 30.29 ondifferent plots. Regenerate Fig. 30.29 if the input signal is a 1 V peak sinewave at5 MHz and zero offset. Explain the resulting plot.

30.11 Sketch the input and output spectrum for the following block diagram. Assume theDC component of the input is 0.75 V while the AC component is a sinewave at 4MHz with a peak amplitude of 1 V. Assume the clock frequency is 100 MHz.

30.12 Using the models developed in the chapter design a SPICE model for the S/H ofFig. 30.31. Use the model to regenerate Fig. 30.29.

30.13 If VREF+ = 1.5 V and VREF− = 0 regenerate Fig. 30.33 using SPICE. (Design a 3-bitideal DAC model in SPICE.) The y-axis will be voltages in decimal form.

30.14 If, again, VREF+ = 1.5 V and VREF− = 0 sketch Fig. 30.33 for a one-bit DAC. Notethat the digital input code will either be a 0 or a 1 and the analog voltage out of theDAC will be either 0 or 1.5 V. Using Eq. (30.23) what is the voltage value of 1LSB? How does this compare to the value of 1 LSB we get from the sketch? IsEq. (30.23) valid for a 1-bit DAC? Why? The 1-bit DAC will be a ubiquitouscomponent in our noise-shaping modulators in Ch. 32 (see Fig. 32.28).

30.15 Using SPICE implement an ideal 4-bit DAC and regenerate Fig. 30.36.

30.16 Why do the transfer curves of Fig. 30.37 show a shift of 1/2 LSB to the left? Howdo we implement this shift in SPICE?

30.17 Repeat question 30.16 for an ADC.

30.18 Using the models developed in questions 30.15 and 30.17 with a clock frequencyof 100 MHz apply an input sinewave having an amplitude of 750 mV peakcentered around 750 mV DC and a frequency of 5 MHz to the input of the 4-bitADC. If the ideal 4-bit DAC is connected to the digital outputs of the ADC alsoshow the DAC's analog output.

30.19 Using SPICE generate the spectrums of the input and output of the signals inquestion 30.18.


Figure 30.64 Figure used in problem 30.11.


In OutSample andhold (S/H)

clock


30.20 Does an ideal S/H introduce amplitude quantization noise into an input waveform?Why or why not?

30.21 Why are the amplitudes of the mirror images decreasing with an increase infrequency in Fig. 30.44b?

30.22 Show the details of the integration in Eq. (30.30).

30.23 How are voltage spectral density, power spectral density (PSD), average power,and RMS voltage related for a random signal? What are the units of each? Provideanswers for both continuous signals and signals that are only defined at discretefrequencies.

30.24 How would we convert voltage spectral density of Fig. 30.48 into a power spectraldensity plot? What term in Eq. 30.33 is the PSD? How would we rewrite Eq.(30.33) to give the average power of the quantization error?

30.25 Repeat Ex. 30.10 if we want to determine the quantization noise power. Show thesimulation results and the commands used to determine this power.

30.26 Derive Eq. (30.43).

30.27 What term is the PSD in Eqs. (30.42) and (30.44)? What are its units?

30.28 Verify, with simulations, Ex. 30.16.

30.29 Verify, using simple circuit analysis, that resistors can be used to implementaveraging as seen in Fig. 30.59 and Eq. 30.45.

30.30 How does averaging K samples of a random voltage variable reduce its RMSvalue? How does the power contained in the same variable get reduced byaveraging?


Data Converter SNR

In the last chapter we developed the idea of treating an analog-to-digital converter (ADC)as a noisy circuit block where the output of the ADC is the sum of quantization noise andthe input signal. Logically, the next step in our development of concepts is to characterizea system using ADCs and DACs in terms of the signal-to-noise ratio (SNR). The idealSNR for a data converter was developed back in Ch. 28 and is repeated here forconvenience.

If we apply a sinewave with an amplitude of (and thus an RMS value ofVp

to an ADC input then, knowing the RMS quantization noise added to a busyVp/ 2 )ADC input signal is (see Eqs. [30.30] and [30.32]), the resulting SNR for theVLSB/ 12ADC is given by

(31.1)SNRideal = 20 ⋅ logVp/ 2

VLSB/ 12

If we remember that

(31.2)VLSB = 1 LSB = VREF+ − VREF−

2N

and we assume that the largest possible amplitude sinewave is the ADC input (tomaximize the SNR), that is,

(31.3)2Vp = VREF+ − VREF−

then Eq. (31.1) can be re-written as

(in dB) (31.4)SNRideal = 20 ⋅ log2N 12

2 2= 6.02N + 1.76

Chapter

31

Our goal in this chapter is to discuss how to determine the actual SNR of a dataconversion system and to present topologies for improving data conversion system SNR(e.g., averaging, noise shaping, etc.).

31.1 Data Converter SNR: An Overview

In this section we describe data converter performance, defining terms such as effectivenumber of bits, dynamic range, signal-to-noise plus distortion ratio (SNRD), andspurious-free-dynamic range (SFDR). This discussion will be useful in understandingwhere problems or limitations with data converter performance originate.

31.1.1 Effective Number of Bits

Equation (31.4) relates the number of bits used in a data converter to the ideal SNR whenthe input signal is a sinewave that ranges from to . In reality the measuredVREF+ VREF−SNR, in most cases, will be different from the ideal value calculated using this equation.When an SNR is measured, we relate it to the effective number of bits using

(31.5)Neff = SNRmeas − 1.766.02

where the measured SNR ( ) is specified in dB.SNRmeas

Example 31.1Determine the effective number of bits for an ADC with , ,VREF+ = 1.5 VREF− = 0and a measured of 2 mV.VQe,RMS

If we assume that the input peak amplitude, Vp , is or 0.75 V,0.5 ⋅ (VREF+ − VREF−)then the measured SNR is given by

SNRmeas = 0.75/ 22 mV

= 265 = 48.5 dB

The effective number of bits, Neff , is (from Eq. (31.5]) 7.76 bits.

Normally, the measured SNR ( ) is determined from the RMS quantizationSNRmeas

noise, which is determined using Eq. (30.33) with measured data. The amplitude andfrequency of the input sinewave can be selected to maximize the SNR.

Example 31.2Using the ideal 8-bit ADC and DAC shown in Fig. 31.1, which were developed inthe last chapter, and a sampling frequency of 100 MHz ( ) show, using= f s

SPICE, that applying a full-scale sinewave at 24 MHz to this configuration willcause the resulting SNR to approach the ideal value given by Eq. 31.4.

Let's begin by calculating . From Eq. (31.4), SNRideal is roughly 50 dB, asSNRideal

the data converters have 8-bit resolution.

The time-domain input and output of the circuit shown in Fig. 31.1, andcorresponding DAC output spectrum, are shown in Fig. 31.2. The input to the


ADC in Fig. 31.1 is a 24 MHz sinewave with a peak amplitude of 0.75 V centeredon a DC voltage of 0.75 V (the peak-to-peak voltage of the input waveform is 1.5V). The VQE,RMS measured with SPICE, remembering to zero out the wantedsignals at DC and 24 MHz and the images at 76 MHz, 124 MHz, and 176 MHzbefore calculating the noise (see Ex. 30.15), is 1.682 mV. The simulated SNR is

or 315 which is the ideal value of 50 dB calculated at the(0.75/ 2 )/1.682 mVbeginning of the example.

It's important to understand that poor selection of the input frequency can result inan SNR that is different from the ideal value calculated using Eq. (31.4). If, for example,we select an input sinewave frequency to measure SNR that is comparable to the Nyquistfrequency, the resulting DAC output will contain unwanted tones, and the desired tone

Chapter 31 Data Converter SNR 65

Ideal8-bit ADC

8Ideal

8-bit DAC

VDD = 1.5 VDD = 1.5

Figure 31.1 Test setup used in Ex. 31.2 to show deviation from ideal SNR.

Analog Digital Analog

VIN (24 MHz) VOUT

fs = 100 MHz

Figure 31.2 Example 31.2 (a) time-domain input and output and (b) Spectrum of DAC output.

(a) (b)

ADCInput

DACoutput

Sign

al p

lus

Noi

se

will undergo amplitude attenuation (−3.9 dB at fn see Fig. 30.29). Consider the followingexample.

Example 31.3Repeat Ex. 31.2 if the input sinewave frequency is increased to 45 MHz.

The results of increasing the ADC input sinewave frequency in Fig. 31.1 to 45MHz are shown in Fig. 31.3. Note how the DAC output contains tones at 5 MHz,10 MHz, 15 MHz, etc., in addition to the desired tone at 45 MHz. The simulatedVQe,RMS is 2.26 mV. The input amplitude of the 45 MHz sinewave is 0.75 V (−2.5dB). The simulated peak output amplitude at 45 MHz is 0.53 V (−5.5 dB). Thesimulated SNR can be calculated

SNR = 20 log0.53/ 22.26 mV

= 44.4 dB

or 5.6 dB below the ideal value of 50 dB calculated using Eq. (31.4) for a dataconverter with a resolution of 8 bits.

Signal-to-Noise Plus Distortion Ratio (SNDR)

In a practical data converter the output spectrum contains not only quantization noise butdistortion resulting from nonlinearities and mismatch in the data converter circuitry. When


Figure 31.3 (a) DAC output with 45 MHz input and (b) the DAC output spectrum.

(a) (b)

Sign

al p

lus

Noi

se

we calculate the RMS quantization noise voltage using Eq. (30.33) and nonidealcomponents, we are actually calculating the noise plus the distortion in the spectrum. Upto this point we have only used ideal components, so that distortion in the outputspectrums was absent. We can re-write Eq. 30.33 to indicate that when it is used with ameasured spectrum, both noise and distortion are included in the result as

where (31.6)VQe+D,RMS = 12

Σk=0

M−1

VFFT2 (k ⋅ fRES) M = #FFTpoints

The signal-to-noise plus distortion ratio is then given by

(31.7)SNDR = 20 logVp/ 2

VQe+D,RMS

The effective number of bits, from Eq. (31.5), can then be calculated using

(31.8)Neff = SNDR − 1.766.02

Example 31.4Suppose that the test setup shown in Fig. 31.1 is used with an input sinewavehaving a frequency of 8 MHz, a peak amplitude of 0.75 V, and centered around0.75 V (so that, once again, the sinewave swings from 0 V to 1.5 V.) UsingSPICE simulation, determine the SNDR if there is a gain error in the ideal ADC inFig. 31.1 (it's no longer ideal) so that each stage in the pipeline algorithm used toimplement the ideal SPICE ADC has a gain of 2.1 instead of the ideal 2.0.

The resulting DAC output spectrum is shown in Fig. 31.4. The RMS noise plusdistortion voltage, , is calculated as 17.4 mV, using SPICE andVQe+D,RMS

remembering to zero out the desired terms at DC and 8 MHz as well as theundesired images at 92 MHz, 108 MHz, and 192 MHz. The SNDR is then

SNDR = 20 log0.75/ 217.4mV

= 29.7 dB

while the effective number of bits is 4.6. In other words, a 5% gain error in theADC amplifiers results in an effective resolution of almost half the ideal, 8-bit,value.

Measuring SNDR requires a spectrum analyzer, when looking at the output of aDAC, or loading digital data (most often in decimal form) into a program that can performan FFT (such as WinSPICE [utilizing the load command] or Matlab) when looking at theoutput of an ADC. Trying to measure SNDR using a time-domain instrument, such as anoscilloscope, is usually a waste of time because the dynamic range of the instrument isusually comparable to the dynamic range of the data converter under test. Spectrumanalyzers utilize narrow band filtering on their input to reduce the inherent noise measuredin a circuit and can have dynamic ranges in excess of 120 dB over a very wide frequencyspectrum. Also note that the SNDR is sometimes abbreviated as SINAD (SIgnal-to-NoiseAnd Distortion.)


Spurious-Free Dynamic Range (SFDR)

Another specification of interest is the data converter's spurious-free dynamic range. Thisterm relates the peak signal in the output spectrum (the input sinewave or carrier) to thelargest spike in the output spectrum up to the Nyquist frequency. This can be writtenusing

(31.9)SFDR(dBc) = input carrier(dB) − unwanted tone (dB)

For the spectrum shown in Fig. 31.4 the input sinewave (carrier) has an amplitude of 0.75V (−2.5 dB), while the largest unwanted tone has an amplitude of −39.25 dB. The SFDRof this data converter is then 36.75 dBc.

Dynamic Range

The dynamic range of a data converter can be specified in several ways. We defineddynamic range back in Ch. 28 as the ratio of the largest output signal change (e.g.,

) over the smallest output signal change ( ). Remembering 1[VREF+ − 1 LSB] −VREF− 1LSBLSB = the dynamic range, DR, can be written as(VREF+ − VREF−)/2N

(31.10)DR = 20 logVREF+ − (VREF+ − VREF−)/2N − VREF−

(VREF+ − VREF−)/2N= 20 log 2N = 6.02N

If a 1,000 to 1 dynamic range (60 dB) is required, then a data converter with at least 10bits is needed.


Figure 31.4 Output spectrum with ADC gain error (see Ex. 31.3).

Spurious-Free Dynamic Range

Sign

al p

lus

Noi

se a

nd D

isto

rtio

n

Another way to specify DR is as the ratio of the RMS full-scale input sinusoidamplitude, Vp , to the input sinusoid amplitude (RMS) that results in an SNDR of 0 dB/ 2(the RMS amplitude of the input signal is equal to the RMS quantization noise plusdistortion, , when the SNDR is 0 dB). This is nothing more than saying that theVQE+N,RMS

SNDR can be used to specify DR.

Example 31.5Determine the DR for the non-ideal ADC described in Ex. 31.3 using Eq. (31.10).Compare the result to the SNDR calculated in Ex. 31.4.

Using Eq. (31.10) the DR is 48.16 dB (the ideal value). The SNDR calculated inEx. 31.4 was 29.7 dB. Clearly, the SNDR is a better indication of DR than is thevalue obtained using Eq. (31.10).

Specifying SNR and SNDR

The SNR and the SNDR are usually specified as a function of input sinewave amplitude ata fixed frequency, Fig. 31.5. The x-axis in Fig. 31.5 is normalized so that an inputsinewave with a peak-to-peak amplitude of corresponds to 0 dB. We mightVREF+ − VREF−be wondering how we differentiate between SNR and SNDR as both, up to this point,have been calculated in the same way (Eqs. [31.6] and [30.33]). We continue to calculateSNDR using a data converter output spectrum, remembering to zero out the desired tonesand images, and Eq. (31.6) as was done in Ex. 31.4. When we calculate the SNR, wefollow the same procedure except that now we also zero out any spikes or spurs (spuriousresponses) in the spectrum that are "sticking up" above the noise floor in the spectrum.These spikes come from imperfections in the data converter and result in distortion in theoutput waveform. Note in Fig. 31.5 how the SNR and the SNDR coincide until the inputsignal amplitude gets reasonably large (so the distortion tones increase in amplitude abovethe quantization noise).


SNRSNDR

Sign

al-t

o-N

oise

plu

s D

isto

rtio

n, d

B

Normalized input signal amplitude (dB)

00

20

40

60

-20-40-60-80

Figure 31.5 Specfying SNR and SNDR for a data converter.

VREF+ − VREF−

31.1.2 Clock Jitter

We might assume that using the ideal data converters developed in the last chapter in asystem with "real world" input and clock signals would give us a resolution (number ofbits) set by the resolution of the ideal data converters used. However, if the clock signalused isn't ideal, the resolution will be less than ideal. We discussed this problem, aperturejitter, back in Ch. 28. Here we want to relate the amount of clock jitter to the dataconverters SNR and thus the effective number of bits. Clock jitter is the variation in theperiod of the clock signal around the ideal value

Figure 31.6 shows the basic problem. In this figure we have assumed the inputsinewave frequency is running at the Nyquist frequency fn (= fs /2 ) so that the samplingpoint (when the sinewave crosses zero in this figure) is seeing the fastest transition in theinput signal. We assume the peak amount of jitter in the clock signal is . For example,∆Ts

if the sampling clock frequency is 100 MHz ( ) and the peak-to-peak clock jitterTs = 10 nsis 50 ps ( ), then the specification of the sampling clock stability is 5,000 ppm (where= ∆Ts

parts per million [ppm] = 10−6 and ).∆Ts = (stability, ppm) ⋅ (1/f s)

The slew-rate of the signal in Fig. 31.6, at the sampling point, (when the clocksignal transitions high) is given by

(31.11)ddt

(Vpsin πf st) = πf sVp

=1

cosπf st = πf sVp

We can relate the uncertainty in the sampling instant, , to the uncertainty in the∆Ts

sampled voltage, , using∆Vs


Apertureuncertainty/jitter

Error in sampling,

Data converter input signal and clock jitter.Figure 31.6

tIdeal

sampling point

Vpsin2πfnt = Vpsin πf st

∆Ts = peak-to-peak jitter

Ts

∆Vs

(31.12)∆Vs

∆Ts= πfsVp, or ∆Vs = ∆Ts ⋅ πf sVp

If we require the uncertainty in the sampled voltage, , to be at most 0.5 LSB = (VREF+∆Vs

and we remember , then our maximum allowable,−VREF−)/2N+1 Vp = (VREF+ − VREF−)/2peak-to-peak clock jitter can be determined for a particular data converter using

(31.13)∆Ts ≤ 12N

⋅ 1πf s

or in terms of the sampling clock stability

(31.14)Stability, ppm = ∆Ts ⋅ f s = ∆Ts

Ts= 1

π ⋅2N

Table 31.1 relates the stability requirements placed on a sampling clock for a dataconverter resolution, N, if less than 0.5 LSBs aperture error or sampling voltageuncertainty is required of the data converter.

Resolution, N Stability, ppm ∆Ts(max), ps ∆Ts(max), ns

If fs = 100 MHz If fs = 44.1 kHz

6 5,000 50 113.4

8 1,250 12.5 28.3

10 312.5 3.125 7.1

12 78.1 0.78 1.77

14 19.5 0.195 0.443

16 4.9 0.05 0.111

Table 31.1 Maximum jitter, , for 0.5 LSB sampling uncertainty.∆Ts

Example 31.6Suppose a phase-locked loop (PLL) is used to generate a clock signal for a dataconverter. If the resolution of the data converter is 10 bits and the frequency of thesampling clock coming from the PLL is 900 MHz, then specify the maximum jitterallowed in the output of the PLL. Assume that the maximum sampling errorallowed is 0.5 LSB and that the data converter is sampling a sinewave with afrequency of 100 MHz.

Because the sinewave being sampled has a frequency below the Nyquist value, Eq.(31.13) cannot be used directly. Instead, after reviewing the derivation of thisequation, we can rewrite it in terms of any input signal frequency, fin , as

(31.15)∆Ts ≤ 12N

⋅ 12π ⋅f in


noting that when fin = fn = fs /2, Eq. (31.15) reduces to Eq. (31.13). Using Eq.(31.13) with the numbers in this problem results in a peak-to-peak jitter of 1.56 ps!The reader familiar with PLL design will recognize that this is a very challengingrequirement when designing a PLL (that is, to design a PLL with an outputfrequency of 900 MHz and an output jitter of 1.56 ps.)

We're now in a position to answer how, given the peak-to-peak clock jitter ,∆Ts

the SNR of a data converter is degraded from the ideal value (given in Eq. [31.4]) whenthe input sampling clock isn't ideal. Rewriting Eq. (31.15) and assuming

(31.16)∆Ts ≥ 12N

⋅ 12π ⋅f in

(a resolution loss 0.5 LSB), we get≥

(31.17)∆Ts = 12N−NLoss

⋅ 12π ⋅f in

where fin is, once again, the frequency of the input sinewave, and NLoss is the number of bitslost due to the excess jitter. Assuming Eq. (31.16) is valid, then when NLoss is zero due tothe loss in resolution is 0.5 LSB and Eq. (31.17) reduces to the equality condition in Eqs.(31.15) or (31.16). The ideal data converter's SNR, assuming the only non-ideal factor inthe system is clock jitter, can be written as

(31.18)SNR = 6.02(

effective bits, Neff

N − NLoss − 0.5) + 1.76 (in dB)

Example 31.7For an ideal 8-bit ADC clocked at 100 MHz, determine the SNR of the dataconverter with 100 ps of peak-to-peak jitter in the input sampling clock, ,∆Ts

assuming the ADCs input is a full scale sinewave at 25 MHz.

We can write the number of bits loss by solving Eq. (31.17) as a function ofpeak-to-peak jitter as

assuming (31.19)NLoss = N + 3.33 ⋅ log (2π ⋅f in ⋅ ∆Ts) ∆Ts ≥ 12N

⋅ 12π ⋅f in

or

NLoss = 8 + 3.33 ⋅ log(2π ⋅25MEG ⋅ 100ps) = 2 bits

The effective number of bits, Neff , is then 5.5 and the SNR is 34.87 dB.

Using Oversampling to Reduce Sampling Clock Jitter Stability Requirements

Suppose we limit the maximum input frequency coming into an ADC to fin , such that thesampling frequency is related to the maximum ADC input frequency by

or (31.20)f s

2= K ⋅ f in = fn f in =

f s

2K


In other words, we are getting at least 2K samples for every cycle of the input sinewave. Ifwe were sampling at twice the Nyquist frequency ( fs ), where K = 1, then we would gettwo samples for every cycle of the input signal. Notice that Eq. (31.15) gives themaximum jitter specification for a given input frequency and data converter resolution, butit doesn't specify the sampling frequency, fs , or the sampling frequency period, Ts .

For a given maximum jitter, , we can reduce the requirements placed on the∆Ts

stability of the oscillator by increasing the sampling frequency. This can be written as

(31.21)Stability(new), ppm = [stability(old), ppm] ⋅ K

If we were sampling at 1 MHz and the stability required was 10 ppm, then the jitter in thesampling clock would be at most 10 ps, peak-to-peak. Increasing the sampling rate to 100MHz, with 10 ps jitter would require an oscillator stability of 1,000 ppm. If we were toincrease the sampling clock frequency to 1 GHz, then the stability of the clock would be atleast 10,000 ppm (the period of the sampling signal is 1 ns and the jitter is 10 ps or 1%[10,000 ppm] of the sampling period.)

Note that the oversampling factor symbol, K, is the same symbol that indicates thenumber of samples averaged on the output of a data converter to reduce RMSquantization noise voltage (see Sec. 30.3.2). The choice of variable was made for a reason(which will be discussed further in the next section.)

Example 31.8In Table 31.1 we saw that the 16-bit data converter clocked at 44.1 kHz couldhave at most 111 ps peak-to-peak jitter to limit the sampling uncertainty to 0.5LSB. We saw that the stability required of the oscillator under these circumstanceswas 5 ppm at 44.1 kHz. What would happen to the stability requirements of theoscillator generating the sampling clock if we increased the sampling clockfrequency to ?128 ⋅ 44.1 kHz = 5.645 MHz

We know that the input bandwidth, prior to increasing the sampling frequency, islimited to 44.1 kHz/2 or 22.05 kHz (= B, the bandwidth of the input signal). Wethen assume the maximum input frequency, fin , remains at or below 22.05 kHzeven after we increase the sampling frequency. We can define the oversamplingfactor, in this example, as

K =f s/2f in

= 2.822 × 106

22.05 × 103= 128

The jitter requirement remains 111 ps whether we use a sampling frequency of44.1 kHz or 5.645 Mhz. However, now that the clock frequency has increased to5.645 MHz, the stability required of the oscillator has gone from approximately 5ppm to 640 ppm.

It's important to note that the oversampling ratio, K, is given by

for (31.22)K =f s/2B

=fn

Bfin ≤ B


If we desire less than 0.5 LSBs aperture error, and we are using oversampling, then wecan use Eqs. (31.13) and (31.22) to write

(31.23)∆Ts ≤ 12N

⋅ Kπf s

= 12N

⋅ 12πB

where, once again, B is the bandwidth of the input signal and K is the oversampling ratio.As shown by this equation and in Eq. (31.21), using oversampling reduces therequirements placed on the stability of the sampling clock.

A Practical Note

We need to point out that the effects of clock jitter are possible even if the clock isperfectly stable because of the clock's finite transition times (rise- and falltimes). If therisetime of the clock signal in Fig. 31.6 is finite, say 50 ps, then the same derivations anddiscussions concerning jitter in the previous section can be applied to determine how theSNR of the data converter is affected. We would assume the aperture window is afunction of the transition times of the sampling clock signal. The slower the transitiontimes, the larger the sampling uncertainty. In any practical data converter the SNR, andthus the effective number of bits, will be reduced because of the clock jitter and finitetransition times as the input signal frequency increases.

Modeling Clock Jitter with SPICE

It's useful in many situations to determine how clock jitter will affect a data converter'sperformance. Consider the block diagram shown in Fig. 31.7. This is our basicconfiguration, used previously, to show data converter operation. Now, however, we havechanged the sampling clock from an ideal pulse source to a source that contains jitter. Thequestions we want to answer in this section is "How do we use SPICE to model a jitteryclock source, and how does the jitter affect the SNDR of the data converter?"

To begin let's consider the Single Frequency Frequency Modulation (SFFM)source available in SPICE. This source generates a Frequency Modulated (FM) sinewaveusing the following syntax

SFFM(VO VA FC MDI FS)

where the parameters describe the following function

(31.24)VSFFM(t) = VO + VA sin ([2π ⋅FC ⋅ t] + [MDI ⋅ sin (2π ⋅FS ⋅ t)])


Ideal8-bit DAC

VDD = 1.5

Figure 31.7 Simulating ideal data converters using a sampling clock with jitter.

Ideal8-bit ADC

8

VDD = 1.5

Analog

Digital

Analog

Jittering clock

VOUTVIN (8MHz)f s = 100 MHz

The modulation index, MDI, will set the peak-to-peak jitter time in the waveform whilethe signal frequency, FS, describes the rate at which this jitter varies. The carrierfrequency, FC, will set the clock frequency (FC = 100 MHz in Fig. 31.7). The term VO isavailable to add a DC offset to the signal (which we will assume is zero in our discussion),and the value VA sets the amplitude of the frequency modulated sinewave. The questionwe need to answer now is, "How do we convert the FM sinewave generated using Eq.(31.24) into a squarewave suitable for driving our ADC?"

Figure 31.8 shows that a switch and the SFFM source can be used to generate thesampling clock with jitter. When the FM source transitions above zero, the top switchcloses and the clock output goes high. When the source transitions below zero, the bottomswitch closes and the clock output goes low.

The average period of the sampling clock generated by the SFFM source is given

by

(31.25)Ts = 1FC

or f s = FC

The peak phase excursion of the clock signal is set by MDI. The peak phase excursion canbe related to the sampling frequency using

(31.26)MDI = 2π ⋅ ∆Ts

Ts

or the peak-to-peak jitter, ∆Ts, is given by

(31.27)∆Ts = 12π

⋅ MDIFC

= MDI2πf s

Example 31.9Using SPICE, generate the output spectrum of an oscillator assuming the oscillatorfrequency is 100 MHz and the peak-to-peak jitter is 100 ps. Assume FS = 1 MEG.

We can begin this example by noting FC = 100 MHz and the modulation index is. The SPICE netlist and the resulting spectrum are2π ⋅100ps ⋅ 100MEG = 0.0628

shown below and in Fig. 31.9 respectively.


Figure 31.8 Generating a clock with jitter using a switch and an SFFM source.

VDD = 1.5V

Closed when V > 0

Closed when V < 0Clock out

SFFMsource

with jitterV

* Figure 31.9 CMOS2: Mixed-Signal Circuit Design *.tran .2n 10000n 0 .2n UIC*WinSPICE command scripts*#destroy all*#run*#plot clock xlimit 0 100n*#plot vclock xlimit 0 100n*#linearize clock*#spec 90MEG 110MEG 200k clock*#plot db(clock)VDD VDD 0 DC 1.5

Vclock Vclock 0 DC 0 SFFM 0 1 100MEG 0.0628 1MEGRclock Vclock 0 100MEG

SH VDD clock Vclock 0 SwitmodSL 0 clock 0 Vclock SwitmodRload clock 0 100MEG

.model switmod SW

.endNote that the resolution of the FFT was 200 kHz (set by Eq. (30.35) and that thesignal frequency, FS, was 1 MEG (which sets the spacing between the tones in Fig.31.9.). The period of the 100 MHz clock, in this example, varies sinusoidal from9.95 ns to 10.05 ns over a time frame of 1 µs (1/FS.) While this spectrum isinteresting, it isn't representative of an actual oscillator where the noise is random.


Figure 31.9 Spectrum of a sampling clock signal with noise.

Peak

Sig

nal p

lus

Noi

se V

olta

ge, d

B

While our simple model will never be capable of generating truly random noise, wecan, for a given simulation time, make the simulated spectrum of the oscillatorapproach something that looks more realistic (and thus more random over a givensimulation time). Toward this goal, let's attempt to make the oscillator spectrummore continuous. We can do this by requiring

(31.28)FS = 1Simulation time, Ts

We apply this result in the following example.

Example 31.10Repeat Ex. 31.9 if the FS is set using Eq. (31.28).

Using Eq. (31.28) and a simulation time of 10,000 ns, we get an FS = 100 kHz.Resimulating, using this value of FS, gives the results shown in Fig. 31.10 Theamplitude of the square wave varied from 0 to 1.5 V (varied from 0 to A.)Remembering that the harmonics of the clock (a square wave) have a value of A/2at DC and a value of , where n = 1, 3, 5, ... at the other harmonics, we can2A/nπcalculate the peak amplitude of the fundamental tone in Fig. 31.10 (or Fig. 31.9) as

or −0.4 dB. (2 ⋅ 1.5)/π =0.955V

Note that a measured spectrum with anomalous spikes would generally indicatethat the noise (the spikes) is not random and could be the result of coupling from anadjacent circuit. The coupling could be through the substrate or power connections or it


Figure 31.10 Oscillator spectrum using Eq. (31.28) to set phase variation time.

Peak

Sig

nal p

lus

Noi

se V

olta

ge, d

B

could be capacitive. If the oscillator jitter is due only to MOSFET noise, in general, nounwanted spikes will exist in the oscillator's output spectrum.

In the frequency domain the jitter (which is called phase noise) is usually specifiedat some offset to the fundamental carrier and taken with reference to the carrier. Forexample, at a 1 MHz offset in Fig. 31.10 (at 99 MHz or 101 MHz), the spectrum has apeak amplitude of approximately −50 dB. The phase noise at a 1 MHz offset would thenbe given with reference to the carrier as −50 dB − (−0.4 dB) (the carrier amplitude) =−49.6 dBc. However, when talking about phase noise, we are generally referring to asingle-tone sinusoid (not a square wave with odd harmonics).

Using Our SPICE Jitter Model

The model we've just developed is difficult to use in a practical simulation because of thefinite step time used by SPICE. For example, if we are trying to model the effects of 100ps of clock jitter on a data converter's performance then our step size in the simulationshould be much smaller than 100 ps. This requirement can lead to very long simulationtimes or, if the step size is comparable to the simulated jitter, questionable results (see theexample below). Nevertheless, the model is useful in many situations.

Example 31.11Suppose a 100 MHz sampling clock has 500 ps of jitter. Determine how the SNRof an ideal data converter will be affected when clocked with this signal. Assumethe topology and input signal of Fig. 31.1 are used.

We begin by using Eq. (31.19) to calculate the number of bits lost

NLoss = 8 + 3.33 log(2π ⋅25MEG ⋅ 500p) = 4.3 bits

The SNR of the 8-bit system is determined using Eq. (31.18)

SNR = 6.02(8 − 4.3 − 0.5) + 1.76 = 21 dB

The next factor that we need to determine is the modulation index, MDI, whichsimulates 500 ps of jitter. Using Eq. (31.27) we get

MDI = 2π ⋅100MEG ⋅ 500p = 0.314

To keep the simulation time relatively short we'll simulate for 2,000 ns with a stepsize of 100 ps. The resolution of the FFT used will be 1 MHz (set by Eq. [30.35]).The rate at which the jitter varies is set by Eq. (31.27) and is 500 kHz. The DACoutput spectrum is shown in Fig. 31.11. The simulated is 93 mV. TheVQe+N,RMS

SNR is then given by (practically worthless).20 ⋅ log 0.75/ 2 /93mV

= 15 dB

We see the simulated SNR is fully 6 dB below the calculated SNR. We mayspeculate that this is due to both the jitter we introduced into the clock purposelyand the jitter introduced by the varying step size in the SPICE simulation. Whenwe used a pulse source to clock our ADC in previous simulations, the jitter wasabsent because of the exact timing of the pulse statement and the fact that the rise-and fall-times were set by the simulation step size.


31.1.3 A Tool: The Spectral Density

The observant reader may have noticed, in the last section, that we only discussed thepeak-to-peak jitter, , and how it affects the data converter's performance. It is very∆Ts

useful, in many situations, to also have an idea of how the spectrum or spectralcharacteristics of the data converter's output change as a function of the random samplingjitter or a random variable such as noise. In this section we discuss tools useful indescribing the spectrum of a random signal.

The Spectral Density of Deterministic Signals: An Overview

Consider the simple sinewave signal of the form

(units, V ) (31.29)Vin(t) = Vpsin 2πf int

This signal is termed "deterministic" because the signal has a well-defined shape whether itis continuous or sampled. We can find the average value of this signal, as a function oftime Rin(t), using the autocorrelation function (ACF) for continuous signals given by

(units, V 2 ) (31.30)Rin(t) =T0→∞lim 1

T0∫

−T0/2

T0/2

Vin(τ) ⋅ Vin(τ + t) ⋅ dτ

The average value of Eq. (31.29) as a function of time is then

(31.31)Rin(t) =T0→∞lim 1

T0∫

−T0/2

T0/2

[Vpsin2πf inτ] ⋅ [Vpsin 2πf in(τ + t)]dτ


Figure 31.11 DAC output spectrum for Ex. 31.11.

Peak

Sig

nal p

lus

Noi

se a

nd D

isto

rtio

n V

olta

ge, d

B

or knowing

(31.32)sinA ⋅ sinB = 12

[cos(A − B) − cos(A + B)]

we can write

(31.33)Vp2 ⋅ sin2πf inτ ⋅ sin 2πf in(t + τ) =

Vp2

2[cos 2πf int − cos 2πf in(t + 2τ)]

When we integrate this result, the term represents a sinusoid with acos [2πfin(t + 2τ)]frequency of (remembering our integration variable is τ) and a phase shift of .4πf in 2πf intOver a long period of time this term averages to zero. Therefore, we can write the averagevalue of Eq. (31.29) as a function of time (the autocorrelation function) as

(units, V 2) (31.34)Rin(t) =T0→∞lim 1

T0∫

−T0/2

T0/2Vp

2

2⋅ cos 2πf int ⋅ dτ =

Vp2

2⋅ cos 2πf int

The spectrum of the average value of a function can be found by taking the Fouriertransform of the autocorrelation function. The result is called the Power Spectral Densityfunction (PSD) and is given by

(31.35)Pin( f ) = ∫−∞

∞

Rin(t) ⋅ e−j⋅2πf⋅t ⋅ dt (units, V2/Hz or V2 ⋅ s)

The power spectral density function of Eq. (31.29) is then, with the help of Eq. (31.34),

(units, V 2/Hz ) (31.36)Pin( f ) =Vp

2

4⋅ [δ( f + f in ) + δ( f − f in )]

This is simply two impulses in the frequency spectrum located at fin with an amplitude of±. The total average power of this signal is given byVp

2/4 (V2/Hz)

(units, V 2/Ω or Watts) (31.37)PAVG = ∫−∞

∞

Pin( f ) ⋅ df = 2 ⋅ ∫0

∞

Pin( f ) ⋅ df

assuming a 1-Ω (normalized) load, which, for Eq. (31.29), is . Vp2/2 (V2)

The voltage spectral density, with units of , is simply the square root ofV/ HzEq. (31.35) (that is, the square root of the PSD [ ]). The root mean square= Pin( f )(RMS) voltage of a signal is given by

(31.38)VRMS = PAVG = 2 ∫0

∞

Pin( f ) ⋅ df = 2 ∫0

∞

(Voltage Spectral Density)2 ⋅ df

The RMS value of Eq. (31.29) is simply, as one would expect for a sinewave, .Vp/ 2Note the similarity between Eq. (31.38) and Eq. (31.6). The factor of root two in Eq.(31.6) is used because VFFT ( f ), the output of WinSPICE, is the peak voltage at a given(one-sided spectrum) frequency (and so dividing VFFT [ f ] by results in RMS voltages2as a function of frequency).


Example 31.12Determine the ACF, PSD, average power, and RMS value of a signal V(t) made upof three sine waves with peak amplitudes of V1 , V2 , and V3 with frequencies of f1 , f2 , and f3 .

Using Eqs. (31.30) and (31.34), the ACF is

R(t) = V12

2cos 2πf1t + V2

2

2cos 2πf2t + V3

2

2cos 2πf3t (units, V2)

The PSD (positive frequencies) is determined using Eqs. (31.35) and (31.36)

P( f ) = V12

4⋅ δ( f − f1) + V2

2

4⋅ δ( f − f2) + V3

2

4⋅ δ( f − f3) (units, V2/Hz)

The average power, using Eq. (31.37), is

(units, Watts)PAVG = V12 + V2

2 + V32

2

Finally, the RMS value of the signal is given by

VRMS = V12 + V2

2 + V32

2(units, V)

Note that if we added phase shifts to our signals the results would be the same; thephase shift doesn't change the signal's average value, so we get the same resultswhether sines or cosines are used in our original spectrum.

Next, suppose that the sinewave specified by Eq. (31.29) is sampled at a rate of Ts

(31.39)Vin(nTs) = Vpsin (2πf in ⋅ nTs)

The ACF for a sampled signal can be written as

(31.40)Rin(nTs) =N→∞lim 1

(2N + 1) Σk=−N

N

Vin(kTs) ⋅ Vin(kTs + nTs)

which results in

(31.41)Rin(nTs) =Vp

2

2cos 2πf in ⋅ nTs (units, V2)

The PSD is the Fourier transform of this equation (see Eq. [30.2] in the last chapter),

(31.42)Pin( f ) =Vp

2

4TsΣ

k=−∞

∞[δ( f − f in + kfs) + δ( f + f in + kfs)]

The RMS value of the sampled sinewave, Eq. (31.39), assuming we have passed the signalthrough an ideal reconstruction filter (RCF) with a bandwidth of fs /2, is simply, onceagain, . The PSD of the signal, after passing through the RCF, has an amplitude ofVp/ 2

at frequencies of fin.Vp2/4 ±


The Spectral Density of Random Signals: An Overview

Let's use our jitter discussion of the last section to illustrate how to look at the spectrumof a random signal. We'll do this in two parts: 1) we'll begin by assuming the jitter is arandom variable that falls between two limits and has equal probability of lying anywherein the region (just as was assumed for the quantization error probability density functionwhen calculating the RMS quantization noise voltage in the last chapter) and 2) thenassume the jitter has a Gaussian distribution around some average value (the morepractical and realistic situation) and determine how the output of the ADC is affected.

Consider the representations of clock jitter shown in Fig. 31.12. Trace 1 in thisfigure shows the ideal position of the rising edge of a clock signal. This point isrepresented on the probability density function (PDF), , at time zero. On the nextρ(t)rising edge of the clock, trace 2, the edge is a little too early and is represented on thePDF as shown. We are assuming, probably incorrectly for most practical situations, thatthe rising edge of the clock is falling within the peak-to-peak boundaries with the equalprobability of being in the correct position (as shown in trace 1) or at the edge of aboundary (as shown in trace 4). We also know that the area under the PDF curve in Fig.31.12 must equal unity, and the average value (also known as the mean or the expectedvalue and denoted by < y > or ) of a PDF is given byy

(31.43)Average value, y, = ∫−∞

∞

t ⋅ ρ(t) ⋅ dt

Example 31.13Determine the average value of the jitter with PDF shown in Fig. 31.12.


Figure 31.12 Clock jitter assuming the edge falls with the same probability anywhere within the peak-to-peak limits.

Ideal clock edge position

Edge too early

Edge too late

Edge at the boundary

Edge close to boundary

peak-to-peak jitter,

1

2

3

4

5 0

12

3 45

Probability density function, PDF

time

Trace

∆Ts

−∆Ts

2∆Ts

2

1∆Ts

ρ(t)

We can use Eq. (31.43) to determine the average value of any PDF. Applying thisequation to the PDF shown in Fig. 31.12 results in

Average value, y, = ∫−∆Ts2

∆Ts/2

t ⋅ 1∆Ts

⋅ dt = 0

This somewhat obvious result means that the average position of the clock risingedge is the ideal position indicated by trace 1 in Fig. 31.12. Any PDF that issymmetrical about some center point will have an average equal to the centerpoint.

The variance of the PDF is defined as the average of the square of the signal'sdeparture from its average value. For a random signal this can be written as

(31.44)σ2 = (y − y)2 = ∫−∞

∞

(y − y)2 ⋅ ρ(y) ⋅ dy

where is the standard deviation of the PDF (the square root of Eq. [31.44]). For ourσpurposes, in this book, we can think of variance as the average power of a random(voltage) signal and the standard deviation as the RMS value of the signal (see Eqs.[31.37] and [31.38]). Example random signals include the time difference between theactual edge of a clock and the ideal edge location (jitter), the voltage difference betweenthe input of an ADC and the ADC's reconstructed output (quantization noise), and therandom fluctuations of electrons due to thermal motion in a resistor (thermal noise).

Example 31.14Determine the RMS value of the jitter when the jitter has a probability densityfunction, PDF, as shown in Fig. 31.12.

Using Eq. (31.44) the variance of the jitter PDF is

(seconds2)σ2 = ∫−∆Ts/2

∆Ts/2

t2 ⋅ 1∆Ts

⋅ dt = 13 ⋅ ∆Ts

⋅ t3−∆Ts/2∆Ts/2 = (∆Ts)2

12

and thus the RMS jitter is

RMS jitter, (seconds)σ = ∆Ts

12

where ∆Ts is the peak-to-peak jitter in the sampling clock rising edge. Note thesimilarity to the derivation of VQE,RMS in the last chapter.

A more useful discussion of jitter can be constructed if we assume the jitter has aGaussian PDF, as shown in Fig. 31.13, and attempt to describe how the jitter in thesampling clock affects an ADC output spectrum with a single-tone input. Using Eqs.(31.11), (31.12), and (31.15) we can write the sampling error voltage (review Fig. 31.6),at a given time, as

(31.45)∆Vs(t) = δTs(t) ⋅ Vp ⋅ 2πf in ⋅ cos 2πf int


where is a random variable indicating the jitter in the sampling clock at a given timeδTs(t)( is the time difference between the actual clock transition time and the expectedδTs(t)transition times that are spaced by Ts (see Fig. 31.12). The peak-to-peak value of isδTs(t)

, while its average value is zero. Again, we assume that the jitter probability∆Ts

distribution function is Gaussian, as seen in Fig. 31.13.

Rewriting Eq. (31.45) using a discrete time step nTs, the sampling error can bewritten as

(31.46)∆Vs(nTs) =

sampling error amplitude

δTs(nTs) ⋅ Vp ⋅ 2πf in ⋅carrier term

cos 2πf innTs

We're interested in the spectrum of this error signal as it will add to our RMS quantizationnoise plus distortion voltage, effectively lowering the data converter's SNDR. Notice thatthe spectrum of Eq. (31.46) will have aliased components (and so will the sampled signal)so we need to filter out these components above fs /2 (with the reconstruction filter.) Alsonote that multiplying the sampling error by the cosine term in Eq. (31.46) simply shifts theerror spectrum to a frequency fin. The cosine terms acts like a carrier in an amplitude-modulated signal. This is illustrated in Fig. 31.14.


0


time

Figure 31.13 Sampling jitter with a Gaussian probability distribution.

6σ ≈ ∆Ts

RMS jitter = σ ≈ ∆Ts

6ρ(t) = 1

σ 2π⋅ exp

− t2

2σ2

ρ(t)

peak-to-peak jitter ≈ ∆Ts

σ

3σ

2σ

Figure 31.14 Modulating sampling error with an input sinewave frequency.

f

Sampling error amplitude spectrum

0 0 f

Data converter output spectral content resulting from jitter

f in

Example 31.15Repeat Ex. 31.7 assuming the clock jitter has a Gaussian PDF.

In this example the peak amplitude of the input signal, Vp , is 0.75V, the inputfrequency, fin , is 25 MHz, and the peak-to-peak jitter is 100 ps. The averagepower in the sampling error amplitude spectrum is

(31.47)PAVG,jitter = σ2 ⋅ (Vp ⋅ 2πf in)2

2=

∆Ts

6

2

⋅ (Vp ⋅ 2πf in)2

2

or

PAVG,jitter =

100 ps6

2

⋅ (0.75 ⋅ 2π ⋅25 MHz)2

2= 1.93 × 10−6 V2

while the RMS voltage associated with this error is 1.39 mV. The quantizationnoise associated with this 8-bit data converter is

VQe,RMS = VLSB

12= VREF+ − VREF−

2N 12= 1.69 mV

The RMS noise voltage due to clock jitter and quantization effects is then given by

1.392 + 1.692 mV = 2.1 mV

We can calculate the SNR using

SNR = 20 ⋅ log0.75/ 22.1 mV

= 48.1 dB

giving an effective number of bits, from Eq. (31.5), equal to 7.7. Note that this is asignificant improvement over what was calculated in Ex. 31.7, where the jittervariation was always the peak-to-peak value.

The PSD of the sampling error amplitude, described by Eq. (31.46), can bedetermined with the help of Eq. (31.37)

(31.48)σ2 ⋅ (Vp ⋅ 2πf in)2

2= 2 ∫

0

∞

Pjitter( f ) ⋅ df

If the spectrum of the phase noise due to jitter is narrow, as seen in Fig. 31.14, then thespectral density of the sampling error, Pjitter( f ), is concentrated around the frequency ofthe input sinusoid. However, if we assume the phase noise spectrum is white and evenlydistributed throughout the base spectrum (so that we integrate Eq. (31.48) from DC tofs/2), we can write

(31.49)Pjitter( f ) = σ2

f s⋅ (Vp ⋅ 2πfin)2

2

The power spectral density of the sampling error voltage, assuming even distribution ofthe noise throughout the base spectrum, is shown in Fig. 31.15.


Specifying Phase Noise from Measured Data

It's important to note that we have been discussing clock signals that are square waves(that is, have odd order harmonics) and so discussing jitter (a time-domain term) is,generally, more appropriate than discussing phase noise (a frequency domain term).However, because the terms are both widely used to indicate the same, basic, effect (avariation in the period of a periodic waveform), we will briefly discuss phase noisespecification from measured oscillator data.

Consider the representation of a measured oscillator spectrum (power spectraldensity) shown in Fig. 31.16. In general, oscillator noise is specified in terms of the carriervoltage (or power) with units of dBc (decibels with respect to the carrier). The ratio of thevoltage of the fundamental, carrier, or sampling clock in our case, fs , is taken to the noisein a bandwidth at some offset from the fundamental

(31.50)Phase noise, dBc/Hz =

10⋅log (V2)

10 ⋅ log

∫

fL1

fH1

Posc( f ) ⋅ df

−

10⋅log (V2/Hz)

10 ⋅ log P( f s )

where the first term is the noise power at an offset from fs.


Figure 31.15 Sampling amplitude error PSD assuming sampling error spectrum is white.

0 f

Pjitter( f ), V2/Hz

fs/2

σ2

f s⋅ (Vp ⋅ 2π ⋅f in)2

2

Figure 31.16 Measured oscillator spectrum.

0 f

Posc( f ), V2/Hz

fs

fL1

fH1

31.2 Improving SNR using Averaging

We first introduced the concept of averaging back in Sec. 30.3.2 to reduce the RMSquantization noise voltage. In this section we'll continue this discussion showing that theSNR of a data converter can be improved by using averaging provided: the data converteris linear to within the resolution of the improvement, the input signal is bandlimited, andthe input signal is busy (not a DC signal).

31.2.1 Using Averaging to Improve SNR

Recalling that averaging K samples output from a data converter with a busy input resultsin an RMS quantization noise voltage (see Eq. [30.47]) of

(31.51)VQe,RMS = 1

K⋅ VLSB

12

we can now, with the help of Eq. (31.1), write the ideal signal-to-noise ratio usingaveraging as

(31.52)SNRideal = 6.02N + 1.76 + 10 log K

N is the number of bits (the resolution) of the data converter whose output is beingaveraged. Using no averaging, that is K = 1, results in Eq. (31.52) simplifying to Eq.(31.4). Averaging two samples causes the SNRideal to increase by 3 dB or the effectiveresolution of the data converter to increase by 0.5 bits. The increase in resolution, becauseof averaging, can be written as

(31.53)Increased resolution, NInc =10 log K

6.02

Figure 31.17 shows how averaging the output of a data converter changes the effectiveresolution of the data converter. Note that the increase in resolution is based on thefollowing assumptions: a busy input signal, the input signal is bandlimited, and the dataconverter is linear to the final resolution (data converter resolution, N, + improvement inresolution, NInc) coming out of the averaging circuit.


Figure 31.17 Using averaging to improve data converter resolution.

1 10 100 1k0

1.67

3.33

5.00

K Number of points averaged

(Bits added)Improvement in resolution,

SNRideal = 6.02(N + NInc) + 1.76

NInc

Spectral Density View of Averaging Revisited

We know, from our previous discussions, that if the quantization noise is random, we candetermine its spectral density using

(31.54)σ = VLSB

12= 2 ∫

0

∞

PQe( f ) ⋅ df

where is the quantization noise power spectral density. Also, from the last chapterPQe( f )we can write

(31.55)PQe( f ) = [VQe( f )] 2

We might think that if the quantization noise is white (Bennett's criteria hold, sothere is no correlation from one data converter output sample to the next) then thespectral content of the noise is spread evenly in frequency from zero to infinity ( isPQe[ f ]a constant with frequency). This would also mean that approaches zero, from Eq.PQe( f )(31.54), in order to make the average power, that is, the variance , of the quantization(σ2)noise equal to .(VLSB)2/12

Before we address this concern (our spectral density approaching zero), let'sreview how we calculated the RMS quantization noise voltage, , from theVQe,RMS

spectrum given in Fig. 30.48 back in Ch. 30. In this figure we looked at the entirespectrum (or most of the spectrum, up to 200 MHz or 2fs , where significant spectralcontent is found) to determine (see Ex. 30.11 and the discussion concerning theVQe,RMS

figure). We know that the quantization noise doesn't experience aliasing since quantizationoccurs after sampling. So while it is correct to look at a wide spectrum to calculate noise,it would be more useful to limit our view of the spectrum to frequencies up to the Nyquistfrequency , where our desired signal spectrum should reside. We can do this(= fn = fs/2)by assuming the entire quantization noise power lies in the base spectrum or

(31.56)VLSB

2

12= 2 ∫

0

fs/2

PQe( f ) ⋅ df

or

(31.57)PQe( f ) = 1f s

⋅VLSB

2

12

The PSD of the quantization noise is plotted in Fig. 31.18. Note the similarity to Fig.30.57 (the voltage spectral density of the quantization error).

Consider the result of adding two consecutive ADC outputs as shown in Fig.31.19. A simple sum will be considered the average of the two consecutive ADC outputsignals. The finite digital output word length, in this case eight bits, can limit the resolutionof the resulting sum. In the cases where we do need to do a division by two we couldsimply use the top eight bits of the sum (a shift-right operation.) In most of the discussionsrelated to digital words in this book, averaging will be equivalent to addition. The


current-time sample coming out of the ADC is labeled , while the previous ADCx(nTs)output is . The output of the simple digital averager is x[(n − 1)Ts]

(31.58)y(nTs) = x(nTs) + x[(n − 1)Ts]

remembering that Bennett's criteria must be valid for averaging to effectively reduce thequantization noise. For example, applying a DC input signal to the circuit of Fig. 31.19will not result in higher accuracy (the output of the averager will remain the same as theoutput of the ADC [actually the averaged output is twice the ADC output]). We'll discussthis restriction in more detail in a moment when we discuss adding a dither orpsuedo-random noise signal to the input to randomize the quantization noise (make itsspectrum white). Also note that there are restrictions on the allowable range of inputfrequencies when using this configuration to avoid amplitude distortion. For example, if

is 50 MHz (with ), then it's easy to show that the resulting digitalf in f s = 100 MHzaverager output is zero (see Fig. 31.20).

Let's show that the digital averager of Fig. 31.19 can be thought of as a filter andlook at how passing the ADC output through the averager affects the ADC's signal plusquantization noise and distortion output spectrum. This will also tell us how we have torestrict the input frequencies applied to the ADC to avoid amplitude distortion orsomething similar to what's shown in Fig. 31.20.


Figure 31.18 Quantization Noise Power Spectral Density.

f fn = f s/2

PQe( f ), V2/Hz

VLSB2

12 ⋅ f s

Figure 31.19 Using two paths to average the quantization noise.

8Ideal

8-bit ADC

Analog

Digital

8

9Output

(averaged)

Simple digital averager.

adder

Eightlatches

Digital

8

VIN = Vpsin (2πf in ⋅ t)fclk = 100 MHz

x[(n − 1)Ts]

x[nTs]y[nTs]

Consider the redrawn (Fig. 31.21) z-domain version of the digital averaging filterof Fig. 31.19. The filter's transfer function can be found directly from Fig. 31.21 or bytaking the z-transform of Eq. (31.58) as

(31.59)H(z) = Y(z)X(z)

= 1 + z−1

Remembering from Eq. (30.12) that we can writez = ej2π f

fs

(31.60)H(z) = 1 + e−j2πfinfs =

real

1 + cos −2π f in

f s

+ j⋅

imaginary

sin −2πf in

f s

Taking the magnitude of this equation results in

(31.61)H(z) = 1 + cos

2πf in

f s

2

+ sin

2πf in

f s

2

or changing the notation to with H( f ) f = f in

(31.62)H( f ) = 2 1 + cos

2π

ff s

and the phase is given by

(31.63)∠ H( f ) = tan−1

−sin 2π f

fs

1 + cos 2π f

fs


Figure 31.20 Showing the limitations placed on ADC input frequency when using averaging.

20 ns 40ns

These two points average to zero

time

Vin(t)

Figure 31.21 Z-domain representation of the averager shown in Fig. 31.19.

OutputSimple digital filterADC outputY(z)

X(z)

z−1 z−1X(z)

Referring to Ex. 30.4 of the last chapter the phase can be written as

(units, radians) for (31.64)∠ H( f ) = −π ⋅ff s

f < f s/2

The magnitude and phase responses of this simple digital filter are shown in Fig. 31.22.Note that this is the discrete version of the comb filter discussed in Ex. 30.4. Also notethat 1) the phase response is linear, 2) the response is periodic (as is the response of anydigital filter), and 3) at an input frequency of half the Nyquist frequency, , thef s/4magnitude response is (3 dB down from the DC gain of two).2

We can also see that 1) averaging results in an attenuation of many of the inputsignal frequencies (as shown in Fig. 31.22) and 2) indeed the average of the input signalgoes to zero, as was shown in Fig. 31.20, when the input signal frequency is f s/2.

If we assume the output quantization noise power spectral density, , for thePQe( f )ADC shown in Fig. 31.19 is white then the output of the simple digital filter has a PSD asshown in Fig. 31.23 (the product of the filter response squared with the noise PSD). Theaverage power contained in this PSD is

(31.65)PAVG = 2 ∫0

fs/2VLSB

2

12 ⋅ f s⋅ 2

1 + cos 2π f

f s

df


Figure 31.23 Quantization noise power spectral density after averaging two samples.

f fn = f s/2

PQe( f ), V2/Hz

VLSB2

3 ⋅ f s

Figure 31.22 Magnitude and phase response for the simple digital filter of Fig. 31.21.

2

degrees

90

-90f in (Hz)f s/2 3f s/2f s/4 f s f s/2 3f s/2

H( f )∠ H( f )

2

f in (Hz)

or

(31.66)PAVG = VLSB2

6+ VLSB

2

6π sin 2π f

f s

f = 0

f = fs/2

= VLSB2

6

The power in an input sinewave before averaging is (the RMS voltage of theVp2/2

sinewave is ). Averaging (adding) two samples results in an increase in the desiredVp/ 2

signal amplitude by two and so the power increases to (the RMS voltage increases to2Vp2

). This is important because now the SNR, on the output of the digital averaging(2Vp)/ 2filter, is

(31.67)SNR = 20 log2Vp/ 2

VLSB/ 6= 20 log

Vp/ 2

VLSB/ 24

or in terms of a generic averaging constant K (see Eqs. (31.51) or (30.47)), the effectiveRMS quantization noise voltage is

(31.68).VQe,RMS = 1

K⋅ VLSB

12

Without rederiving the equations presented at the beginning of this section, we should seehow averaging affects a data converter's SNR.

An important observation

Eq. (31.68) assumes the averaging filter does not attenuate the input signal. If, forexample, the input frequency were , then the RMS amplitude of the desired signalf s/4

would change from to or simply (because of the root two(2Vp)/ 2 Vp ⋅ 2

/ 2 Vp

gain at , as shown in Fig. 31.22) and the SNR would be the same as the output of thef s/4ADC in the non-averaged circuit. If the input frequency were greater than , then thef s/4SNR would actually be worse than the non-averaged SNR! Therefore, we have to restrictthe input frequency bandwidth, B, to frequencies less than when averaging two termsf s/4in order to avoid degrading the data converter's SNR. In general, for an arbitrary numberof averages K, we can write the restrictions on the input bandwidth using

and (31.69)B =fs/2K

=fn

Kfin ≤ B

We have already presented this equation (Eq. [31.22]) when discussing how oversamplingaffects sampling clock jitter stability requirements. The averaging factor K is commonlycalled the oversampling ratio to denote the ratio of the Nyquist frequency to the inputsignal bandwidth. This can sometimes be confusing since, as we showed in the lastchapter, oversampling an input waveform alone, without averaging, does not lower theamount of quantization noise in a data converter's output spectrum. Nevertheless, statingthat a data converter is using oversampling is synonymous with stating the data converteremploys an averaging filter. The averaging filter used on the output of an ADC is called a


decimating filter while the reverse averaging filter used on the input of a DAC is called aninterpolating filter. We will discuss these filters in detail in the next sections.

Example 31.16Suppose the input sinewave in Fig. 31.19 has a peak amplitude of 0.5 V and afrequency of 20 MHz. Determine the peak amplitude of the averager output andthe delay through the circuit. Comment on any assumptions made.

Using Eq. (31.62) we get

H( f ) = 2 1 + cos

2π 20100

= 1.62

and so the peak amplitude of the output sinewave is . Ideally,0.5 ⋅ 1.62 = 809 mVthe amplitude out of the averager is twice the input or, in this case, 1 V.

The delay through the filter is determined using Eq. (31.64) and knowingPhase shift

2π ⋅f s ⋅ ∆t = −πff s

The delay (knowing the minus sign indicates the output of the filter occurs after, orlater in time than, the input signal) can then be written as

(31.70)∆t =f

2f s2

and so, for this example, .∆t = 1 ns

Note that we are not discussing the effects of quantization noise, that is, thefundamental minimum voltage that can be resolved. We are assuming continuousamplitude signals throughout the system in order to simplify the filter calculations.This assumption falls apart if, for example, the peak-to-peak amplitude of the inputsinewave is reduced to a value below one least significant bit. This will cause thecircuit to function as if the input were a DC signal.

Jitter and Averaging

We can apply the averaging discussion just developed directly to the jitter discussionpresented earlier in the chapter and answer the question, "How does averaging affect thesampling amplitude error power (resulting from jitter) in a data conversion system?" If weassume that the jitter has a Gaussian PDF, then the average power in the sampling erroramplitude, from Ex. 31.15, is

(31.71)PAVG,jitter =

σ ⋅

Vp

2⋅ 2πf in

2

where is the standard deviation of the jitter (see Fig. 31.13). It may be helpful toσre-write Eq. (31.68) in terms of the quantization error power as


(31.72)PQe,AVG = (VQe,RMS)2 = 1K

⋅VLSB

2

12

and apply the same derivation to Eq. (31.71) to give

(31.73)PAVG,jitter = 1K

⋅

σ ⋅

Vp

2⋅ 2πf in

2

This equation shows that the sampling error amplitude power, PAVG,jitter, introduced into thedata converter's output spectrum decreases with averaging. Averaging two samples causesthe sampling error amplitude power to decrease by 3 dB. This effectively reduces the jitterrequirements placed on the sampling clock. While this may not appear to be verysignificant at first glance, consider what happens if, for example, 256 samples are averaged( ). The sampling error power decreases by 24 dB, making clock jitter, when usingK = 256a reasonably stable oscillator, almost not an issue. Also note that a doubling in the jitter'sstandard deviation, , results in a 6 dB increase in sampling error amplitude power. σ

Relaxed Requirements Placed on the Anti-Aliasing Filter

The use of averaging will also lead to relaxed requirements of the anti-aliasing filter(AAF). Figure 31.24a shows the requirements placed on the AAF without averaging. Aswe saw in the last chapter, ideally, the transition from the 3 dB frequency to the "stopfrequency" or Nyquist frequency should be infinitely fast (the filter should abruptly changefrom a gain of unity to a gain of zero [something small]). When using averaging, Fig.31.24b, we have to limit our desired input signal bandwidth to B, see Eq. (31.69). Therolloff of the filter in (b) can be much slower and in many cases a simple, single pole, RCfilter is all that's need for an AAF. Also, our averaging filter will attenuate the ADC outputspectrum, as seen in Fig. 31.22, and help to remove input signal power above . Thef s/2Ksignificance of this will be easier to see as the number of points averaged increases and ouraveraging filter's response gets sharper with more attenuation (as discussed in the nextsection). Of course, the penalty for the relaxed requirements of the AAF is reduced signalbandwidth for a fixed sampling frequency.


Figure 31.24 (a) AAF requirements without averaging and (b) AAF requirements with averaging.

1 1

f f

(a) (b)

fn = f s/2

B = f s/(2K)H( f )H( f )

f3dB

fn = f s/2

Data Converter Linearity Requirements

Consider the cases for averaging ADC outputs shown in Fig. 31.25. In part (a) we showthe ideal situation where the black dots indicate two consecutive outputs spaced by oneLSB (time is not shown in this figure). The ADC outputs, in part (a), are located on theideal levels, while the averaged output falls exactly in the middle of these levels (and henceour increased resolution).

Part (b) of this figure shows the situation where the ADC outputs are shifteddownwards by 0.5 LSBs from their ideal levels. Following this offset, the averaged pointshifts downwards as well. In part (c) the top output of the ADC (the top black dot) isshifted downwards by 0.5 LSBs and so the averaged point shows a 0.25 LSB offset fromits ideal position. While we used a single LSB difference to show averaging, we could useany number of LSBs to show that the ADC accuracy must be equal to or better than thedesired final digital filter output accuracy.

The number of bits in the ADC (its resolution) N, and the number of bitsimprovement in resolution after filtering, NInc , are used with the final, total number of bits(the number of bits coming out of the digital filter) to give

(31.74)NFinal = N + NInc

The ADC output should, ideally, change in increments of the exact LSB voltage. Inreality, the changes will be different from the ideal output levels (as just discussed.) Inorder to achieve an increase in the number of final bits, the output of the ADC must beaccurate (its actual levels must be spaced from the ideal levels) to within

(31.75)± VREF+ − VREF−

2NFinal+1= ± (0.5 LSB) ⋅ 1

2NInc

where no averaging (NInc = 0 and K = 1) means the ADC is at least 0.5 LSBs accurate.This is a significant limitation when using averaging to increase the resolution of an ADC.


Figure 31.25 Linearity requirements when averaging.

1 LSB

Averaging two points (ideal)

ADC output 1

ADC output 2

Averaged point1 LSB

Averaging two points (nonideal)

Averaged point

Ideal level

offset of 0.5

1 LSB

Averaging two points (nonideal)DNL of 0.5

0.5 LSBDNL

(a)

(b)

(c)

This is especially true when a resolution greater than 10 bits is desired with INL and DNLless than 0.5 LSBs. Later in the chapter, and in the next chapter, we will look at±feedback topologies that may relax the accuracy requirements placed on the ADC andallow averaging to more effectively remove quantization noise.

Example 31.17To illustrate the requirements placed on the accuracy of the original ADC in moredetail, consider averaging 16 consecutive ADC output samples; 15 at a digitalcode of zero and one at a digital code of 1 LSB. Determine the accuracy requiredof the ADC, the size of the word coming out of the averaging filter assuming theADC is 8-bits, and the final word size after considering the increase in resolution.

The ideal output of the digital filter will be 1/16 of the original ADC's LSB. Wecan write this as

Average =

16 consecutive ADC outputs

1 + 0 + 0 + ... + 016

⋅ (Original LSBs)

where 1 is a data converter output of 00000001 and 0 is 00000000. Averaging 16sample points, from Eq. (31.53), will give an increase in resolution of 2 bits.(Getting only 2-bits increase may be tough to see using only a single LSBdifference in the ADC outputs but may be easier to see if the codes are different byseveral LSBs.) Because the ADC is 8-bits, the final resolution will be 10-bits.(Note: that an increase in resolution of 1.5 bits would also require a 10-bit word.)However, if we add 16 8-bit words (where the value of the words, in the generalcase, can range from 00000000 to 11111111) we end up with a 12-bit word size.To get to our desired 10-bit word size we throw out the lower 2-bits. Another wayof stating this is that we divide the 12-bit word by four (shift right two times toremove the lower two bits in the word). Here, where only 1 ADC output of the 16is 00000001, the output of the averaging filter would end up being 0000000000.We would need to see at least four ADC outputs of 00000001 in order to see the10-bit filter output go to 0000000001. Of course, if the input is busy, we willunlikely have the case where only one of the sixteen filter inputs is 00000001 andthe other inputs are 00000000. (More on this below in the dither discussion.)

The INL and DNL of the ADC must be less than 0.125 LSBs (8-bit LSB), from±Eq. (31.75), in order for the output of the filter to be 0.5 LSBs accurate (a±10-bit LSB).

Finally, note that an ADC output of all ones, that is, 11111111 (255) correspondsto an analog voltage of where VDD − 1 LSB 1 LSB = (VREF+ − VREF−)/256

. The maximum output of the filter, after averaging(VDD − 1 LSB =255 ⋅ 1 LSB)16 ADC output samples, is or, in terms of a(16 ⋅ 255)/4 = 1111111100 (1020)voltage, . In both cases an1020 ⋅ 1 LSB where 1 LSB = (VREF+ − VREF−)/1024output of all zeroes corresponds to and, also in both cases, the maximumVREF−analog output voltage is . Vout = 0.9961 ⋅ (VREF+ − VREF−)


Example 31.18Specify the accuracy required of an 8-bit ADC if it is to be used with oversamplingto attain 12 bits with INL and DNL of 0.5 LSBs.±

The increase in the number of bits, NInc , is 4. The accuracy required of the 8-bitADC, from Eq. (31.75), is (1/32) of an LSB. If VREF+=1.5 V and VREF−= 0 then±the LSB of the ADC is 5.86 mV. The output of the ADC must be within ± 183 µVof the ideal ADC output levels in order to arrive at a final, after averaging,resolution of 12 bits (with a 12-bit accuracy of 0.5 LSBs). Also, we will have to±average, according to Eq. (31.53), 256 consecutive ADC outputs to get a 12-bitoutput.

Adding a Noise Dither to the ADC input

Our assumption, when discussing the benefits of averaging or calculating the spectraldensity of the quantization noise, falls apart for DC or slow-moving signals (the ADCinput is not "busy"). To solve this problem consider adding a noise signal, to the ADCinput, that has a frequency content that falls within the range

(31.76)f s

2K≤ f <

f s

2

so that it can be filtered out with the averaging filter. This noise is often called dither (astate of indecision or agitation) because it helps to randomize the spectral content of thequantization noise making it white (a flat spectrum, see Fig. 31.18).

Figure 31.26 shows the basic idea. In (a) a DC signal is applied to the ADC thatfalls half way between two ADC transition codes spaced apart by 1 LSB. The output codeof the ADC remains unchanged with time. In (b) a noise signal is added to the DC inputwhich has two benefits: 1) the quantization noise (the difference between the input signaland the reconstructed ADC output code) changes with time, and 2) the output of the ADChas some variation which makes it possible to determine the DC voltage after averaging.


1LSB DC Input Signal

(a) (b)

Figure 31.26 (a) DC input signal (b) DC input signal with dither added.

ADC Output code N

ADC Output code N-1

We can add the noise signal to our desired input signal with a circuit similar towhat's shown in Fig. 31.27. Simple resistors add and reduce the noise signal to the ADCinput. The noise signal source is, most easily, derived from some sort of asynchronouslogic circuit and has a peak amplitude (before reduction) of VDD (= 1.5 V in this chapter).In this figure note that we have indicated that the dither signal amplitude should beapproximately 0.5 LSB RMS (remembering the signal is, ideally, random and bandlimitedas specified by Eq. [31.76]). This number, 0.5 LSB RMS, is subjective, and no exact rulesas to its selection can be given other than the desire that the peak-to-peak amplitude begreater than 1 LSB. One disadvantage of adding the dither is that the allowable range ofinput signals shrinks (a DC signal at VDD − 1 LSB will not benefit from dithering sincethe ADC will be at its full-scale output).

Before we discuss the implementation of a dither source, consider one possibility(a Gaussian PDF) for the desired probability density function (PDF) of the dither signaland DC input shown in Fig. 31.28 (the input to the ADC). If we average this signal over along time, we get the average or DC input signal since the dither averages to zero. This


Figure 31.27 Adding dither to an ADC input signal.

ADC

Dither

Input

Input with dither

Block diagram

ADCInput

Input with dither

digitalcircuit

50

0 to 1.5V

5,000Approximately 0.5 LSB RMS dither

noisesource

Circuit implementation

Dithergenerating


Volts

Figure 31.28 Input to the ADC, dither and DC, with a Gaussian probability distribution.

Amplitude variation with time

RMS dither = σ = 0.5 LSBρ(t) = 1

σ 2π⋅ exp

−(Vin − Vin )2

2σ2

ρ(t)

σ = 0.5 LSB

DC in, Vin

would also mean that we can have some dither spectral content below as long asf s/2Kwe average enough ADC output samples to make its contribution to the SNDR small. Itis generally a good idea to use Eq. (31.76) as a guide for allowable dither spectral content.Finally, it's important that any dither signal we generate has a symmetrical PDF (the dithersignal must average to VDD/2 before amplitude reduction). If not, an unknown DC offset(the known DC offset is the VDD/2 attenuated by the resistive divider in Fig. 31.27) in thedata converter's (actually the filter's) output will result.

An example of an implementation of a dither noise source is shown in Fig. 31.29.The outputs of the rows of inverters, which are tied together, will occur asyncronouslyand fight against each other causing the amplitude of the dither signal to occupy levelsother than the normal logic levels of VDD and ground for significant amounts of time. Thedither signal can be made more random by adding more rows of inverters. The challengeto this design is setting the number of inverters used in each row so that the spectralcontent falls within the desired range (which may require a large number of inverters) andkeeping the output of the dither circuit uncorrelated with the sampling clock. Othertechniques for generating random noise, such as using linear serial feedback registers, canbe found in most books covering communication systems.

The Z-plane

It will be very helpful in our discussion of mixed-signal circuits and systems to gain anintuitive feel for the frequency response of a discrete-time system by looking at thez-domain representation of the system. Towards this goal, consider the transfer function ofthe simple digital averager depicted in Figs. 31.19 and 31.21 with a z-transform of

(31.77)H(z) = Y(z)X(z)

= 1 + z−1 = z + 1z

is the system's output, while is the system's input. Note that the system isY(z) X(z)discrete in time but not necessarily in amplitude. We can apply the z-transform toswitched-capacitor circuits with continuous-valued amplitudes as well as to dataconverters with quantized values of amplitude. It is very useful, for an intuitive


Figure 31.29 One possible implementation of a dither circuit.

Ditherout

understanding of the frequency response of a discrete system, to plot the transfer functionin the z-plane (Fig. 31.30). Figure 31.30 also shows how Eq. (31.77) can be displayed onthe z-plane. A pole is located at z = 0 (at the location the denominator goes to zero andthe transfer function goes to infinity) and a zero is located at z = −1 (at the location wherethe numerator goes to zero).

The z-plane is usually used to describe the frequency response of a discrete timesystem, H( f ), by assuming the input to the system is a unit magnitude sinusoid with

varying frequency, f. This input, , evaluates the output of the system or1 ⋅ ej2π f

fs ( = z)

evaluated when (31.78)H( f ) = H(z) z =

magnitude

1 ⋅

phase

e j2π ffs

We should now see that the unit circle, shown in Fig. 31.30, indicates the relationshipbetween z and f when specified by Eq. (31.78). Therefore, to determine H( f ) from a plotof H(z) on the z-plane, we simply evaluate H(z) along the unit circle. To show how thistransfer function evaluation is performed, consider Eq. (31.77) and the corresponding plotof its pole and zero shown in Fig. 31.30 along with the magnitude of Eq. (31.77) or Eq.(31.59) plotted against the frequency in Fig. 31.22. At DC ( f = 0 and z = 1 ⋅ e0 = 1∠ 0)point A in Fig. 31.31, the gain of the circuit is two and is calculated using

(31.79)H( f ) = distance to zerodistance to pole

The distance from the zero to point A is 2 while the distance between the pole to point Ais 1. Therefore, as shown in Fig. 31.22, the magnitude of H( f ) is 2. The phase of thetransfer function is calculated along the positive x-axis using

(31.80)∠ H( f ) = ∠ of zero − ∠ of pole


Figure 31.30 The z-plane.

z-plane

Real

Imaginary

Indicates a pole

Indicates a zero

Indicates six poles at a location6

Indicates two zeroes at a location2

1

1

Unit circle indicates the magnitude of a z-domain signalis unity.

z = ej2π⋅ f

fs

which, as seen in Fig. 31.22, results in a phase angle of zero. Next consider evaluating the

H(z) at , point B in Fig. 31.31. The distance fromf s/4 f = f s/4 and z = 1 ⋅ e jπ

2 = 1∠ 90

the pole to point B is 1 while the distance from the zero is resulting in a magnitude2. The angle from the pole along the x-axis to point B is 90°, while the angle from the2

zero is 45° resulting in overall phase response of −45° (verify with Fig. 31.22).

Also note 1) any digital filter's or system's frequency response is periodic withperiod (one complete revolution around the unit circle), 2) we normally are onlyf s

concerned with evaluating H(z) over the top half of the unit circle (from DC to [thef s/2Nyquist frequency, ]), and 3) a pole at the origin has no effect on the magnitudefn

response of H(z) but does affect the phase response (as shown in Ex. 30.6 in whichmultiplying H(z) by z−1, adding a pole at the origin to H(z), simply shifts the output later intime). Finally note that the number of poles in H(z) must be greater than or equal to thenumber of zeroes if the digital filter/system is to be realizable in hardware (the output ofthe system cannot occur before the system's input).

Example 31.19Determine, using the graphical approach just discussed, the magnitude and phaseof the transfer function shown in Fig. 31.32 at a frequency of .f s/4

If we label the length from a pole (zero) to the evaluation point p (z), then themagnitude of the transfer function is given by

H(z) = z1p1 ⋅ p2

Labeling the angles for the poles and zeroes as indicated in the figure, we can writethe phase response as

∠ H(z) = θ3 − θ2 − θ1


Figure 31.31 The z-plane pole and zero for Eq. (31.77).

z-plane

Point A, DC or

Point B,

Also at point B,

f = 0, f s, 2f s ...

z = ej2π⋅ f

fs

H(z) = z + 1z

f = f s/4, 5f s/4 ...

z = e jπ/2

Example 31.20Determine the frequency response of a digital system with the time domainresponse

y[nTs] = x[nTs] + y[(n − 1)Ts]

Sketch the hardware implementation of the system and its frequency response.

The z-domain transfer function for this system is

Y(z) = X(z) + Y(z) ⋅ z−1

or

(31.81)H(z) = 11 − z−1

= zz − 1

The hardware implementation of the system is shown in Fig. 31.33 along with thez-domain representation. Note that the size of the words used (the number of bitscoming out of the adder and the number of latches) depends on the application.


Figure 31.32 The z-plane pole and zero plot for Ex. 31.19.

z-plane

Evaluated here

z-plane

Magnitude reponse Phase response

p1

p2

z1 θ1

θ2

θ3

x[nTs]

y[(n − 1)Ts]

y[nTs]

Figure 31.33 Block diagram used in Ex. 31.20 of a digital integrator.

LatchesClock

Y(z)X(z)

z−1

Y(z)z−1

H(z) = 11 − z−1

= zz − 1

Figure 31.34 shows the z-plane representation of this system along with themagnitude and phase response of the system. This circuit is called a digitalintegrator. To show why, let's determine the magnitude and phase responses, usingEq. (31.81), and noting the z in the numerator is simply a phase shift

(31.82)H(z) = zz − 1

→

phase shift

ej2π f

fs ⋅ 1

ej2π f

fs − 1= ej2π f

fs ⋅ 1

(−1 + cos 2π f

fs) + j sin 2π f

fs

Knowing

(31.83)1a + jb

= 1

a2 + b2

we can write (see Eq. [31.61])

(31.84)H( f ) = 1

−1 + cos 2π f

fs

2

+ sin2π f

fs

2= 1

2(1 − cos 2π f

fs)

and, evaluating the phase directly from the z-plane plot,

(degrees) for (31.85)∠ H( f ) =

from zero

2π ff s

−

from pole

π f

f s+ π

2 = 180

ff s

− 90 0 < f < f s

At DC the phase contribution from the zero is 0°, while the phase contributionfrom the pole, at a frequency just above DC, is 90°. The result is an overall phaseresponse of −90°. At fs /4 the phase contribution from the zero is 90°, while thephase contribution from the pole is 135°, resulting in an overall phase response of−45 °.


z-plane

Figure 31.34 The z-plane representation along with magnitude and phase response for a digital integrator.

degrees

90

-90

0.5

f

f

f s/2 3f s/2f s

H( f )

∠ H( f )

H(z) = 11 − z−1

= zz − 1

Consider the possible input to our digital integrator (Fig. 31.33) and the resultingoutput shown in Fig. 31.35a and b respectively. In this figure we are using +1 to indicatethe peak positive input sinewave amplitude and −1 to indicate the peak negative inputamplitude. The frequency of the sinewave is and so, according to our magnitude plotf s/2in Fig. 31.34, the gain is 0.5 (the peak-to-peak amplitude of the sinewave is reduced byone-half). Looking at Fig. 31.35, we should see that the initial state of the register (thelatches) used in the integrator will, together with the input, determine the DC offset in theoutput waveform. For example, if the latches initially contained zero and the first samplewas +1, as seen in Fig. 31.35a, then we would get the waveform shown in Fig. 31.35b. If,instead, the first sample were −1, then the entire waveform in Fig. 31.35b would shiftdownwards by +1. In any integrator, digital or analog, the "initial conditions" will affectthe output waveform.

The next important factor we should notice in Fig. 31.35 is that we picked thepeaks of the input sinusoid as our inputs to the digital integrator. Shifting our ADC outputsampling points by Ts /2 results in a signal of all zeroes being applied to the digitalintegrator. The result is no change in the integrator's output. Shifting the sampling pointsby Ts /3 results in an integrator input of with a corresponding integrator peak-to-±0.5peak output of . In any case, at , the output of the digital integrator is one-half±0.25 f s/2the input signal's amplitude.

In the above discussion we used decimal numbers to represent the input and outputsignals of the integrator. In a practical implementation we use binary numbers. Let's useour ideal 8-bit data converters to illustrate the number system concerns. In theseconverters and with . A code of all zeroesVREF− = 0 VREF+ = 1.5 V VLSB = 5.859 mVcorresponds to 0 V while a code of all ones corresponds to 1.494 V. The common modevoltage, . Again this number system is called offsetVCM , = (VREF+ − VREF−)/2 = 0.75 Vbinary. Figure 31.36 illustrates the representation of a full scale sinusoid using the offsetbinary number format.


Figure 31.35 (a) Input and (b) output of the digital integrator of Fig. 31.33.

time

time

+1

-1

+1

(a)

(b)

x(t)x(nTs)

2Ts 4Tsy(t)

y(nTs)

We should compare the binary offset numbers of Fig. 31.36 to the decimalnumbers of Fig. 31.35 and notice that if we apply the DC components of each signal to theintegrator, we get totally different results. In Fig. 31.35 the DC component of the inputhas a decimal value of 0. Applying 0 to our integrator causes the output of the integratorto remain unchanged. In Fig. 31.36 the DC component of the input is the common modevoltage (halfway between the reference voltages) of 10000000. Applying this value to theintegrator results in the integrator's output increasing until the output changes from allones to all zeroes (the output rolls over). Clearly, the binary offset representation hassome practical limitations when used in a digital integrator. To avoid these problems, thebinary offset format is usually converted into the two's complement format prior toapplication to the digital integrator.

In two's complement the left-most bit is the sign bit. A zero represents a positivenumber (except for all zeroes, 00000000, or the common mode voltage) and a onerepresents a negative number (see Fig. 31.37). A binary offset number can be translatedback and forth between a two's complement number by simply complementing the MSB ofthe code (running the MSB through an inverter). For this reason, and others that will bediscussed later (ease of implementing subtraction and no overflow problems), two'scomplement is the preferred format for data words in digital filtering.


time

00000000 (0 V)

11111111 (1.494 V)

10000000 (0.75 V)

Figure 31.36 Representing a sinusoid in binary offset format.

(0)

(128)

(255)

time

10000000 (0 V)

01111111 (1.494 V)

00000000 (0.75 V)

Figure 31.37 Representing a sinusoid in two's complement format.

(+127)

(−128)

VCM + 127 ⋅ VLSB

VCM − 128 ⋅ VLSB

VCM = 0.75

31.2.2 Decimating Filters for ADCs

We saw, from Eq. (31.69), that when we employ averaging in a data converter we have tolimit the input signal bandwidth, B, to the Nyquist frequency, fn , divided by the number ofpoints averaged, K. Knowing this, we may want to lower the rate at which these samplesare coming out of the averaging filter to simplify the circuitry after averaging and to lowerthe power dissipation. Our new, effective sampling frequency is given by

(31.86)f s,new = 2B =f s

K

This reduction in the effective sampling frequency is termed decimation and is illustratedwith the block diagram shown in Fig. 31.38. The term decimation (or decimate) can beconfusing since, among other things, the dictionary definition is, "to select by lot and killone in every ten." The origin of the word comes from a method of punishing militarytroops by selecting one in every ten for execution. Our definition will mean that we arepassing the input word through a low-pass digital filter and then down-sampling the result.This procedure is effectively passing the digital data through an anti-aliasing filter and thenre-sampling the result at a lower rate.

The Accumulate and Dump

In the simplest form we can write the input and output of the decimation filter, in the timedomain, as

(31.87)y[Ki ⋅ Ts] = Σn=K(i−1)

K⋅i−1 x[n ⋅ Ts]K

which is nothing more than averaging K input samples. Before going any further, weshould make sure we understand this equation. Our decimation filter will take K inputsamples, add them together, and then divide the result by K to obtain the average of theinput. If K = 16 and i = 1, then samples through are summed and divided by 16.x[0] x[15]

As we saw in Ex. 31.17, the actual division by K is dependent on the increase inthe number of bits in the output word. For example, if our input word is 8-bits and K = 16then the output word, before dividing by K, is 12-bits (adding 16, 8-bit words, results in a12-bit word). If the ultimate increase in resolution is 2-bits, then the final output word sizeis 10-bits and we throw the lower 2-bits away. This could effectively mean that instead ofdividing by 16, we divide by 4.


In Out

Decimate and average

K

Input word rate, Output word rate,

Figure 31.38 Block diagram of a decimation filter.

f s f s/K

x[nTs] y[Ki ⋅ Ts]

We can re-write Eq. (31.87) in the z-domain (so that we have the z-domainrepresentation for the decimation filter) as

(31.88)H(z) = Y(z)X(z)

= 1K Σ

n=0

K−1

z−n = 1K

(1 + z−1 + z−2 + ... + z1−K)

or

(31.89)H(z) = 1K

⋅ 1 − z−1

1 − z−1⋅ (1 + z−1 + z−2 + ... + z1−K)

or finally, the z-domain transfer function for the decimator (averager), is

(31.90)H(z) = 1K

1 − z−K

1 − z−1

If K = 2 Eq. (31.90) becomes

(31.91)H(z) = 1K

(z + 1)(z − 1)z(z − 1) = 1

K(1 + z−1)

noting that we have already discussed this case, Eq. (31.59), earlier. Note also that thedivision by K may be ignored in this case since, as discussed earlier, the word sizeincreases by one bit when adding the two words. (However, our realized increase inresolution is only 0.5 bits meaning the SNR increases by 3 dB.)

One circuit used to implement Eq. (31.90) is shown in Fig. 31.39 and is called anaccumulate and dump circuit. To understand the operation of this circuit let's assume thebottom set of latches are reset. The sampling clock is used to clock this set of latches Ktimes until the sum of K inputs is accumulated. At this time the accumulated sum isdumped into the output latches. Also, at this time, the bottom set of latches is reset to zeroto start the accumulation process for the next set of K input samples. Note the clock rateon the input of the circuit is fs and the clock rate coming out of the circuit is fs /K.


Figure 31.39 An accumulate-and-dump circuit used for decimation and averaging.

Latches

Latches

Clock,

divide by K

Input, Output,

Reset

Clock

Accumulate the sum in thisset of latches.

Dump the sum intothis set of latches.

Assuming

f s

f s,new = f s/K

x[nTs] y[Ki ⋅ Ts]

K = 8

We can determine the frequency response of the accumulate-and-dump circuit by

setting in Eq. (31.90) orz = ej2π f

fs

(31.92)H( f ) = 1K

⋅ 1 − e −j⋅K⋅2π f

fs

1 − e−j⋅2π⋅ f

fs

= 1K

⋅ 1 − e−j⋅2π f

fs,new

1 − e−j⋅2π⋅ f

fs

or, knowing ,1 − e−jx = (1 − cos x) + j sin x = (1 − cos x)2 + (sinx)2 = 2(1 − cos x)

(31.93)H( f ) = 1K

⋅2(1 − cos K2π f

fs)

2 1 − cos 2π f

fs

= 1K

⋅sin

Kπ f

fs

sin π f

fs

=sinc

Kπ f

fs

sinc π f

fs

We can sketch the frequency response of the accumulate-and-dump averager/decimatorfor different values of K as seen in Fig. 31.40. Note that the accumulate-and-dump circuitaverages K samples while also reducing the output word rate to (decimation). Forf s/K


Figure 31.40 Frequency response of the accumulate and dump for various values of K.

In Out,

Decimate and average

KADCOutAnalog in

Clock in

Clock out,

2

3

z-plane

7

B4

B

Note different scale!

8

B

Note different scale!

1.08

1.7

f s

f s/K

x[nTs]y[Ki ⋅ Ts]

H( f )

f in (Hz)f s/2 3f s/2

H( f )

H(z) = 1 − z−2

1 − z−1

H(z) = 1 − z−4

1 − z−1

H(z) = 1 − z−8

1 − z−1

f s/4 f s/2 3 f s/4

f s/4 3f s/8f s/8

K = 2

K = 4

K = 8

obvious reasons, Eq. (31.93), the frequency response of the accumulate-and-dump circuit,or an averaging filter with the z-domain response given by Eq. (31.90), is sometimescalled a sinc filter.

Example 31.21Determine the pole and zero locations (verify the z-plane plot in Fig. 31.40) for anaveraging filter that averages eight samples.

We can write the z-domain representation of the averager using Eq. (31.90)without the scaling factor K as

H(z) = 1 − z−8

1 − z−1= z8 − 1

z7(z − 1)

or

H(z) =(z − 1)(z + 1)(z − j )(z + j ) z + 1

2 − j ⋅ 12

z + 1

2 + j ⋅ 12

z − 1

2 − j ⋅ 12

z − 1

2 + j ⋅ 12

z7(z − 1)

The general shape of the frequency response of an averaging filter is shown in Fig.31.41. It's desirable to determine the amount of attenuation provided by this filter byspecifying the ratio of the peak value of the main lobe to the peak value of the first sidelobe. If this ratio is large enough, we can limit our concerns to the filter response below

. Also note that the "gain" of the filter K is somewhat irrelevant in a frequencyf s/Kresponse discussion because increasing K simply means our digital word size is increasing.The output of the filter is scaled (divided), as discussed earlier, by some number less thanK to get the final increase in resolution (the final number of bits increase over the inputword size).

The attenuation can be determined using Eq. (31.93) evaluated at as1.5(f s/K)

for (31.94)Main lobeFirst side lobe

= K ⋅ sin

1.5πK

K ≥ 3

This equation is plotted in Fig. 31.42 against averaging factor K. Note how the maximumamount of attenuation, as the number of averages increases, approaches 13.5 dB. This is asignificant limitation and results in the need to cascade averaging filter stages to attain alarge amount of attenuation at frequencies above (more on this topic in a moment).f s/K


Figure 31.41 General frequency response of an averaging filter, Eq. (31.90).

Main lobe

First side lobe

Maximum input signalbandwidth f 2( f s/K)f s/K

H( f )K

3( f s/K)B = 0.5( f s/K)

It's also of interest to determine how much droop the filter will introduce into thesignal frequencies of interest. Figure 31.43 shows the droop (attenuation) at the maximuminput bandwidth, B. We can calculate the amount of droop, again using Eq. (31.93) when

, asf = f s /(2K) = B

(31.95)droop = 1

K ⋅ sin

π2K

It should be obvious that if we desire large amounts of attenuation through ourdigital averaging (sinc) filter, we have severe limitations (only 13.5 dB attenuationmaximum) when using the basic accumulate-and-dump circuit of Fig. 31.39. To increasethe attenuation we might try to cascade accumulate-and-dump circuits as seen in Fig.31.44. This cascade has several practical problems. While the attenuation can be increasedto , where L is the number of stages, the final output sampling frequency dropsL ⋅ 13.5 dBto and the maximum input frequency, B, drops to . To illustrate thef s /KL 0.5f s /KL

limitations imposed by a cascade of accumulate-and-dumps, let's assume we need 60 dB ofattenuation through the filter and our sampling frequency, . If K = 8, thenf s = 100 MHzwe need to cascade five accumulate-and-dump stages. The sampling frequency coming outof the final stage is 3 kHz! The droop at 1.5 kHz (B) remains 3.9 dB. Clearly, cascadingaccumulate-and-dump circuits is not practical for most situations.


Figure 31.42 Averaging filter attenuation versus number of points averaged K.

dB

3 4 6 8 10 K

9

11

1313.5 dB

Main lobeFirst side lobe

Figure 31.43 Droop at edge of signal bandwidth when using an averaging filter.

droop

f

3 4 6 8 10 K

droop, dB

-3.5

-3.6

-3.8

-4.0

H( f )

B = 0.5( f s/K)

K

Averaging without Decimation

The accumulate-and-dump performed averaging and decimation in one stage. In otherwords, for example with K = 4, it summed four input samples, as shown in the sequencebelow, and passed the result to the output:

(31.96)

First output of the accumulate and dump

x(1) + x(2) + x(3) + x(4) +

Second output

x(5) + x(6) + x(7) + x(8) + x(9) + ...

We can get a much more efficient and practical filter if we average the input sampleswithout decimation (sample frequency reduction). The final output clocking frequency(after decimation) can be set to (Eq. [31.69]) and can occur in a stage later in the2Bfilter's construction. The reduction in sampling frequency reduces power and circuitcomplexity (for example, serial multipliers can be used in a digital filter).

Consider the running sum shown belowFirst output of averager

x(1) + x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ...

x(1) +

Second output of averager

x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ...

x(1) + x(2) +

Third output of averager

x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ...

(31.97)x(1) + x(2) + x(3) +

Fourth output of averager

x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ...

It should be obvious that the outputs of the averager occur at the same rate as theaveraging filter's input (no change in the sampling frequency). The z-domainrepresentation of the averager is the same as the accumulate-and-dump's transfer function

y(nTs) = x[nTs] + x[(n − 1)Ts] + x[(n − 2)Ts] + ...K

→ Y(z) = X(z)(1 + z−1 + z−2 + ... + z1−K)K

(31.98)

or, reviewing Eqs. (31.88) and (31.89), results once again in

(31.99)H(z) = 1K

1 − z−K

1 − z−1

where the division by the number of points averaged, K, (K is four in Eq. [31.97]) isperformed by simply adjusting the final word size to the desired length (as discussed


Figure 31.44 Cascading accumulate-and-dump circuits to increase filter attenuation.

Accumulateand dump

Accumulateand dump

Accumulateand dump

In Out

clk clk clkclkfsf s/K fs/K2

f s/K3

earlier and in Ex. 31.17). The transfer function of a cascade of L of these averaging filterscan be written as

(31.100)H(z) =

1K

1 − z−K

1 − z−1

L

or

(31.101)H( f ) =

sinc Kπ f

fs

sinc π f

fs

L

Before we discuss the implementation of the averaging filter (a.k.a. sinc filter), let'sborrow the results from Figs. 31.42 and 31.43 and notice the attenuation for a cascade ofL averaging filters is

for (31.102)Main lobeFirst side lobe

= K ⋅ sin

1.5πK

L

≈ L ⋅ 13 dB K ≥ 8

while the droop, at the maximum input frequency B, is

for (31.103)droop = K ⋅ sin

π

2K

−L

≈ L ⋅ (−3.9) dB K ≥ 8

Also note that Eq. (31.69) is still valid, which means that we don't have a significantrestriction on the maximum allowable input frequency.

To compare the cascade of averaging filters to the limitations imposed by acascade of accumulate-and-dumps as discussed earlier, let's once again assume we need 60dB of attenuation through the averaging filter and our sampling frequency is

. If K = 8, then we need to cascade five averaging filter stages as seen inf s = 100 MHzFig. 31.45. The clock frequency coming out of the final stage is 100 MHz and needs to bereduced to 12.5 MHz in the last stage by simply dividing the clock down before clocking afinal set of latches or by using an accumulate-and-dump for the final stage. The 12.5 MHzoutput rate and 6.25 MHz input frequency bandwidth, B, should be compared to the 3kHz output clock frequency and 1.5 kHz input frequency calculated earlier for the cascadeof accumulate-and-dumps. The droop B remains 19.5 dB and can be a serious concern inmany situations. Obviously, limiting the input bandwidth further reduces the droop at B.Figure 31.46 shows the frequency response of a cascade of averaging filters (the frequencyresponse is given by Eq. [31.101]).


Figure 31.45 Cascading averaging circuits to increase filter attenuation.

OutIn

clk clk

All sections are clocked at 100 MHz.

1 − z−8

1 − z−11 − z−8

1 − z−11 − z−8

1 − z−11 − z−8

1 − z−11 − z−8

1 − z−1

L = 5

Relaxed Requirements Placed on the Anti-Aliasing Filter Revisited

Consider the input, to the ADC, spectrum shown in Fig. 31.47a resulting from passing aninput signal through an anti-aliasing filter (AAF.) The AAF has to remove all spectralcontent above , as we'll show in a moment, to avoid aliasing when using a digitalf s − f s/Kaveraging filter (with spectral response shown in Fig. 31.46). On the output of the ADC,after sampling and aliasing, the characteristics of the signal are shown in Figs. 31.47b andc. In Fig. 31.47b we show the individual reproductions of the original base spectrum. In(c) we combine the spectrums to show the continuous ADC output spectrum and includea sketch of the digital filter frequency response. From Fig. 31.47c we should see why the


Figure 31.46 General frequency response of an averaging filter, Eq. (31.101).

f 2( f s/K)f s/K

H( f )

KL

3( f s/K)

B = 0.5( f s/K)

Figure 31.47 How a digital (averaging) filter helps remove aliased spectral components.

f

(a) Input spectrum to the ADC.

In

f

(b) Output spectrum of the ADC with aliasing.

ADC, out

f

ADC, out

(c) Same as (b) except showing a continuous

ADC, out

f

ADC, out

spectrum. Thin line is digital filter response.(d) Output of the digital filter after removing

Filter out

f

aliased components.

digital filterresponse

f s − f s/K

B = f s/(2K)

f s − f s/Kfs/(2K)

f s

f s/(2K) f s − f s/K

fs/K

fs/(2K) f s − f s/K

fs

fs/K

L ⋅ 3.9 dB

L ⋅ 13 dB

fs/K

fs/(2K)

AAF has to limit the ADC input spectral content to . At the output of thef − f s/K fs/Kdigital filter goes to zero. This assumes the first side lobe, in the digital filter, is sufficientlysmall so that the amount of aliasing past fs /K is negligible. In many systems that employ adigital signal processor, an additional abrupt cutoff low pass digital filter is used after theaveraging and decimation process to provide additional alias signal removal.

Note, in Fig. 31.47d the output of the digital filter, as mentioned earlier, has aperiodic frequency response (and so the spectrum out of the digital filter will still havealiased components but hopefully not in the base spectrum). As a further example of theperiodic nature of all digital filters, consider the averaging filter frequency responseK = 8shown in Fig. 31.48 (see Fig. 31.40 for a comparison). Note that the number of points inthe frequency response between DC and that go to zero (the number of zeroes in thef s

transfer function) is seven (since the zero at DC is canceled by the pole at DC [ ].)z = 1

Implementing Averaging Filters

If not careful, the averaging filter can take up a large amount of chip area. In this sectionwe discuss how to implement an averaging filter with a response given by Eqs. (31.100)and (31.101). To begin, let's break the averaging filter up into two parts, without includingthe scaling factor K,

(31.104)H(z) =

1 − z−K

1 − z−1

L

=

L differentiators

(1 − z−K)L ⋅

L integrators

11 − z−1

L

We have already looked at the transfer function of an integrator in Ex. 31.20. An alternatedigital integrator design is shown in Fig. 31.49. The only difference between the circuit ofFig. 31.49 and Fig. 31.33 is the change in the phase response of the circuit.


Figure 31.48 The periodic nature of a K = 8 averaging filter.

8

B

H(z) = 1 − z−8

1 − z−1

f s/4

3f s/8f s/8

f s/2

f s 2f s

H( f )K = 8

Figure 31.49 Alternate digital integrator.

Y(z)X(z)z−1

Y(z) = [Y(z) + X(z)]z−1

H(z) = Y(z)X(z)

= z−1

1 − z−1

y(nTs) = y[(n − 1)Ts] + x[(n − 1)Ts]

The z-domain representation and schematic of a differentiator are shown in Fig.31.50. Note the use of subtraction in the differentiator. The time domain description of adigital differentiator is given by

(31.105)y[nTs] = x[nTs] − x[(n − 1)Ts]

and the z-domain transfer function is given by

(31.106)H(z) = Y(z)X(z)

= (1 − z−1)

The frequency response of the differentiator is (see Fig. 31.51)

(31.107)H( f ) = 2 1 − cos 2π

ff s

and the phase response is

for (31.108)∠ H( f ) = π2

− πff s

0 < f < fs

Again, like all of the digital filters we have discussed in this chapter, the phase response islinear (constant delay meaning no phase distortion). Also note, assuming two'scomplement number representation is used for the I/O in the differentiator, thatsubtraction of two numbers, , can be accomplished by using an adder with the BA − Binput complimented (run through inverters) prior to application to the adder and the addercarry-in tied to a logic one.


Figure 31.50 Block diagram of a digital differentiator.

LatchesClock

x[nTs]

x[(n − 1)Ts]

y[nTs] Y(z)X(z)

z−1X(z)z−1

Figure 31.51 Magnitude and phase response of digital differentiator.

2

degrees

90

-90f (Hz)f s/2 3f s/2f s/4 f s f s/2 3f s/2

H( f )∠ H( f )

2

f (Hz)

H(z) = (1 − z−1) = z − 1z

H(z) = (1 − z−1)

Next consider the digital comb filter (or differentiator over a range of frequencies)circuit shown in Fig. 31.52. We should recognize this circuit's transfer function from Eq.(31.104) as

H(z) = 1 − z−K = zK − 1zk

with a magnitude response given by

H( f ) = 2 1 − cos 2πK

ffs

Figure 31.53 shows the z-plane and frequency responses for comb filters withvarious values of comb filter delays K. Before we proceed with the implementation of theaveraging filter defined by Eq. (31.104), let's discuss, intuitively, how we take the basicdigital comb filter and make a low-pass, averaging filter. Remember that we evaluate

around the unit circle, in the z-plane, to determine . If we look at Fig. 31.40,1 − z−K H( f )we see that the only difference between a comb filter and a low-pass averaging filter is thefact that we have added a pole to the transfer function at DC (i.e. z = 1) to cancel the zeroat DC. This is important as we will be able to make high-pass and band-pass averagingcircuits by taking a comb filter and canceling the zeroes placed at other points on the unitcircle. We'll discuss this in more detail in the next two sections. Note that by using Eqs.(31.79) and (31.80), we should be able to see why canceling a zero with a pole at DCresults in an a low-pass filter.

The comb filter of Fig. 31.52, or the differentiator of Fig. 31.50, is an example of afinite impulse response (FIR) digital filter. Applying a unit amplitude impulse to the inputof the comb filter, and zeroes at all other times, will cause the output of the comb filter togo to a one at the moment the impulse is applied and seconds later, and a zero atKTs

other times. In other words, the output response of the filter has a finite duration.

The integrator (sometimes called an accumulator) shown in Fig. 31.34 is anexample of an infinite impulse response (IIR) digital filter. Applying a unit amplitudeimpulse to the input of the digital integrator, with zeroes the remaining times, causes theoutput of the integrator to increase to one and remain at one indefinitely. In other words,the output response of the integrator is of infinite duration.


Figure 31.52 Block diagram of a digital comb filter.

Clock

D Q

clk

D Q

clk

D Q

clk

x[nTs]

x[(n − K)Ts]

y[nTs] Y(z)X(z)

z−KX(z)z−KK Latches

H(z) = 1 − z−K = zK − 1zk

fs

Eq. (31.104) can be implemented by cascading L integrators and L comb(differentiators) filters as shown in Fig. 31.54. As we discussed earlier, the integratorshave "infinite" gain at DC, which can result in register overflow. However, if we use two'scomplement number representation, we'll see that we get the correct answer out of thefilter as long as the word length used to implement the filter is long enough (using two'scomplement will avoid overflow problems).

Example 31.22Consider an averaging filter (Eq. 31.104) using L = 3 and K = 8 with an inputword length of 8-bits. Determine the final number of bits coming out of the filterand show that a constant input of 01110000 (+112 two's complement) results inthe correct output code. Also, discuss overflow concerns.


Figure 31.53 Frequency response and z-plane plots for various values of K in a comb filter.

z-plane2

3

z-plane2

3

z-plane2

4

z-plane2

z-plane2

16

z-plane2

f (Hz)f sf s/3

H( f )

2f s/3

K = 3

f (Hz)f sf s/2

H( f )

3f s/4

K = 4

f s/4

f (Hz)f sf s/2

H( f )

3f s/4

K = 16

f s/4

H(z) = 1 − z−K = zK − 1zk

H(z) = 1 − z−3

H(z) = 1 − z−4

H(z) = 1 − z−16

f s/16 15 f s/16

In Out

Figure 31.54 Implementation of an averaging filter using integrators and comb filters.

All sections clocked at the same rate.

11 − z−1

11 − z−1

11 − z−1

L integrators

1 − z−K 1 − z−K 1 − z−K

L comb filters

From Eq. (31.53) we can calculate an increase in resolution of 1.5 bits so the finaloutput word size should be 10 bits (the original 8-bits input plus an additional 1.5bits from averaging 8 samples.)

The "gain" of the filter at DC is, from Fig. 31.46, . This means thatKL = 512our 8-bit input of 112 (0111 0000) will be multiplied by 512 and result in anoutput, prior to scaling, of 57344, or a binary code of 0 1110 0000 0000 0000 (17bits in the general case). From Eq. (31.101) we would then divide this code by 512(drop the lower 9-bits.) However, this would result in an output word size equal tothe input word size (both 8-bits and no increase in resolution). So, for the generalinput signal that is time-varying and to get the final ten bits, we divide the 17-bitfilter output by 128 (drop the lower 7-bits so our final output is 10-bits or 01 11000000 [448 = since 10-bits].) A block diagram of the filter implementation4 ⋅ 112is shown in Fig. 31.55. A MUX is needed in between each integrator stage toadjust the two's complement word size up by bits (see first stage.)log2K

Let's discuss overflow concerns. To keep the discussion simple, let's justconsider a single integrator and comb filter stage, that is, L = 1. A constant two'scomplement, 8-bit, input of 0111 0000 (+112) into the integrator will result in anoutput, assuming we start with all zeroes, of

Output (Sum0) 000 0000 0000 0 (or [two's complement])VCMInput1 000 0111 0000 112 Sum1 000 0111 0000 112


Figure 31.55 Block diagram of the filter discussed in Ex. 31.22.

ADC

8-bits Binary Offset 1111 0000

MSB

11

11

14

17

D Q

clk

D Q

clk

D Q

clk

17

8 registers

17 17 17

Drop lower 7-bits.(To change to binaryoffset complementthe MSB.)

Out, 10-bits

In, 8

Use inverter forsubtraction in two'scomplement

17

17

17

1

Carryin

Word size increases 7

MUX10

00001111

select

000 0111 0000 (filter input)Two's complement, 11-bit,

integrator stage.

11

Add MUX here11 − z−1

11 − z−1

11 − z−1

1 − z−8

1 − z−8 1 − z−8

log2K bits in each

z−1

Input2 000 0111 0000 112Sum2 000 1110 0000 224

or since the input is a constant 000 0111 0000 (112)Sum3 001 0101 0000 336Sum4 001 1100 0000 448Sum5 010 0011 0000 560Sum6 010 1010 0000 672 Sum7 011 0001 0000 784 Sum8 011 1000 0000 896 Sum9 011 1111 0000 1008Sum10 100 0110 0000 1120 Sum11 100 1101 0000 1232 Sum12 101 0100 0000 1344 Sum13 101 1011 0000 1456 Sum14 110 0010 0000 1568 Sum15 110 1001 0000 1680 Sum16 111 0000 0000 1792 Sum17 111 0111 0000 1904 Sum18 111 1110 0000 2016 Sum19 000 0101 0000 80 Overflow!Sum20 000 1010 0000 192

These sums are applied to our comb filter. Since K = 8, we won't have ameaningful comb filter output until our ninth integrator output. At this time theoutput of the comb filter will be the difference between Sum1 and Sum9, that is,Sum9 − Sum1. The ninth integrator output is 1008 while the first is 112. Thedifference being 896 (011 1000 0000 or since 11-bits). In fact, we can take8 ⋅ 112any difference between sums spaced 8 clock cycles apart, even after overflow, andget this result (looking only at the lower 11-bits.) For example, Sum18 − Sum10 is

Sum18 111 1110 0000 (2016) minus Sum10 100 0110 0000 (1120)

(896)

In two's complement, for subtraction, we complement, and add one (set the addercarry-in bit high) to the number we are subtracting, which results, for this example,in

Sum18 111 1110 0000Sum10(comp) 011 1001 1111 plus 1 (adder carry)

011 1000 0000 (896)

noting that we threw out the 12th bit in the sum. As a final example,

Sum19 000 0101 0000 (80) or Sum19 000 0101 0000minus Sum11 100 1101 0000 (1232) or Sum11(comp) 011 0010 1111

difference (-1152 or 896) plus 1011 1000 0000 (896)

While this last discussion focused on L = 1, we could use any number of stages aslong as the register size in our integrators can accommodate a binary number of atleast , where N is the number of bits in the input word. K ⋅ 2N


We might notice from this example that the amount of hardware needed toimplement the averaging filter is significant. The main contributor to the final filter layoutsize is the registers used in the comb filters (a total of twenty-four 17-bit registers areused.) It turns out, as discussed earlier, that we can use the reduction in clock frequency(decimation) to reduce the number of registers used in the comb filter, Fig. 31.56. Bydividing the clock frequency down by K, we can reduce the number of registers used ineach comb filter to one. In either Fig. 31.54 or Fig. 31.56 the delay used in the comb filteris KTs. Figure 31.56 is the preferable way to implement decimation/averaging filters(however, see aliasing description below for practical implementation concerns).

Aliasing Concerns when using Decimation

While we are used to discussing aliasing concerns when sampling an analog waveform, wecan also discuss aliasing when (re-) sampling a digital waveform. Reducing the samplingor clocking frequency (decimation) can be thought of as re-sampling a digital waveform ata lower rate, Fig. 31.57. In Fig. 31.57 the averaging filter can be thought of as theanti-aliasing filter with non-zero spectral content up to (assuming the side lobes aref s/Ksufficiently below the main lobe), while the set of latches, on the output, can be thought ofas the sampler.

Figure 31.58a shows the output spectrum of the averaging filter (see, also, Fig.31.47) assuming the side lobes are sufficiently small so that they are not a concern. If were-sample this signal at , we get the spectrum shown in Fig. 31.58b. The resultingf s/Kspectrum shows a problem (aliasing in the base spectrum) that would be encounteredusing the filter of Fig. 31.56 unless our input signal bandwidth, B, is limited, using ananalog anti-aliasing filter or a separate digital filter, to . Because, as discussed earlierf s/2K


In

Out

Figure 31.56 Using a reduction in clock frequency to lower complexity in averaging filters.

clock

clock

Note the use of one register

Transfer function of decimating and averaging filter

K

Decimate and Average(schematic symbol)

In Out

(Important: See aliasing discussion below.)

11 − z−1

11 − z−1

11 − z−1

L integrators

1 − z−1 1 − z−1 1 − z−1

L comb filters

÷ K

fs/K

fs

1 − z−K

1 − z−1

L

(Fig. 31.47), we can use the averaging filter for additional aliased signal removal. Whilewe may only be interested in signal content up to B (Eq. [31.69]), we can still haveunwanted signal content between B and that will alias in the base spectrum, it isf s/Kdesirable to eliminate the problem all together. We can do this by resampling at .2(f s/K)The averaging/decimation filter shown in Fig. 31.56 is changed so that the divider divides


Figure 31.58 Showing signal spectrum prior to decimation (a) and after (b) and (c).

f

Averaging filter output spectrum

(a)

f

Output spectrum after re-sampling at

(b)

f

Output spectrum after re-sampling at

(c)

Figure 31.57 Re-sampling a digital waveform.

In

Digital Averaging Filter

D Qclk

Out

clock Clock Out

Used for sample rate reduction.

f s ÷ Kfs/K

fs/8 3f s/8 5f s/8

f s/2 f sf s/4 3f s/4

7f s/8

f s/2 f sf s/4 3f s/4

f s/2 f s

Assuming K = 8

f s/K

fs/K (= 2B = f s/8 here).

Throw out K − 1 samples

2( f s/K) = f s/(K/2) (= 4B = f s/4 here.)

f s/K = 2B

by . And by adding a register to the comb filter the comb filters are . TheK/2 1 − z−2

resulting spectrum is shown in Fig. 31.58c. Note that aliasing is a very important concernwhen designing the averaging filter.

If the first side lobe amplitude isn't sufficiently small, as was assumed in Fig. 31.58,a larger re-sampling frequency or decimation frequency can be used to minimize aliasing.A common intermediate clocking frequency is . A sample averaging filter output4 ⋅ (f s/K)waveform is shown in Fig. 31.59a, where the side lobe amplitude is no longer insignificant.Figure 31.59b shows the spectrum, assuming K = 8 and the re-sampling frequency is

(meaning the divider in Fig. 31.56 is and each comb filter stagef s/2 (= 4 ⋅ [ f s/8]) f s/(K/4)uses four registers ). Note how the third side lobe is aliased into the base[1 − z−4]spectrum in this example, while the first side lobe was aliased into the base spectrum inFig. 31.58c (although it was not shown in the figure). Figure 31.60 shows that the ratio ofthe main lobe to the third side lobe is approximately 20 dB (assuming K .) The possible≥ 8large amount of baseband aliasing together with the droop at B may result in the desiredinput bandwidth, B, being limited to frequencies below with an the externalf s/(2K)analog AAF or an additional digital filter (more on this in a moment). Finally, notice thatat DC (or very low frequencies) in Figs. 31.58b, 31.58c or 31.59b there is essentially noaliased signal. This is the result of the zeroes in the averaging filter transfer function, Eq.(31.99), falling at multiples of the decimation frequency.

A Note Concerning Stability

Consider the weighted integrating filter block diagram shown in Fig. 31.61. The output ofthe circuit is fed back to the input after it is multiplied by a. Multiplication by a may beperformed with a dedicated multiplier or it may simply be a shift operation (multiplying by


f

(a)

Averaging spectrum with significant side lobes.

f

Spectrum after decimation.

Figure 31.59 Showing signal spectrum with significant side lobes (a) prior to decimation (b) and after decimation.

Third sidelobe aliasedin the basespectrum

(b)

f s/2 f sf s/8

f s/2 f sf s/8

4(f s/K) = f s/2 = 8B

Assuming K = 8

0.5 is simply a shift-right operation). The output of the circuit, in the time-domain, may bewritten as

(31.109)y[nTs] = x[(n − 1)Ts] + a ⋅ y[(n − 1)Ts]

or

, (31.110)y[nTs] = x[(n − 1)Ts] + a ⋅ x[(n − 2)Ts] + a2 ⋅ x[(n − 3)Ts] + a3 ⋅ x[(n − 4)Ts] + ...

which will obviously blow-up if . a > 1

The z-domain representation of Eq. (31.109) is

(31.111)H(z) = 1z − a

Figure 31.62 shows the z-plane and magnitude plots specified by this equation. If a > 1H(z) becomes unstable, so for a stable system we must require our poles to reside withinthe unit circle. There are no restrictions on the location of zeroes.) This sounds simpleenough; however, notice that we have, in most of the previously discussed digital filters,placed poles right on the unit circle. If there is rounding in our digital numbers, we couldbe faced with an unstable digital filter. This would be a very common occurrence, in adigital filter implemented using software, if care was not taken to avoid rounding errors.Since we use integer numbers in our hardware implementations, instability shouldn't be aproblem unless we start to try to round numbers to decrease hardware complexity(performing divisions or multiplications) without being careful.


Figure 31.60 Decimating at four times the Nyquist rate. Showing (aliased) third side lobe.

f

Droop

2( f s/K)f s/K

H( f )

KL

3( f s/K)B = 0.5( f s/K)

L ⋅ 3.9 dB≈ L ⋅ 20 dB

(7/2)( f s/K)

Figure 31.61 A weighted integrating filter.

a

Y(z)X(z)z−1

Y(z) = [aY(z) + X(z)]z−1

H(z) = Y(z)X(z)

= z−1

1 − a ⋅ z−1

y(nTs) = a ⋅ y[(n − 1)Ts] + x[(n − 1)Ts]

Decimating Down to 2B

In many situations (for example, we want to transmit the modulator output) it is desirableto reduce the clocking frequency down to twice the Nyquist frequency. Since the Nyquistfrequency for our input bandwidth B is , our final output clocking frequencyf s/(2K)would be . As we have just discussed this further, or second stage, decimationf s/K = 2Bcan result in significant aliasing. To eliminate this aliasing, a digital filter is often used tolimit the bandwidth, after the first stage decimation, to (= B). Before we proceedf s/(2K)any further, let's summarize the discussion so far for the different situations.

1. The input, to the ADC, is band-limited to B . In this situation we can[= f s/(2K)]use the topology of Fig. 31.56 directly, decimating the sampling clock from fs to fs /K inone stage. The comb filters use one register. The smallest size averaging/decimation filterresults in this situation and the output clock rate is 2B.

2. The input, to the ADC, is band-limited to 2B . In this situation the(= f s/K)averaging filter provides some aliased signal removal, see Fig. 31.47. Assuming the aliasedsignal content in the first side lobe is insignificant, we can use the topology of Fig. 31.56with a divider of and two registers in each comb filter; that is, each comb filter has a(K/2)transfer function of . The sampling clock gets reduced from fs to fs /(K/2). The1 − z−2

output clocking rate is now 4B.

3. The input, to the ADC, is band-limited to the Nyquist frequency fs /2 (thegeneral situation where the analog AAF has the most relaxed requirements). In thissituation the averaging filter will again provide some aliased signal removal. We can usethe topology of Fig. 31.56 with a divider of and four registers in each comb filter,(K/4)that is, each comb filter has a transfer function of . The sampling clock gets reduced1 − z−4

from fs to fs/(K/4) and the output clock rate is 8B.


z-plane

Figure 31.62 The z-plane representation and magnitude responsefor a weighted integrating filter.

a

f

H(z) = z−1

1 − az−1= 1

z − a

fs/2 3f s/2f s

H( f )1

1 − a

11 + a

4. Figure 31.63 shows the entire system for case 3, above, with the addition of adigital filter on the output of the first stage decimation for reducing the sampling, oroutput clocking frequency, to 2B. The digital filter used in the second decimation stage isgenerally a half-band digital filter (covered in most books on digital filtering.) Half-bandfilters are used because of the simplicity of their implementation (half of the filter'scoefficient are zero) and the fact that the filter's transition frequency is symmetric aroundits clocking frequency divided by four (which we can use, with a divider or using two,cascaded, half-band filters, to set the filter's cutoff frequency to B when the clockingfrequency is ). 4[ f s/K] = 8B

Figure 31.64 shows the spectrum of the signals in Fig. 31.63 for the generalsituation. Part 31.64a of the figure is the AAF input, which we have drawn with anarbitrary shape. In 31.64b we see that the AAF limits the input signal spectrum to f s/2(and we should see, once again, the relaxed requirements placed on the AAF when usingoversampling). Figure 31.64c shows the ADC's output spectrum resulting from samplingthe input waveform (actually the output of the AAF.) After first stage decimation, 31.64d,the signal is passed through a sinc (averaging) filter and then resampled at (4(f s/K) = f s/2when K = 8). Figure 31.64e shows the output of the half-band filter prior todown-sampling (second stage decimation.) The figure assumes the half-band filter isclocked with an effective clock frequency of 4B (the actual clock frequency is 8B asdiscussed above) or . So the filter's cutoff frequency is B. The half-band filter's4[ f s/(K/4)]implementation may also use the high frequency clock signal to simplify the filter'simplementation. Finally, 31.64f shows the spectrum resulting after final decimation. Theclock frequency out of the final stage is 2B, while the desired signal bandwidth is B.

It's important to remember that unless there is some reason to lower the clockfrequency (for example, we want to store the ADC/averaging filter's digital output inmemory), we can avoid the aliasing problems associated with decimation (see Fig. 31.58)and the added complexity. Also note that the desired spectrum of Fig. 31.64e mustultimately be reconstructed using a DAC and a reconstruction filter (RCF). Because of theunwanted spectral content, directly adjacent to the desired content the reconstructionbecomes more challenging when decimating down to 2B.


Analog in, AAF ADC

Limits input frequency content to

Clock in,

clk D Q

Out

Figure 31.63 General averaging and decimation topology for an oversampled ADC.

Higher frequency clock can be usedin the digital filter to simplify circuitry

First stage decimation Second stage decimation

Clk

digitalfilter

Fig. 31.64(a) (b) (c) (d) (e) (f)

f s/2

f s

f in

÷ K/4 ÷ 4

11 − z−1

L[1 − z−4] L

fs/K = 2B

31.2.3 Interpolating Filters for DACs

In the last section we discussed how we were able to average the outputs of a lowerresolution ADC with an averaging filter to increase the effective ADC resolution, Fig.31.40. In this section we discuss how to interpolate between adjacent digital DAC inputwords to attain a large effective output resolution while reducing the required resolutionof the DAC, Fig. 31.65. (To interpolate is to estimate a value between two known values)We use the same symbols and terminology of the last section in this section.


2B f

f

Figure 31.64 Spectrums of the resulting signals for the decimation scheme shown in Fig. 31.63.

Input signal spectrum

f

Spectrum after AAF

f

B

f

ADC output

After first stage decimation

(a)

(b)

(c)

(d)

(e)

After passing through half-band filter4 B

f

(f)

After second stage decimation down to

BDesired signal spectrum.

f s/2 f s Assuming K = 88B = f s/2

In

Interpolate and introduce

K DACOutDigital in

Clock in

RCFAnalog out

Figure 31.65 Block diagram of a DAC that uses interpolation to increase effective DACresolution.

additional digital words.

Interpolation Filter

Reconstructionfilter

f s

N + NInc

N bitsx[Ki ⋅ Ts]

y[nTs]

Also, as in the last section, Bennett's criteria must be valid. In particular, the digitalword must be busy and the DAC must be linear to the final desired resolution (that is, theN-bit DAC must be linear to N + NInc).

The Dump and Interpolate

Figure 31.66 shows the basic idea of introducing digital words in between the wordscoming into the interpolation circuit of Fig. 31.65. The inputs to the interpolating filter areindicated by the thicker lines in the figure. The interpolator introduces additional samplesin between these inputs. If the frequency of the input samples is 2B then the frequency ofthe samples coming out of the interpolator is

(31.112)f s = K ⋅ 2B

noting that, since we are using the same notation as used in the last section, the rate ofwords being clocking into the DAC is the same as the rate at which the ADC was( f s)clocked in the last section.

If the inputs to the interpolator are and the outputs of the interpolatorx[Ki ⋅ Ts]are we can write y[nTs]

(31.113)y[n ⋅ Ts] = x[K(i − 1) ⋅ Ts] + Σn=K(i−1)

K⋅i−1

[n − K(i − 1)] ⋅ x[Ki ⋅ Ts] − x[K(i − 1) ⋅ Ts]K

to describe the operation of the interpolator. Rewriting this equation to show only thechange between adjacent outputs results in

(31.114)y[n ⋅ Ts] − y[(n − 1) ⋅ Ts] = x[Ki ⋅ Ts] − x[K(i − 1) ⋅ Ts]K

Taking the z-transform of this equation results in

(31.115)Y(z)(1 − z−1) = X(z) ⋅ 1 − z−K

K

or

(31.116)H(z) = Y(z)X(z)

= 1K

1 − z−K

1 − z−1


Figure 31.66 How the interpolation circuit increases the sample rate while introducing samples in between the existing samples.

time

Digital wordsinput to DAC

Interpolator inputs

Interpolator adds these digital words(adds K − 1 samples)

which is the familiar transfer function for our averager presented in the last section. Theimplementation of our interpolator, termed a Dump and Interpolate, is shown in Fig.31.67. The input words are dumped into latches which serve two purposes: 1) to storetwo consecutive, slow input words for generation of the incremental change in the fastoutput samples and 2) to pass the interpolator input words directly to the output, throughthe multiplexer (MUX), every K clock cycles. The is implemented simply by removing÷ Kthe lower bits of the adders output word. As we saw with the accumulate-and-dumpcircuit, this implementation has practical problems that result in the need to use otherimplementations (which we'll discuss next.)

Practical Implementations of Interpolators

We can demonstrate the implementation of interpolating filters for reducing therequirements placed on the resolution of the DAC by considering the four basic casesdiscussed in the last section concerning the spectral content of the input signals (which arenow digital signals, that is, in the last section our input signal to the ADC was analog,while in this section the input to the interpolating filter is digital.)

1. The input signal bandwidth is limited to B and is clocked at 2B. In[= f s/(2K)]this case we can perform the interpolation in one stage as seen in Fig. 31.68. Note how wehave, when compared to Fig. 31.56, switched the order of the integrators and the combfilters. We are still using the slower clock, , to generate the delay in the combf s/K K ⋅ Ts

filters. The rate at which the words are coming out of the interpolator is iff s (= 16B. The word size coming out of the comb filters is the same as the input word size,K = 8)

that is, . The word size increases as we move through the integrators, as we sawN + NInc

in Ex. 31.22. The word size coming out of the final integrating stage, prior to dropping thelower bits, is . The digital bits we connect to the DAC are the MSBsN + NInc + L ⋅ log2Kof this word, where the lower bits are dropped.NInc + L ⋅ log2K


divide by K

Figure 31.67 A dump-and-interpolate circuit used for interpolation and reverse averaging.

Latches Latches

Clock,

Input,

Output,

Dump input into these latchesInterpolate the additional values using latches and adder.

Clock,

Latches

LatchesMUX

f s

f s/K

x[Ki ⋅ Ts]

y[nTs]

÷ K2. The input to the interpolator/DAC has the spectrum shown in Fig. 31.58c and is

clocked at 4B. The interpolating filter has the same topology shown in Fig. 31.68 exceptthat two registers are used in the comb filter and the divider is changed to Again, theK/2.DAC is clocked at fs. The reconstruction filter together with the sinc filter used in theinterpolator limits the output spectral content.

3. The input to the interpolator/DAC has the spectrum shown in Fig. 31.59b and isclocked at 8B. The interpolating filter has the same topology as the one shown in Fig.31.68 except that four registers are used in the comb filter (see Fig. 31.63) and the divideris changed to Again, the DAC is clocked at fs. The reconstruction filter together withK/4.the sinc filter used in the interpolator limit the output spectral content.

4. Our input spectrum is shown in Fig. 31.64f and clocked into the interpolationfilter at 2B (the general situation that results in the most relaxed requirements on thereconstruction filter). The basic, general interpolation structure is shown in Fig. 31.69.Figure 31.70 shows the spectrums at various points in this circuit. The input spectrum tothe interpolation circuit is shown in Fig. 31.70a. This input is connected to a set of latchesclocked at 2B. The output of these latches is connected to the digital filter, which clocksthe values in at 8B and has a response, as seen in Fig. 31.70b. We need to understandwhat's happening at this point. If we look at the output register used in Fig. 31.63, we see


L comb filters

In

clk

clock

Output to DAC

L integrators

Clock to DAC

Figure 31.68 Implementation of a single stage interpolation filter. See Fig. 31.55for handling the word size increase in the integrators.

(1 − z−1)L

÷ Kfs/K

N + Ninc bits

N + Ninc

fs

11 − z−1

L

Drop all but N MSB bits

N + Ninc + L ⋅ log2K bits

Analog

RCFDACclk

D QIn

Figure 31.69 General interpolation and reverse averaging topology for an oversampled DAC.

First stage interpolation Second stage interpolation

Clock,

digitalfilter

Out

(a) (c) (d) (e)(b)

f s

4( f s/K) = 8B÷ K/4

11 − z−1

L

[1 − z−4] L

fs/K = 2B÷ 4

that we were only saving one out of every four samples coming out of the digital filter. InFig. 31.69 we are "estimating" these samples by simply clocking each input value fourtimes into the digital filter. Figure 31.71 shows the situation in more detail. It is desirableto determine how this input hold register affects the spectrum of the input signal. We canrelate the input of the register (a set of latches) to the register's output using

(31.117)y[nTs] = Σn=4(i−1)

4⋅i−1 x[4(i − 1) ⋅ Ts]4

If we look at the change between adjacent outputs we get

where (31.118)y[n ⋅ Ts] − y[(n − 1) ⋅ Ts] = x[4i ⋅ Ts] − x[4(i − 1) ⋅ Ts] n = 4(i − 1)

which results in a transfer function of

(a sinc filter) (31.119)H(z) = 1 − z−4

1 − z−1

Since we are only looking at one out of every four pairs of possible samples, set by therequirement that (where n and i are both integers), the value of the transfern = 4(i − 1)function will actually be 1/4 of Eq. (31.119).


B

Figure 31.70 Spectrums of the resulting signals for the interpolation scheme shown in Fig. 31.69.

f

(a)

B

f

(b)

B 4 B

Input Nyquist rate

Nyquist rate after re-sampling

f

(c)

B 4 B

f

(d)

After passing through half-band filter

After passing through second stage interpolator filter

Nyquist rate after re-samplingDesired signal spectrum.

f

(e)

3

RCF reponse eliminates all unwanted spectral contentRCF response may leave some unwanted spectral content

Sinc response

Input holding register sinc response

f s/2 = 8B here f s Assuming K = 8

In the general interpolation scheme discussed in most digital signal processingbooks, zeroes, that is digital words with a value of zero, are used for the extra valueswhen interpolating (increasing the sampling frequency). This is commonly known aszeroes padding the input waveform. Adding zero values into a waveform results inX − 1an effective reduction in the input waveform's amplitude by X. This is easy to understand ifwe think of a DC input of 1 and then add three adjacent zeroes. The resulting waveformwill now have an average value of 0.25. The reduction in amplitude can be compensatedfor by multiplying the input by four, in this example, which is simply a shift left two times.Here, in Fig. 31.69, we are avoiding the amplitude reduction by simply clocking the sameinput value four times (here ). The drawback, as discussed above, is the added sincX = 4response in the signal path.

Figure 31.70c shows the output of the digital filter which, again, is generally (butnot necessarily) implemented using a half-band digital filter. At this point the digital wordsize is essentially the same size as the input word size. After passing through the sinc filter,the word size and word rate (frequency) increases, as indicated in Fig. 31.68 and Ex.31.22, with a resulting attenuation of the images in the spectrum, Fig. 31.70d. Note howthe first side lobe amplitude affects the amount of residual spectral content from theimages at 4B. Finally, the reconstruction filter, RCF, attenuates the remaining unwantedspectral content.

The RCF deserves additional comment. Figure 31.70e shows two RCF responses.In one case the RCF limits the spectral content to 3B. This results in elimination of anyunwanted spectral content at the cost of a complex analog filter implementation. In thesecond case the RCF limits the spectral content to (the same response as the AAF).f s/2While resulting in a simpler filter, the spectrum still contains unwanted spectral content, inaddition to the desired content between DC and B, as shown in Fig. 31.70e. The actualRCF used depends on the application. The point here is that the design of the RCF can bemore challenging than the design of the AAF in a mixed-signal system.


In

Figure 31.71 Showing effects of digital filter input holding register on the input data.

clk D Q

Digital filterOut

t

clk D Q

In

same signal In,

t

Out,Filter input holding register

4( f s/K) = 8Bfs/K = 2B ÷ 4

x[4i ⋅ Ts]

x[4i ⋅ Ts]

y[nTs]

y[nTs]

nTs

4iTs

31.2.4 Bandpass and Highpass Sinc Filters

There are many situations, especially in communication systems, where we may want toperform data conversion on a range of frequencies that doesn't extend from DC to B, ashas been assumed in this book up until this point. Bandpass ADCs and DACs, forexample, are becoming popular in radio communication systems. In this section, weintroduce bandpass and highpass averaging sinc-shaped filters.

Canceling Zeroes to Create Highpass and Bandpass Filters

As we saw in Fig. 31.40, we can generate a lowpass filter by canceling the zero at DC in acomb filter, see also Eq. (31.79) for an intuitive explanation of the lowpass frequencyresponse. We can generate a highpass filter by canceling a comb filter zero at , as seenf s/2in the example shown in Fig. 31.72 with K = 8. The same equations, Eqs. (31.94) and(31.95), can be used to describe the behavior of this filter where, in the highpass response,the main lobe has shifted to . Also, when looking at Fig. 31.72, remember that thef s/2frequency response of a digital filter is periodic with period fs.

We can generate a bandpass filter by canceling the zeroes at and , orf s/4 3f s/4some other frequencies, using a digital resonator. The general topology of the bandpassdigital filter is shown in Fig. 31.73. Keeping in mind that the digital resonator is used tocancel the zeroes of the comb filter we can write

HD(z) = 1

1 − 2 cos 2π f

fs ⋅ z−1 + z−2

= z2

z2 − 2 cos 2π f

fs ⋅ z1 + 1

= z2

z − e+j⋅2π f

fs

z − e−j⋅2π f

fs

(31.120)


Figure 31.72 A highpass filter implementation using a comb filter.

7

f

8

DC

1 − z−8

1 + z−1= z8 − 1

z7(z + 1)

f s/2 f s

3f s/8f s/4 f s/2

Comb filter Digital resonator

In Out

Figure 31.73 Implementing a sinc bandpass filter.

1 − z−K1

1 − 2 cos 2π f

fs ⋅ z−1 + z−2

The time-domain representation of this equation is

(31.121)y[nTs] = 2 cos 2π

ff s

⋅ y[(n − 1)Ts] − y[(n − 2)Ts] + x[nTs]

It's desirable to determine at which frequencies the cosine term is an integer, a zero, or avalue that results in a trivial multiplication, that is, a shift so that we can implement thebandpass filter without nontrivial multiplications. In other words, we want a filter that usesonly delays and additions so that its implementation is simple. The first frequency we willinvestigate is At this frequency the cosine term is zero and the digital-resonator/f s/4.comb-filter transfer function (the bandpass transfer function in Fig. 31.73) reduces to

(31.122)H(z) = 1 − z−K

1 + z−2

The magnitude and z-plane response of this filter, for K = 8, is shown in Fig. 31.74.

We can determine the magnitude response of Eq. (31.122) following the sameprocedure used to determine Eq. (31.93). The result, for the resonator, isf s/4

(31.123)H( f ) =2

1 − cos K2π f

fs

2 1 + cos 4π f

fs

=sin

Kπ f

fs

cos 2π f

fs

K = 4, 8, 12, 16, ...

At the center of the passband, that is , The ratio of the main lobe to thef s/4 H( f ) = K/2.first side lobe, on either side, is plotted in Fig. 31.75 along with the low pass sinc filterresponse and is calculated using

(31.124)Main lobeFirst side lobe

= K2

⋅ sin 3πK

The cosine term in Eq. (31.121) can be set to when or resulting in±1 f = f s/6 f s/3a bandpass filter that is easy to implement. It should be clear that with the appropriatechoice of sampling frequency, number of zeroes K used in the comb filter, and value of thecosine term, many different combinations of simple bandpass filters can be implementedusing these techniques.


Figure 31.74 A bandpass filter implementation using a comb filter and digital resonator.

6

f

4

DC

1 − z−8

1 + z−2= z8 − 1

z6(z2 + 1)

3f s/8f s/2

f s/8f s/4

f s/4

f s

The ratio of the main lobe to the first side lobe for is given,f = f s/6 or f s/3assuming , byK = 12, 24, ...

(31.125)Main lobeFirst side lobe

=K sin

3π2K

sin

π3 − 3π

2K

sin π3

= 1.15K sin

3π2K

sin

π3

− 3π2K

which is approximately 13.5 dB for and 10.15 dB for K = 12, see Fig.K = 24, 36, 48...31.75.

To increase the amount of attenuation between the main lobe and the first side lobein a bandpass filter implementation, we can cascade filter sections (as we did in thelowpass filter implementations discussed earlier). For example, cascading five f s/4bandpass filters with K = 8 will result in an attenuation of 57 dB. Also, note that bychanging the sampling, or filter clock frequency fs , we can easily change the bandpassfilter's center frequency. A change in the clock frequency, and its selection, can easily beimplemented using a counter and some control logic.

Example 31.23Sketch the block level circuit diagram for an digital resonator.f s/4

From Eq. (31.121) the time-domain representation of the resonator can bef s/4written as

y[nTs] = x[nTs] − y[(n − 2)Ts]

The implementation is shown in Fig. 31.76.


Figure 31.75 Lowpass and bandpass filter attenuation versus number of comb filer zeroes K.

dB

3 4 6 8 10 K

9

11

1313.5 dB

Low pass response

1612

7

5

3

Bandpass attenuation when

Bandpass response when Main lobe

First side lobe

f = f s/4

f = f s/6 or f s/3Frequency Sampling Filters

Consider the topology of a comb filter and resonators shown in Fig. 31.77. We are feedingthe output of the comb filter through the resonators (with different center frequencies) andthen using the combined sum of the resulting bandpass filter responses (the sinc shapes) tobuild a bandpass filter. This is exactly the same as reconstructing a waveform in thetime-domain using an ideal RCF, as discussed in the last chapter (see Fig. 30.17), exceptnow we are using the summation of the frequency domain sinc responses to generate abandpass filter with a variable width. Note how every other digital resonator is subtractedrather than added from the final result. This is to account for the phase reversal betweenadjacent resonator outputs.


Figure 31.76 Implementation of a digital resonator.

clk Q D

clk Q D

x[nTs] y[nTs]

f s

H(z) = 11 + z−2

Figure 31.77 A frequency sampling filter.

Digital resonators

In Out

Comb filter

Desired filter responseSinc responses

Side lobes not shown

1 − z−K

f1

f2

f3

fX−1

fX

f1

f2

f3

f4

f5

f6

f1

−1

−1

f s/4 resonator

31.3 Using Feedback to Improve SNR

We have seen that by averaging the outputs of an ADC, or interpolating between inputs ofa DAC, the effective data converter resolution can be increased. As specified by Eq.(31.52), every doubling in (octave increase in) K (where K is the number of pointsaveraged or the oversampling ratio) results in a 0.5-bit increase in effective resolution. Aneffective ADC resolution increase of 6-bits requires averaging 4,096 samples. If a 1 MHzsignal bandwidth is of interest, our sampling clock frequency, , will have to be 8.192f s

GHz!

In this section we briefly introduce the idea that feedback can be used with dataconverters (ADCs and DACs) to improve overall data conversion system performance(lower the amount of averaging or oversampling needed to attain a given resolution over acertain bandwidth). A topology of this nature is called a modulator or coder (foranalog-to-digital conversion) or a demodulator or decoder (for digital-to-analogconversion.) The complete analog-to-digital interface (a circuit block that functions as anADC) would be made up of a modulator and a decimating filter, while thedigital-to-analog interface (a circuit block that functions as a DAC) would consist of aninterpolating filter and a demodulator. This can be confusing since, for example, amodulator will contain a low-resolution ADC in a feedback configuration which, togetherwith the decimating filter, behaves like a high-resolution ADC.

31.3.1 The Discrete Analog Integrator

An analog building block that we will find useful in implementing our data converters,using feedback, is the discrete analog integrator, DAI, shown in Fig. 31.78. Here we'reassuming the reader is familiar with the material presented back in Ch. 27 coveringswitched-capacitor circuits (for example, the reader is familiar with the operation ofparasitic insensitive integrators). The two clocks signals, and , form nonoverlappingφ1 φ2

clock signals (see Fig. 14.5 in Ch. 14). Also, we are assuming the common mode voltage,VCM , falls halfway between the mixed-signal's high- and low-reference voltages.

Table 31.2 shows the various relationships between the possible inputs and outputsfor the DAI of Fig. 31.78. Let's derive the input/output relationships for the most generalsituations where both v1 and v2 are the inputs.

Input Output connected to φ1 Output connected to φ2

v1 = input and v2 = VCM z−1

1 − z−1⋅ CI

CF

z−1/2

1 − z−1⋅ CI

CF

v2 = input and v1 = VCM −z−1/2

1 − z−1⋅ CI

CF

−11 − z−1

⋅ CI

CF

v1 and v2 are both inputs V1(z) ⋅ z−1 − V2(z) ⋅ z−1/2

1 − z−1⋅ CI

CF

V1(z) ⋅ z−1/2 − V2(z)1 − z−1

⋅ CI

CF

Table 31.2 Discrete analog integrator input/output relationships (see also Eqs. [31.136] and [31.137]).


To begin, let's assume the output of the DAI is connected to the op-amp throughthe switch. When the switches are closed ( is high) at (the instance whenφ1 φ1 φ1 n − 1the switches shut off), the charge stored on CI is

(31.126)Q1 = CI(VCM − v1[(n − 1)Ts])

and the output of the integrator is . When the switches turn on thevout[(n − 1)Ts] φ2

charge stored on CI becomes

(31.127)Q2 = CI(VCM − v2[(n − 1/2)Ts])

remembering that the op-amp's holds its noninverting input terminal at VCM. The differencein these charges, , is transferred to the op-amp's feedback capacitor resulting in anQ2 − Q1

output voltage change. This change can be written as

(31.128)(vout[nTs] − vout[(n − 1)Ts])CF = CI(v1[(n − 1)Ts] − v2[(n − 1/2)]Ts)

or writing this equation in the z-domain results in

(31.129)Vout(z)(1 − z−1) = CI

CF(V1(z) ⋅ z−1 − V2(z) ⋅ z−1/2)

The transfer function of the DAI with the output connected to the switches is thenφ1

(31.130)Vout(z) = CI

CF⋅ V1(z) ⋅ z−1 − V2(z) ⋅ z−1/2

1 − z−1

Similarly, if we connect the output through the switches (the edges we label n in Fig.φ2

31.78 shifts in time by ) we can writeTs/2


Figure 31.78 Schematic diagram of a Discrete Analog Integrator (DAI.)

Bottomplate

t

(the plate closestto the substrate).

VCM

CF

v1

v2

CI

φ1φ1

φ2

φ2

VCM = VREF+ + VREF−

2

vout

φ1

φ2

nn − 1/2

n − 1

Ts

(31.131)Q1 = CI(VCM − v1[(n − 1/2)Ts])

(31.132)Q2 = CI(VCM − v2[nTs])

and

(31.133)(vout[nTs] − vout[(n − 1)Ts])CF = CI(vI[(n − 1/2)Ts] − v2[nTs])

The transfer function of the DAI with the output connected to the switches is thenφ2

(31.134)Vout(z) = CI

CF⋅ V1(z) ⋅ z−1/2 − V2(z)

1 − z−1

Note that if this equation can be written asV2(z) = VCM

(31.135)H(z) = Vout(z)V1(z)

= CI

CF⋅ z−1/2

1 − z−1

which has a frequency response, , shown in Fig. 31.34. Note that the factor H( f ) CI/CF

simply scales the amplitude response. If this factor is unity then the magnitude response, asshown in Fig. 31.34, is 0.5 at . The term, in the numerator, simply modifies thef s/2 z−1/2

phase response of the DAI (delaying the output by or −180 degrees) and has noTs/2effect on the magnitude response. (We'll discuss this more in a moment.) Note that at thispoint we could discuss the frequency responses of the transfer functions given in Table31.2. However, we would see that the discussions and results earlier in the chapter for thedigital integrator would apply to the DAI with no, or little, modifications.

Example 31.24Determine the transfer function of the DAI of Fig. 31.78 without the switches onthe output of the op-amp.

Reviewing Fig. 31.78 we see that charge is transferred to the feedback capacitoronly when the switches are closed. Therefore, the output only changes statesφ2

during the time interval when the switches are closed. The transfer function ofφ2

the DAI, when no switches are used on the output of the op-amp, is given by Eq.(31.134). Using the switches simply adds a half clock cycle delay, , to theφ1 z−1/2

integrator's transfer function (instead of the output changing with the rising edgeof , the output changes one-half cycle later on the rising edge of ). φ2 φ1

A Note Concerning Block Diagrams

As we draw block diagrams describing our modulator topologies, in this chapter and thenext, we often show a circuit like the one shown in Fig. 31.79. The summation, gain, andintegrating blocks are implemented with a single switched-capacitor DAI having thetransfer function given by Eq. (31.134). The gain, G, of the DAI is set by the ratio ofcapacitors as indicated in the figure. It's important to realize that this circuit is entirelyanalog and is interfaced to, in general, both ADCs (Vout[z] is connected to the input of anADC ) and DACs (V2[z] is connected to the output of a DAC.) It should be clear fromboth Fig. 31.79 and Table 31.2 that many different combinations of discrete analogbuilding blocks are possible.


An Important Note

In Fig. 31.78 notice how we derived the transfer function of the DAI based on falling edgetime locations. This is the time when the switches turn off and the capacitor is charged toan input voltage value. In a practical switched-capacitor integrator, the inputs and outputare changing over the time interval when the clock signal is high (the switches are closed).Because the time between going low and going high (and charge being transferredφ1 φ2

from CI to CF ) in a practical switched-capacitor circuit is small, we could argue that thereshouldn't be a Ts/2 delay, , in series with the input signal. This is especially true if thez−1/2

transfer of charge between CI and CF is fast (being limited by the slew-rate of the op-amp).Another way of thinking about this is that this delay simply means the input signal isarriving a little later. In any case, the delay doesn't affect the magnitude response of theDAI just the phase response (delay) between the DAI output and the v1 input. For thisreason the relationships in Table 31.2 are sometimes written as

(31.136)Vout(z) = CI

CF⋅ 1

1 − z−1⋅ (V1(z) − V2(z))

when using no switch or the switch on the output of the op-amp andφ2

(31.137)Vout(z) = CI

CF⋅ z−1/2

1 − z−1⋅ (V1(z) − V2(z))

when using the switch on the output of the op-amp. Figure 31.80 shows Fig. 31.79φ1

redrawn with this assumption (no delay in series with the input, v1).


Figure 31.79 Block diagram of a DAI.

Discrete Analog Integrator

11 − z−1 Vout(z) = CI

CF⋅ V1(z) ⋅ z−1/2 − V2(z)

1 − z−1

V2(z)

V1(z)G ⋅ z−1/2

G G = CI

CF

Figure 31.80 Block diagram of a DAI assuming no input delay.

Discrete analog integrator

Vout(z) = CI

CF⋅ 1

1 − z−1⋅ (V1(z) − V2(z))

V2(z)

V1(z) G1 − z−1

G = CI

CF

31.3.2 Modulators

The basic topology of a feedback modulator or coder is shown in Fig. 31.81. Dependingon the circuit blocks used for A(z) and B(z) feedback modulators can be separated intotwo categories: predictive modulators and noise-shaping modulators.

Predictive modulators (aka predictive coders), an example being delta- modulation,attempt to feedback an analog signal with the same value as the input signal. This drivesthe output of the summer to zero, reducing the required input range of the ADC and,possibly, the quantization error introduced by the ADC. Predictive modulators effectivelyoutput the change in the input signal over time. Noise-shaping modulators, an examplebeing sigma-delta-modulation (also known as delta-sigma-modulation), on the other hand,feed back the average value of the input signal that can be filtered (averaged) to reduce theaccuracy required of the analog circuit components. Noise-shaping modulators effectivelyoutput the average of the input signal over time. In a noise-shaping data converter theaveraging and decimating filter, as discussed earlier, is connected to the output of themodulator. Because of the averaging used in noise-shaping modulators, the analogcomponents, in the forward path of Fig. 31.81, require less accuracy. However, the DAC'soutput, in the feedback path (which is subtracted from the input), doesn't experience theaveraging so, once again, the DAC must be linear to the final desired resolution of the dataconverter. DAC linearity concerns have led to the use of a single-bit DAC (an inverter, seeCh. 29), in many noise-shaping data converter applications. The one-bit DAC is inherentlylinear. (Two output points determine a line!) Because of the relaxed requirements placedon the analog circuit components, we will concentrate the next chapter, in detail, onnoise-shaping topologies for both ADCs and DACs. Notice that both predictive- andnoise-shaping modulators utilize oversampling.

To understand these statements in more detail, let's use the additive quantizationnoise model for the ADC developed in Ch. 30 and shown in Fig. 30.56. Figure 31.82shows Fig. 31.81 redrawn using this model where the quantization noise is represented inthe z-domain by E(z). We can relate the inputs (the wanted input signal and the unwantedquantization noise) to the output of the feedback modulator by


Figure 31.81 Block diagram of a feedback modulator.

ADC

DAC

Out

DigitalAnalog

In

Analog

(to digitalfiltering.)

A(z)

B(z)

X(z) Y(z)

(31.138)Y(z) =

Signal transfer function, STF(z)

A(z)1 + A(z) ⋅ B(z)

⋅X(z) +

Noise transfer function, NTF(z)

11 + A(z)B(z)

⋅E(z)

In a predictive modulator the feedback filter, B(z), has a large gain so that, ideally, the fedback signal equals the input signal. If A(z) = 1 (a wire), then both the STF (signal transferfunction) and the NTF (noise transfer function) have a value of, approximately, 1/B(z).Recovering the input signal requires passing the output of the predictive modulatorthrough an analog filter with a transfer function of precisely B(z) (noting that B(z) is adigital filter in the modulator of Fig. 31.82). The required precision of the analog filter (thematching between the filter in the modulator and the filter in the demodulator) limits theattainable resolution when using predictive modulators. Notice that both the input signaland the quantization noise experience the same spectral shaping (spectral discrimination isabsent in a predictive modulator). Also note that the name "predictive" comes from themodulator attempting to predict the input signal in order to drive the output of thesummer to zero. If the prediction is perfect, the signal that's fed back exactly matches theinput signal.

In a noise-shaping modulator the gain of the forward path, A(z), is large in thesignal bandwidth so that the STF is approximately unity (assuming B(z) = 1). The NTF, onthe other hand, will approach zero, ideally, in the bandwidth of interest. Note that thesignal spectrum passes through the modulator essentially unchanged, while thequantization noise spectrum is shaped (and thus the name noise-shaping.) No precisionfilter or analog components are required, as discussed earlier, except, perhaps, for theDAC in the feedback path of the modulator. We'll see in the next chapter that if A(z) is anintegrator, the quantization noise is pushed to higher frequencies so that it can be removedwith the averaging filter. This is a very important concept as a noise-shaping modulatordoes not reduce the quantization noise to attain higher resolutions but rather pushes thenoise to frequencies outside of the signal bandwidth of interest.



DAC

Out

DigitalAnalog

In

Analog

z-domain representation of the quantization error

ADC

A(z)

B(z)

E(z)

X(z) Y(z)

REFERENCES

[1] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS: Circuit Design, Layout, andSimulation, IEEE Press, 1998. ISBN 0-7803-3416-7

[2] L. W. Couch, Modern Communication Systems: Principles and Applications,Prentice-Hall, 1995. ISBN 0-02325286-3

[3] S. Haykin, An Introduction to Analog and Digital Communications, John Wiley andSons, 1989. ISBN 0-471-85978-8




[7] W. R. Bennett, "Spectra of Quantized Signals," Bell System Technical Journal, Vol.27, pp. 446-472, July 1948.



LIST OF SYMBOLS/ACRONYMS

ACF - Autocorrelation Function, see Eq. (31.30)

ADC - Analog-to-Digital Converter

B - Bandwidth of the input signal, see Eq. (31.69)

DAC - Digital-to-Analog Converter

dBc - Decibels with respect to the carrier, see Eq. 31.9

DR - Dynamic Range, see Eq. (31.10)

- Peak amount of clock jitter∆Ts

- Uncertainty in the sampled voltage∆Vs

fclk - Clock frequency. Also, sometimes called sampling frequency, fs

fin - Input sinewave frequency

fn - Nyquist frequency which is fs /2. Sometimes also called the folding frequency.

fres - Resolution of an FFT

fs - Sampling frequency. Also, sometimes called clock frequency, fclk or Nyquist rate.


H( f ) - Transfer function of a system

H(z) - Z-domain representation of H( f )

K - Oversampling factor or number of points averaged. See Eq. (31.22) or Eq. (31.51)

L - Order of sinc averaging filter

LSB - Least Significant Bit, see Eq. (31.2)

M - Order of a noise-shaping modulator (see Ch. 32.)

N - Ideal data converter resolution (number of bits)

Neff - Effective number of bits, see Eq. (31.5)

NFinal - Final data converter resolution after averaging, see Eq. (31.74)

NInc - Increase in data converter resolution, see Eq. (31.53)

NLoss - Number of bits lost because of sampling jitter. see Eq. (31.17)

PDF - Probability density function, see also ρ(t)

PAVG - Total average power in a waveform

Pin( f ) - Power Spectral Density (PSD), see Eq. (31.35)

Pjitter( f ) - PSD of the sampling error voltage due to jitter, see Eq. (31.49)

Posc( f ) - PSD of the output of an oscillator, see Eq. (31.50)

PSD - Power Spectral Density

PQe( f ) - Quantization noise power spectral density

ppm - Parts per million, a multiplier of 10−6

L - Number of sections used in an averaging filter

Rin(t) - Autocorrelation function, see Eq. (31.30)

- Probability density function, PDFρ(t)

- Standard deviation or square root of the varianceσ

- Variance of a PDF, see Eq. (31.44)σ2

Rin(t) - Autocorrelation function, see Eq. (31.30)

RMS - Root Mean Square

SFDR - Spurious Free Dynamic Range, see Eq. (31.9)

SINAD - SIgnal-to-Noise And Distortion. Same as SNDR.

SNR - Signal-to-noise ratio

SNRideal - Ideal signal-to-noise ratio for a data converter, see Eq. (31.1)


SNRmeas - Measured signal-to-noise ratio for a data converter, see Ex. 31.1

SNDR - Signal-to-Noise plus Distortion Ratio, see Eq. (31.7)

Ts - Sampling period

VFFT( f ) - Fast Fourier transform of a function

VLSB - The voltage weighting of a least-significant bit, see Eq. (31.2)

Vp - Peak value of a sinewave

Vin(t) - Input signal, see Eq. (31.29)

VQe( f ) - Power Spectral Density of the quantization noise, see Eq. (31.54)

VQe,RMS - Root Mean Squared quantization noise, see Ch. 30.

VQe+D,RMS - Root Mean Squared quantization noise and distortion, see Eq. (31.7)

VREF+ - Positive reference voltage used in a data converter.

VREF− - Negative reference voltage used in a data converter.

VRMS - An RMS voltage

- Average value of y, see Eq. (31.44)y

- Defined as z ej2π f

fs = ej2πfTs

QUESTIONS

31.1 Develop an expression for the effective number of bits in terms of the measuredsignal-to-noise ratio if the input sinewave has a peak amplitude of 40% of (VREF+ −VREF−).

31.2 Determine a data conversion systems SNR if the measured VQe,RMS is 1 mV and themaximum peak-to-peak amplitude of an input sinewave is 1 V.

31.3 Repeat Ex. 31.2 if the sampling frequency is increased to 200 MHz. Does the SNRchange?

31.4 Why is the amplitude of the tone at 45 MHz in the DAC output spectrum shown inFig. 31.3b smaller than the amplitude of the ADC input signal? What is the originof the noise added to the DAC output signal in Fig. 31.3b?

31.5 When using Eq. (31.8) what is the assumed ADC input signal? Put your answer interms of the ADC reference voltages.

31.6 Describe in your own words the difference between specifying SNR and SNDR.

31.7 Suppose a perfectly stable clock is available, ∆Ts is zero in Eq. (31.12). Would westill have a finite aperture window if the clock has a finite risetime? Describe whyor why not?


31.8 How do the number of bits lost because of aperture jitter change with thefrequency of an ADC input sinewave? If the ADC input is a DC signal is aperturejitter a concern? Why?

31.9 Show the time-domain signal that generates the spectrum shown in Fig. 31.10.Verify in the time-domain that the signal's rising and falling edges do indeed varyfrom their ideal positions.

31.10 Describe in your own words the problems with simulating clock jitter usingSPICE.

31.11 What does the autocorrelation function (ACF) tell us about a signal? What is theACF of a 1 V DC signal. Show the simple calculations leading up to your answer.

31.12 Plot the power spectral density of a sinewave. From this plot show how todetermine the average and RMS values of the sinewave. Show the procedure forboth one-sided and two-sided spectrums.

31.13 Sometimes the average power specified by Eq. (31.37) is termed total averagenormalized power of a signal. Why?

31.14 When WinSPICE generates a plot from an FFT the units on the y-axis are voltspeak (the peak value of a sinewave at a given frequency). How do we change thisplot into RMS voltages, voltage spectral density, and power spectral density vs.frequency?

31.15 Repeat Ex. 31.12 if the sinewaves are first sampled.

31.16 Suppose the jitter in a clock signal can be characterized using the PDF shown inFig. 31.12. Further if ∆Ts = 100 ps estimate the RMS value of clock jitter, standarddeviation, and variance of the jitter.

31.17 Suppose that a noise voltage has the PDF shown in Fig. 31.12. If the maximumvoltage deviation from the ideal value is 10 µV estimate the RMS value of thenoise (the standard deviation) and the noise power (the variance).

31.18 Repeat question 31.17 if the noise voltage has a gaussian PDF as seen in Fig.31.13.

31.19 Repeat Ex. 31.1 if we want to include an error from sampling jitter, PAVG,jitter of 1µW.

31.20 If a DC signal is input to a data conversion system is Eq. (31.51) valid. Name threeconditions on the input signal in order for this equation to be valid.

31.21 Suppose the standard deviation of the quantization noise in a data conversionsystem is 1 mV. Using Eq. (31.56) plot the PSD of the quantization noise.Comment on the assumption that the noise power is limited to the Nyquistfrequency. Does this result in an over- or underestimate for the actual noise powerin the spectrum of interest?


31.22 Show why averaging two 8-bit words, as seen in Fig. 31.19, must result in a 9-bitword. (Why isn't the sum of the two words divided by two [the average] another8-bit word?)

31.23 Why must Bennett's criteria be valid for the averaging to reduce the quantizationnoise in Fig. 31.19? Given an example where averaging will not reducequantization noise.

31.24 Show a figure similar to Fig. 31.20 where an input sinewave with a frequency offs/4 is sampled at fs. Show that the magnitude of the resulting fundamental(indicating that the sinewave lies in the frequency range of DC to fn) sinewave is

as indicated in Fig. 31.22.2

31.25 Assuming Eq. (31.68) is valid re-derive Eq. (31.4) including the effects ofaveraging K ADC output samples. Is Eq. (31.4) or the equation derived here validfor a slow or DC input signal? Comment on why or why not.

31.26 Assuming Bennett's criteria are valid does averaging ADC outputs (or DACinputs) put any restrictions on the bandwidth of the input signal? Why? Give anexample.

31.27 Comment on the statement "The factor of two in the magnitude response of Fig.31.22 at low-frequencies simply indicates that the digital word length increases by1-bit."

31.28 What is the magnitude response of .z−2 + z−3

31.29 Repeat Ex. 31.15 if 16 ADC outputs are averaged, that is, K = 16.

31.30 How accurate does an 8-bit ADC have to be in order to use a digital filter toaverage 16 output samples for a final output resolution of 10-bits (see Eq.[31.53]). Assume the ideal LSB of the 8-bit converter is 10 mV. Your answershould be given in both mV and % of the full-scale.

31.31 If a DC signal is applied to a data converter can a digital averaging filter be used toincrease the system's resolution? What about if a dither signal is added to the DCinput? Use simple time-domain drawings to illustrate your answers.

31.32 Name three characteristics of all digital filters.

31.33 Plot Eq. (31.59) on a z-plane. Using this plot show how to graphically determinethe magnitude and phase responses shown in Fig. 31.22.

31.34 The magnitude response shown in Fig. 31.34 becomes infinite as the input signalapproaches DC. Since the filter is digital what is the maximum output of the filter?

31.35 Show that the peak (+127) and valley (−128) amplitudes of the two's complementsignals in Fig. 31.37 sum to −1.

31.36 Summarize the method of changing a number from binary-offset to two'scomplement. Demonstrate addition and subtraction using two's complement


numbers. Show how, in two's complement, 8, 33, and 111 sum to 152. Assume a10-bit word size.

31.37 Suppose a digital filter sums 16 inputs and then outputs the total. If the filter isclocked at 100 MHz plot the magnitude response of the filter.

31.38 Comment on the benefits and drawbacks of using an averaging filter with andwithout decimation.

31.39 Verify the z-domain function specified by Eq. (31.100) has a frequency responsegiven by Eq. (31.101). How are the typical input and output signals in the timedomain related for this filter?

31.40 What is the magnitude response of . Sketch a block diagram(1 − z−1)3

implementation for this filter.

31.41 Re-sketch Fig. 31.53 if, in each transfer function H(z), a pole is added at DC.

31.42 Show the problem with not using a MUX at the input of the adders in Fig. 31.55.

31.43 Is it possible for the accumulate-and-dump circuit to output a spectrum withaliasing if the input signal is bandlimited to fs? Why or why not?

31.44 In the discussions in this chapter we assumed the digital signals are much largerthan an LSB of a data converter. What happens if this is not the situation for theSinc averaging filter?

31.45 Is it possible to decimate a digital waveform down to 2B and then later, with someother hardware or software digital filter, remove all of the aliased signal from thedesired signal?

31.46 Suppose the waveform shown in Fig. 31.66 is the input to a decimator. If K = 8what would the output of the decimator look like? Use integers to illustrate yourunderstanding.

31.47 Suppose a digital word is clocked into a hold register and held there for 8 clockcycles before another word is clocked into the hold register. Is this similar to theanalog sample-and-hold? If the sampling rate (clock frequency) is increased by afactor of 8 after the hold register what kind of digital filter can we think of the holdregister as being?

31.48 Show that the digital resonator of Fig. 31.76 can be modified, if we add amultiplier to the circuit, so that Eq. (31.120) can be implemented.

31.49 It is more correct to write our DAI continuous time input signals in Fig. 31.78 as

and v1(t) + VCM v2(t) + VCM

Knowing this rederive Eq. (31.130).

31.50 Repeat question 31.49 for Eq. (31.134).


31.51 Using the results from question 31.49 derive the transfer function, Eq. (32.139),for the circuit shown in Fig. 32.92 (in the next chapter).

31.52 Show the detailed derivation of Eq. (31.138).

31.53 Summarize the advantages and disadvantages of predictive and noise-shaping dataconverters.


Noise-Shaping Data Converters

In this chapter we discuss the design of noise-shaping (NS) data converters. Our approachwill be to develop NS theory along with SPICE behavioral models to illustrate, usingsimulations, the operation of NS ADCs and DACs. Our goals are to discuss thefundamentals of NS data converter design and to put a framework together for SPICEsimulations. Having a simulation framework available will allow us to: 1) perform abehavioral simulation using nearly ideal components to determine fundamentalperformance limitations of a particular NS converter topology and 2) replace behavioralmodels with actual, MOSFET-based circuits in steps to design and simulate the operationof a NS data converter in stages. While we can replace the behavioral models withMOSFET-based circuits, we will delay this discussion (MOSFET-based circuit design in asubmicron process) until the next chapter. This chapter will focus on NS theory andexamples, using simulations, to illustrate the use of the theory.

32.1 Noise-Shaping Fundamentals

In this section we develop SPICE behavioral models to illustrate NS data converter designand then we present the theory behind the design of first- and second-order NS dataconverters using single-bit DACs and ADCs.

32.1.1 SPICE Models

Because data converters employing averaging, such as an NS data converter, can require asignificant number of samples for meaningful operation (the simulation time may berelatively long), we need to be careful not to develop simulation models that are inefficientor too complex. At the same time it is desirable to have models complex enough to includethe nonideal effects that occur in the actual circuits used. For example, an op-amp willhave finite gain and an offset voltage while the switches will have nonzero on resistance.

Chapter

32

In the material that follows we attempt to develop models that are robust, includingfundamental limitations of the circuits used, while at the same time attempting to generatesimple models for fast simulations.

Nonoverlapping Clock Generation and Switches

In this chapter, as we did in Chs. 30 and 31, we assume VDD = 1.5 V (the positive powersupply voltage), VSS = 0 V (the negative power supply voltage), VREF+ = 1.5 V (thepositive data converter reference voltage), = 0 V (the negative data converterVREF−reference voltage), and (the sampling, or clock frequency, of the dataf s = fclk = 100 MHzconverter). The SPICE pulse statements used to generate two 100 MHz, nonoverlappingclocks, can be written as

Vphi1 phi1 0 DC 0 Pulse 0 1.5 0 200p 200p 4n 10nVphi2 phi2 0 DC 0 Pulse 0 1.5 5n 200p 200p 4n 10nR2 phi1 0 1MEGR3 phi2 0 1MEG

where the resistors ensure that the clocks are not floating (not the only elementsconnected to the nodes phi1 and phi2 as the clocks may be used exclusively to controlswitches in a simulation). The statements used to set up the power supply voltages,reference voltages (if used), common mode voltage, and switch trip points can be writtenas

VDD VDD 0 DC 1.5Vtrip Vtrip 0 DC 0.75VCM VCM 0 DC 0.75VREFP VREFP 0 DC 1.5VREFMVREFM0 DC 0

The trip voltage is used in simulating the operation of the switches to indicate when theswitch should be opened or closed. Figure 32.1a shows the use of the basic switch inSPICE. When phi1 is above the trip voltage (0.75 V here), the S1 switch is closed.(φ1)When the node phi2 is above the trip voltage, S2 is closed. The SPICE statementsspecifying the operation of these switches, in the manner described, are

S1 1 2 phi1 Vtrip switmodS2 2 3 phi2 Vtrip switmod.model switmod SW RON=1k

The parameter RON can be used to model the switches on resistance as shown in Fig.32.1b. This may be useful when simulating finite settling time effects in a data converter.


Figure 32.1 Using a switch in SPICE.

S1 S2

1 2 3

Node numbers

(a)

RON

(b)

φ1 φ2

Op-Amp Modeling

Behavioral modeling of op-amps could take up an entire chapter by itself. Here weintroduce a trivial model that is easily modified to account for real op-amp imperfections.Figure 32.2 shows the basic op-amp symbol and a voltage-controlled-voltage-source usedto simulate the operation of an op-amp. The SPICE statement that specifies the op-amp is

Ein 3 0 2 1 100MEG

where the open loop gain of the op-amp is 100 million.

Example 32.1Determine and simulate the gain of the circuit shown in Fig. 32.3.

This circuit is our Discrete Analog Integrator (DAI) shown in Fig. 31.78 with thev2 input connected to VCM. The transfer function of this circuit in the z-domain is

(32.1)H(z) = z−1

1 − z−1

From Fig. 31.34 and Eq. (31.84) the magnitude of Eq. (32.1), in the frequencydomain, is (noting the in the numerator of Eq. [32.1] is a delay of Ts that addsz−1

to the phase of the integrator but doesn't affect the magnitude response)

Chapter 32 Noise-Shaping Data Converters 151

Figure 32.2 Simple SPICE op-amp model.

1

23 1

2

3

E1

Figure 32.3 Circuit used in Ex. 32.1.

φ1

VCM = 0.75 V

1p

fclk = f s = 100 MHz

0.75 + 0.05 ⋅ sin (2π ⋅5MHz ⋅ t)

Vin

VCM

CF = 1pφ1 φ2

CI = 1p

Vout

(32.2)H( f ) = 1

2 1 − cos 2π 5

100

= 3.2

resulting in a peak output voltage of 160 mV (peak-to-peak voltage of 320 mV).The simulation results are shown in Fig. 32.4. Notice how the output, at DC, isdefined by the initial state of the feedback capacitor, CF . In this case the input andoutput of the integrator start at the same voltage. The phase shift can becalculated, using Eq. (31.85) and knowing the zero is not present, as − 99 °.Finally, the SPICE netlist used to generate this plot is listed below.

* Figure 32.4 CMOS: Mixed-Signal Circuit Design *

.tran 1n 500n 0 1n UIC

*WinSPICE command scripts*#destroy all*#run*#plot Vout Vin ylimit 0.6 1.2

*Input power and referencesVtrip Vtrip 0 DC 0.75VCM VCM 0 DC 0.75

*Input SignalVin Vin 0 DC 0 Sin 0.75 50m 5MEG

*Clock SignalsVphi1 phi1 0 DC 0 Pulse 0 1.5 0 200p 200p 4n 10nVphi2 phi2 0 DC 0 Pulse 0 1.5 5n 200p 200p 4n 10nR2 phi1 0 1MEGR3 phi2 0 1MEG

*Use a VCVS for the op-ampEopamp Voutop 0 VCM Vinm 100MEG

*Setup switched capacitors and loadCI Vtop Vbot 1p CF Voutop Vinm 1p Cload Vout 0 1p

*Setup switches for the integratorS1 VCM Vtop phi1 VTRIP switmodS2 Vin Vbot phi1 VTRIP switmodS3 Vtop Vinm phi2 VTRIP switmodS4 Vbot VCM phi2 VTRIP switmodS5 Voutop Vout phi1 VTRIP switmod.model switmod SW RON=100

.end


SPICE modeling a 1-bit ADC (A Comparator)

Modeling a non-clocked comparator is straightforward using switches as seen in Fig. 32.5.When the positive comparator input is greater than the negative input, the output of thecomparator is high. When the negative input is greater than the positive input, the outputof the comparator is low. In the implementation we might need to connect large, dummy,resistors (or small capacitors) to the comparator inputs to keep the nodes from floating.For a clocked comparator we will add, before the continuous comparator, a sample andhold (S/H). The basic topology of our S/H was shown back in Fig. 30.24.


Output

Input

Figure 32.4 Integrator input and output for Ex. 32.1.

Figure 32.5 Modeling a comparator in SPICE.

VDD

Vinp Vout

S1

S2 S1 Vout 0 Vinm Vinp switmod

InputsVinm

S2 VDD Vout Vinp Vinm switmod.model switmod RON=100

32.1.2 First-Order Noise-Shaping

The block diagram of a noise-shaping feedback modulator is shown in Fig. 32.6. In theend of Ch. 31 we showed that the output of the modulator, Y(z), can be related to theinput, X(z), and the ADC's quantization noise, E(z), by

(32.3)Y(z) =

STF(z)

A(z)1 + A(z)

⋅X(z) +

NTF(z)

11 + A(z)

⋅E(z)

where STF( f ) is the signal's transfer function and NTF( f ) is the noise's transfer function.

Consider what happens if A(z) is an integrator (implemented using a DAI) asshown in the figure. Equation 32.3 becomes

(32.4)Y(z) = z−1X(z) + (1 − z−1)E(z)

This equation is important! It shows the input signal simply passes through the modulatorwith a delay while the quantization noise is differentiated (see Fig. 31.51 for the magnituderesponse of a digital differentiator with a transfer function ). We can think of the1 − z−1

noise differentiation as pushing the quantization noise to higher frequencies. We'll comeback to how noise-shaping affects the quantization noise spectral density, VQe( f ), in amoment. But first let's attempt to understand what's happening here.

In Fig. 32.6 the summer takes the difference (Delta) between the input signal andthe fed back signal. The integrator accumulates or sums (Sigma) this difference and feedsthe result back, via the ADC and DAC, to the summer. This forces the output of themodulator to track the average of the input. Sometimes the fed back signal will have avalue greater than the input signal, while at other times the fed back signal will be less thanthe input signal. The average signal fed back, however, should ideally be the same as theinput signal. Note that this type of NS modulator is often called a Delta-Sigma orSigma-Delta modulator. Also, at this point, we should see the need for the averagingfilters discussed in the last chapter.


Figure 32.6 Block diagram of a noise-shaping (NS) modulator.

DAC

Out

DigitalAnalog

In

ADCDelta Sigma

Integrator

A(z) = z−1

1 − z−1

E(z)

X(z) Y(z)

A circuit implementation of a first-order NS modulator is shown in Fig. 32.7. Forthe moment we use a single-bit ADC and DAC (both implemented using the clockedcomparator) for gain linearity reasons (discussed in more detail later). The analog voltagecoming out of the integrator is compared to the common-mode voltage (this is our 1-bitADC) using the comparator. For the 1-bit DAC a logic-0 has an analog voltage of 0 V,while a logic-1 has an analog voltage of VDD (= 1.5 V here) so that the comparator'soutput can be used directly (fed back to the DAI).

The comparator is clocked on the rising edge of resulting in a Ts delay ( ) inφ1 z−1

series with the fed back signal and a delay of Ts/2 ( ) in series with the input signal. Toz−1/2

understand this statement, remember that the nonoverlapping clock dead time (the timeboth and are low) is short and, practically, the falling edge of occurs at the sameφ1 φ2 φ2

instance as the rising edge of (and so we could also use to clock the comparator).φ1 φ2

This results in a transfer function (see Eq. 31.130 and Table 31.2) to the input of thecomparator (which can also be thought of as the ADC output since the fed back signal andmodulator output are the same signal) of

(32.5)Desired ADC input/output = z−1

1 − z−1(Vin − Vout)

After careful review we should see that the circuit implementation of Fig. 32.7corresponds to the NS modulator represented by the block diagram shown in Fig. 32.6.

We can use the SPICE models developed in the last section to demonstrate theoperation of the NS modulator of Fig. 32.7. Assuming our sampling frequency is 100MHz, the input is a 500 kHz sinewave centered around VCM (= 0.75 V) with a peakamplitude of 0.7 V. The input and output of the modulator are shown in Fig. 32.8. It'simportant to understand the signals in this figure. When the sinewave is at its peakamplitude, the output of the modulator stays high, a logic one, most of the time. When thesinewave is moving through the common mode voltage, the output bounces back andforth between VDD and ground so that its average value, VDD/2, matches the input value.

To construct a (higher-resolution) ADC the output of the modulator is connectedto a digital averaging filter as shown in Fig. 32.9. The output of the digital filter is a digital


1p

1p

Figure 32.7 Circuit implementation of a first-order NS modulator.

Clocked comparator

VCM

VCM

VCM

φ1 φ2φ1

Vin

Vout

f s = 100 MHz

word representing the analog input voltage. For a detailed discussion of the requirementsplaced on the anti-aliasing filter (AAF) and the digital filter (or digital-decimation filter ifdecimation is used) see Ch. 31.

We might wonder if we can use an analog filter, instead of a digital filter in thetopology of Fig. 32.9, to remove the high-frequency quantization noise. The output of theresulting circuit will be analog, so it can't be used as an ADC. While this may not be ofpractical use, at the moment, it does help in understanding how the NS modulatorfunctions. Passing the modulator output of Fig. 32.8 through a simple RC low pass filter,with a time constant of 100 ns, results in the waveform shown in Fig. 32.10. Increasing thetime constant results in a smoother output signal. However, increasing the time constanttoo much can affect the amplitude of the desired signal. Also, note the phase shift throughthe modulator and filter.


Modulator outputModulator input

Figure 32.8 Modulator, Fig. 32.7, input and output.

Figure 32.9 ADC using a NS modulator and digital filter.

NS modulatorDigitalFilter

AAFAnalog input

Digital Output

Clock input Decimation filter

1-bit

f s

A Digital First-Order NS Demodulator

So far our noise-shaping discussion has centered around analog-to-digital conversion.Figure 32.11 shows a first-order NS demodulator-based topology for digital-to-analogconversion. While, once again, the discussion concerning selection of the digitalinterpolating and reconstruction filters is given in Ch. 31, we are interested here in thetopology of the first-order NS demodulator for use in a DAC.

Figure 32.12a shows a block diagram of a first-order NS demodulator for use in aDAC. Figure 32.12b shows the practical implementation. The only differences betweenthis circuit and the circuit of Fig. 32.6 is that the DAI is replaced with an all-digitalintegrator (see Fig. 31.49) and the quantizer (comparator) is replaced with a circuit thatperforms quantization by selecting (using the MSB of the accumulator output word)digital VREF+ (= 011111... in two's complement, see Fig. 31.37) or VREF− (= 10000...)which, for our current discussion, are VDD and ground.


Input

Output after RC

Figure 32.10 Using a simple RC lowpass filter on the output of the NS modulator of Fig. 32.7.

filtering

Figure 32.11 DAC using a NS modulator and digital filter.

NS demodulatorDigitalFilter

RCFAnalog outputDigital input

Clock inputInterpolation filter

1-bit

f s

Modulation Noise in First-Order NS Modulators

Here we present a more detailed discussion of the quantization noise spectrum for afirst-order NS modulator. To begin let's write Eq. (32.4) in the time domain,

(32.6)Y[nTs] = X(n − 1)Ts + E[nTs] − E[(n − 1)Ts]

which shows the output is a function of the first difference (order) of the quantizationnoise E[nTs] − E[(n − 1)Ts]. Intuitively note that the smaller we make Ts (the faster wesample since ), the closer our digital output Y[nTs] approaches the analog inputTs = 1/f s

X[nTs].

Next let's, using Eq. (32.4), write the product of the noise-transfer-function andE[z] (the modulation noise) of the first-order NS modulator in the frequency domain as

(32.7)NTF(z)E(z) = (1 − z−1)E(z) → NTF( f )VQe( f ) = 1 − e−j2π f

fs ⋅ VLSB

12f s

where we have used, see Fig. 30.57,

for (32.8)E( f ) = VQe( f ) = VLSB

12f s

units, V/ Hz

0 ≤ f ≤ fs/2

and

(32.9)VLSB = VREF+ − VREF−

2N


Out

Digital

In

Quantizer

AccumulatorDigital

OutInD Q

clk

Accumulator Quantizer

Figure 32.12 Block diagram of a noise-shaping (NS) demodulator (a) and a moredetailed implementation (b) for use in a DAC.

(b)

(a)

MSB

MUX011111...100000...

10

z−1

1 − z−1

E(z)

X(z)

f s

VCM = 00000.... = 0.75 V (here)

where N is the number of bits used in the low-resolution ADC/DAC in the modulator.Using a single-bit ADC/DAC in a NS modulator, N = 1, results in (seeVLSB = 1.5 Vproblem 30.14 for a discussion of when Eq. [32.9] isn't valid). This again shows that weare not reducing the quantization noise but rather pushing it to higher frequencies so thatit can be filtered out. Using Eq. (31.107) we can write the power-spectral density (PSD)of the noise-transfer-function (the PSD of the first-order modulator's modulation noise) as

(32.10)NTF( f ) 2 ⋅ VQe( f ) 2 =VLSB

2

12f s⋅ 2

1 − cos 2π ff s

(units, V2/Hz)

Figure 32.13 shows the PSD of the first-order NS modulation noise for andVLSB = 1.5 V. Note how now we are discussing modulation noise instead of quantizationf s = 100 MHz

noise. The modulation noise is the quantization noise after being differentiated by the NSmodulator. The modulation noise is the unwanted signal added to the input signal. Afterreviewing Fig. 32.13 we see that the magnitude of the modulation noise is significant.However, after passing this signal through a low-pass filter, we can remove the higherfrequency noise resulting in a lower value of data converter RMS quantization noise,VQe,RMS. Figure 32.14 shows the PSD of the noise if we limit our view to 1 MHz. The pointhere is that by restricting the bandwidth of the modulation noise we can, theoretically,drive the RMS quantization noise in our signal to zero. Of course, by lowering thebandwidth of the digital filter on the output of the modulator we also limit the possiblebandwidth, B, of the input signal. Notice that we have violated Bennett's criteria byutilizing a quantizer with an LSB that is comparable to the input signal. Now, however,we are using feedback that adds or subtracts a signal from the input and ultimately affectsthe quantizer input.


Figure 32.13 Modulation noise for a first order NS modulator.

V2/Hz, × 10−9

f, Hz, × 106

fn = f s/2 = 50 MHz

Example 32.2Show, using SPICE, the modulation noise spectrum associated with the NSmodulator of Fig. 32.7. Compare the simulation results to the theoretical resultsshown in Fig. 32.13.

Following the procedure given back in Sec. 30.3.1, Fig. 30.46, to determine a dataconverter's quantization noise spectrum, we apply a slowly moving voltage rampto the input of the modulator. Then we look at the difference between the inputand output of the modulator (the modulation noise). The simulation results areshown in Figs. 32.15a and 32.15b. We used the following WinSPICE commandsto generate these plots (added directly into the netlist)

*#plot Vout Vin *#let Vqev=Vout-Vin*#linearize Vqev *#spec 0 100MEG 200k Vqev*#let Vqedb=db(Vqev)*#plot Vqedb

The first command was used to generate Fig. 32.15a. The second command is usedto generate the difference between the modulator's input and output (themodulation noise). Notice how, in Fig. 31.15a, the output of the modulator stayslow most of the time, when the input to the modulator is close to ground, while theoutput stays high most of the time when the input is close to VDD. The third and


Figure 32.14 A limited view of the modulation noise of Fig. 32.13.

V2/Hz, × 10−12

f, Hz, × 106


Figure 32.15 (a) Input and output of the NS modulator of Fig. 32.7 and (b)modulation noise output spectrum.

Input ramp

Modulator output

Vol

tage

, pea

k

(a)

(b)

Volts

fourth commands in the above list generate the spectrum of the modulation noise(the spectrally shaped quantization noise.) The last commands are used to plot,Fig. 32.15b, the spectrum of the modulation noise (units of ). It may beVoltshelpful, at this point, to review Fig. 30.48 and the associated discussion. Tochange this plot (Fig. 31.15b) into a power spectral density (units of ) weV2/Hzcan square the magnitude of the modulation noise and then divide the result by theresolution of the Fourier Transform in Fig. 32.15). The list of( f res = 200 kHzcommands used to generate a power spectral density from Fig. 32.15b would be

*#let m=mag(Vqev)*#let Vqepsd=db(m*m/200k)*#plot Vqepsd

Using this sequence of commands results in a spectrum with amplitude values thatare similar to the values given in Fig. 32.13 (and have the same units). However,the shape would remain essentially unchanged from Fig. 32.15b.

Notice that the shape of the modulation noise shown in Fig. 32.15b (indecibels) matches fairly well with the spectrum shown in Fig. 32.13. This is thecase even though the quantization noise spectral density, E( f ), is not flat (is notwhite) as was assumed in Eq. (32.7). The important thing to notice in Fig. 31.15bis that the modulation noise spectrum decreases with decreasing frequency (at 20MHz and below) as was predicted using Eq. (32.10) and shown in Fig. 32.13.

RMS Quantization Noise in a First-order Modulator

If we limit the range of frequencies we look at to calculate the quantization noise to valuesbelow fs , then we can re-write Eq. (32.10) as

(32.11)NTF( f ) ⋅ VQe( f ) = VLSB

12f s

⋅ 2 sinπffs

units, V/ Hz

The RMS quantization noise present in a bandwidth B can be calculated, see Eq. (30.44),using

(32.12)VQe,RMS2 = 2 ∫

0

B

NTF( f ) 2 VQe( f ) 2 ⋅ df = 2 ⋅ VLSB2

12f s⋅ 4 ⋅ ∫

0

B

sin2π ff s

⋅ df

Remembering that the maximum bandwidth of our input signal is related to the samplingfrequency, fs , and the oversampling ratio, K, by

(32.13)B =f s

2K

and, for small values of x,

(32.14)sinx ≈ x

then


(32.15)VQe,RMS ≈ VLSB

12⋅ π

3⋅ 1

K3/2

This equation should be compared to Eq. (31.51). Further we can describe the ideal dataconverter signal-to-noise ratio using first-order noise-shaping, see Eqs. (31.1) - (31.4) as

(in dB) (32.16)SNRideal = 20 ⋅ logVp/ 2VQe,RMS

= 6.02N + 1.76 − 20 log π3

+ 20 log K3/2

or

(in dB) (32.17)SNRideal = 6.02N + 1.76 − 5.17 + 30 log K

This equation should be compared to Eq. (31.52) where we saw every doubling in theoversampling ratio, K, results in a 0.5 bit increase in resolution (called simpleoversampling). Here we see that every doubling in the oversampling ratio results in 1.5bits increase in the resolution (or a 9 dB increase in SNRideal ). A first-order NSmodulator's performance is compared to simple oversampling in Fig. 32.16.

Examples 32.3Determine the ideal signal-to-noise ratio and the maximum signal bandwidthallowed, B, for the first-order NS modulator of Fig. 32.7 if 16 of its outputsamples are averaged (K = 16).

Because the sampling frequency, fs , is 100 MHz, we can use Eq. (32.13) todetermine the maximum input signal bandwidth, B, is 3.125 MHz. Using Eq.(32.17) we can solve for the SNRideal as (knowing that the NS modulator of Fig.32.7 uses a 1-bit quantizer) 38.73 dB. This corresponds to an equivalent dataconverter (ADC) resolution, using Eq. (31.4), of 6.14 bits (number of bits added is


Figure 32.16 Comparing simple oversampling to first-order noise-shaping.

1 10 100 1k0

3.33

6.66

10.0

K ,Oversampling ratio

Simple oversampling


13.3

16.6

10k

First-order noise-shaping

Ninc =30 log K − 5.17

6.02

Ninc

SNRideal = 6.02(N + Ninc) + 1.76

5.14). Note that the ADC is made with the components, modulator and digitalfilter, shown in Fig. 32.9.

Decimating and Filtering the Output of a NS Modulator

It's important to note that Eq. (32.17) was derived assuming the output of the modulatorwas passed through a perfect low pass filter with a bandwidth of B. Passing the outputthrough a sinc averaging filter, see Fig. 31.41, will result in a poorer SNR because thehigher frequency noise components will not be entirely filtered out. In this section we wantto answer two questions: 1) what order, L (see Eq. [31.104]), of sinc averaging filtershould be used in the digital filter on the output of the NS modulator, and 2) assuming weuse only this filter (no half-band filter or additional filtering), how will the ideal SNR of thefirst-order NS modulator be affected?

The answer to the first question begins by writing the increase in the number ofbits, Ninc , as

(32.18)Ninc =30 log K − 5.17

6.02

If our NS modulator uses a 1-bit ADC, then the final, after the digital filter, resolution ofthe resulting data converter is Ninc + 1 bits. (An NS modulator using a 5-bit ADC [oftencalled a multi-bit NS modulator] would ideally have an output resolution of Ninc + 5 bits).Further, we saw in Ex. 31.22 and Fig. 31.55 that the word size increased by bits inlog2Keach stage so that we can require

(32.19)L ⋅ log2K ≥30 log K − 5.17

6.02

Solving this equation results in L being greater than or equal to 2. In general, we can write

(32.20)L = 1 + M

where M is the order of the modulator. For a first-order modulator we use two stages inthe averaging filter, or,

(32.21)H(z) =

1K

1 − z−K

1 − z−1

2

In the next section we discuss second-order NS modulators (M = 2). For these modulatorswe use a sinc averaging filter with L = 3.

Example 32.4Sketch the implementation of the digital decimation filter for the modulatordescribed in Ex. 32.3. Assume the final output clocking frequency is 100 MHz/16or 6.25 MHz. Do not be concerned with aliasing (use only the averaging filter.)

The transfer function of the digital filter is (see Eq. [31.93])


H(z) =

1 − z−16

1 − z−1

2

= H( f ) =

116

⋅sin

16 ⋅ π f

fs

sin π f

fs

2

The block diagram of the filter is shown in Fig. 32.17. The increase in resolutionthrough each accumulator (integrator) stage is bits. The resolutionlog216 = 4calculated in Ex. 32.3 was 6.14 bits, which we round up to 7-bits. Because theoutput of the digital filter is 9-bits, we drop the lower two bits (divide by 4) to getour final 7-bit resolution.

Next let's answer how filtering with a sinc filter affects the SNR of the dataconverter. Remember the SNRideal was calculated in Eq. (32.17) assuming the modulationnoise was strictly bandlimited to B. Figure 32.18 shows the PSD of the NTF2( f )

(the modulation noise) of the first order NS modulator. Also shown in this⋅ VQe( f ) 2

figure is the shape of the averaging filter's magnitude response squared (see Eqs. [32.22],[31.90] and [31.93]). Here we are showing the shape of a filter with L = 2 (set by Eq.[32.20] for a first-order modulator) and K = 16. We limit our range to fs /2.


Figure 32.17 Sinc filter used for decimating the output of the NS modulator of Fig. 32.7.

Out

Digital

clock

9 995 9

Drop the lowertwo-bits so that output is 7-bits.Decimation filter

MUX10

00001111

select 5In

Add MUXLSB

1 − z−111 − z−1

1 − z−1

÷K

11 − z−1

f s f s/K

Figure 32.18 Showing modulation noise and filter response.

BIdeal maximum input frequency

NTF( f ) 2 ⋅ VQe( f ) 2 =VLSB

2

12f s⋅ 4 sin2π f

f s

H( f ) 2 =

1K

⋅sin

Kπ f

fs

sin π f

fs

4

f s/2f s/K

We can calculate the RMS quantization noise resulting from a cascade of a first-order modulator and an averaging filter using

(32.22)VQe,RMS2 = 2 ∫

0

fs/2

NTF( f ) 2 ⋅ VQe( f ) 2 ⋅ H( f ) 2 ⋅ df

(32.23)VQe,RMS2 = VLSB

2

12f s⋅ 8

K4⋅ ∫

0

fs/2 sin4 Kπ f

fs

sin2 π f

fs

⋅ df

If we let , then this equation can be written asθ = πffs

(32.24)VQe,RMS2 =

VLSB2

12f s⋅ 8

K4 ⋅f s

π ⋅

= K⋅ π4

∫0

π2

sin4(Kθ)sin2θ

dθ

and finally,


12⋅

2

K3/2

This equation should be compared to Eq. (32.15), which was derived assuming the digitalfilter was ideal with a bandwidth of B. The SNR resulting from using a first-order (M = 1)NS modulator and a second-order (L = 2) sinc averaging filter is

(in dB) (32.26)SNRsinc = 6.02N + 1.76 − 3.01 + 30 log K

Comparing this to SNRideal given in Eq. (32.17), we see that using a sinc filter foraveraging results in only a 2.16 dB difference (increase) in SNR over the ideal filter. If weremember that using a sinc filter results in a droop in the desired signal, see Fig. 31.46, theSNR will be lower than what is predicted by Eq. (32.26). (Note that an analysis of higherorder modulators using sinc averaging filters would show that as long as Eq. [32.20] isvalid the deviation from SNRideal is negligible.)

We have not talked about the effects of sample-rate reduction (decimation) on theSNR. The modulation noise aliased into the base spectrum is a concern when decimatingthe output of the modulator. The major difference between filtering the outputs of the dataconverters in the last chapter and filtering the output of an NS modulator is the spectralcharacteristics of the noise. In the last two chapters we assumed the quantization noisespectral density was white (see Fig. 30.57). As we've seen in this chapter the modulationnoise increases with increasing frequency (see Fig. 32.18). This can mean that the amountof modulation noise aliased into the base, or desired, spectrum can be more of a concern.The major concern when decimating, in most situations, is the input signals that reside atfrequencies > B and the resulting aliasing degradation of the SNR (see, for example, Fig.31.59).


Implementing the Sinc Averaging Filter Revisited

We chose to implement the sinc averaging filter for the first-order NS modulator of Fig.32.7 with the topology shown in Fig. 32.17. We might wonder what the implementation ofthe averaging filter would look like if we had used a cascade of accumulate-and-dumpssimilar to what is shown in Fig. 31.44 (assuming the larger reduction in output clockingfrequency [ fs /K

2 instead of fs /K] and the possible aliasing isn't a concern [as discussed inSec. 31.2.2]). For a first-order NS modulator (M = 1) the desired transfer function of theaveraging filter (L = 2) was given by Eq. (32.21).

A cascade of two accumulate-and-dumps is shown in Fig. 32.19. Since z ≡ e−j2π ffs

the overall transfer function of the averaging filter is

(32.27)H(z) = 1 − z−K2

1 − z−1

This equation shows that adding a second accumulate-and-dump results in averaging K2

samples while not providing a reduction in the first side lobe's amplitude. Because thebandwidth of the filter is reduced using this topology, we get a corresponding reduction inquantization noise on the output of the filter (and corresponding increase in theattenuation when looking at a fixed frequency in the stop band). While we could modifythe cascade of accumulate-and-dumps to operate properly, with a final output clockingfrequency of fs /K, the simplicity and ease of designing the averaging filter using thetopology of Figs. 32.17, 31.54, or 31.56 makes them the topology of choice, in mostsituations, for a NS modulator averaging filter.

The time interval we average the output of the modulator over is related to theorder of sinc averaging filter as shown in the following two examples. A time intervallonger than KTs is used when L .≥ 2

Example 32.5Determine the time-domain impulse response of a first-order averaging filter (L =1) with K = 8. Assume decimation is not employed in the filter.

The transfer function of the filter is given, after reviewing Eqs. (31.89) and(31.90), by


Figure 32.19 Problems with cascading accumulate-and-dump circuits.

In Out

clk clk clk

Accumulate-and-dumps

f sf s/K fs/K2

1 − z−K

1 − z−11 − z−K2

1 − z−K

H(z) = 1 − z−8

1 − z−1= 1 + z−1 + z−2 + z−3 + z−4 + z−5 + z−6 + z−7

The time-domain relationship between the input and the output is then

y[nTs] = x[nTs] + x[(n − 1)Ts] + x[(n − 2)Ts] + ... + x[(n − 7)Ts]

The time-domain impulse response of the first-order averaging filter is shown inFig. 32.20. Note the rectangular shape.

Example 32.6Repeat Ex. 32.5 if a second-order averaging filter is used.

The transfer function of the filter is

H(z) =

1 − z−8

1 − z−1

2

= 1 + 2z−1 + 3z−2 + 4z−3 + 5z−4 + ... + 3z−12 + 2z−13 + z−14

The time-domain relationship is

y[nTs] = x[nTs] + 2x[(n − 1)Ts] + 3x[(n − 2)Ts] + ... + 2x[(n − 13)Ts] + x[(n − 14)Ts]

The impulse response of the second-order averaging filter is shown in Fig. 32.21.Note the triangular shape of the curve and how the impulse response of thesecond-order filter lasts twice as long as the first-order's response.


Figure 32.21 Impulse response of an L = 2 averaging filter.

time,0 1 2 3 4 5 6 7 8 9 10 11

1

12 13 14 15 16

8

y[nTs]

n/Ts

Figure 32.20 Impulse response of an L = 1 averaging filter.

time,

time,

Impulse input

0

0 1 2 3 4 5 6 7 8 9 10 11

1

1 Output

y[nTs]

n/Ts

x[nTs]

n/Ts

Analog Sinc Averaging Filters using SPICE

It can be very useful to simulate the operation of a sinc averaging filter of the form

(32.28)H(z) =

1K

1 − z−K

1 − z−1

L

Implementing this filter using digital circuits can result in long simulation times. Also, theoutput of the filter will be digital requiring the use of a DAC to reconstruct the analoginput voltage. While in an actual chip design we may (will) want to simulate the actualcircuit fabricated (the digital implementation of the filter), it is still nice to have acomputationally efficient, ideal, filter for fast simulations during the development of themodulator.

After reviewing Fig. 32.10, and the associated discussion, we see that we can passthe output of the modulator directly through an analog filter to reconstruct the analoginput voltage (with the unwanted quantization noise). Using an analog filter eliminates theneed for an additional DAC and makes observing the resulting modulator/filter outputsimulation spectrum straightforward. The question now becomes, "How do we make asimple sinc-shaped analog filter that models the digital implementation?"

We saw in Fig. 31.53 that a digital comb filter has a transfer function of .1 − z−K

We also saw, in Ch. 30, that we can implement an analog comb filter using a transmissionline, Fig. 30.11. Here we attempt to use the simple circuit shown in Fig. 32.22a toimplement a comb filter in SPICE. The integrator, Fig. 31.33, can be implemented using asimilar topology and is shown in Fig. 32.22b. To get a filter with a continuous-time


OutIn

Transmission line delay of (a)

Figure 32.22 (a) Implementation of a comb filter in SPICE and (b)implementation of an integrator.

OutIn

(b)

1

Voltage controlled voltage sourceused for summing.

Used as an inverting buffer

Transmission line

1

1

KTs

KTs

H(z) = 1 − z−K

Ts

H(z) = 11 − z−1

transfer function equivalent to Eq. (32.28) (see Eqs. [31.100] and [31.101]) we cancascade L of these sections. The resistors used on the output of the transmission lines, inFig. 32.22, are used to terminate the transmission lines. The following exampledemonstrates the implementation of a sinc averaging filter in SPICE.

Example 32.7Generate a SPICE model for the digital filter used with the first-order modulatorof Fig. 32.7. Assume, as in Ex. 32.4, that K = 16. Specify the droop in the outputwhen an input sinewave has a frequency of B.

In this modulator the clocking frequency is 100 MHz (Ts = 10 ns). The delay in thecomb filters is 160 ns, while the delay in the integrators is 10 ns. The SPICE netlistis shown below. Note how the input to the filter is isolated using a buffer, and theintegrators are isolated by the comb filters. The output is scaled at the end of thenetlist to 1/K2 to normalize the filter's gain (see Fig. 31.46).

The simulation results are shown in Fig. 32.23. The input to the filter is a 1-Vsinewave that is swept from DC to 50 MHz (= fs /2). The droop at B (= 100MHz/(2 16) = 3.125MHz) is 7.8 dB (which matches what was predicted in Fig.⋅31.46).

* Figure 32.23 CMOS: Mixed-Signal Circuit Design *

.AC LIN 1000 1k 50MEG

*WinSPICE command scripts*#destroy all *#run*#set units=degrees**#plot db(vo2) ylimit 30 0*#plot db(vout) ylimit 0 -60

Vin Vin 0 DC 0 AC 1

*Input bufferEbuf1 Vobuf 0 Vin 0 1

*Comb filter 1EC1 Vo1 0 Vobuf Vf1 1TC1 Vobuf 0 Vf1 0 ZO=50 TD=160nRC1 Vf1 0 50

*Integrator filter 1EI1 Vo2 0 Vo1 Vb1 1TI1 Vo2 0 Vf2 0 ZO=50 TD=10nRI1 Vf2 0 50EB1 Vb1 0 0 Vf2 1

*Comb filter 2EC2 Vo3 0 Vo2 Vf3 1TC2 Vo2 0 Vf3 0 ZO=50 TD=160nRC2 Vf3 0 50


*Integrator filter 2EI2 Vo4 0 Vo3 Vb2 1TI2 Vo4 0 Vf4 0 ZO=50 TD=10nRI2 Vf4 0 50EB2 Vb2 0 0 Vf4 1

*Scale the output by 1/K^2 (1/256=0.00390625)Ebuf2 Vout 0 Vo4 0 .00390625

.end

Using our SPICE Sinc Filter Model

The analog sinc averaging filter model we've just developed is difficult to use in a practicalsimulation for several reasons. To begin with, the actual shape of the pulses (their rise-and fall-times together with the over- and under-shoot in the pulse shape) coming out ofthe modulator is now important where, in a digital implementation, it is not. The frequencycontent of the analog pulse stream differs from the spectral content of the digital data.This leads to analog sinc filter output waveforms with distortion that wouldn't be found inthe output of the digital sinc filter. For a digital implementation a modulator outputrisetime of 1ns is no different from a rise-time of 100 ps. In the analog implementation,however, the rise-time does matter (consider what happens, in Fig. 32.10, if the rise-timeof the digital data coming out of the modulator is slowed down.) Also, the SPICEimplementation of the transmission lines isn't tolerant to fast pulse edge transitions. Thisleads to difficulty with convergence and, possibly, long simulation times.


Figure 32.23 Frequency response of the L = 2 sinc averaging filter.

B

Analog Implementation of the First-Order NS Modulator

A continuous time implementation of a first-order NS modulator is shown in Fig. 32.24. Ifwe write the sum of the currents through the resistors (and thus through the feedbackcapacitor) as

(32.29)iF = VCM − Vin

R+ VCM + Vout

R

then the output of the integrator can be written, assuming the input and output arereferenced to VCM , as

(32.30)VOI = iF

jωC= −1

jωRC(Vin − Vout)

where and noting how we switched the inverting and noninverting inputs of theω =2πfcomparator to compensate for the inverting gain of the integrator. Knowing, from Eq.(31.82), that

(32.31)z−1

1 − z−1= 1

−1 + cos 2π f

fs

+ j sin 2π f

fs

or, for (which must be valid for any oversampling converter) where f << f s cos 2π f

fs≈ 1

and , thensin2π f

fs≈ 2π f

fs

(32.32)z−1

1 − z−1≈ 1

j2π f

fs

Finally, we see that the topology of Fig. 32.24 behaves like a modulator with a blockdiagram of Fig. 32.6 when

(32.33)f s = 1RC

If this equation doesn't hold, the topology of Fig. 32.24 may still function correctly as aNS modulator except that the above analysis would include an integrator gain. (Which,


Figure 32.24 Analog circuit implementation of a first-order NS modulator.

CR

R

VCM

φ

VoutVin

VCM

−Vout

combined with the high-gain of the comparator, may still result in an overall forward pathgain of one. We will discuss component gains in the modulator later.)

Analog integrator-based implementations of modulators can be simpler, easier tobreadboard and test on the bench, lower power, and less susceptible to clocking noise(capacitive feedthrough and charge injection.) The two main-drawbacks are the difficultyin setting the integrator gain to a precise value (in integrated versions) and the integratorssusceptibility to the fedback pulse shape (a problem also encountered using the analog sincfilters of the last section).

Using a DAI, the gain of the integrator is set by a ratio of capacitors, see Fig.31.79 (and Ch. 27). Variations in the absolute oxide capacitance for a given process rundon't affect the integrator's gain. Using the analog integrator, in a purely monolithic form,however, can result in RC time constant variations of 50% or more.

Figure 32.25 shows how the shape of the pulse affects the output of the analogintegrator. In (a) we see the ideal pulse shape and the ideal area under the pulse (theshaded area). In (b) we see how the finite rise time and fall time can affect the actual areaunder the curve and thus the output of the integrator. To minimize these unwanted effectswe can use wider pulses as shown in (c) and (d), which means we run the modulator at aslower clocking frequency. Increasing the width of the pulses minimizes the percentage ofthe area affected by the transition times. Note that the feedback signal directly subtractsfrom the input signal so that any noise or unwanted variation in the fed back signal, suchas an amplitude variation, can be considered as adding noise to the input (and thusdegrading the modulator's SNR). This is important! We will discuss the fed back signal,and how to isolate/implement the actual voltage fedback to the integrator, again in thenext section.

The DAI is less susceptible to the pulse shape fed back from the comparator.Reviewing Fig. 32.7 we see that as long as the output of the comparator can charge ordischarge the switched capacitor to within the final resolution of the converter, before the

switches turn off, the circuit functions as expected. Note that the comparator, having aφ2


Figure 32.25 Comparator output pulse shapes, input to the integrator.

Ideal shape Shape with under-and overshoot(ideal area is

shaded)

Ideal area

(a) (b)

(c) Wider, ideal, pulse shape

(d) Increasing pulse width (goingslower) to minimize nonideal pulsecharacteristics.

digital output, doesn't limit the rate the switched capacitor is charged but rather thelimiting factor is the op-amp (since the top plate is tied to the op-amp's inverting input andcharged from the op-amp's output through the feedback capacitor).

The Feedback DAC

Up until this point we have been feeding the output of the comparator directly back to theintegrator. This works fine as long as the logic "1" (VDD) or logic "0" (ground) voltagesare clean (have no noise on them). Noise on these fed back voltages directly adds orsubtracts from the input signal and thus decreases the modulator's SNR. In any practicalmixed-signal integrated circuit the digital supply and return are noisy with variations in thehundreds of mV common. As discussed in Ch. 28, it is common to separate the analog anddigital power supplies on-chip (and so the modulator should be powered with the analogsupply). Because of this, and the desire to set the fedback voltage and VREF+ VREF−independent of VDD and ground, the output of the comparator is often connected to thesimple one-bit DAC circuit shown in Fig. 32.26. It's important to remember that theoutput of the DAC must be able to charge the integrator's input switching capacitance (seeFig. 32.7) to within the final desired resolution of the converter in half a clock cycle(before the switches open).φ2

Understanding Averaging and the Use of Digital Filtering with the Modulator

In the following discussion we assume, as before, that and VREF+ = VDD = 1.5 V VREF− =ground . We also assume the input voltage to the modulator falls within(1 LSB = 1.5 V)VDD and ground so that the output of the modulator doesn't saturate in a string of ones orzeroes (more on this below). In this section we want to discuss, intuitively, the operationof the digital filter used on the output of the modulator (see Fig. 32.9).

Before discussing the digital filter let's remember that we can recover the analoginput voltage using an analog filter as shown in Fig. 32.10. This means that if the output ofthe modulator is a continuous string of zeroes, then the output of the analog filter will bezero volts. Other possible modulator outputs and their averages are shown in Fig. 32.27.


Figure 32.26 One-bit DAC for use in a NS modulator.

To integrator To comparator

Decoupling capacitor (may be an NMOS device)VREF+

VREF−

1 LSB = VREF+ − VREF−

Example 32.8Plot the ideal input/output transfer curve for the 1-bit DAC. Also plot thenon-ideal transfer curve if (instead of 1.5 V). Comment on how theVREF+ = 1.45 Voutput of the NS-modulator/decimator (the data converter) will be affected.

The transfer curves are shown in Fig. 32.28. The offset in the positive referencevoltage results in a gain error in the data converter (but no nonlinearity).

Next let's consider the case where the modulator's input is a DC signal and ourdata converter's resolution is only limited by the number of samples we can take in a giventime, KTs . Equation (32.12) shows that as K approaches infinity, B approaches zero (DC).Figure 32.14 shows that at DC the spectral density of the modulation noise is zero.Feeding the output of our first-order modulator to a single accumulate-and-dump, seeFigs. 31.39 and 31.41, can provide the needed digital filtering. As seen in Fig. 31.41,


Figure 32.27 Modulator outputs and their corresponding averages.

Mod

ulat

or o

utpu

t

0

0

1.50

1.5

8 16 24 32 40

Average =

Average =

Average =

0

1.5

0

1.5

Average =

Average =

0

1.5Average =

(Repeats every 32)

0 V

1.58

(7)⋅(1.5)8

(31)⋅(1.5)32

1.52

= 0.75

1.54

= 0.375

Figure 32.28 Ideal and nonideal transfer curves for the one-bit DAC and comparator cascade.

Ideal

Nonideal

1.5

1.50.750

0 Comparator input, V

Out

put,

V

increasing K causes the filter's amplitude response at DC to increase (the number of bitscoming out of the counter increases) and the side lobes move towards DC. Also, as seenin Fig. 31.58b, we don't have aliasing at DC so the reduction in output clocking frequency(decimation) to can be accomplished with the single accumulate-and- dump stagef s/KHowever, there may still be aliasing from higher frequencies. Note that we have justdescribed a first-order NS modulator driving a counter where the counter, is reset andread-out every KTs clock cycles and clocked at a rate of fs . Practically, for large K, thelimiting factor in the resolution of the NS modulator is the noise inherent in the circuit(mainly thermal and flicker noise sources from the MOSFETs) and, more importantly, thefinite gain and linearity of the op-amp (more on this later). Note that in our perfectmodulator a single output going high out of one-million outputs would correspond to anaverage input voltage of only . This would also mean that we would need to15 µVaverage at least one-million and one (1,000,001) modulator outputs with our simplecounter for a constant output.

In our cascade of two accumulate-and-dumps, Eq. (32.27) and Fig. 32.19, weaverage K2 samples. The cascade behaves, from a frequency response point of view, like asingle accumulate-and-dump. For the cascade of L sinc filters, however, the number ofmodulator outputs averaged is

(32.34)Number of modulator outputs averaged = L ⋅ K − 1

As we saw in Ex. 32.6, the cascade of sinc filters results in a weighted average of thefilter's inputs. For our first-order modulator of Fig. 32.7 and the digital filter of Fig. 32.17with a transfer function, once again, of

(32.35)H(z) =

1 − z−16

1 − z−1

2

we perform a weighted average on 31 of the modulator's outputs. The time-domainimpulse response of this filter (without decimation), again see Ex. 32.6, is given by

y[nTs] = x[nTs] + 2x[(n − 1)Ts] + 3x[(n − 2)Ts] + ... + 15x[(n − 14)Ts] + 16[(n − 15)Ts] +

(32.36)15x[(n − 16)Ts] + 14x[(n − 17)Ts] + ... + 2x[(n − 29)Ts] + x[(n − 30)Ts]

For a continuous filter input of "1" the output of the filter is 256. Note that this is the sameresult we get with the cascade of two accumulate-and-dumps and is the "gain" ( KL ) of thefilter at DC. For our current discussion the minimum resolution we can represent with themaximum output value of 256 (realizing the minimum output value, which corresponds toa continuous modulator output of all zeroes, is 0) is . We want this(1.5)/256 = 5.86 mVvalue to be less than the resolution calculated in Ex. 32.3, which was 6.14 bits (1.5/26.14 =21.27 mV) so that our modulation noise, for a given bandwidth, limits the data converter'sresolution and not the digital filter. This is why adding an additional sinc filter stage (say,L = 3) will not increase the data converter's resolution. The fundamental way to increasethe first-order modulator's resolution is to increase the number of samples averaged (theoversampling ratio), K. Note also, that increasing L will have the undesirable effect ofincreasing droop in the bandwidth of interest.


Example 32.9If the desired input to an ideal first-order NS modulator is a DC signal, would it bebetter to use a single sinc filter (a counter or accumulate-and-dump) or a cascadeof two sinc filters of the form given by Eq. (32.35)?

Equation (32.20) was derived assuming we wanted to maximize the input signalbandwidth, B. If we are measuring a DC signal with, ideally, zero-bandwidth, thenwe want to minimize the digital filter's bandwidth to remove unwanted noise thatmay corrupt the DC signal. This means, for higher resolution with correspondinglylonger conversion time, the single-stage filter is the best choice.

In Fig. 32.17 we indicated that the word size coming out of the filter, afterdropping the lower two-bits, is seven-bits. This means, in two's complement, that outputsof 011 1111 (+63), 100 0000 (−64), and 000 0000 (0) correspond to the maximum input

), minimum input ( ), and common-mode voltage (VCM = 0.75 V)(VREF+ − 1 LSB VREF−respectively, see Fig. 31.37. A continuous modulator output of "1" would correspond toan input of VREF+ , which would be outside the possible digital filter output words andresult in the incorrect filter output code of 100 0000. Note that here

, which is, again, below the 21.27 mV fundamental1 LSB = (VREF+ − VREF−)/27 = 11.719 mVRMS noise limit of the modulator in a bandwidth, B.

Next, let's consider the situation where one out of every 64 modulator outputs is alogic one (and the sequence repeats indefinitely). As we saw in Fig. 32.27, averaging thisoutput results in an analog voltage of 1.5/64 or 23.44 mV. Using Eq. (32.36) we can writethe sequence of digital filter outputs (in decimal form and assuming our single pulse inputto the filter marks the beginning of the output) without decimation as

1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0, (followedby 32 more zeroes and then the sequence repeats itself.)

If decimation is employed, as in Fig. 32.17, then the outputs of the filter look like

1,15,0,0 (summed = 16)

noting that shifting in time doesn't change the sum of the sequence if the samples outputby the decimation process are spaced apart by 16 ( K ). For example, the sequence

4,12,0,0 (summed = 16)

also has the same sum of 16. Figure 32.29 shows plots of our modulator input and thereconstructed filter output. Our modulator input is a constant DC signal of 23.44 mVwhile, at the same time, the digital filter output is a repeating sequence. What we areseeing is the ripple associated with passing the output of the modulator through the filter.Additional filtering, including the RCF, will reduce the ripple (because of the reduction inbandwidth). We should point out that this ripple represents a major difference betweenNyquist rate data converters and oversampling converters. Note how averaging 4 outputsamples after decimation or 64 samples before decimation results in the digitalreconstructed output value matching the input value.


Figure 32.30 shows the output of an RC filter, with a time constant of 1µs, whenconnected to the output of the modulator of Fig. 32.7. The modulator input voltage is23.44 mV. The analog RC filter, like the digital filter, will not totally filter out the higherfrequency components of the modulation noise and thus there will be some ripple on theoutput signal. Again, as in the digital filter, reducing the bandwidth of the filter (increasingthe time constant) will reduce the peak-to-peak amount of ripple.

Example 32.10What are the 7-bit, two's complement, representations of the numbers in Fig. 32.29assuming they are originally represented using 9-bit, two's complement, words asin Fig. 32.17? What is the four sample average of these words?


1

15

5.86 mV

87.9 mV

23.44 mV

16 32 48 64 96 128 14480

Dig

ital f

ilter

out

Figure 32.29 Ripple in the output of a digital filter. Note how theaverage of the filter output is equal to the input voltage.

Sample number

Decimated output

Input voltage

Figure 32.30 Showing how we have ripple on the output of an analog filter connected to a modulator with a DC input.

The 9-bit two's complement representations of 0, 1, and 15 are 1 0000 0000, 10000 0001, and 1 0000 1111, respectively. Dropping the lower two bits andknowing, for our 7-bit representation that , results in 100 00001 LSB = 11.719 mV(0), 100 0000 (0), and 100 0011 (VCM − 61 = 35.157 mV). Averaging⋅11.719 mVthe filter outputs, as we did in Fig. 32.29, results in a value of 8.79 mV, which isdifferent from the input voltage of 23.44 mV. By dropping the lower 2 bits weactually lost resolution. This can be confusing until we remember that at DC thepossible resolution of the ideal modulator and digital filter is infinite. Over abandwidth, B, however the resolution of the converter is limited to less than 7 bitsas discussed in Ex. 32.3. Not throwing out the two lower bits is useful if additionaldigital filtering is used in the mixed-signal system. Otherwise the two lower bits arejust random values (noting that when we averaged the four samples in Fig. 32.29 itwas equivalent to passing the digital data through an additional low-pass, sincaveraging filter with K = 4).

Pattern Noise from DC Inputs (Limit Cycle Oscillations)

The ripple on the output of the filter can cause noise in the base spectrum of interest. Thefrequency of the ripple and the amplitude of the ripple depend on the DC input value. Ascompared with Fig. 32.30, Fig. 32.31 shows the RC filter output if the modulator input ischanged to 0.75 V (the common-mode voltage.) The frequency of the ripple is higher andthe peak-to-peak amplitude of the ripple is smaller. The modulator output, with an inputof 0.75, is a square wave of alternating ones and zeroes. The first harmonic of this signal isat half the clocking frequency or, in this example, 50 MHz. Since the ripple frequency lies


Figure 32.31 Filter ripple when input is the common-mode voltage of 0.75 V.

outside our base spectrum (which, from Ex. 32.3, is from DC to 3.125 MHz) it will not, ina significant way, affect the SNR. (In the digital filter a zero in the digital filter's transferfunction will most likely fall at half the clocking frequency eliminating the ripple altogetherand resulting in a constant filter output value.) The frequency of the ripple in Fig. 32.30,however, is 1/640 ns or 1.564 MHz, which is well within our base spectrum. The resultingtone will lower the SFDR and the SNR of the data converter. The question now becomes,"How do we minimize the possibility of unwanted tones appearing in the data converter'soutput spectrum?"

If we look at the digital filter output data shown in Fig. 32.29 we see that the"ripple" amplitude of the digital data is fully 87.9 mV peak-to-peak or significantly abovethe data converter's LSB value (noting that after the RCF/half-band filter this ripple valuewill be reduced). Looking at this figure, we see that it would be better to spread or flattenthe data out over all four cycles of the repeating waveform. Although we may still have atone, or repeating sequence, at a frequency in the base spectrum the amplitude of the tonewill be well below the LSB of the data converter (and so it won't affect the SFDR of thedata converter). To accomplish this spread or randomization we can add a noise dithersource (see the last chapter) to our basic NS modulator as seen in Fig. 32.32.

The output of the modulator in our discussion and generation of Fig. 32.29, was asingle bit going high followed by 63 zeroes as shown in Fig. 32.33a. Note how the periodof the output is repetitive. If our dither source is used, the output may look something likewhat is seen in Fig. 32.33b. The average of the waveform, over several cycles, is the sameas in (a), while the period of the waveform varies and randomizes the power contained in aparticular frequency (tone). What this means is that the output spectrum of a dataconverter, with a DC input, will not contain tones at specific frequencies sticking up abovethe noise floor and resulting in a decrease in the SFDR. However, the peak-to-peakamplitude of the ripple, in the time-domain, may actually get worse. As seen in Fig.32.33b, the occasional shorter spacing between the output ones can result in a largerdigital filter output code. Again, we should point out that this variation, or ripple, in theoutput code is a basic difference between a NS modulator-based data converter and aNyquist-rate data converter.


1p

1p

Figure 32.32 Adding a dither source to a first-order NS modulator.

DitherSource

VCM

VCM

VCM

φ1 φ2φ1

Vin

Vout

As a final example, let's consider how a tone can occur in a modulator output thathas heavy transition densities (numerous one-zero transitions.) If the input to themodulator is the common mode voltage, VCM , of 0.75 V, then the output of the modulatoris an alternating sequence of ones and zeroes. Changing the input voltage upwards by asmall amount will result in the output of the modulator staying high once in a while insteadof going low (resulting in two consecutive logic one outputs). An example is seen in Fig.32.34 where the input to the modulator was increased to 0.77 V. As the double ones arespaced apart by approximately 350 ns, we can estimate a tone in the resulting outputspectrum at a frequency of 1/350 ns or 2.86 MHz.

Finally, note that unwanted tones are usually not a problem if the input signal isbusy and random (not DC as discussed in this section). Later in the chapter, we discusssecond-order modulators that utilize two integrators. The second integration helps tospread the repeating sequences out over a longer period of time so that, hopefully,negligible unwanted tone energy is present in the base spectrum.


Figure 32.33 Output of our modulator without (a) and with (b) a dither source.

Mod

ulat

or o

utpu

t

time

63 zeroes 63 zeroes 63 zeroes 63 zeroes

Output going highOutput of the modulator without dither added

(a)

Output of the modulator with dither added

(b)

time

Figure 32.34 Modulator output showing how tones can occur with higher transition density.

Two consecutive output ones

Integrator and Forward Modulator Gain

So far we haven't discussed the shape or amplitude of the integrator's output. Because weare using near-ideal components in our simulations, we haven't seen any limitations due tothe finite op-amp output swing. Figure 32.35 shows the integrator's output for the inputand output signals shown in Fig. 32.8 (using the modulator of Fig. 32.7). Clearly theoutput swing of the op-amp is beyond the power supply rails. If the transistor level modelof the op-amp were to replace the ideal op-amp, the integrator's output would saturate atvoltages less than VDD (= 1.5 V here) or greater than ground. While in some situationsop-amp saturation is not necessarily bad (the gain of the integrator goes to zero), it isdesirable to understand how decreasing forward loop gain affects the performance of themodulator. Note also, in Fig. 32.35, how the output of the integrator makes the largestchange when it passes through the comparator reference voltage, VCM = 0.75 V, since thefed-back signal, the comparator output (a full-scale signal), is input to the integrator.

Consider the linearized model of our first-order NS modulator shown in Fig.32.36. The gain of the integrator, see Eq. (31.135) or Fig. 31.79, is given by

(32.37)GI = CI

CF

We have also drawn the comparator with a gain. Up until this point we have assumed thegain of the comparator is unity. We'll comment on this more in a moment. Let's define themodulator's forward gain as


Maximum op-amp swing

Figure 32.35 Output swing limitations in the op-amp (integrator.)

0.75

(32.38)GF = GI ⋅ Gc

We can rewrite Eq. (32.4) using this gain as

(32.39)Y(z) = z−1 ⋅ GF

1 + z−1(GF − 1)⋅ X(z) + 1 − z−1

1 + z−1(GF − 1)⋅ E(z)

If GF approaches zero (the integrator saturates while the comparator gain stays finite),then the output of the modulator is the sum of the integrated input and the quantizationnoise. (This is bad.) Since the quantization noise is not spectrally shaped it will be difficultto filter the modulator's output to recover the input signal. If the forward gain is greaterthan two, then, as seen in Fig. 31.62 and the associated discussion, the poles of thetransfer function reside outside the unit circuit and the modulator will be unstable. We canrestrict the values of the forward gain to

(32.40)0 ≤ GF ≤ 2

Ideally, however, the gain is one.

Example 32.11Show, using SPICE simulations and the modulator of Fig. 32.7, that an integratorgain of 0.4 will result in an op-amp output range well within the power supplyrange.

Figure 32.37a shows a schematic of the modulator with GI = 0.4. Figure 32.37bshows the output of the integrator (the output of the op-amp) in the modulator of(a) with the input sinewave shown in Fig. 32.8. The output swing is limited toroughly 80% of the supply range. For general design it is desirable to set ourintegrator gain to 0.4. This ensures our integrator doesn't saturate unless the inputto the modulator goes outside the supply voltage range.

It's interesting to note that in both modulators, Fig. 32.7 and Fig. 32.37, theforward gain is unity. This is a result of the effective gain of the comparatorchanging forcing the forward gain, controlled by the fedback signal, to unity. Whatthis means is that our modulator functions as expected with a signal gain of one(Eq. (32.4) is valid) whether GI is 1 or 0.4. We discuss how this change incomparator gain occurs next.


Figure 32.36 Block diagram of a noise-shaping (NS) modulator showing forward gains.

OutIn

ADC

z−1

1 − z−1

E(z)

X(z) Y(z)GcGI

GF = GI ⋅ Gc

Figure 32.38a shows the transfer curves for the comparator. The x-axis, thecomparator input, is the output of the integrator in our modulator. Shrinking theintegrator's output swing while holding the output swing of the comparator at the supplyrails (1.5 V) results in an increase in effective comparator gain. This gain variation, withthe integrator output swing, helps to set the forward gain of the modulator to precisely 1.We can write this using equations as

(32.41)

Integrator gain, GI

Integrator outputModulator input

⋅

Comparator gain, Gc

Comparator(modulator) outputIntegrator output

=

GF

Modulator outputModulator input


(a)

Figure 32.37 (a) First-order NS modulator with an integrator gain of 0.4 and (b)the output of the op-amp.

(b)

1p

0.4p Clocked comparator

VCM

VCM

VCM

φ1 φ2φ1

Vin

Vout

f s = 100 MHz

If the modulator is functioning properly, then the average value of the modulator outputwill be equal to the modulator input and thus GF = 1. It's interesting to note that this result(precise integrator gain isn't important) will apply to any integrator that is directlyfollowed by an ADC.

Before leaving this section, let's point out a couple of problems with a noise-shaping modulator that uses a multi-bit ADC, Fig. 32.39. Since the output of theintegrator is the input signal to the ADC, the limited integrator output swing will directlyaffect the range of ADC output codes. Limiting the range of ADC output codes will thenlimit the allowable range of modulator inputs unless scaling is used (shifting the outputcodes or sizing of capacitors in the DAI). Next, notice in Fig. 32.39 how the variation inthe gain of the ADC, with input signal, is more limited than the gains attainable with thesimple comparator of Fig. 32.38. Limiting the range of ADC gains can result in modulator


1.5

1.50.750

0 Comparator input, V

Out

put,

V

Figure 32.38 Comparator gain as a function of input voltage.

Input signal

Gain is the slope of these lines.

000

001

010

011

100

101

110

111

Digitaloutput code

0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 8/8

Figure 32.39 A 3-bit ADC.

Analog input voltage (integrator output)

Dashed lines indicate ADC gain

forward gains that are not exactly unity. This is especially true at high input frequencieswhere the gain of the integrator is low. However, if the integrator gain is high, theeffective gain of the ADC is not important. The point here is that using a multi-bit ADCwill increase the open-loop gain requirements of the op-amp used in the integrator.

Comparator Gain, Offset, Noise, and Hysteresis

It's of interest to determine how the performance of the comparator affects the operationof the modulator. Both the comparator's offset and input-referred noise, Fig. 32.40a, canbe referred back to the modulator's input, Fig. 32.40b. By doing so we can determine howthey effectively change the input signal seen by the modulator. As seen in Fig. 32.40, thehigh gain of the integrator, A( f ), reduces the effect of the comparator's noise and offseton the input signal. For example, if the gain of the integrator at DC is 1,000 and the offsetvoltage of the comparator is 50 mV, then the input-referred offset is only 50 µV.

To determine the minimum gain and maximum allowable hysteresis requirementsof the comparator, let's review Fig. 32.37. We see that when the output of the comparatorchanges states, the output of the integrator changes by at least

(32.42)Change in integrator output = GI ⋅ (VDD − VCM) = CI

CF⋅ VREF+ − VREF−

2

For the modulator of Fig. 32.27 this equation can be evaluated as 0.3 V. As long as thehysteresis is much less than this value and the gain of the comparator (1.5/0.3 or 5) islarge enough so that the comparator can make a full output transition with this inputdifference then the modulator will function properly. Very simple, low-performancecomparator designs can be used while not affecting the modulator's performance.

Op-Amp Gain (Integrator Leakage)

Now that we've discussed the gain of the comparator, let's determine how high theopen-loop gain of the op-amp must be for proper integrator action. With low op-ampgain, some of the charge stored on the integrator's input capacitor, CI , is not transferredto the feedback capacitor, CF . This loss of charge is sometimes referred to as integratorleakage. The charge on the input capacitance effectively leaks off when it is transferred tothe feedback capacitance.


A( f )

Figure 32.40 Referring the comparator offset and noise (a) to the input of the modulator (b).

IntegratorComparator

Comparator's input-referred

In Out


Input-referred noise and offset,

In Out

(a) (b)

noise and offset,

A( f )

Vn,comp( f ) Vn,comp( f )/A( f )

We can write the open-loop, frequency dependent gain of the op-amp as AOL( f ).The output voltage of the op-amp is then , where is ourvout = AOL( f )(v+ − v−) v+common-mode voltage VCM (the noninverting terminal of the op-amp), see Fig. 31.78, and

is the op-amp's inverting input terminal. Following the procedure to derive Eq.v−(31.134), we can rewrite Eq. (31.132) with finite op-amp gain as

(32.43)Q2 = CI VCM − vout[nTs]

AOL( f )− v2[nTs]

or, rewrite Eq. (31.134) to include the effects of finite op-amp gain, to get

(32.44)Vout(z) = CI

CF⋅ V1(z) ⋅ z−1/2 − V2(z)

1 + CI

CF

1AOL( f )

− z−1

Using this result in Eq. (32.3) and, as discussed in the last section, assuming the forwardgain of the modulator, GF , is one gives

(32.45)Y(z) = z−1

1 + CI

CF

1AOL( f )

⋅ X(z) +1 + CI

CF

1AOL( f ) − z−1

1 + CI

CF

1AOL( f )

⋅ E(z)

The gain error term

(32.46)εgain = CI

CF⋅ 1

AOL( f )

is ideally zero so that Eq. (32.45) reduces to Eq. (32.4). Note how reducing theintegrator's gain, CI / CF , reduces the gain error while increasing the gain required of thecomparator. Note also how the denominator term is common in both the signal and thenoise. This term will result in a data converter gain error (it behaves as if it were anop-amp offset voltage that is a function of the integrator's output amplitude [which resultsin the gain error] and frequency), but it will not affect the modulator's SNR. To determinethe increase in the modulator's output noise (the change in the shape of the modulationnoise) we need to look at the noise transfer function including the effects of the gain error

(32.47)NTFε(z) = (1 + εgain) − z−1

or, in the frequency domain,

(32.48)NTF( f ) 2 = 2(1 + εgain) 1 − cos 2πff s

+ εgain

2

Following the same procedure used to arrive at Eq. (32.15) and assuming constantop-amp gain, AOL( f ), from DC to B results in

(32.49)VQe,RMS2 = 2 ⋅

VLSB2

12f s⋅ 4(1 + εgain)π2

f s2

⋅ 13

⋅

f s

2K

3

+ εgain2 ⋅ f s

2K

noting that if , this equation reduces to Eq. (32.15). εgain = 0


If we assume the contribution to the noise from the error term squared, , isεgain2

small, which is valid for op-amp gain

(the oversampling ratio) (32.50)AOL( f ) > K

over the frequency range of DC to B, then we can rewrite Eq. (32.16), to include theeffects of finite op-amp gain, as

(32.51)SNRgerr = 6.02N + 1.76 − 20 log π3

+ 20 log K3/2 − 10 log (1 + εgain)

The largest degradation in the SNR, resulting from integrator leakage, can be estimated as0.5 dB if K 8 ( 1/8 neglecting GI ). The gain bandwidth product of the op-amp is≥ εgain ≈ ⋅estimated as

(32.52)Op-amp unity gain frequency, fu = K ⋅ B = f s/2

assuming the op-amp is rolling off at 20 dB/decade at B (a dominant pole compensatedop-amp). Otherwise, the minimum gain of the op-amp can be estimated simply as theoversampling ratio, K.

To illustrate typical op-amp requirements, let's consider the modulator of Fig.32.37 with K = 16 and B = 3.125 MHz (see Ex. 32.3). The fu of the op-amp is estimated,using Eq. (32.51), as 50 MHz. If the open-loop response of the op-amp starts to roll-off at10 kHz, then the DC gain of the op-amp must be at least 5,000. However, we could alsouse an op-amp with a DC gain of 100 (remembering low integrator gain increases theundesirable effects [noise and offset] of the comparator on the performance of themodulator) that rolls-off at 500 kHz.

Op-Amp Settling Time

Equation (32.52) can be used, for the moment, to provide an estimate for the settling timerequirements of the op-amp in a first-order modulator. Assuming the settling time is linear,and not slew-rate limited, we can write the change in the op-amp's output (assuming adominant pole compensated op-amp, see Eqs. [27.37] and [27.38]) as

where (32.53)vout = Voutfinal(1 − e−t/τ) τ = 12πfu ⋅ β

where, for the DAI (see Fig. 32.41), the feedback factor is

(32.54)β = CF

CF + CI

The feedback factor is 0.714 in the modulator of Fig. 32.37. The output of the DAI, vout ,must settle in a time, t (< Ts /2), to some percentage of an ideal value, Voutfinal. Solving forthis percentage using Eqs. (32.52), (32.53), and (32.54) and assuming results inTs/2 = t

(32.55)vout

Voutfinal× 100% = 1 − exp

−π

2⋅ CF

CF + CI

× 100%


The output will only reach 67% of its ideal final value in the modulator of Fig. 32.37 whenthe op-amp used has a unity gain frequency of fs /2.

In deriving Eq. (32.55) we used an op-amp unity gain frequency specified by Eq.(32.52) to determine the settling response of the integrator. If the settling is linear thenincomplete settling will result in a constant DAI gain error (0.67 above). Every time theoutput changes it will change by some constant percentage of its ideal value. Rewriting thetransfer function of our DAI to include this constant gain error results in

(32.56)Vout(z) = CI

CF⋅

Settling gain error, Gs

(1 − e−πβ⋅(fu/fs )) ⋅V1(z) ⋅ z−1/2 − V2(z)1 − z−1

Full, or complete, settling requires the op-amps unity gain frequency, fu , be much largerthan the sampling frequency fs (in other words we can't use Eq. [32.52] to specify therequired bandwidth of the op-amp if settling time is important). The constant gain error,resulting from incomplete settling, can be tolerated in the first-order modulator becausethe integrator is directly followed by a comparator, as discussed earlier. In some of themodulator topologies, though, the integrator is not followed by a comparator so settlingtime becomes more important. To determine to what percentage the integrator outputmust settle in these topologies a gain term, say Gs , is added to the linearized blockdiagram of the modulator (integrator). The transfer function of the modulator is thenevaluated to determine the allowable values of Gs for the application.

It's important to realize that we are assuming the op-amp doesn't experienceslew-rate limitations. If slewing is present then the added gain term, in Eq. (32.56), willnot be a constant and will introduce distortion into the modulator's output spectrum(whether a comparator follows the integrator or not).

Op-Amp Offset

The operation of the DAI is subject to the op-amp's offset. It can be shown that this offsetwill effectively add (or subtract) from the common-mode voltage, VCM , and thuseffectively shift the input signals upwards or downwards. The resulting modulator outputwill then show an offset equal to the op-amp's offset. To circumvent this problem, offsetstorage can be used in the integrator.


Figure 32.41 The feedback factor in the DAI.

CF

CI vout

vf

β ⋅ vout = vf = voutCF

CI + CF

Op-Amp Input-Referred Noise

We'll discuss the calculation of the DAI input-referred noise (with power-spectral density,PSD, of ), at the transistor level, in the next chapter. Here we discuss how theVn,DAI

2 ( f )DAI's unwanted noise contributions affect the SNR of the modulator, assuming we know

. Figure 32.42 shows the modulator's input-referred noise source, , inVn,DAI2 ( f ) Vn,ckt( f )

series with the input signal. This noise source, with units of V/ , includes both theHzintegrator's and the comparator's contributions. However, as discussed earlier, the noisecontributions from the comparator are usually negligible.

Because the modulator's input-referred noise adds directly to the input signal, wecan use the derivations developed earlier in the chapter. As specified in Eq. (32.4), themodulator's input, and thus its input-referred noise, pass through the modulator with adelay of z-1. If we assume the modulator's input-referred noise is white and bandlimited tofs /2 such that

for (32.57)Vn,ckt( f ) = Vn

fs

f < f s/2

then passing the output of the modulator through an ideal low-pass filter with a bandwidthof B ( = fs /[2K] ) results in

(32.58)Vckt,RMS = 2 ⋅ ∫0

BVn

2

fs⋅ df = Vn

K

Noting that not passing the output of the modulator through a low-pass filter results in anRMS output noise of Vn , we see that the averaging filter (the low-pass filter) reduces thenoise by the root of K. We could also think of the filtering as reducing the PSD of themodulator's input-referred noise by K. Remembering the jitter discussion from the lastchapter, we see a direct parallel in the derivations of how averaging affects the RMS valueof a random signal (noise or jitter).

Finally, as used in Ex. 31.15, we can estimate the finite SNR of a data converterfrom quantization noise, jitter, and circuit noise using

(32.59)Vn,RMS = VQe,RMS2 + Vjitter,RMS

2 + Vckt,RMS2


In


Out

Figure 32.42 The modulator's input-referred noise contributions from both thecomparator and the integrator.

Modulator's input-referred noise, Vn,ckt( f ) = Vn,DAI2 ( f ) + Vn,comp

2 ( f )

and

(32.60)SNR = 20 ⋅ logVp/ 2Vn,RMS

where Vp is the peak amplitude of an input sinewave (see Eq. 31.1) and

(see Eq. [31.47]) (32.61)Vjitter,RMS = PAVG,jitter

Practical Implementation of the First-Order NS Modulator

As discussed in Ch. 27, switched-capacitor circuits suffer from the problems of capacitivefeedthrough and charge injection. To reduce these effects, fully-differential circuittopologies are used. It could be stated that if reasonable size capacitors and dynamic rangeare required, fully-differential topologies are a necessity simply because they subtract out,to a first-order, the voltage changes on the switched-capacitors resulting from theseproblems. In addition, again as discussed in Ch. 27, fully-differential topologies are usedbecause they improve power supply and substrate-coupled noise rejection, and improvedistortion (even-order harmonics cancel).

Figure 32.43 shows the fully-differential implementation of the DAI of Fig. 31.78.The inputs are now differential, that is, now and , as is thev1 = v1+ − v1− v2 = v2+ − v2−output of the integrator, . The fully-differential DAI has the samevout = vout+ − vout−transfer function as the single-ended DAI assuming the input signals are differential.

It's important to understand the signal levels in the fully-differential DAI. Let'sassume VCM = 0.75 V and the input voltages can range in amplitude from 0 to 1.5 V.Assuming the input is balanced correctly if , then must equal 0.65 V. Thev1+ = 0.85 V v1−

maximum input voltage is v1max= 1.5 − 0 = 1.5 V. The minimum input signal, on the otherhand, is v1min = 0 − 1.5 = −1.5 V. The range of inputs, or outputs, is then 3 V or twice therange of the single-ended DAI.


Figure 32.43 Fully-differential discrete-analog integrator (DAI) implementation.

VCM

CFφ1 φ2

CI

vout+

CF

vout−

CI

v1+

v1−

v2+

v2−

Vout(z) = CI

CF⋅ V1(z) ⋅ z−1/2 − V2(z)

1 − z−1

Figure 32.44 shows the implementation of a first-order NS modulation utilizing afully-differential DAI. Figure 32.45 shows the SPICE model used for a differentialinput/output op-amp (see also, Fig. 26.29). We'll use this model to simulate the operationof the modulator of Fig. 32.44 with the input signals and capacitor sizes used in Fig. 32.37( fs = 100 MHz, CI = 0.4 pF, and CF = 1 pF, fin = 250 kHz, and a 0.7 V peak inputsinewave [the input sinewave, , has a peak amplitude of 2.8 V]).Vin+ − Vin−

Figure 32.46 shows the simulation results for the outputs of the modulator of Fig.32.44 after being passed through two RC filters with time constants of 100 ns. Passing asingle modulator output to the decimating filter would result in an output that is half theinput signal amplitude, which can be compensated for at the output of the filter by ashift-left operation (multiply by two). Note, because the gain of the integrators is 0.4, theintegrator outputs swing is at most 80% of the supply rails. Also note that the inputcommon-mode voltage of the op-amp remains at 0.75 V. This is important as the design ofthe op-amp becomes more challenging if the common-mode voltage is not constant. Thefinite op-amp common-mode rejection ratio (CMRR) can introduce distortion into theoutput of the modulator. Because many input signals will not be fully-differential, webriefly discuss differential modulator design with single-ended inputs next.


Vin+

Vin−

Figure 32.44 Fully-differential implementation of a first-order NS modulator.

VCM

CFφ1 φ2

CI

CF

CI

Vout

−Vout

Vout

φ1

E1

E2

SPICE modeling a differential input/output op-amp with common-mode voltage.Figure 32.45

vo+

vo−

v−

v+

vo+

vo−

v−

v+

VCM

Fully-Differential Modulator with a Single-Ended Input

If we connect our modulator's minus input, , to the common mode voltage, VCM , weVin−

can apply a single-ended input to the modulator's Vin+ input. We need to note severaldifferences when the modulator is used with a single-ended input. The maximum inputsignal is now half of the modulator's input range. This means that we can increase ourintegrator's gain to 0.8 and still avoid DAI output saturation. It also means that ourmodulator output range will be at most half of the full scale range, Fig. 32.47a. Finally,and probably most importantly, the op-amp's input common mode range now changeswith the input signal, Fig. 32.47b.


Figure 32.46 Outputs of the fully-differential first-order modulator after RC filtering.

Figure 32.47 (a) Filtered modulator outputs with full-scale (1.5 V peak-to-peak) single-ended input, and (b) how the input common-mode range of the op-amp changes.

(a) (b)

32.1.3 Second-Order Noise-Shaping

If we review Eq. (32.4), we might wonder if further filtering of the quantization noise,E(z), can result in an improvement in the data converter's SNR over an input signalbandwidth B. The second-order modulator's output shows a double differentiation of thequantization noise

(32.62)Y(z) = z−1X(z) + (1 − z−1)2E(z)

The modulation noise may then be written, see Eqs. (32.10) and (32.11), as

(32.63)NTF( f ) 2 ⋅ VQe( f ) 2 =VLSB

2

12f s⋅ 4

1 − cos 2π ff s

2

Figure 32.48 shows a comparison between the modulation noise of first and second orderNS modulators. Notice how the modulation noise is "flatter" in the bandwidth of interest.

If we restrict our frequency range to frequencies less than fs /2, then we can rewriteEq. (32.63) as

(32.64)NTF( f ) ⋅ VQe( f ) = VLSB

12f s

⋅ 4 sin2πff s

Calculating the RMS quantization noise in a bandwidth B results in

(32.65)VQe,RMS ≈ VLSB

12⋅ π2

5⋅ 1

K5/2

with an increase in the SNR of

(32.66)SNRideal = 6.02N + 1.76 − 12.9 + 50 log K

Every doubling in the oversampling ratio results in an increase in SNR of 15 dB or 2.5bits increase in resolution! Figure 32.49 shows a comparison between simpleoversampling, first-order NS, and second-order NS based data converters. Note that, asdiscussed earlier, the oversampling ratio is generally greater than or equal to eight.


Figure 32.48 Comparing first- and second-order NS modulator's modulation noise.

First-order modulation noise

Second-order modulation noise

V2/Hz ×10−9V2/Hz ×10−9

f, Hz ×106 f, Hz ×106

f s = 100 MHz

Second-Order Modulator Topology

Consider the block diagram of a noise-shaping modulator shown in Fig. 32.50 (see Fig.31.82). The transfer function of this modulator may be written as

(32.67)Y(z) = A(z)1 + A(z)B(z) ⋅ X(z) + 1

1 + A(z)B(z) ⋅ Y(z)

Comparing this equation to Eq. (32.62), we can solve for the forward and fed-back circuitblocks, A(z) and B(z), by equating coefficients

(32.68)STF(z) = A(z)1 + A(z)B(z)

= z−1

and

(32.69)NTF(z) = 11 + A(z)B(z)

= (1 − z−1)2


Figure 32.49 Comparing improvement in modulator resolution.

1 10 100 1k0

3.33

6.66

10.0

K ,Oversampling ratio

Simple oversampling, M = 0


13.3

16.6

10k

First-order noise-shaping, M = 1

Second-order noise-shaping, M = 2Ninc


OutInADC

A(z)

B(z)

E(z)

X(z) Y(z)

The results are

(32.70)A(z) = z−1

(1 − z−1)2

and

(32.71)B(z) = 2 − z−1

The second-order modulator can be implemented using the topology shown in Fig.32.51a. The output of B(z) is the sum of the modulator output and the differentiated,

, modulator output. We can redraw the block diagram of Fig. 32.51a, as shown in(1 − z−1)Fig. 32.51b, resulting in the implementation of a second-order NS modulator shown inFig. 32.51c.


Figure 32.51 Block diagrams of second-order modulators.

OutIn

OutIn

(a)

(b)

OutIn

(c)

Comparator

11 − z−1

1 − z−1

E(z)

X(z) Y(z)z−1

1 − z−1

A(z)

B(z)

11 − z−1

1 − z−1

E(z)

X(z) Y(z)z−1

1 − z−1

11 − z−1

11 − z−1

E(z)

X(z) Y(z)z−1

1 − z−1

The second-order (de) modulator topology of Fig. 32.51c can be used directly toimplement a NS DAC (see Figs. 32.11 and 32.12). However, this topology doesn't lenditself directly to implementation using the DAI. The major concern, as discussed in the lastsection, is the op-amp's output going to the power supply rails (integrator saturation). Thisis more of a concern in the second-order modulator since the output of the first integratorisn't connected directly to a comparator.

Figure 32.52a shows how we can add an integrator gain to the block diagram ofFig. 32.51c without changing the system's transfer function. Figure 32.52b shows pushingthe gain, 1/GI , through the second summer so that it is directly preceding the secondintegrator. Notice how, in Fig. 32.52b, this (the second integrator's gain) is in series withthe comparator's gain (not shown, see Fig. 32.36 and the associated discussion). Thismeans we can arbitrarily change the second integrator's gain because of how the


OutIn

(a)

Can be selected arbitrarly because

OutIn

(b)

of comparator gain (not shown.)

(c)

Figure 32.52 Block diagrams of second-order modulator introducing integrator gains.

Out

Comparator

GI1

GI

11 − z−1

E(z)

X(z) Y(z)z−1

1 − z−1

GI

E(z)

GI1

GI

11 − z−1

X(z) Y(z)z−1

1 − z−1

G1

X(z)

E(z)

11 − z−1

Y(z)z−1

1 − z−1G2z−1/2

X(z) ⋅ z−1/2

comparator gain changes to force the loop gain to unity (see Fig. 32.38). Figure 32.52cshows the resulting configuration where the second integrator has the a gain of G2 and thefirst integrator has a gain of G1. Also notice how we have added a delay in series with theinput signal. This delay was added to show how using a DAI results in an added delay inseries with the input signal. The delay doesn't affect the magnitude of modulator's transferfunction but rather indicates the input signal arrives half a clock cycle later.

Figure 32.53 shows the DAI implementation of the second-order modulator of Fig.32.52c. Note how the output of the modulator is fed back and immediately passes throughthe first integrator and is applied to the second integrator (no delay as seen in Fig. 32.52c).This is a result of switching the phases of the clock signals in the first integrator. Weshould also see how the input signal sees an added half-clock cycle delay. Note that at thispoint it should be trivial to sketch the circuit implementation of the fully-differential,second-order modulator (see Fig. 32.44).

Integrator Gain

As we showed in Eq. (32.41) for the first-order modulator, the forward gain of second-order modulator will be unity when the modulator is functioning properly. We now needto discuss how to select the integrator gains to avoid harmful integrator saturation. Ifnoise and offsets were not a concern, as shown in Fig. 32.40 and the associateddiscussions, then we could make our integrator gains very small (ultimately limited byimperfections in the switches such as clock feed through and charge injection). In apractical modulator, integrator saturation (the integrator's gain going to zero) can alsolead to modulator instability, as shown in Eq. (32.40), and the associated discussion.

Figure 32.54 shows the integrator outputs for the modulator of Fig. 32.53 if bothintegrator gains are set to 0.4. Notice how both outputs go outside the supply voltagerange. If we replace the ideal op-amps in the simulation with transistor-based op-amps, theintegrator outputs will saturate at some voltage within the supply range. This saturationcan be thought of as noise and ultimately limits the data converter's SNR. Integratorsaturation can be avoided by limiting the input signal range, designing with smallintegrator gain, and using op-amps that have a wide output swing.


Figure 32.53 Implementation of the second-order modulator of Fig. 32.52c.

VCM

CI2

VCM

VCM

φ1

φ2φ1

Vin

Vout

f s = 100 MHz

φ2

φ1 VCMCF1

CF2

G1 = CI1

CF1G2 = CI2

CF2

VCM

CI1

Example 32.12Show, using SPICE simulations, how an ideal second-order NS modulator canbecome unstable if the integrator gain is too low.

Because the second integrator is directly followed by a comparator, its gain ismore tolerant to variations allowing it (the gain) to be made small. The firstintegrator's gain, however, is isolated from the comparator by the secondintegrator restricting its values. Figure 32.55a shows the (unstable) output of themodulator in Fig. 32.53 if G1 = 0.01, while Fig. 32.55b shows the integratoroutputs.


Supply voltage rangeOutput2Output1

Figure 32.54 Showing integrator outputs using ideal components.

Figure 32.55 (a) Modulator output and (b) integrator outputs if

(a) (b)

G1 = 0.01

For a more quantitative view of how the gains in a second-order NS modulatoraffect performance, let's consider a couple of different topologies. Figure 32.56 shows theblock diagram of the second-order NS modulator topology of Fig. 32.50, with anintegrator gain coefficient, GI , and a comparator gain, Gc , added. Deriving the transferfunction of this linearized model with results inGF = GI ⋅ Gc

Y(z) = GF ⋅ z−1

1 + z−1 ⋅ 2(GF − 1) + z−2 ⋅ (1 − GF)⋅ X(z) + (1 − z−1)2

1 + z−1 ⋅ 2(GF − 1) + z−2 ⋅ (1 − GF)⋅ E(z)

(32.72)

The poles of this transfer function are located at

(32.73)zp1,p2 = (1 − GF) ± (1 − GF)2 − (1 − GF)

We know that for the modulator to remain stable the poles must reside within the unitcircle. This means that our values of forward gain are restricted to

(32.74)0 ≤ GF ≤ 1.333

Again, if the modulator is functioning properly, GF = 1 (because of the comparator's gainvariation as seen in Fig. 32.28 and the associated discussion).

We should make some observations at this point. Reviewing Eq. (32.40), we seethat the allowable range of forward gain, in the first-order modulator, is larger than theallowable range in the second-order modulator. However, as long as the integrators don'tsaturate (GI doesn't approach zero), stability for either modulator is easy to attain. Ananalysis of the stability of higher-order modulators show that the range of allowableforward gains decreases with the order of the modulator. For example, a third-ordermodulator can have a forward gain of almost 1.15. Finally, notice that the input signalrange is more restricted for the second-order modulator, in order to avoid integratorsaturation, as seen in Fig. 32.54. We'll discuss methods to attain wider input signal rangeand more robust stability criteria by adjusting the feedback gains later in this section.


Figure 32.56 Block diagram of a second-order feedback modulator with gains.

OutIn GI

E(z)

X(z) Y(z)Gc

z−1

(1 − z−1)2

2 − z−1

GF = GI ⋅ Gc

Notice that we are treating our modulator as a linear system even though it isn'tlinear; the comparator gain is a nonlinear variable. The linear approximation is useful togive an idea of the stability of the modulator under certain operating conditions. Generally,a DC input is applied to the modulator, in the simulation, while low-pass filters are addedto determine the average comparator gain, Gc. Figure 32.57 shows this schematically.Assuming we know GI (the gain coefficient of the integrators) we can then look at thestability and forward gain of the modulator for varying DC input signal voltages.

Next consider the more generic block diagram of the second-order NS modulatorshown in Fig. 32.58. We'll discuss how to implement the feedback gain, G3 , using theDAI in a moment. The transfer function of this topology can be written as

(32.75)Y(z) = G1G2Gc ⋅ z−1X(z) + (1 − z−1)2 ⋅ E(z)1 + z−1 ⋅ (G1G2Gc + G2G3Gc − 2) + z−2 ⋅ (1 − G2G3Gc)

Notice that if (where ) then this equation reduces toG1 = G2 = G3 = Gc = 1 G1G2Gc = GF

Eq. (32.62). The poles of this equation are located at

zp1,p2 =2 − G1G2Gc − G2G3Gc ± (2 − G1G2Gc − G2G3Gc)2 − 4(1 − G2G3Gc)

2

(32.76)

When the modulator is functioning properly we require the (linearized) coefficient of theinput, X(z) in Eq. (32.75), to be unity

(32.77)G1G2Gc

(z − zp1)(z − zp2)= 1

Again, if we set (and Gc = 1), then the poles are located at DC, that is,G1 = G2 = G3 = 1

(32.78)zp1,p2 = 0

Equation (32.76) is useful to estimate the modulator's stability when scaling amplitudes byadjusting the integrator gain coefficients, G1, G2, and G3.


Figure 32.57 Simulating the gain of the comparator.

LPF LPF

DC input

vinc voutc

Gc = voutcvinc

Implementing Feedback Gains in the DAI

Consider the modified DAI shown in Fig. 32.59. Notice that if CI2 = CI3 , this topologyreduces to the DAI shown in Fig. 31.78. Also note that some of the switches can becombined to simplify the circuitry. Assuming that the output is connected through the φ2

switches (or that there are no switches connected to the output of the op-amp, see Eq.[31.136]) we can write the transfer function of the integrator as

(32.79)Vout(z) = V1(z) ⋅ CI2

CF2⋅ z−1/2

1 − z−1− V2(z) ⋅ CI3

CF2⋅ 1

1 − z−1

The block diagram of this topology is shown in Fig. 32.60a. We want to implement ablock diagram like the one shown in Fig. 32.60b. Because we have already defined

(32.80)G2 = CI2

CF2

we define our feedback gain, G3 , as

(32.81)G3 = CI3

CF2⋅ 1

G1= CI3

CI2


OutIn

Figure 32.58 Generic block diagram of a second-order NS modulator.

X(z)

E(z)

G1

1 − z−1Y(z)G2 ⋅ z−1

1 − z−1

G3

Gc

Figure 32.59 Adding an additional gain setting to our DAI.

vout

CF2

CI2

CI3

v1

v2

φ1 φ2

VCM

VCM

GF = G1G2Gc

Example 32.13Sketch the circuit implementation of a second-order NS modulator based on thetopology of Fig. 32.58, where . Comment on the stability ofG1 = G2 = G3 = 0.4the resulting configuration. Simulate the design and show the integrator outputswing.

The block diagram of the modulator is shown in Fig. 32.61. We could dissect Eq.(32.76), at this point, to determine the transient properties of the modulator.However, before discussing the transient characteristics of the modulator, let'slook at the integrator output swing.


Figure 31.60 Block diagram of a DAI.

DAI of Fig. 32.59

DAI of Fig. 32.59

(a)

(b)

11 − z−1

Vout(z)

V2(z)

V1(z) CI2

CF2⋅ z−1/2

CI3

CF2

G2 = CI2

CF2

z−1/2 G2

1 − z−1

G3G3 = CI3

CI2

Vout(z)

V2(z)

V1(z)

Figure 32.61 Implementation of a second-order modulator with feedback gain.

0 .4 p

1 p

0 .4 p

0. 16 p

1 p

Vin

φ1φ2φ1 φ2

VoutVCM

VCM

VCM

VCM

φ1

VCM

Figure 32.62 shows the output swing of the integrators. This figure should becompared with Fig. 32.54. The output of the first integrator now falls within thepower supply range. The output of the second integrator is reduced but stillexceeds the power supply range. This, as discussed earlier, has less impact onperformance in the actual transistor-based modulator because the integrator isfollowed by a comparator.

Let's attempt to get an idea for the stability of the modulator by adding LPFs,as seen in Fig. 32.57, to the simulation (with a DC input) to measure Gc. Figure32.63 shows how we will implement the LPFs. The voltage-controlled voltagesource is used to keep from loading the modulator with the RC circuit when it isadded into the general simulation. In our ideal modulator shown in Fig. 32.61 boththe comparator output and integrator outputs are ideal voltage sources, so wedon't need the isolation (and therefore we can add the RC LPF directly into thesimulation).


Figure 32.62 Integrator output signals in the modulator shown in Fig. 32.61.

Output2

1In 10k

100 pF

Out

Figure 32.63 SPICE implementation of a LPF for determining comparator gain.

RC >> 1/f s

Figure 32.64 shows the comparator input and output, after low-pass filtering,for the modulator of Fig. 32.61 when the input signal is 0.1 V (DC). Longersimulations times reveal the average comparator input is 0.4 V. The resultingcomparator gain is then only 0.25. Using Eq. (32.76) to calculate the location ofthe poles results in . These poles are very close to the unitzp1.p2 = 0.96 ± j ⋅ 0.195circle. Small shifts in the DAI gains can result in an unstable modulator. Increasingthe input signal amplitude makes the modulator more stable. Increasing G3 alsoincreases the modulator's stability.

The simulation that generated Fig. 32.64 can be very useful in understandingbasic second-order modulator's stability criteria. Changing the simulation variablesand looking at the resulting simulation outputs can be very instructional. Note thatincreasing the simulation time in the netlist that generated Fig. 32.64 would revealthat the comparator input actually has small amplitude oscillations. Also note howFig. 32.62 shows the output of the second integrator going way outside the powersupply limits when transitioning negative (going well below 0 V) while stayingbounded to the power supply rail when transitioning positive (above 1.5 V). This isrelated to the stability of the modulator being a function of the input voltage.

Using Two Delaying Integrators to Implement the Second-Order Modulator

Consider the second-order modulator topology shown in Fig. 32.65. This topology can beimplemented using the circuits of Figs. 32.53 or 32.61 by simply switching the phases of


Average modulator output

Average comparator input voltage

Figure 32.64 Average comparator input and output when using the modulator of Fig. 32.61 with an input signal of 0.1 V.

the clocks in the first integrator (by making both integrators delaying). The transferfunction of this topology is

(32.82)Y(z) = G1G2Gc ⋅ z−2X(z) + (1 − z−1)2 ⋅ E(z)1 + z−1 ⋅ (G2G3Gc − 2) + z−2 ⋅ (1 − G2G3Gc + G1G2Gc)

The poles are located at

(32.83)zp1,p2 =2 − G2G3Gc ± (2 − G2G3Gc)2 − 4(1 − G2G3Gc + G1G2Gc)

2

This equation should be compared to Eq. (32.76). Remembering, for a stable modulator,the poles must be inside the unit circle we see that using two delaying integrators will notresult in a modulator that has as robust stability criteria as the general implementation ofFig. 32.58. Figure 32.66 shows the implementation of a second-order NS modulator usingtwo delaying integrators. One advantage of this topology over the topology of Fig. 32.58is the reduced slew-rate requirements of the op-amps since neither op-amp, in Fig. 32.66,has to drive both the feedback capacitance and the switched input capacitance of the nextstage during the same clock phase.


OutIn

Figure 32.65 Second-order NS modulator using two delaying integrators.

X(z)

E(z)

G1 ⋅ z−1

1 − z−1

Y(z)G2 ⋅ z−1

1 − z−1

G3

Gc

Figure 32.66 Implementation of a delaying second-order NS modulator.

Note the change in clock phases.

VCM

CI2

VCM

VCM

φ2

φ2φ1

Vin

Vout

f s = 100 MHz

φ1

φ1 VCMCF1

CF2

G1 = CI1

CF1G2 = CI2

CF2

VCM

CI1

G3 = 1

Selecting Modulator (Integrator) Gains

Before leaving this section, let's discuss the general selection of modulator gains. Ingeneral, for good stability, the inner loop feedback gain, G3 , should be made as large aspossible. For general design, set G3 = 1. This simplifies the design of the modulatorcircuitry and provides good flexibility when selecting the values of G1 and G2. If G3 = 1then Eq. (32.76) may be rewritten to show the location of the poles as

(32.84)zp1,p2 =2 − G1G2Gc − G2Gc ± (2 − G1G2Gc − G2Gc)2 − 4(1 − G2Gc)

2

Keeping in mind that the reason we are not setting all gains to one is to avoid integratorsaturation, we can look at Eq. (32.84) as a guide to determine how we can reduce G1 andG2. Since G2 is directly followed by the comparator, we can set its gain to 0.4 as discussedearlier. Practically then, we can reduce the value of G1 to a very small number and stillhave a stable modulator (see Ex. 32.12). At the same time using small G1 avoids integratorsaturation. The practical problem with small G1 , as discussed earlier, is the increase in theinput-referred noise. Again trade-offs must be made for given design criteria. Figure 32.67shows the integrator outputs for the modulator of Fig. 32.58 when G1 = 0.2, G2 = 0.4, andG3 = 1. Note how, when compared to Figs. 32.54 and 32.62, the outputs are very wellbehaved. We don't have the abnormal transitions above the power supply rails indicatingthe modulator stability is becoming marginal with input signal values close to the powersupply rails.


Figure 32.67 Integrator outputs for a modulator with first integrator gain of 0.2.

Second integrator output.

G1 = 0.2G2 = 0.4G3 = 1

Understanding Modulator SNR

Figure 32.68 shows the output spectrum of a first-order NS modulator clocked at 100MHz. This spectrum should be compared to the spectrum of the second-order NSmodulator shown in Fig. 32.69. Note how the spectrum of the first-order modulatorappears to contain more tones in the base spectrum of interest than the spectrum of Fig.32.69. As discussed earlier, unwanted tones are less of a problem in second-ordermodulators.

We know that for the modulator to be useful its output must be passed through alow-pass filter to remove the modulation noise. In simulations we can approximate a low-pass filter with a bandwidth B by limiting the spectral analysis range. To estimate the SNRfrom the simulations of Figs. 32.68 or 32.69, with K = 16, we perform the spectralanalysis up to 50 MHz/16 or 3.125 MHz. The quantization noise plus distortion iscalculated as discussed in the last chapter and shown in the SPICE netlists.

To demonstrate the calculation of a modulator's SNR let's use the second-ordermodulator used to generate Fig. 32.69. Using Eq. (32.65) with VLSB = 1.5 V and K = 16results in an RMS quantization noise of 1.86 mV. The SNRideal is calculated, using Eq.(32.66) as 55 dB. However, Eq. (32.66) was derived assuming Eq. (32.9) was valid. Forthe 1-bit ADC/DAC it is not. For the 1-bit DAC/ADC VLSB is twice the value given by Eq.(32.66) or VREF+ − VREF−. The doubling in VLSB results in a subtraction of 6 dB from Eq.(32.66). The SNRideal is 49 dB. To discuss this further consider a sinewave with apeak-to-peak amplitude of VLSB (= 1.5 here). We can write the SNR of the modulator as


Volts

Figure 32.68 Output spectrum of a first-order modulator.

Vol

tage

, pea

k

G = 0.4

Vin = 0.75 + 0.5 sin (2π ⋅500kHz ⋅ t)

(32.85)SNRideal = 20 log [1.5/2]/ 2

/(1.86 mV) = 49 dB

Modifying Eq. (32.66) for the 1-bit case and the increase in VLSB results in

(32.86)SNRideal = 50 ⋅ log K − 8.3 = 49 dB

In practice the SNR (SNRD) is considerably worse than the ideal value. Thisvariation comes from the fact that our assumed quantization noise spectrum isn't white andthe modulator output can contain unwanted tones at multiples of the input sinewave signalfrequency. Figure 32.70 shows the output of the second-order modulator of Fig. 32.69when we limit the spectral analysis to B (= 3.125 MHz). Calculating the SNR using Eq.(32.85) with a peak input sinewave amplitude of 0.5 V gives 45.6 dB. Simulations usingideal components, however, give a 37 dB SNRD. Zeroing out the tones (see thecommands in the netlist where we have already zeroed out the DC term and thefundamental at 500 kHz) will obviously increase the SNR. Note also that we didn't use afull-scale input sinusoid (peak amplitude of 0.75 V). Full-scale inputs inherently result in areduction in SNR because our modulator has less output signal range to average over. Forexample, an input signal approaching the supply rails causes the output of the modulatorto remain high most of the time, while a mid-scale signal results in more modulator outputvariation allowing better averaging. The reduction in SNRD with input signal amplitudewas shown back in Fig. 31.5. Finally, note that by using a high-frequency input signal,which has the same effect as an added dither signal, the output modulation noise becomesmore random and the SNR increases. To illustrate this we could resimulate the netlist usedfor Fig. 32.70 with an input frequency of 5 MHz (outside our signal band of interest).


Volts

Figure 32.69 Output spectrum of a second-order modulator.

Vol

tage

, pea

k

Vin = 0.75 + 0.5 sin (2π ⋅500kHz ⋅ t)G1 = 0.2 G2 = 0.4 G3 = 1

32.2 Noise-Shaping Topologies

The last section presented the fundamentals of noise-shaping (NS) data converters. It'simportant to understand this fundamental material before proceeding with the topicspresented in this section.

In this section we cover 1) higher-order NS modulators, 2) NS modulators usingmultibit ADCs and DACs (multibit modulators), 3) cascaded modulators (higher-ordermodulators built with a cascade of first- and/or second-order modulators), and 4)bandpass modulators (modulators that perform data conversion over a band of frequenciesthat doesn't include DC).

32.2.1 Higher-Order Modulators

We can take the theory developed for our first- and second-order modulators in the lastsection and generalize it for an M th-order modulator (a modulator having M integratorsand M feedback loops). Rewriting Eqs. (32.11) and (32.64) for the general M th-ordermodulator results in

(32.87)NTF( f ) ⋅ VQe( f ) = VLSB

12f s

⋅ 2 sinπ f

f s

M

The RMS noise in a bandwidth B can be written, see Eqs. (32.25) and (32.65), as


12⋅ πM

2M + 1⋅ 1

KM +1/2


Figure 32.70 Same as Fig. 32.69 but with limited spectral range.

Second harmonic

Third harmonic

0.5 V peak input sinewave0.75 DC

Volts The ideal increase in the SNR can be written as

(32.89)SNRideal = 6.02N + 1.76 − 20 log

πM

2M + 1

+ [20M + 10] ⋅ log K

or

(32.90)SNRideal = 6.02(N + Ninc) + 1.76

The increase in resolution, Ninc , is given by

(32.91)Ninc = 16.02

(20M + 10) ⋅ log K − 20 log

πM

2M + 1

This equation shows that for every doubling in the oversampling ratio, K, the resolutionincreases by M + 0.5 bits. In practice, as we have seen already, this equation results in anoverestimate for the increase in resolution because the quantization noise is not truly white(because of the 1-bit ADC) and the modulation noise contains unwanted spectral tones (asseen in Fig. 32.70).

M th-Order Modulator Topology

Reviewing the general NS modulator topology of Fig. 32.50 we want to determine theforward transfer function, A(z), and the feedback transfer function, B(z), for an M th-orderNS modulator. The transfer function of a general M th-order modulator is

(32.92)Y(z) = X(z) ⋅ (z−1) + E(z) ⋅ (1 − z−1)M

Using this equation together with Eq. (32.67) results in a forward modulator transferfunction of

(32.93)A(z) = z−1

(1 − z−1)M

and a feedback filter transfer function of

(32.94)B(z) =1 − (1 − z−1)M

z−1

The block diagram of an M th-order NS modulator is shown in Fig. 32.71.


OutIn

Figure 32.71 Generic block diagram of an M -order NS modulator.th

Non-delaying integrators Delaying integrator

X(z)

E(z)

11 − z−1

Y(z)z−1

1 − z−1

11 − z−1

Decimating the Output of an M th-Order NS Modulator

Let's revisit the derivation of Eq. (32.20). This equation states that the number of sincstages, L, used in cascade, for near optimum removal of the modulation noise, is one morethan the order of the modulator (L = M + 1). Rewriting Eq. (32.22)

(32.95)VQe,RMS2 = 2 ∫

0

fs/2

NTF( f ) 2 ⋅ VQe( f ) 2 ⋅ H( f ) 2 ⋅ df

where the decimation filter's transfer function is given by

(32.96)H( f ) 2 =

1K

⋅sin

Kπ f

fs

sin π f

fs

2(M+1)

The mean-squared quantization noise is calculated by evaluating

(32.97)VQe,RMS2 = 2 ⋅

VQe( f ) 2

VLSB2

12f s⋅ ∫

0

fs/2

NTF( f ) 2

2 sinπ f

f s

2M

⋅

1K

⋅sin

Kπ f

fs

sin π f

fs

2(M+1)

⋅ df

or

(32.98)VQe,RMS2 = 2 ⋅

VLSB2

12f s⋅ 22M ⋅

1K

2(M+1)⋅ ∫

0

fs/2 sin2(M+1) Kπ f

fs

sin2M π f

fs

⋅ df

If we let , then we getθ = πffs

(32.99)VQe,RMS2 =

VLSB2

12f s⋅

2K

2(M+1)⋅ f s

π ⋅

= K2 π⋅Π

m=1

M2m−1

2m

∫0

π2

sin2(M+1)(Kθ)sin2Mθ

⋅ dθ

Finally, the RMS quantization noise associated with an M th-order modulator followed byan M + 1 (= L) sinc averaging filter is


12⋅

2K

M+1/2

⋅ Πm=1

M 2m − 12m

The change in SNR, when using the sinc averaging filter decimator instead of the idealfilter with bandwidth B, is given by looking at the ratio of Eq. (32.88) to Eq. (32.100)

(32.101)Increase in SNR = −20 log

2M+1/2 ⋅ Π

m=1

M 2m − 12m

⋅ 2M + 1

πM


For first-, second-, and third-order modulators, the difference in the SNRs is 2.16, 6.35,and 10.39 dB respectively. This shows that using a sinc averager, theoretically, increasesthe SNR if we neglect the decrease in the desired signal amplitude because of the droop,Figs. 31.43 or 31.46. To avoid the droop, as discussed earlier, the desired signal content isoften limited to frequencies well below fs/2K (= B). When the droop (reduction in thedesired signal amplitude) is taken under consideration, the SNR, when using the sincaveraging filter, is worse than the ideal filter with bandwidth B.

Implementing Higher-Order, Single-Stage, Modulators

The single-stage, higher-order modulator of Fig. 32.71 can be difficult to implementdirectly. It is impossible to implement a higher-order modulator, when using DAIs, whereall but the last integrator are non-delaying. However, as we saw with the second-ordermodulator using two delaying integrators in Fig. 32.65 and Eqs. (32.82) and (32.83), thestability criteria of a modulator using only delaying integrators is poorer than the criteriaof the topology shown in Fig. 32.71 (where only the last integrator is delaying). While wecan help the situation by staggering delaying and non-delaying integrators in a modulator,the point is that implementing a higher-order modulator without modifying our basic NStopology will result in an unstable circuit. Intuitively, we can understand this by notingthat if the modulator's forward gain is too high and the delay through the forward path istoo long (because of the large number of integrators), the signal fed back may add to theinput signal instead of subtracting from it.

To help with the stability of a higher-order modulator a topology that feeds theinput signal forward into additional points in the modulator (thereby reducing the forwardgain and delay) and feeds the output signal back as discussed earlier (allowing scaling ofamplitudes) is needed. Towards this goal, consider the modified NS topology forhigher-order modulators shown in Fig. 32.72. The forward and feedback transfer functionscan be written as

A(z) = a1 ⋅ z−M

(1 − z−1)M+ a2 ⋅ z−(M−1)

(1 − z−1)M−1+ a3 ⋅ z−(M−2)

(1 − z−1)M−2+ ... + aM ⋅ z−1

1 − z−1 = Σi=1

M

ai ⋅

z−1

1 − z−1

M−i+1

(32.102)

or

(32.103)A(z) = (z − 1)−M ⋅ a1 + a2(z − 1)1 + a3(z − 1)2 + ... + aM(z − 1)M−1 and

−A(z)B(z) = b1 ⋅ z−M

(1 − z−1)M+ b2 ⋅ z−(M−1)

(1 − z−1)M−1+ b3 ⋅ z−(M−2)

(1 − z−1)M−2+ ... + bM ⋅ z−1

1 − z−1= Σ

i=1

M

bi ⋅

1z − 1

M−i+1

(32.104)

or

(32.105)−A(z)B(z) = (z − 1)−M ⋅ b1 + b2(z − 1)1 + b3(z − 1)2 + ... + bM(z − 1)M−1


Before going any further, let's explain what we are trying to do with the modified,higher-order, noise-shaping topology of Fig. 32.72. We know that the NTF(z), for ageneral modulator, is of the form with a shape seen in Fig. 32.73. At high(1 − z−1)M

frequencies the modulation noise will get very large. At fs /2, for example, the magnitude

of the noise-transfer function, , is (see Fig. 31.51). For the modified NSNTF( f ) 2

M

modulator we will try to reduce the modulation noise at higher frequencies by changingthe shape of the NTF(z). Our modified NTF(z) will be of the form

(32.106)NTF(z) = LPF(z) ⋅ (1 − z−1)M = LPF(z) ⋅

z − 1z

M

= HPF(z)

where LPF(z) [HPF(z)] is a low-pass [high-pass] filter implemented with the feedbackcoefficients bx. The goal is to flatten out the higher frequency modulation noise (keep thenoise from getting too large) thereby reducing the NTF( f ) at high frequencies andkeeping the modulator stable. One drawback of using this technique is that the signal nolonger sees just a delay in its transfer function but rather it sees the low-pass response. Themodified STF will be of the form

(32.107)STF(z) = NTF(z) ⋅ A(z) = LPF(z) ⋅ Σi=1

M

ai ⋅ (z − 1) i−1


Out

In

thFigure 32.72 Block diagram of a modified M -order NS modulator.

X(z)E(z)

z−1

1 − z−1

Y(z)z−1

1 − z−1z−1

1 − z−1

a1 a2 aM

bM

b2b1

fB

higher-order NTF.

Figure 32.73 Showing the change in the NTF in a higher-order modulator.

An example shape of a

(Less gain at high-frequnencies.)

NTF( f )

(1 − z−1)M

LPF(z) ⋅ (1 − z−1)M

so that the feed forward coefficients, ax , can be used to help make the STF( f ) constantover the region of interest (the STF can be made to have an overall low pass response).The NTF is given by

(32.108)NTF(z) = 11 + A(z)B(z)

or

(32.109)NTF(z) = 1

1 −Σi=1

M

bi ⋅ (z − 1) i−1

= HPF(z)

The coefficients, bx , are selected for a high-pass response. Note also that our coefficientsare positive since the feedback paths, as seen in Fig. 32.72, are subtracting. The design ofthe modulator, at this point, is to determine the feed-forward and feedback coefficientsusing basic digital-signal processing filter design (and, to keep the algebra simple, acomputer program of some sort) then to simulate the design to see if it exceedsspecifications. One challenge, among others, is to meet a given SNR without causingharmful integrator saturation.

Other topologies have been developed to implement higher-order NS modulators.The reader is referred to Chs. 4 and 5 of reference [2] for further information.

32.2.2 Multi-Bit Modulators

Throughout this chapter we have assumed N = 1; that is, we have used a comparator forour quantizer in the forward path of our NS modulator. The main advantage of single-bitmodulators, as discussed earlier, is the inherent linearity of the 1-bit feedback DAC.Feedback DAC linearity is important because the output of the DAC is directly subtractedfrom the input signal. Any distortion or nonlinearity (or noise) in the output of the DACwill directly affect the modulator's performance and, ultimately, limit the modulator's SNR.The benefits of using a multi-bit (N > 1) quantizer in a NS modulator are increased SNR(see Eq. 32.89), better stability (the modulator behaves closer to the linearized theorydeveloped in this chapter), fewer spectral tones, and simpler digital decimation filter. Thedrawbacks of using multi-bit topologies, are the increase in ADC complexity (the ADCmust be a flash converter) and the need for the DAC to be accurate to the final accuracyof the modulator. The ADC errors, like gain errors in the integrators, are less importantsince they are in the forward, high-gain, path of the modulator.

Simulating a Multi-bit NS Modulator using SPICE

Figure 32.74 shows a circuit-level implementation of a first-order, multi-bit, NS modulatorusing a 4-bit ADC and DAC. Figure 32.75 shows the SPICE simulation outputs of thismodulator in the time and frequency domains with the same input sinewave used ingenerating Fig. 32.68. Comparing Fig. 32.75 to Fig. 32.68 the decrease in modulationnoise is obvious. Note that (a) of the figure shows both the input to the modulator and theoutput of the ideal DAC while (b) is the DAC's output spectrum. Looking at the output ofthe DAC avoids the need for a Fourier Transform on the modulator's output digital data.


Most of the design effort, when developing multi-bit modulators, goes into thedesign of the feedback DAC. Because it is nearly impossible to design highly-accurateDACs without trimming, or some sort of error correction, methods have been developedthat attempt to randomize DAC errors. If the errors appear as a random variable, they mayappear as white noise in the output spectrum and not affect the SNR of the data converter.

Figure 32.76 shows one possible implementation of a DAC that utilizes resistiveunit elements. While this figure is busy, let's attempt to explain how the DAC functions.The DAC is based on unit element (equal value) resistors. In one case we connect VDD toone corner of the resistor cube and ground to the opposite corner (assuming VREF+ = VDDand VREF− = 0). There exist two voltage dividers along each of the sides of the resistorsquare. The output of the DAC can change from zero, to (1/8)VDD, to (2/8)VDD, ... upto (8/8)VDD. Depending on the output of the decoder, one tap from each side is fed to theanalog output. Because there are two sides, the outputs from each side are combined andeffectively averaged.

The purpose of the counter is to vary the connections of VDD and ground aroundthe outside of the resistive divider to randomize variations in the output voltage due toresistor mismatch. To understand this in more detail consider a constant DAC output


1p

0.4p

Figure 32.74 Circuit implementation of a first-order multi-bit NS modulator.

4-bitADC

4-bitDAC

inout

in

outclk

4-bits

VCM

VCM

VREF− = 0

φ1 φ2

φ1

Vin

Vout

f s = 100 MHz

VREF+ = VDD

Figure 32.75 Output of the mult-bit modulator (a) and its spectrum (b).

(a) (b)

voltage of VDD/2. As the counter changes output values, so do the connections to VDDand ground in the resistor string. To keep a constant output voltage of VDD/2 theswitches in the center of the DAC move accordingly based on the output of the counterand the input to the decoder. In this way variations in the resistors, hopefully, average outto a constant value.

Multi-bit Demodulator (used in a NS DAC) Implementation (Error Feedback)

The NS topologies we've discussed so far are sometimes called Interpolative Modulatorssince the signal fed back is an estimate of the input signal interpolated between knownvalues of the modulator output (the average of the modulator outputs should be the inputsignal). However, NS modulators were first introduced (see C. C. Cutler, "Transmissionsystems employing quantization," 1960, U.S. Patent No. 2,927,962 [filed 1954]) using theerror feedback topology shown in Fig. 32.77. Error feedback topologies are not used inanalog input modulators because errors in the analog subtraction directly add to the inputsignal. We can use this topology, however, in the implementation of a digital inputdemodulator (sometimes also called a modulator) as the subtraction is digital.


OutputAnalog

Dec

oder 8

3-bit DAC inputs

VDD

Cou

nter 16Clock

Connected to VDD when counter output is 8and connected to ground when counter output 0

Connected to VDD when counter output is 0and connected to ground when counter output is 8

8,07,156,145,134,12

3,11

2,10

1,9

9,1

10,2

11,3

12,413,514,60,8 15,7

Figure 32.76 Implementation of a DAC for use in a multi-bit NS modulator.

Switch

VDD bus

Ground bus

b0

b1

b2

Looking at Fig. 32.77 we note that by definition the difference between the inputand the output of the quantizer is the quantization noise, E(z). This noise is subtractedfrom the input after a delay (for a first-order modulator) resulting in

(32.110)Y(z) = X(z) − F(z) ⋅ E(z) + E(z) = X(z) + E(z)[1 − F(z)]

Note that the signal-transfer function for an error feedback-based modulator is simply one;that is, STF( f ) = 1. For a first-order NS modulator we set F( z ) = z−1 (a register), whichresults in

(32.111)Y(z) = X(z) + E(z) ⋅ (1 − z−1)

A second-order modulator with a would use a feedback filter,NTF( f ) = (1 − z−1)2

noticing from Eq. (32.110) that , ofNTF( f ) = 1 − F(z)

(32.112)F(z) = 1 − (1 − z−1)2 = z−1 ⋅ (2 − z−1)

Implementation of a second-order NS modulator is shown in Fig. 32.78. Note that whentrying to implement higher-order modulators using error feedback we run into the sameproblem we encountered when using an interpolative modulator, namely, instabilityresulting from too large of an NTF at higher-frequencies. As with interpolativemodulators, we can design the NTF to be a high-pass response.


z−1

Figure 32.77 Block diagram of an error feedback modulator.

OutIn

Quantizer

in out

E(z)

X(z) Y(z)

E(z)F(z)

Figure 32.78 Block diagram of a second-order error feedback modulator.

OutIn

Quantizer

in out

shift-left

E(z)

X(z) Y(z)

z−1

z−1

×2

We've introduced the error feedback topology with the idea that it can be used in amodulator (demodulator) that performs digital-to-analog conversion. We first introduceda modulator for use in a DAC back in Fig. 32.12. At this point we need to answer thequestion, "Why is the NS topology of Fig. 32.77 a better choice for DAC implementation,in general, then the topologies of Figs. 32.12 and 32.71?" The answer to this comes fromthe realization that the quantizer and difference block in Fig. 32.77 can be implemented bysimply removing lower bits from the digital input words. This is illustrated in Fig. 32.79.The resulting error feedback modulator will be simpler to implement than the modulatorsbased on interpolative topologies. Figure 32.80 shows Fig. 32.77 redrawn to show thesimpler implementation.

The number of bits used in the modulator, N, is selected to avoid overflow whenthe maximum input signal and fed-back signal are subtracted. When using two'scomplement numbers, the words input to the adder must be the same length. The smallerword's MSB is used to increase the smaller word's size until the word lengths match. We'llcomment more on this important concern in a moment.

Figure 32.81 shows the block diagram of an NS based DAC. As we saw in Fig.32.11, if a 1-bit output is used, the modulator can be connected directly to thereconstruction filter (RCF). The 1-bit DAC is perfectly linear so distortion concerns arereduced. Using a multibit modulator and DAC gives a better SNR, for a givenoversampling ratio and modulator order, as well as easing the requirements placed on theRCF. The drawback, as discussed earlier, is that the DAC must be accurate to the finaldesired output resolution since it is in series with the output signal path.


Figure 32.79 Showing how quantizer and difference block are implemented.

Out

Quantizer

in out

This is implemented using

E(z)

Y(z)Y(z)N bits

F bits

N − F bitsN bits

N − F bits

F bits

Figure 32.80 Block diagram of an error feedback modulator.

OutIn X(z) Y(z)

F(z)N − F bits

N bits

F bits

Let's comment on how to estimate the quantization noise added to the signal fromthe error feedback quantization process. Assuming we are using two's complementnumbers we know

(32.113)

N - bits

0111111... = VREF+ −

1 LSB

VREF+ − VREF−

2N

and

(32.114)1000000... = VREF−

For the DAC to function properly we must change the numbers back to binary offset(complement the left-most or most-significant bit) unless the DAC input uses two'scomplement format. This is easy to see if the output of the modulator is a single bit

since an MSB of and a where .(N − F = 1) 1 = VREF+ 0 = VREF− VLSB = [VREF+ − VREF−]/2By dropping F bits the voltage weighting of an LSB in the modulator output can bewritten as

(32.115)VLSB = VREF+ − VREF−

2N−F

This result is used in Eq. (32.8) to estimate the quantization noise spectrum in a NSmodulator.

Implementation Concerns

We know from our discussions in the last chapter that most digital additions andsubtractions utilize two's complement numbers because of the simplicity (see Fig. 31.55and the associated discussion) in implementing the hardware. However, consider the two'scomplement N-bit input in Fig. 32.79. If we drop the lower F bits, the resulting numberfed back to F(z) (the quantization noise) is not in two's complement format.

To circumvent these types of problems, the topology shown in Fig. 32.82 can beused. The input to the quantizer/subtractor is changed from two's complement format intobinary offset format. (See Figs. 31.36 and 31.37 for a comparison of the formats.)Quantization is then performed; the lower bits are dropped from the output and fed back.The fed-back word (the quantization error) is then changed from a binary offset numberback into a two's complement number. The size of the word fed back is adjusted to matchthe size of the modulator's input (knowing that the words used in two's complementarithmetic must be the same size so that the sign bit is in the same location in each word,see also Fig. 31.55).


Figure 32.81 DAC using a NS modulator and digital filter.

NS (de)modulatorDigitalFilter

RCFAnalog outputDigital input

Interpolation filter

DAC

32.2.3 Cascaded Modulators

The NS modulators discussed in this chapter, up to this point, have been single feedbackloop topologies with the general form seen in Fig. 31.81. This includes the higher-ordertopologies discussed in Sec. 32.2.1 and the error-feedback topologies of the last section.In this section we discuss cascaded or multistage NS modulators. The cascadedmodulators discussed here are sometimes called MultistAge noise SHaping or MASHmodulators. While our focus, in this section, is on modulators for ADCs, it is easy toextend the theory developed to modulators used in DACs.

We indicated, in the last section, that feeding back the quantization noise, E(z), tothe input isn't practical in analog implementations of NS modulators. The output of theanalog subtraction [E(z)] would be added directly to the input signal. Instead of feedingE(z) back to the input, cascaded modulators feed it forward to the input of anothermodulator. The second modulator's output is then a delayed version of E(z) as well as itsown unwanted modulation noise. If this output is subtracted from the output of the firstmodulator, we can effectively reduce the resulting, overall, quantization noise.

The major benefit of a cascaded topology is stability. Unconditionally stable first-and second-order loops can be cascaded to implement higher-order modulators. Inaddition, as we'll briefly discuss, modulators consisting of a first-stage modulator using a1-bit ADC and DAC followed by a multi-bit modulator can provide reasonable resolutionswith low oversampling ratio K.

Second-Order (1-1) Modulators

A second-order NS modulator can be implemented using a cascade of two first-ordermodulators (called a 1-1 modulator) as seen in Fig. 32.83. The output of the firstmodulator is given by

(32.116)Y1(z) = z−1X(z) + (1 − z−1)E1(z)


Figure 32.82 Implementation of the quantizer and difference blocks.

MUX

MSB

10

0000...1111...

select

MSB

Two's complement Binary offset Binary offsetIn

Binary offset

Two's complement

Adjust, using the MUX, the output word size so that it matches the modulator's input word size. The adder,on the input of the modulator, should see the same size words.

Y(z)N bits

F bits

N − F bitsN bits

while the output of the second modulator is

(32.117)Y2(z) = −z−1E1(z) + (1 − z−1)E2(z)

The overall modulator output is given by

Y(z) = z−1Y1(z) + (1 − z−1)Y2(z)

= z−2X(z) + z−1(1 − z−1)E1(z) − z−1(1 − z−1)E1(z) + (1 − z−1)2E2(z)

(32.118)= z−2X(z) + (1 − z−1)2E2(z)

Note how the second modulator is used to subtract the first's quantization noise, E1(z),from the final output. If all of the components are ideal, the resulting modulator hassecond-order noise shaping. In practice, however, the coefficients of E1(z) in Eq. (32.118)will not exactly cancel. When this occurs, E1(z) is said to leak to the output of themodulator. Differences in the coefficients are caused by gain errors in the first modulator'sanalog integrator when compared to the output of the digital differentiator.

Let's attempt to characterize the performance of the 1-1 modulator if theintegrators have gain coefficients, GI , other than one as seen in Fig. 32.36. We can writethe output of the first modulator's integrator in Fig. 32.83 as

(32.119)O1(z) = GI1 ⋅ z−1

1 + (GF − 1)z−1⋅ X(z) − GI1 ⋅ z−1

1 + (GF − 1)z−1 ⋅ E1(z)

Using Eq. (32.39) with this equation we can write

(32.120)E1out(z) = Y1(z) − O1(z) = (GF − GI1) ⋅ z−1

1 +(GF − 1)z−1⋅ X(z) +

1 − (1 − GI1) ⋅ z−1

1 + (GF − 1)z−1⋅ E1(z)


Out

In

Figure 32.83 Second-order (1-1) cascaded modulator.

delay

differentiatorsee Fig. 31.51

X(z)

Y(z)

z−1

1 − z−1

z−1

1 − z−1

E1(z)

E2(z)

z−1

1 − z−1

Y1(z)

Y2(z)−E1(z)

−E1(z)

O1(z)

where, ideally, the output quantization noise of the first modulator, E1out(z) , is E1(z). If themodulator is functioning properly, then GF = 1 independent of GI as discussed earlier.Equation (32.120) can then be written as

(32.121)E1out(z) = (1 − GI1) ⋅ z−1 ⋅ X(z) + [1 − (1 − GI1) ⋅ z−1] ⋅ E1(z)

Using this equation in Eq. (32.117) while assuming the second modulator uses anintegrator scaling factor, GI2 , and GF2 is one results in (rewriting Eq. [32.118])

Y(z) = z−2X(z) + z−1(1 − z−1)E1(z) − z−1(1 − z−1)E1out(z) + (1 − z−1)2E2(z)

(32.122)=

Desired output

z−2X(z) + (1 − z−1)2E2(z) +

Unwanted term

[E1(z) − X(z)] ⋅ z−2(1 − z−1) ⋅ (1 − GI1)

While we can set the second modulator's integrator gain coefficient, GI2 , to 0.4 to avoidintegrator saturation, as discussed earlier, we must set GI1 as close to unity as possible.Using a unity gain coefficient results in a reduction in the modulator's overall dynamicrange (see Fig. 32.35 and the associated discussion). Note how the input signal appears inthe unwanted term in Eq. (32.122). It should be obvious at this point that we can addscaling parameters at various points in the modulator to attempt to maximize themodulator's dynamic range. Also note how the number of bits in the 1-1 modulator'soutput will be more than 1-bit (two bits if comparators are used in each first-ordermodulator).

Third-Order (1-1-1) Modulators

By adding a third, first-order, modulator to our 1-1 modulator of Fig. 32.83 we get a1-1-1 or third order modulator, Fig. 32.84. The output of the added, third, modulator canbe written as

(32.123)Y3(z) = −z−1E2(z) + (1 − z−1)E3(z)

while the ideal output of the 1-1-1 cascade is given by

(32.124)Y(z) = Y1(z) + Y2(z) + Y3(z) = z−3X(z) + (1 − z−1)3E3(z)

Again, as we saw in Eq. (32.122), noise from the first modulator can leak through to theoutput and spoil the overall cascade's SNR. Indeed, if the leakage from the first modulatoris large enough, we get no benefit from adding the third modulator. Notice, in Eq.(32.122), that the unwanted term exhibits first-order differentiation, . We might(1 − z−1)expect better overall performance, that is, less leakage if the first modulator issecond-order. The unwanted term would then exhibit second-order differentiation.

Third-Order (2-1) Modulators

A third-order modulator formed by using a second-order modulator followed by a first-order modulator is shown in Fig. 32.85. The output of the first modulator is given by

(32.125)Y1(z) = z−1X(z) + (1 − z−1)2E1(z)



Out

In

Figure 32.84 Third-order (1-1-1) cascaded modulator.

X(z)

Y(z)

z−1

1 − z−1

z−1

1 − z−1

E1(z)

E2(z)

z−2

(1 − z−1)

Y1(z)

Y2(z)−E1(z)

O1(z)

z−1

E3(z)

z−1

1 − z−1

−E2(z)(1 − z−1)2Y3(z)

Out

In

Figure 32.85 Third-order (2-1) cascaded modulator.

X(z)

Y(z)

z−1

1 − z−1

z−1

1 − z−1

E1(z)

E2(z)

z−1

(1 − z−1)2

Y1(z)

Y2(z)−E1(z)

11 − z−1

O1(z)

Y1(z) = O1(z) + E1(z) while the output of the second modulator is

(32.126)Y2(z) = −z−1E1(z) + (1 − z−1)E2(z)

The output of the 2-1 modulator is then, ideally,

(32.127)Y(z) = Y1(z)z−1 + (1 − z−1)2Y2(z) = z−2X(z) + (1 − z−1)3E2(z)

Let's attempt to characterize the leakage to the output by first determining theoutput of the second integrator O1(z) (the input to the comparator). We'll use the topologyshown in Fig. 32.58, with G3 = 1, to define our gains. The output, O1(z), is (assuming that

)GF = G1G2Gc = 1

(32.128)O1(z) =G1G2 ⋅ z−1X(z) − [(G1G2 + G2) − G2z−1] ⋅ z−1E1(z)

1 + z−1 ⋅ (G2Gc − 1) + z−2(1 − G2Gc)

Again writing the input to the second modulator as (using Eq. [32.75])

E1out(z) = Y1(z) − O1(z)

(32.129)=(1 − G1G2) ⋅ z−1X(z) + (1 − z−1)2 + (G1G2 + G2) ⋅ z−1 − G2z−2 E1(z)

1 + z−1 ⋅ (G2Gc − 1) + z−2(1 − G2Gc)

noting that if then . If we write the output of theG1 = G2 = Gc = 1 E1out(z) = E1(z)cascade as

(32.130)Y(z) = z−2X(z) + z−1(1 − z−1)2E1(z) − z−1(1 − z−1)2E1out(z) + (1 − z−1)3E2(z)

then

Y(z) =

Desired output

z−2X(z) + (1 − z−1)3E2(z) +Undesired term

z−1(1 − z−1)2 (1 − G1G2) ⋅ z−1X(z) + [(1 − G2) − (G2Gc − G2)z−1] ⋅ z−1E1(z)

1 + z−1 ⋅ (G2Gc − 1) + z−2(1 − G2Gc)

(32.131)

When this equation is compared to Eq. (32.122), we see that the undesired term is second-order differentiated. Also, we have more control over the integrator gains. Third-ordermodulators using the 2-1 topology are much more robust than the 1-1-1 based topologyand can provide outputs signals free of unwanted tones. Again, if integrator saturation(and thus dynamic range) isn't a concern, then we can set . G1 = G2 = 1

One of the interesting uses of the 2-1 modulator is the configuration where the first(second-order) modulator utilizes a 1-bit ADC and DAC, while the second (first-order)modulator utilizes a multibit ADC and DAC. The overall linearity of this topology isdominated by the second-order modulator, while the multibit modulator provides anenhancement in dynamic range for a given oversampling ratio. These very interesting, andpotentially ubiquitous, data converters are discussed in greater detail in Ch. 7 of [2].


Implementing the Additional Summing Input

Before leaving our introduction to cascaded converters, let's discuss the implementation ofthe extra summing block used to generate the quantization noise, E(z). Figure 32.86shows the topology of the two summing blocks and how they can be combined.

One way to implement the extra subtracting input and the integrator is shown inFig. 32.87. This DAI is a modification of the DAI shown in Fig. 32.59. The output of thisintegrator is related to the inputs by

(32.132)Vout(z) = O1(z) ⋅ CI2

CF2⋅ z−1/2

1 − z−1− Y2(z) ⋅ CI2

CF2⋅ 1

1 − z−1− Y1(z) ⋅ CI22

CF2⋅ 1

1 − z−1

If we set CI2 = CI22 = CF2 and we realize that the comparator in the second modulator,assuming it is clocked with the rising edge of (or the falling edge of ), adds aφ1 φ2

half-clock cycle delay in series with the Y1(z) input and a full clock cycle delay in serieswith O1(z) and Y2(z) then we can write

(32.133)Vout(z) = [O1(z) − Y1(z) − Y2(z)] ⋅ z−1

1 − z−1

Figure 32.88 shows the implementation of a 2-1 modulator.


Figure 32.86 Showing implementation of the dual summing block as a single block.

Out to integratorOut

Y1(z)

Y2(z)

−E1(z)

O1(z)O1(z)

Y2(z)

Y1(z)

Figure 32.87 Implementing the dual summing block for a cascaded modulator.

CF2

CI2

CI22

Vout(z)

φ1 φ2

VCM

VCM

Y2(z)

O1(z)

Y1(z)

Y1(z) = O1(z) + E1(z)

We could also use the topology shown in Fig. 32.89 to implement the summingblock of Fig. 32.86. This topology has the benefit of using a single capacitor for a simplercircuit and no matching differences between CI2 and CI22 . Unfortunately, as discussed inCh. 27, the topology is no longer insensitive to the parasitic capacitance on the top plateof the switched capacitor. In the parasitic insensitive topologies, Fig. 32.87 for example,the top plate of the capacitor is always held at the common mode voltage VCM. In thetopology of Fig. 32.89 the top plate is charged to y1( t ) when the switches are closedφ1

and discharged to VCM when the switches are closed. The difference between theseφ2

voltages combined with the value of the unwanted parasitic capacitance to ground on thetop plate causes unwanted charge to transfer to the feedback capacitor and a gain error.This by itself isn't too bad. However, the unwanted capacitance can have a large depletioncapacitance component resulting in a voltage dependent capacitance and thus nonlineargain. Nevertheless, in some applications this topology may still prove useful.


Figure 32.88 Implementation of a 2-1 NS modulator.

φ1φ2

φ2φ1

Vin

Y1(z)

φ1

φ2φ1

Y2(z)

Y1(z)

O1(z)

φ1

Figure 32.89 Implementing the dual summing block with a single capacitorresults in sensitivity to the top plate parasitic capacitance.

Vout(z)

φ1 φ2

VCM

Y2(z)

O1(z)

Y1(z)

32.2.4 Bandpass Modulators

The modulators we've discussed so far in this chapter have been low-pass topologies; thatis, the desired signal resides from DC to B. In this section we briefly discuss the idea thatwe can perform data conversion on a range of frequencies that doesn't include DC. Abandpass modulator is one that pushes the modulation noise away from some desiredbandwidth of interest.

In Sec. 31.2.4 we discussed the idea that we can implement a sinc-shapedaveraging bandpass filter centered around fs /4 (or fs /6) having a transfer function of

(32.134)H(z) = 1 − z−K

1 + z−2

Comparing this equation to the equation for the equivalent low-pass averaging filter, Eq.(31.99), we can see that transforming our low pass modulator topologies into bandpassmodulator topologies with bandpass responses centered at fs /4 can be accomplished by

(32.135)substituting z−2 for −z−1

Figure 32.90 shows the result of a low-pass second-order modulator transformed into afourth-order bandpass modulator. It's now called a fourth-order modulator because thenumber of poles in the NTF is now four. The transfer function for this, fs /4 , bandpassmodulator is

(32.136)Y(z) = X(z)⋅

STF

(−z−2) + E(z)⋅

NTF

(1 + z−2)2

Writing the modulation noise for a bandpass modulator results in

(32.137)NTF( f ) 2 ⋅ VQe( f ) 2 = VLSB2

12f s⋅ 2 cos 2π f

f s

4


Out

Figure 32.90 Block diagram of a fourth-order bandpass modulator.

G1X(z)

E(z)

11 + z−2

Y(z)−z−2

1 + z−2G2

Figure 32.91 shows the modulation noise spectrum of a fourth-order modulator, Eq.(32.127). Notice how, at fs /4 , the modulation noise goes to zero. The oversampling ratiois, once again, defined as

(32.138)K =f s

2B

If fs /4 = 25 MHz and the desired bandwidth is 50 kHz, then K = 1000.

Implementing a Bandpass Modulator

Towards implementing a bandpass modulator, consider the circuit shown in Fig. 32.92.The top portion of the circuit is simply the DAI discussed in Sec. 31.3.1. The bottomportion provides the positive feedback needed for the addition (instead of subtraction) ofthe delayed output. We've adjusted the values of the capacitors so that the resultingtransfer function of the DAI is (see question 31.51 in the last chapter)

(32.139)Vout(z) = V1(z) ⋅ z−1/2 − V2(z)1 + z−1

⋅ CI

CF

To change the denominator in this equation to , we can use a clocking frequency of1 + z−2

fs,new = 2fs , effectively changing the z−1 to z−2 where z is still . In most practicalej2π⋅ f

fs

implementations fully-differential integrators are used [6]. The inverting block in Fig.32.92 is implemented with the inverting output of the fully-differential op-amp.


Figure 32.91 Modulation noise in a bandpass modulator.

B

V2/Hz

fs/4 f s = 100 MHz

In a bandpass modulators 1/f noise isn't a concern since it is filtered out with thedigital filter. If the modulator is used in a wireless application where the intermediatefrequency (IF) is fs /4, extracting the real (I, or in-phase component) and imaginary (Q, orquadrature component) becomes trivial (see Fig. 32.93). Since a single modulator is used,and the I/Q extraction is digital, the channel mismatch encountered in typical basebanddemodulators is absent.

We might wonder, after looking at this figure, how we multiply the modulatoroutput, a one-bit word, by 1, 0, and −1. We know that a 1 coming out of the modulatorcorresponds to VREF+ and a zero corresponds to VREF−. After reviewing Fig. 31.37 in the


Figure 32.92 Implementing a DAI for use in a bandpass modulator.

1

CF

CI

2CF

φ1 φ2

VCM

VCM

V2(z)

V1(z)

VCM

−Vout(z)

Vout(z)VCM

Bandpassmodulator

IF

In

Figure 32.93 Digital I/Q demodulation.

BPF

BPF

I output

Q output

Centered at

Multipliers See Fig. 31.74

f s = 4 ⋅ f IF

f IF =f s

4

cos 2πfIF ⋅ nTs = cos nπ2

= 1, 0, −1, 0...

sin2πf IF ⋅ nTs = sinnπ2

= 0, 1, 0, −1...

last chapter, we can convert these one-bit outputs to two-bit words in two's complementformat. A 1 output is changed to 01 (+1) and a modulator output of 0 becomes 11 (−1) intwo's complement prior to multiplication. Multiplication results in 01 × 1 = 01, 01 × 0 =00, 01 × −1 = 11, 11 × 1 = 11, 11 × 0 = 00, or 11 × −1 = 01. A simple MUX with somelogic for output selection can be used to implement the multiplier.

REFERENCES






[6] A. K. Ong, "Bandpass Analog-to-Digital Conversion for Wireless Applications," Ph.D.Dissertation, Stanford University, September 1998.

QUESTIONS

32.1 Show the details and assumptions leading to Eq. (32.1).

32.2 Would it be possible to operate the DAI of Fig. 32.3 without a 0.75 V supply?Give an example. Show simulation results with the output initially at 0.75 V andthe same input used to generate Fig. 32.4. Are the DAI outputs the same?

32.3 Show the derivation of Eq. (32.4) from the block diagram shown in Fig. 32.6.

32.4 In the basic NS modulator shown in Fig. 32.7 what component serves as the ADC?What component serves as the DAC?

32.5 Show, using timing diagrams, how Eq. (32.5) is correct.

32.6 Show, using SPICE simulations, how increasing the RC circuit's time constant inFig. 32.10 will remove additional modulation noise making the output smoother.What happens to the amplitude of the desired signal?

32.7 Show the spectrums (modulator input, output, and output after filtering) of thesignals in question 32.6. Discuss what the spectrums indicate.

32.8 Explain how the quantizer in Fig. 32.12 functions.

32.9 What are we assuming about an input signal if the modulation noise follows Eq.(32.7)?


32.10 What is the magnitude of Eq. (32.7)?

32.11 What is the difference between quantization noise and modulation noise?

32.12 Show the steps and assumptions leading to Eq. (32.15)?

32.13 Is the statement that on page 163 that "every doubling in the oversampling ratioresults in 1.5 bits increase in resolution" really true if K is small (say 8 or 16)?Explain?

32.14 Does noise-shaping work for DC input signals? If so, how?

32.15 Show the steps leading up to Eq. (32.25).

32.16 What is the impulse response of the following z-domain transfer function?

H(z) =

1 − z−16

1 − z−1

2

32.17 Regenerate Fig. 32.23 if L = 3. What is the droop at B?

32.18 Is it possible to eliminate the op-amp in Fig. 32.24 and use the following topology?Comment on the problems associated with this topology.

32.19 Simulate the operation of the circuit shown in Fig. 32.94.

32.20 Sketch a modulator output, similar to Fig. 32.27, if the input is 0.2 V.

32.21 In your own words describe ripple in the output of a digital filter connected to anNS modulator.

32.22 Does adding a dither signal to the input of a NS modulator help reduce thepeak-to-peak ripple in the digital filter output? Does it help to break up tones inthe filter's output?

32.23 Derive Eq. (32.39).


Figure 32.94 First-order NS modulator for question 32.18.

C

R

R

VCM

φ

VoutVin

−Vout

32.24 Repeat Ex. 32.11 if the integrator's gain is set to 0.5.

32.25 Verify Eq. 32.43 is correct. Use pictures if needed.

32.26 Would large parasitic op-amp input capacitance affect the settling time of a DAI?

32.27 Determine the transfer function of the DAI shown in Fig. 32.43.

32.28 Derive Eq. (32.65).

32.29 Sketch the implementation of the full-differential second-order NS modulator.

32.30 Derive Eq. (32.75)

32.31 Sketch the fully-differential equivalent of Fig. 32.59.

32.32 Resimulate the modulator in Ex. 32.13 if the gains are set to one. Comment on thestability of the resulting circuit.

32.33 Resimulate the modulator in Ex. 32.13 if the input is only 50 mV. Comment on thestability of the resulting circuit.

32.34 Regenerate Fig. 32.67 by selecting integrator gains so that the maximum outputswing of any op-amp is 1.3 V.

32.35 Comment, in your own words, why the actual SNR of a NS-based data convertercan be worse than the ideal values calculated in the chapter.

32.36 Derive Eq. (32.91). Make sure each step of the derivation includes comments.

32.37 Resimulate Fig. 32.74 using two-bit ADC and DAC.

32.38 Sketch a possible implementation of a quantizer for the error feedback modulatorshown in Fig. 32.78.

32.39 What transfer function does the following block diagram implement.

32.40 In Fig. 32.84 sketch the block diagram implementation of the circuit in series withthe Y2(z) output.

32.41 Sketch the block diagram implementation of the transfer function . What(1 − z−2)2

kind of filter does this transfer function implement?


shift-left

Figure 32.95 Circuit for problem 32.39.

Y(z)X(z)

×2

z−1

z−2

32.42 Sketch the implementation of the multipliers in Fig. 32.93.

32.43 Would clock jitter be a concern in a bandpass modulator? (Hint: review Fig. 31.14in the last chapter and the associated discussion.)


Submicron CMOS Circuit Design

In this chapter we turn our attention towards transistor-level circuit design using asubmicron CMOS process, that is, a CMOS process with a minimum channel length, Lmin ,less than 1 µm. We divide the chapter up into three sections. The first section covers basicsubmicron CMOS processes and device models. The second and third sections providedigital and analog circuit design examples and discussions, respectively. We assume,throughout the chapter, that the reader is well grounded in the material presented inCMOS: Circuit Design, Layout, and Simulation [1] (the first CMOS book).

Before getting too far into this chapter, let's discuss how we distinguish thematerial presented here from the material presented in the first CMOS book. If we recall,in the first CMOS book, an older CMOS process was used to illustrate the fundamentaldesign ideas, methods, and procedures and to provide practical models for comparinghand- calculations and simulation results. The older CMOS devices followed the"square-law" MOSFET model. While one can argue that the older CMOS processes willnever be obsolete because of their inherent higher voltage handling capability (a modernCMOS process generally limits VDD, with VSS = 0, to between 1 and 3.3 Volts), this isn'tthe main reason for using them to illustrate design fundamentals. The main reason comesfrom the fact that hand-calculation parameters (transconductance and output resistance,for example) are derived from the SPICE Level 1 square-law model. An older MOSFETthat can then be modeled relatively well using the Level 1 model yields simulation resultswhich match hand-calculations and provides immediate feedback to the designer that "Iknow what I'm doing." The Level 1 model can accurately model devices with an Lmin > 5µm. Reasonable hand-calculation accuracy, say within 20 percent, can be achieved in aprocess with Lmin between 1 µm and 5 µm (in any case, though, the most accurate SPICEMOSFET model available should be used). However, if hand-calculations, based on theLevel 1 square-law model, are used in a submicron CMOS process, the error is generallywell above 100 percent! As an example, Fig. 33.1a shows an IV plot of a typical 0.5 µm(= Lmin ) NMOS transistor while Fig. 33.1b shows the Level 1 SPICE results.

Chapter

33

Looking at Fig. 33.1 we should make several key observations. To begin, noticehow the drain current, ID , varies as the square of the gate-source voltage, VGS , in the level1 model (b) while the variation in the actual curves (a) is more or less linear with VGS .Next, notice how the point the MOSFET enters the saturation region, VDS,sat , is defined byVGS − VTHN (the gate-source voltage minus the NMOS threshold voltage) in the level 1model (b). This, as was discussed in Chs. 5 and 6, results in an overestimate of VDS,sat and isthe reason body-effect is neglected so often in DC hand-calculations. Finally, notice howthe slope of the curves, when the MOSFET is operating in the saturation region, is largerin (b) then in (a). We know that the small-signal output resistance of the MOSFET is thereciprocal of this slope. Further then, we would expect the Level 1 model to provide lowervalues of gain in simulations than a model that more exactly matches (a).

33.1 Submicron CMOS: Overview and Models

In this section we discuss the CMOS process flow [2] for devices with Lmin less than 0.35µm, implementation of capacitors and resistors, and lastly the EKV MOSFET model [3-5]and why we'll use this model to illustrate circuit design techniques in this book.

33.1.1 CMOS Process Flow

Figure 33.2 shows the basic CMOS process flow for a sub-0.35 µm process. This processflow illustrates the differences between a submicron process and the older process flowsdiscussed in Chs. 2−4. In particular: 1) shallow trench isolation (STI) is used instead ofthe local oxidation of silicon (LOCOS) for device isolation, 2) n+ poly is used for NMOSformation while p+ poly is used in PMOS formation, 3) lightly doped drains are used toreduce short channel effects, 4) silicided source/drains/gates are used to reduce parasiticresistances, and 5) both devices are surface devices (the PMOS is no longer a buriedchannel device).

We can summarize the process steps, shown in Fig. 33.2, as follows:


Figure 33.1 (a) IV characteristics of a submicron MOSFET and (b) its Level 1SPICE representation.

(a) (b)

L = 0.5 µm and W = 3 µm

ID ID

VDSVDS

VGS = 3V VGS = 3V

(a) starts with a p-type wafer or a p+ wafer with a p- epitaxial layer as discussed inCh. 2. The active areas are patterned by first depositing a thin oxide and a nitride. Aphotoresist is deposited and patterned on the top of the nitride. The exposed areas ofnitride are removed

(b) shows the result of etching down into the silicon areas that are exposed, that is,those not covered with the photoresist (or nitride after the nitride is etched off).

(c) shows the cross-section of the wafer after a thick oxide has been deposited overthe entire wafer and the top of the wafer has undergone polishing using chemical-mechanical polishing (CMP). Notice how the top of the wafer is flat. Also notice theshallow trenches are filled with a chemical vapor deposited (CVD) oxide (called STI orshallow trench isolation). STI is used in place of LOCOS because of the ability todefine smaller openings in the top of the wafer (smaller active area windows.) Theeffective encroachment on the devices' width is reduced and the MOSFETs can beplaced closer together.

(d) shows the implant used for making the body of the PMOS transistors (then-well) and the implants used to adjust the threshold voltage.

(e), at the top of the next page, shows the result of patterning the polysilicon gateson the top of the wafer.

Chapter 33 Submicron CMOS Circuit Design 237

p-type

Pad oxide

Nitride

Photoresist (after patterning)

(a)

p-type (b)After etching

p-type (c)

STI STISTIIsolation

p-type (d)

STI STISTIImplantsn-well

Threshold voltage implant

p-dopingn-doping

Figure 33.2 CMOS process flow.

In Figure 33.2f light, and shallow, implants are shown which are used in lightlydoped drain, or LDD, MOSFET formation.

(g) shows formation of the lateral oxide spacer adjacent to the gate poly (used forLDD MOSFET formation) and the results of using implants to heavily dope the gates,sources and drains. Implanting the gate polysilicon is important. The p+ poly used inthe PMOS formation here results in a surface device (conduction between the drain andsource occurs along the oxide/semiconductor interface) rather than a buried device(conduction occurs through a buried channel.) The threshold voltage of the PMOS iseasier to set precisely (because we don't have to counter dope the channel) and theshort channel effects become less severe. The drawbacks of switching from aburied-channel PMOS to a surface-channel PMOS are the reduction in mobility and theincrease in flicker (1/f noise.)

Finally, (h) shows the cross-sectional view of the resulting NMOS and PMOSdevices after a silicide (combination of silicon and a refractory metal such as tungsten)has been deposited. The addition of the silicide complicates the process but producesdevices that have significantly less parasitic series gate and source/drain resistance.


(cont'd) CMOS process flow.Figure 33.2

p-type (f)

STI STISTI

p- implantn- implant LDD implant

p-type (g)

STI STISTIn+/p+ implants

n+ p+

n+ n+ p+ p+

p-type (h)

STI STISTIAdd silicide

n+ p+

NMOSPMOS

silicide

p-type (e)

STI STISTIn-well

Gate oxide

Undoped polysilicon

Threshold voltage implant not shown

w/ nitride

33.1.2 Capacitors and Resistors

As we saw in the last chapter, capacitors are an important component when implementinga mixed-signal IC. In this section we briefly discuss implementing capacitors and resistorsin a submicron CMOS process. While in some of these processes (for example, a Flashmemory process) two layers of poly are available for capacitor formation, here we assumethat poly-poly capacitors (discussed in Ch. 7) are not available.

Using a MOSFET as a Capacitor

Figure 33.3 shows the CV curve for an NMOS transistor with source, gate, and bodyconnected to ground. We might try to use this device in one of the discrete-analog-integrators (DAIs) of the last chapter. However, the capacitors used in the DAI are"bipolar" (the voltage across them can be positive or negative). We see in the Fig. 33.3that VGS should be much greater than 400 mV (the threshold voltage) for the device tobehave as a capacitor. If VGS falls close to the knee slightly above VTHN , then thecapacitance can become nonlinear and distortion can appear in a circuit's output. Note thatthis curve shifts to the right with a non-zero VSB.

Using a Native or Natural MOSFET Capacitor

Figure 33.4 shows the layout, CV curves, and schematic symbol of the Native, or alsosometimes called the Natural, MOSFET capacitor. The Native MOSFET capacitor isformed by laying out poly over n+ active in an n-well. The result is a shift in theMOSFET's threshold voltage, VTHN . While the Native MOSFET still cannot be used as abipolar capacitor, it does find uses in many applications where low voltages are a concern.

Note that we might be tempted to use this MOSFET in an amplifier (not as acapacitor) as a near-depletion mode device. However, since the source and drain areshorted together through the resistive n-well, the resulting device may not be too useful.

The Floating MOS Capacitor

A novel method of implementing a capacitor using regular PMOS transistors is shown inFig. 33.5[6]. Two PMOS devices are laid out either adjacent or interdigitated in the samen-well. For the moment let's not concern ourselves with the exact voltage of the n-well but


400 mV

Accumulation Strong inversion

Figure 33.3 Using a MOSFET as a capacitor.

Depletion

Cox = εox

tox

Cg

Cg

VG= VTHNVX

rather assume that the capacitor and resistor time constant is so large compared to thesignal frequencies of interest that little charge, ideally zero on average, flows in the bigresistor. An increase in voltage on A, in the figure, will cause an accumulation of chargeunder the left MOSFET's gate oxide. At the same time an equal and opposite charge willappear under the right MOSFET's gate oxide. The result is that the charge accumulated onB will be equal and opposite to the charge accumulated on A. Since the capacitors are inseries the overall capacitance seen between A and B, CAB is the series connection of eachMOSFET's own gate-oxide capacitance as seen in the figure.


The Native or Natural MOSFET.Figure 33.4

p-type

STISTI

n+

n+ n+n-well

n-well

n+ active

poly

(a) Layout view

(b) Cross-sectional view

(c) CV curves for the native MOSFET

100 mV

Cox = εox

tox

Cg

Cg

VG

Figure 33.5 A floating MOS capacitor

Big resistor

A B

(assuming each MOSFETis the same size.)

CAB = CoxWL/2 = Cox/2

VDD

VDD

VX

VX

CAB = Cox/2

CAB < Cox/2

VB

VA

To implement the big resistor in Fig. 33.5, a topology like the one seen in Fig. 33.6can be used [6]. The long L PMOS device is used to generate a very small current. Thiscurrent is mirrored across and used to hold the n-well and p+ active areas at ground (onaverage.) Because the current is so small the actual voltages seen in the n-well and activeareas can be considerably different than ground over short periods of time allowing thecapacitor action discussed above to occur. Finally notice that the MOSFETs used in thecapacitor operate in accumulation as long as the voltage on either side of the capacitor isgreater than VX . For the PMOS equivalent of Fig. 33.3, VX is positive and VTHP is negativewith the source/drain and body grounded.

Metal Capacitors

Probably the most common method of making capacitors in a submicron CMOS process isusing the metal layers. Consider the cross-sectional view of a parallel plate capacitorshown in Fig. 33.7. If the plate capacitance between the metal1 and metal2 dominatesbecause the metals have a large layout area (that is, the fringe capacitance contribution issmall), then the capacitance can be estimated using

(33.1)C12 = Area ⋅ (capacitance per area)

If the capacitance per area is 50 aF/µm2, then it would take an area of 100 µm by 200 µmto implement a 1 pF capacitor. While large area is a problem, it isn't the main problem witha metal parallel-plate capacitor. The main problem occurs from the extremely large bottom


Figure 33.6 Implementing a large resistor for the floating MOS capacitor.

VDD

Long L Floating capacitor

very small current

Figure 33.7 Parallel plate capacitor using metal1 and metal2.

Substrate (p-type)

InsulatorInsulator

Metal2

Metal1

plate parasitic capacitance, that is, the capacitance from metal1 to substrate. This parasiticcapacitance can be anywhere from 80 to 100% of the desired capacitance. Further itusually slows the circuit response and results in a waste of power.

To help decrease the bottom plate's percentage of the desired capacitor valueconsider the cross-sectional view shown in Fig. 33.8 where four layers of metal implementa capacitor. The capacitance of this structure can be estimated using

(33.2)C = C12 + C23 + C34

If plate capacitance between each metal layer is, again, 50 aF/µm2, then the area requiredto implement a 1 pF capacitor is 100 µm by 66 µm. The area needed is reduced by 1/3 ofthe area used in the metal1/metal2-only capacitor. While we used the same platecapacitance value in between each level, we know that this will vary because of thediffering thickness in between the metals. The absolute value of the capacitors, in mostsituations, isn't important but rather the ratio of capacitors is the important parameter, asseen in the last chapter. Also notice how, in a modern CMOS process, the thickness of themetals (made most often now with copper) increases as we move away from the substrate.

The value of the capacitors in Figs. 33.7 and 33.8 was set by the areas of themetals and the corresponding plate capacitance. We assumed the perimeter of the metalsand the resulting fringe capacitance was a small contributor. Figure 33.9 shows typicalminimum sizes and distances between pieces of metal1 where the fringe capacitancedominates. We can make a capacitor using the two pieces of metal1 shown in this figure.A typical value of capacitance per length is 25 aF/µm. The parasitic bottom platecapacitance is half of this value or 12.5 aF/µm. Since, as seen in Fig. 33.9, the electricfields can terminate on the close adjacent metal, the bottom component is a smallerpercentage than it was when the plate capacitance dominated.


Figure 33.8 Cross-sectional view of a parallel plate capacitor using metal1-metal4.

Substrate (p-type)

Metal4

Tungsten plugsMetal3

Example 33.1Estimate the size of a metal1 only 1pF capacitor. Also estimate the bottomparasitic capacitance.

If we look at the layout of the capacitor shown in Fig. 33.10, we can estimate thecapacitance of a 1 µm by 2 µm section as 25 aF/µm2. This would mean that weneed an area of metal1 that measures 200 µm by 200 µm to implement a 1pFcapacitor. The bottom plate capacitance can be estimated as 0.5 pF.

Note that while this capacitor results in twice the area af the metal1/metal2capacitor of Fig. 33.7 and the associated discussion, it only uses one layer of metaland the bottom parasitic is smaller. One might wonder if further benefits can beachieved by using the fringe capacitance and multi-levels of metal.

Consider the use of metal2 and via1 in the implementation of a capacitor shown inFig. 33.11. While the fringe capacitance is still a major component in this capacitorbecause of the addition of the via between the metals it is sometimes called a lateralcapacitor (there exists a "plate" capacitance between the vias). A typical value of


Figure 33.9 Typical size when fringing capacitance dominates.

Layout view

width and distance.

Cross-sectional view with field lines

substrate

Metal1

0.5 µm

Figure 33.10 Layout of a 1 pF capacitor using only metal1.

Layout view (section)

1 µm

2 µm

25 aF25 aF

capacitance for this structure is 200 aF/µm. The bottom plate capacitance remainsapproximately 15 aF/µm. Using additional vias and metal layers will increase thecapacitance but generally not linearly. The higher levels of metal, e.g. metal4 or metal5,generally have larger spacing and width design rules than do the lower levels of metal.Nonetheless, using the lateral capacitor with several layers of metal and vias is the mostcommon way to implement a capacitor in a mixed-signal circuit.

Example 33.2Repeat Ex. 33.1 using the lateral capacitor of Fig. 33.11.

Since the capacitance per length is now 200 aF/µm, the area required for a 1 pFcapacitor, keeping in mind that both metal1 and metal2 are used, is 50 µm by 100µm. The bottom plate capacitance becomes 0.15 pF.

It's interesting to note that if we used four layers of metal with three vias and alateral capacitance value of 500 aF/µm the area drops to 50 µm by 40 µm.

An Important Note

While we've concentrated on the bottom plate parasitic, it is also possible to have a topplate parasitic. Often, to avoid coupling noise into the relatively large area occupied by thecapacitor, a ground plate is placed above the capacitor. This would allow noisy digitalsignals to be routed above the capacitor, as seen in Fig. 33.12.


Layout view

width and distance.

Cross-sectional view

substrate

Metal1, Metal2,and Via1

Via1Metal2

Metal1Tungsten plug(Via1)

Figure 33.11 Using two layers of metal and the via to implement a lateral capacitor.

0.5 µm

Metal2

Metal1

Metal3

Connected to analog ground(shield for the capacitor)

Digital signals

Figure 33.12 Using a metal3 shield to isolate the lateral capacitor.

Metal4

Resistors

Using a large number of capacitors in a circuit can result in large layout area, as justdiscussed. Because of this, resistors are used whenever and wherever possible. Forexample, a digital-to-analog converter (DAC) may have been implemented using a chargeredistribution topology in the past. Now, however, it can be implemented using an R-2Rtopology and in considerably less space. Table 33.1 shows the various characteristics ofresistors available in a submicron CMOS process. In the following discussion we assumethat we are concerned with implementing an R-2R DAC (see Chs. 29 and 34).

SilicidedResistor

Type

Rs(ohms/sq)

AVG.

TCR1(ppm/C)AVG.

TCR2(ppm/C2)

AVG.

VCR1(ppm/V)AVG.

VCR2(ppm/V2)

AVG.

Mis-match

%

n-well 500 ± 10 2400 ± 50 7 ± 0.5 8000 ± 250 500 ± 50 < 0.1

n+ poly 120 ± 1 21± 10 0.6 ± 0.03 700 ± 50 150 ± 15 < 0.5

p+ poly 300 ± 5 160 ± 10 0.8 ± 0.03 600 ± 50 150 ± 15 < 0.2

n+ diff 100 ± 2 1500 ± 10 0.04 ± 0.1 2500 ± 50 350 ± 20 < 0.4

p+ diff 125 ± 3 1400 ± 20 0.4 ± 0.1 80 ± 80 100 ± 25 < 0.6

* n+ poly 3 ± 0.3 3300 ± 90 1.0 ± 0.2 2500 ± 125 3800 ± 400 < 0.4

* p+ poly 2 ± 0.1 3600 ± 50 1.0 ± 0.2 2500 ± 400 5500 ± 250 < 0.7

* n+ diff 3 ± 0.1 3700 ± 50 1.0 ± 0.2 350 ± 150 600 ± 60 < 1.0

* p+ diff 2.5 ± 0.1 3800 ± 40 1.0 ± 0.2 150 ± 50 800 ± 40 < 1.0

Table 33.1 - Properties of resistors in a submicron CMOS process.

At first glance, after reviewing Table 33.1, it may appear as though the n-welloffers the best choice for a resistor in a data converter since it has < 0.1% matchingcharacteristic. However, after reviewing the voltage coefficient specification for then-well, i.e. 0.008/V, we see a problem. If the voltage across one resistor in the R-2Rstring, is 2 V while the voltage across another resistor is 0 V, we will see a mismatchbetween the two resistors of 1.6%. Such a large, voltage varying mismatch can causesevere linearity problems. It should be mentioned in passing that the origin of the n-wellvoltage coefficient comes from the extension of the depletion region into the n-typematerial used in the n-well (a problem not found in polysilicon resistors).

The polysilicon resistors available depends on the process steps. In one scenariothe poly is doped in-situ while it's being deposited. Since the poly is silicided (called apolycide) the possible pn junction between the p+ and n+ poly isn't a concern. If the polyis doped with an implant after it has been deposited, then a nitride layer above the gateoxide is required to keep the implant from penetrating into the MOSFET's channel. Ineither case, a silicide blocking mask is generally available to block out the siliciding of poly(or active.)


The p+ and n+ diffusions (the source and drain areas) can also be used for resistorimplementation. Again, the silicide block can be used to keep from siliciding the diffusions(a silicided diffusion is called a salicide.) Since the matching characteristics, temperaturebehavior, and voltage coefficient are, overall, better for the polysilicon resistors, they aregenerally preferred in the implementation of precision circuits such as data converters.

In general, the resistor’s width and length should be at least 10 and 100 times theminimum feature size of the process, respectively. For example, if Lmin is 0.15 µm, then theminimum width of the resistor should be 1.5 µm. Requiring minimum widths and lengthsfor the resistors is important both for matching and to ensure that the self-heating, whichoccurs because of the different current densities flowing in the R-2R resistors, doesn'tcause any noticeable differences in DAC linearity. In simple terms, the larger resistor areadissipates heat better than the same valued resistor in a smaller area.

Figure 33.13a shows the conceptual layout of an R-2R resistor string in a minimumarea. Figure 33.13b shows the actual layout of the resistors having large width and lengthalong with a large number of contacts to reduce metal/resistive material contact resistance.Figure 33.13c shows the problem of laying out metal over the resistive material, that is,resistor conductivity modulation. The figure shows what happens when a metal, having apotential greater than the potential of the underlying resistor is laid out directly over aresistor. Electrons are attracted towards the surface of the resistor causing spots of lowerresistivity. The solutions to avoiding or reducing conductivity modulation are: 1) avoidingrunning metal over the resistors, 2) using higher levels of metal to route the resistivesignals so as to increase the distance between the resistor and the overlaying metal(remembering vias and contacts must be plentiful to avoid adding unwanted seriesresistance), or 3) inserting a conducting “shield” connected to analog ground and madewith metal1 between the resistors and the routing wires above the R-2R resistor array.

Finally, to conclude this subsection, we ask, “What is the best method of laying outthe resistors in an R-2R string to avoid process gradients and achieve good matching?”While there are no absolute answers, we will discuss a possibility where layout area is aconcern. In other words, we won't discuss methods that use a large amount of layout areato average out process variations but will limit our averaging to at most twice the layoutarea of the R-2R string shown in Fig. 33.13.

Figure 33.14 shows one possibility for averaging process gradients using acommon-centroid configuration (see Ch. 7) with two R-2R strings connected in series. Inthis figure we are assuming that the process variations change linearly with position. Forexample, the first resistor in the string may have an effective value of 1k, while thesecond's value may be 1.01k, and the third's value is 1.02k, etc. The normalized change inthe resistance value is shown in the figure using numbers. However, we could show thatthe process gradients average out no matter what numbers are used, when using thislayout topology, as long as the sheet resistance varies linearly with position. For example,the MSB 2R in the top string of Fig. 33.14 (on the left) has a value of 14 (6 + 8). TheMSB 2R in the bottom string (on the right) has a value of 24. Adding the values of thetwo resistors, by connecting them in series, results in a resistor value of 38 (2R = 38 whileR = 19). The middle resistor value in the top string has a value of 12 while the bottom

246 Part IV Mixed-Signal Circuits Chapter 33 Submicron CMOS Circuit Design 247

dum

my

dum

my

(a)

Simplified layoutview of a resistor.

Layout of actual resistor with largewidth and length for better matchingand power dissipation.

(b)Metal at a potential higher thanthe resistor will attract electronshere.

Metal

Resistor

(c)

Cross sectional view of metal over resistor.

(a) Minimal layout of R-2R string. (b) Actual layout of resistor, and (c) conductivity modulation of the resistor value.

Figure 33.13

resistor has a value of 7. Again, adding the two resistors results in a value of 19.Fundamentally, the limiting factor in matching then becomes the voltage and temperature(because of the different current densities through the resistors) coefficients of theresistors and the finite resistance of the MOSFET switches used in the DAC (discussed inmore detail in the following chapter).

33.1.3 SPICE MOSFET Modeling

In this section we discuss using the EKV MOSFET model[4] in SPICE mixed-signalsimulations. We present a basic overview of the model and why we have selected it for ourexample simulations.

Model Selection

In general, selecting a SPICE MOSFET model for submicron CMOS circuit design beginswith comparing simulated DC curves against measured curves, for example, ID vs. VDS or

248 Part IV Mixed-Signal Circuitsdu

mm

y

dum

my

dum

my

dum

my

+5

Proc

ess

grad

ient

+0

Process gradients

+1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13

1 2 3 4 5 6 7 8 9 10 11 12 13

6 7 8 9 10 11 12 13 14 15 16 17 18

remaining metal connections not shown

Two-string layout for improving matching of R-2Rs. Assumes the resistors are connected together on higher levels ofmetal to avoid conductivity modulation.

Figure 33.14

ID vs VGS. While this is an important concern, and any SPICE model used for simulatingsubmicron circuits should show good agreement, it won't be what we focus on here. Herewe focus on the ability of the model to transition continuously from weak to stronginversion. While we might think that looking at the DC curves of a device (e.g., ID vs VGS )would show the discontinuities (kinks) between weak and strong inversion, a much betterindication is to look at several devices operating under similar, related conditions.

Consider the binary weighted current mirror shown in Fig. 33.15. In the followingdiscussion we assume the lengths and widths of the devices are so large thatoxide-encroachment and lateral diffusion are not an issue. Clearly, in Fig. 33.15, theMOSFETs will all be operating in the same region, for example, strong inversion. Whatwe are going to do, with the binary weighted current mirror, is utilize the fact thatMOSFETs in series and parallel can be combined, as seen in Fig. 33.16, to implement atest circuit to evaluate the performance of our submircon SPICE model. Note that our testcircuit will have nothing to do, directly, with short-channel behavior but rather it willevaluate the fundamental implementation of the model.


VDD

Figure 33.15 Binary weighted current mirror.

WL W

L12

WL

14

WL

18

WL

116

WL

IREF IREFIREF

2IREF

4IREF

8IREF

16

Figure 33.16 Combining parallel and series MOSFETs.

Drain

Source

Gate

Drain

Source

Gate

Drain

Source

Gate

Drain

Source

Gate

Equivalent Equivalent

WL

W2L

WL

WL

WL

2WL

Figure 33.17 shows the implementation of the binary-weighted current mirrorusing a W-2W topology (based on the R-2R divider discussed in the last section.) Tounderstand the operation of this circuit first note that currents in M1 and M2 have thesame value. Next, notice that the currents flowing in the remaining MOSFETs should sumto IREF. In fact, using the information shown in Fig. 33.16, the remaining MOSFETs can becombined into a MOSFET with the same size as M1 or M2 (and, again, having a draincurrent of IREF). Each stage we add to this topology essentially divides the referencecurrent by two keeping the overall sum of the currents at IREF.

This circuit is useful because it now relates the current flowing in a stronglyinverted device, say M1 or M2 in Fig. 33.17, to a weakly inverted device, say M3. If theMOSFET model is operating with a truly continuous change from one region to anotherthe currents will be binary related and sum to IREF. Figure 33.18 shows the simulationresults for an eight-stage W-2W current mirror modeled with the EKV model. The one totwo-percent error in the binary currents is related to the differing drain-to-source voltages,VDS , of the devices. The minimum length of the device modeled by the EKV model in thissimulation is 0.15 µm while the actual length used in the simulation is 5 µm (33 timesminimum.) The widths of the devices used in the simulation are 20 µm and 40 µm.

Figure 33.19 shows the simulation results using a MOSFET model that doesn'tmodel these transitions well. If one were to use this model where the W-2W section isused in a DAC, the designer might think the DAC performance is circuit-limited and notmatching-limited (keeping in mind that all MOSFETs are perfectly matched in a SPICEsimulation.) This also points out an important point: Simulations don't always tell thetruth! The good design engineer knows the limitations of the models and the simulator.

While there are other reasons for using the EKV model (simulation speed, scaling,well-behaved, etc.) the topic of MOSFET modeling is outside the scope of this book [5].


VDD

Figure 33.17 W-2W current mirror.

M1 M2M3

WL

WL

WL

WL

WL

WL

IREF IREFIREF

2IREF

4IREF

8IREF

8

IREF IREF

2IREF

4

2WL

2WL

2WL


Figure 33.19 Simulated W-2W current mirror showing model problems.

% E

rror

fro

m id

eal v

alue

Figure 33.18 Simulated W-2W current mirror using EKV model.

% E

rror

fro

m id

eal v

alue

Model Parameters

The EKV model parameters are listed below for both NMOS and PMOS devices. Noticethat the minimum length is 0.15 µm and the minimum width is 1.05 µm. Also note that thelevel used depends on the simulator. For the simulations in this book, again, we will utilizeWinSPICE. While some of the model names are discussed in Ch. 5, informationconcerning the remaining names can be found in [4]. Also note that these models arelocated in the file models.txt in the zip file chap33_spice.zip located at cmosedu.com.

*** SPICE Models

*** Models created by Daniel Foty.*** (c) 2001, Gilgamesh Associates and EPFL - All rights reserved.*** These models are provided without warranty or support.*** These models represent a completely fictitious 0.15um process, and do*** NOT correspond to any real silicon process. They are provided expressly for*** use in the examples provided in this text, and should not be used for any *** real silicon product design.

*** NMOS EKV MOSFET Model ****************************************************** Level=44 in WinSPICE and ELDO, Level=55 in ADM/HSPICE, Level=5 in PSPICE, *** Level=EKV in Spectre*** Lmin=0.15u Wmin=1.05u (If Scale=0.15u then Lmin=1 and Wmin=7)*---------------.MODEL nmos nmos+ LEVEL=44

*** Setup Parameters+ UPDATE=2.6

*** Process Related Model Parameters+ COX=9.083E-3 XJ=0.15E-6

*** Intrinsic Model Parameters+ VTO=0.4 GAMMA=0.71 PHI=0.97 KP=453E-6+ E0=88.0E6 UCRIT=4.0E6 + DL=-0.05E-6 DW=-0.02E-6+ LAMBDA = 0.30 LETA=0.28 WETA=0+ Q0=280E-6 LK=0.5E-6

*** Substrate Current Parameters+ IBN=1.0 IBA=200E6 IBB=350E6

*** Intrinsic Model Temperature Parameters+ TNOM=27.0 TCV=1.5E-3 BEX=-1.5 UCEX=1.7 IBBT=0

*** 1/f Noise Model Parameters+ KF=1E-27 AF=1

*** Series Resistance and Area Calculation Parameters+ HDIF=0.24e-6 ACM=3 RSH=5.0 RS=1250.526+ RD=1250.526 LDIF=0.07e-6


*** Junction Current Parameters+ JS=1.0E-6 JSW=5.0E-11 XTI=0 N=1.5

*** Junction Capacitances Parameters+ CJ=1.0E-3 CJSW=2.0E-10 CJGATE=5.0E-10+ MJ=0.5 MJSW=0.3 PB=0.9 PBSW=0.9 FC=0.5

*** Gate Overlap Capacitances+ CGSO=3.0E-10 CGDO=3.0E-10 CGBO=3.0E-11

*** PMOS EKV MOSFET Model ****************************************************** Level=44 in WinSPICE and ELDO, Level=55 in ADM/HSPICE, Level=5 in PSPICE, *** Level=EKV in Spectre*** Lmin=0.15u Wmin=1.05u (If Scale=0.15u then Lmin=1 and Wmin=7)*---------------.MODEL pmos pmos+ LEVEL = 44

*** Setup Parameters+ UPDATE = 2.6

*** Process Related Model Parameters+ COX=9.083E-3 XJ=0.15E-6

*** Intrinsic Model Parameters+ VTO=-0.4 GAMMA=0.69 PHI=0.87 KP=92.15E-6+ E0=51.0E6 UCRIT=18.0E6+ DL=-0.05E-6 DW=-0.03E-6+ LAMBDA=1.1 LETA=0.45 WETA=0+ Q0=200E-6 LK=0.6E-6

*** Substrate Current Parameters + IBN=1.0 IBA=0.0 IBB=300E6

*** Intrinsic Model Temperature Parameters + TNOM=25.0 TCV=-1.4E-3 BEX=-1.4 UCEX=2.0 IBBT=0.0

*** 1/f Noise Model Parameters + KF=1.0E-28 AF=1

*** Series Resistance and Area Calculation Parameters + HDIF=0.24E-6 ACM=3 RSH=5.0 RS=3145.263+ RD=3145.263 LDIF=0.07e-6

*** Junction Current Parameters + JS=1.0E-7 JSW=5.0E-12 XTI=0 N=1.8

*** Junction Capacitances Parameters + CJ=1.3E-3 CJSW=2.5E-10 CJGATE=5.5E-10 + MJ=0.5 MJSW=0.35 PB=0.9 PBSW=0.9 FC=0.5

*** Gate Overlap Capacitances + CGSO=3.2E-10 CGDO=3.2E-10 CGBO=3.0E-11


An Important Note

We will be using the "scale" option available in WinSPICE with the EKV model. Thisoption is added to a netlist as follows

.option scale=0.15u

A MOSFET specified by

M1 1 2 3 4 NMOS L=1 W=10

would indicate that the MOSFET has a length of 0.15 µm and a width of 1.5 µm. Apossible mistake, when writing a netlist manually, would be to forget to add the scaleparameter.

Figures 33.20 and 33.21 show example IV plots for both NMOS and PMOSdevices. The NMOS device is sized 10/1 (actual width 1.5 µm and length 0.15 µm). ThePMOS device is sized twice as large as the NMOS, that is, 20/1 so that its current levelsare similar to the NMOS device. In our example process used in the book VDD is 1.5 V.


D

S

BG

Figure 33.20 NMOS curves for L = 1 and W=10.

10/1

VDS

VGS

VSBVGS

ID

VSB = 0

VSB = 1.25

IDID

VGS = 1.5

VGS = 1.25

VDS

VSB = 0 VDS = 1.5 V

A Note Concerning "Long L MOSFETs"

We might think that with the terminology "Long L" simply by making the MOSFET'slength very long we can avoid short-channel effects. Further, we might believe that using along length would result in a device that follows the square-law model. Unfortunately,though, as the process dimensions shrink the devices are designed to drop large voltagesover small distances. A 5 µm length device in a 0.15 µm process will have significantlydifferent characteristics than a 5 µm device in a 2 µm process. Increasing the channellength will not, significantly, affect the depletion width between the channel and the drain(assuming the MOSFET is in saturation) for a fixed VDS .

33.2 Digital Circuit Design

In this section we discuss digital circuit design using a CMOS submicron process. Ourfocus will be on the digital building blocks used in the last two chapters, that is, switches,delay elements, counters, and adders. We assume the MOSFET models discussed in thelast section accurately model the fictitious submicron process used in the design examplespresented in this chapter.


D

S

BG

Figure 33.21 PMOS curves for L = 1 and W=20.

20/1

VSG

VSD

VBSVSG

ID

VBS = 0

VBS = 1.25

IDID

VSG = 1.5

VSG = 1.25

VSD

VBS = 0 VSD = 1.5 V

33.2.1 The MOSFET Switch

In this section we assume the reader is familiar with the material concerning the switchesdiscussed in Chs. 10 and 27. Figure 33.22 shows a basic NMOS switch in a testconfiguration for determining its effective digital switching resistance. From the simulationresults shown in Fig. 33.23 we can relate the length and width of a MOSFET to theeffective digital resistance in our submicron process using

(33.3)Rn = 10 kΩ ⋅ LW

Notice that this is an average estimate for the resistance in all cases. Also notice that theresistance decreases as the voltage across the switch, here VDS, decreases.


Figure 33.23 NMOS effective resistance from Fig. 33.22.

W/L = 10/1

20/1

50/1

Rn

VDS

1.5

Figure 33.22 Determining resistance of an NMOS switch.

S D

VDSID

Rn = VDS

IDW/L

Example 33.3Estimate, and verify with a SPICE simulation, the delay-time in the followingcircuit.

Using Eq. (33.3) the effective digital resistance of the MOSFET is 1k. Thepropagation delay (input going high and output going low) can then be estimated,knowing the load capacitance is much larger than the MOSFET capacitances,using

tPHL = Rn ⋅ CL = 1k ⋅ 1 pF = 1 ns

The SPICE simulation results are shown in Fig. 33.25.

Figure 33.26 shows the test circuit used to determine the PMOS effective digitalswitching resistance, Rp. From the simulation results shown in Fig. 33.27 we can write

(33.4)Rp = 20 kΩ ⋅ LW

Again this is an average estimate for the resistance for all source-to-drain voltages. Alsonote how it doesn't matter if we use actual device sizes or scaled sizes in this equationbecause of the ratio.


Initially at 1.5 V

1 pF10/10

1.5

Vout

Figure 33.24 Circuit used in Ex. 33.3.

Figure 33.25 Simulation results for Ex. 33.3

tPHL

VinVout

Bi-directional Switches

The NMOS and PMOS switches shown in Figs. 33.22 and 33.26 make use of the fact thatthe NMOS source is connected to ground and the PMOS source is connected to VDD.For complimentary static CMOS logic design we can rely on Eqs. (33.3) and (33.4) toestimate the MOSFET sizes for a particular drive strength. However, if the MOSFET isused as a pass gate where current can flow bi-directionally, the effective switchingresistance can become very large. This is related to the fact that the PMOS switch can'tpass a logic low (0 V) well and an NMOS switch can't pass a logic high well (VDD). Ofcourse, combining the NMOS and PMOS into a transmission gate (TG) eliminates thisconcern at the price of larger layout area and the need for two complimentary clocks.


1.5

Figure 33.26 Determining resistance of an PMOS switch.

Note: body of PMOS istied to 1.5 V.

SD

VDID

Rp = 1.5 − VD

ID

W/L

Figure 33.27 PMOS effective resistance from Fig. 33.26.

W/L = 20/1

40/1

100/1

Rp

VD

Figure 33.28 shows the NMOS device used as a switch with the input at VDD (=1.5 V here.) Figure 33.29 shows how the effective switching resistance of this devicechanges with size under various output voltages. Notice that, as we would expect, Rn getsvery large as the output approaches VDD − VTHN (with body effect).

Another application where a switch can be used bi-directionally was in thediscrete- analog-integrator (DAI) discussed in the last chapter. If the switches used in theDAI can be replaced with NMOS devices the implementation is simpler. If we increase thevoltage of the gate signal, it is possible to turn the MOSFET all the way on and pass VDDfrom the switches' input to its output. Figure 33.30 shows the results if the gate signal inFig. 33.28 is increased to 2.3 V.


1.5

Figure 33.28 Determining resistance of a bidirectional NMOS switch.

In Out

1.5 VoutID

Rn = 1.5 − Vout

IDW/L

Figure 33.29 NMOS effective resistance from Fig. 33.28.

W/L = 10/1

20/1 50/1

Rn

Vout

Towards the goal of increasing the amplitude of the clock signal controlling theswitches consider the bootstrapped clock driver circuit shown in Fig. 33.31. This circuit isa simple implementation of a voltage (charge) pump discussed in Ch. 18. The outputamplitude of the circuit approaches 2VDD so concern for oxide damage or long-termfailure is warranted as discussed in Ch. 6. The inverters are sized with 100/1 PMOS and


Figure 33.30 NMOS effective resistance from Fig. 33.28 with gate at 2.3 V.

W/L = 10/1

20/1

50/1

Rn

Vout

1.5 1.5

20/1 100/1

100/50100/50

Clock in

100f 1,000f

100/1

100/1

Clock out

Figure 33.31 Charge-pump clock driver. Peak output is around 2.8 V.

M1 M2

P

Schematic symbolfor this

In Out

50/1 NMOS devices. The other devices are sized to minimize power while supplying areasonable level of output drive. For example, the 100 fF capacitor only has to supplycharge to the gate of M2, but the 1,000 fF capacitor supplies charge to both the gate ofM1 and the load. Further scaling is possible to further reduce power and enhance outputdrive. Note this circuit is non-inverting and can be used in a nonoverlapping clockgenerator as shown in Fig. 33.32.

The clock generator of Fig. 32.32 provides the two phases of a clock signal as wellas slightly delayed clocks for use in a sample-and-hold, see Ch. 27. As the simulationresults show in Fig. 33.33, the output amplitude is approximately 2.5 V when a 100 fFload is connected to each phase of the output. The time that all four clock signals are low,the non-overlap time (dead-time), can be increased by increasing the delay in series withthe output of the NOR gates. Adding inverter pairs to the outputs of each NOR gate is acommon method of increasing the dead-time. Also note that the capacitors in Fig. 33.31can be implemented using NMOS devices since they will always be in strong inversion.

A Clocked Comparator

One of the circuits that we used often in Ch. 32, in noise-shaping data converters, was aclocked comparator. Let's develop a clocked comparator using inverters and switches.Examine the evolution of circuits shown in Fig. 33.34. In (a) and (b) the basic inverter-based latch is shown. In order to reduce power and make the comparator clocked we addthe NMOS switch shown in (c). Before each comparison, we want to insure thecomparator is equilibrated. To erase the memory of the previous comparison, the PMOSswitch in (d) is added to our circuit. When the clock, φ, goes high, the PMOS device turnsoff and the NMOS device turns on allowing the inverters to latch in a stable condition.The only thing we need to add to this circuit is circuitry to somehow create an imbalanceacross the inverters when φ goes high. We can do this several ways. One possibility isshown in Fig. 33.34e.


CLK

Nonoverlapping clock generation circuit with pumped outputs.Figure 33.32

P P

P P

φ1

φ2

φ2D

φ1D


Figure 33.33 Typical output of Fig. 33.32.

(a) Basic inverter-based latch.

(b) Transistor implementation of (a).

(c) Addition of switch to reduce power.

Figure 33.34 Implementation of a clocked comparator.

(d) Erasing comparator memory.

φφ

In Fig. 33.34e we connect our inputs to two common-source amplifiers whichhave two purposes 1) to amplify the input signals and create an imbalance in the latch and2) to isolate the inputs from the switching noise resulting from the latch positive feedback.(Kickback noise was discussed in Ch. 27.) The two switches we add in series with ourcommon-source amplifiers are not, in all cases, necessary. We add them here to reducepower dissipation when φ is low. The clocked comparator doesn't draw any current whenφ is low. It does, however, draw current when φ is high. The amount is dependent on thevoltage applied to the comparator's inputs. Note also that when φ is low, both Vout+ andVout− are equilibrated to a voltage of VDD − VTHP . This means that the output of thecomparator is essentially a logic high whenever φ is low. In order to make the circuitappear as a truly rising edge comparator, where the comparison from a rising edge is validuntil the next rising, edge an SR flip-flop (see Ch. 13) can be added to the output of theclocked circuit.

Figure 33.35 shows simulation results with a typical input waveform. Note how,when φ is low, the outputs of the latch go to VDD − VTHP . Also note how the final outputsremain valid until the next rising edge of the clock. One thing that this simulation doesn'treveal is the comparator's random offsets. Since the comparator is simulated usingperfectly matched devices, we will only see the comparator's systematic offset (see Ch.25). While comparator offset wasn't a concern in a noise-shaping data converter, it is amajor concern in a Nyquist-rate data converter. We will revisit comparator and op-ampoffsets in Ch. 34.


Figure 33.34 (cont'd) Implementation of a clocked comparator.

NMOS are 10/1PMOS are 20/1

(e) Complete clocked comparator.

Used if both outputs can't gohigh over half of the clock cylcle.

φ

Vout+

Vout−

Vin+ Vin−

out+

out−

One last comment before leaving this topic; notice, after reviewing the simulationnetlist, how we used voltage sources for our comparator inputs. In any practicalsimulation it is a better idea to add some series resistance between the comparator inputsand the voltage sources to simulate finite source impedance. Resistors with 10k values aretypical for simulations of this nature. Using these resistors shows kickback noise on theinputs to the comparator. This noise is often the fundamental limitation of thecomparator's performance in an actual circuit. Methods to reduce this kickback, such ascascoding the input common-source amplifiers or using an additional amplification stagesuch as a diff-amp, should be used in a general application. Note that kickback noiseshouldn't be a problem in the comparator used in a noise-shaping data converter due to thelarge capacitance connected to the input of the comparator (the DAI's integratingcapacitance).

Common-Mode Noise Elimination

High-speed digital signals can often appear more like a sinewave than a squarewave.When these sinewave-like signals are applied to the inputs of a digital gate, the timingdelay between the gate's inputs and output can vary. This delay variation can be the resultof noise coupled onto the wires used to connect the circuits together or because ofpower-supply fluctuations. To avoid these problems in analog circuits, as discussed onpage 191 and in Chs. 25 and 27, fully-differential outputs are used. Using fully-differentialoutputs in a digital system, however, can result in large layout area. The gates must haveboth differential inputs and outputs. Because of this and the large noise-margin of digitalsignals, generally only signals that propagate over long distances will experience


Figure 33.35 Simulation results for the comparator of Fig. 33.34.

φ

Vout+

Vout−

Vin+ = 20mV ⋅ sin 2π ⋅40MHz + 0.75

Vin− = 0.75 V

out+

out−

detrimental noise corruption. However, any digital signal can be corrupted because ofpower-supply fluctuations. In this section we discuss the idea of common-mode noiseelimination, CMNE. The CMNE circuit will, ideally, eliminate common-mode noise on awire pair while, at the same time, not affect the differential component. The technique canbe used to "square-up" digital signals. We apply this technique to the design of ahigh-speed digital buffer.

Towards the design of a CMNE circuit examine Fig. 33.36a. This circuit was theheart, or decision circuit, of our comparator in Ch. 26. Assuming for the moment that alltransistors are sized equally we know that when io+ is greater than io− , the output vo+ isgreater than vo−. Any common signal to both io+ and io− will not be a factor in which signal,vo+ or vo− , is larger. This circuit can only function if both io+ and io− are positive. Figure33.36b shows the decision circuit of (b) where we've added a PMOS decision circuit sothat the currents io+ and io− can be positive or negative. The schematic representation ofthis circuit using inverters is shown in Fig. 33.36c.


Common-mode noise elimation circuit.Figure 33.36

(a) Basic decision circuit.

(c) Schematic diagram of (b)

VDD

(b) CMOS decision circuit.

io+ io−

vo+ vo−vo−vo+

io+io−

vo−

vo+io+

io−

To determine quantitatively how this circuit functions, consider the inverter outputvs. input plot shown in Fig. 33.37. The switching point, VSP , is defined as the point wherethe inverter's input and the output voltages are equal. This is also the DC operating pointof the CMNE circuit in Fig. 33.36c with zero input current. The inverter's model is alsoshown in this figure. When vIN increases, vOUT ( = ) decreases. The actualgm ⋅ vIN ⋅ ro

values of gm and ro are not needed to understand the operation of the CMNE circuit.

Consider the CMNE circuit shown with the inverter currents in Fig. 33.38. In thiscircuit the input current is made up of a common mode component, ICM , and a differencemode component, idiff , so that

(33.5)io+ = iCM + idiff


vIN vOUT

VSP

VSP

vIN

vOUT

vOUT

vIN

gm ⋅ vIN ro

Figure 33.38 Analysis of a CMNE circuit.

vo−

vo+

iCM

iCM

idiff

idiff

gm ⋅ vo−

gm ⋅ vo+

gm ⋅ vo+

gm ⋅ vo− ro

2

ro

2

Figure 33.37 Modeling an inverter.

Inverter model

20/10

and

(33.6)io+ = iCM + idiff

The resistors with values ro/2 connected to the two signal nodes model the parallelcombination of the two inverter's output resistance at each node. The fact that there areonly two signal nodes in this circuit is an important point since we don't want the CMNEcircuit to affect the desired, fully-differential, signals. We want the desired signal to passthrough the CMNE circuit without any delay. If we sum the currents at each node we get

(33.7)idiff = gmvo− + gmvo+ + vo+

ro/2+ iCM

and

(33.8)−idiff = gmvo− + gmvo+ + vo−

ro/2+ iCM

Taking the difference in these two equations results in

(33.9)idiff = vo+ − vo−ro

If we write the outputs as

(33.10)vo+ = vcm + vdiff

and

(33.11)vo− = vcm − vdiff

we notice the common-mode component subtracts leaving

(33.12)vdiff = idiff ⋅ ro

2

This equation shows that the input signal, idiff , generates an output voltage, vdiff , and thatany common-mode noise, vcm , is removed from the output signal.

A simple, yet useful, application of CMNE is shown in Fig. 33.39. Here theCMNE circuit is placed in between two inverters. This circuit essentially behaves like adiff-amp, or a comparator, amplifying the difference in the input signals and rejecting thecommon-mode component. To be more correct, the common-mode component is shortedto an inverter switching point voltage, VSP , so that the difference-mode signals swingaround VSP. The inverters added at the end of the circuit ensure that good, solid CMOSlogic levels are output from the circuit.

Figure 33.40 shows a plot of the buffer's output against its input for referencevoltages, VREF , of 0.7 and 0.9 V. As we would expect, the buffer switches states only afterthe input exceeds the reference voltage. This buffer can also be used if the input signals arecomplementary logic signals. The delay through the buffer is only two inverter delays.

Because of the two inverters with their inputs shorted to their outputs the powerdissipation in this basic example can be excessive (approximately 1 mA for the examplegiven here). To reduce the current draw the CMNE circuit can be scaled.


One might wonder, after reviewing Fig. 33.40, if it's possible to increase the gainof the buffer by adjusting the sizes of the inverters. We see that it takes over 300 mV inputsignal to cause a full logic transition on the buffer's output. Also, it would be nice if thebuffer could be designed to have hysteresis, as discussed in Ch. 26. While we can increasethe length of the devices used in the inverters to both increase the gain and decrease thepower dissipation, the trade-offs are decreases in speed (the delay through the buffer) andfrequency response of the CMNE circuit. At very high-frequencies the inverters aren't fastenough to eliminate common-mode noise.

After reviewing how we introduced hysteresis into our decision circuit back in Ch.26, we see that by increasing the length of the MOSFETs used in the shorted input/outputinverter we can achieve the same results in the buffer of Fig. 33.39. Consider Fig. 33.41, aredrawn version of Fig. 33.38, with weak inverters. By weak we mean that the W/L ratio


Figure 33.39 A digital buffer (comparator) using CMNE.

NMOS 10/1PMOS 20/1

vin vout

voutVREF or vin

Figure 33.40 Simulating the circuit in Fig. 33.39 showing switching-pointsfor references of 0.7 and 0.9 V.

VREF = 0.7 V

VREF = 0.9 Vvout and vout

vin

of the transistors used in this inverter is smaller than the other W/Ls used in the circuit.We indicate that the modified inverter's gm is now weak, and thus less than the otherinverter's gm, by relabeling it gmw. We can rewrite Eq. (33.9) as

(33.13)idiff = vo+ − vo−ro

+ (gmw − gm) ⋅ vo+ − vo−

2

or

(33.14)idiff =

2vdiff

(vo+ − vo−) ⋅ 1

ro+ 1

2/(gmw − gm)

This equation can be written as

(33.15)vdiff = idiff ⋅

ro

21

gmw − gm

Since gmw is less than gm , the effective resistor added in parallel with ro is negative havingthe effect of increasing the resistive loading of the CMNE circuit. This increase has theeffect of boosting the differential gain of the buffer of Fig. 33.39 and introducinghysteresis into the switching point. Note that if gmw is equal to gm , then Eq. (33.15)reduces to Eq. (33.12).

The allowable range of VREF is set by the threshold voltages and the powersupplies. For example, VREF can be no larger than VDD − VTHP. In reality VREF is limited tovoltages less than this because the drive of the inverter connected to VREF decreases.Notice, in Fig. 33.40, how the final output crossover point is creeping towards VDD.

The CMNE technique can be used in a variety of places including delay-lockedloops or input and output buffers or simply to balance two differential digital signals.While we used CMOS inverters here the technique can be extended to use invertingamplifiers. We will extend this technique to balancing the outputs of fully-differentialop-amps later in the chapter.


Figure 33.41 Figure 33.38 redrawn with weak inverters for hysteresis.

Make a weak inverter

Make a weak inverter

vo−

vo+

iCM

iCM

idiff

idiff

gmw ⋅ vo−

gmw ⋅ vo+

gm ⋅ vo+

gm ⋅ vo− ro

2

ro

2

Example 33.4Resimulate the buffer shown in Fig. 33.39 if the length of the MOSFETs isincreased to 2. Rerun the simulation if weak inverters, Fig. 33.41, are used withtheir Ls increased from 2 to 2.1.

Figure 33.42 shows the simulation results. In (a) the increase in gain with theincrease in L from 1 to 2 is evident. The current drawn from VDD decreases from1 mA to 0.5 mA. Note, in this figure, we show VREF = 0.5, 0.7, and 0.9 V. Thereferences at 0.5 and 0.9 are at the edge of the allowable reference voltages, VREF.In (b) the small increase in the weak inverter's width (only 5%) shows that the gainis improved further. This small increase introduces little hysteresis into the inputbuffer. Increasing the weak inverter's length further, say to 3, causes both the gainand hysteresis to further increase.


Figure 33.42 Simulation results for the buffers described in Ex. 33.4.

(a)

(b)

VREF = 0.5 V

VREF = 0.7 V VREF = 0.9 V

vin

VREF = 0.5 V

VREF = 0.7 V VREF = 0.9 V

vin

vout and vout

vout and vout

33.2.2 Delay Elements

Delay elements were used to implement our digital averaging or comb filters in Ch. 31.We used these filters on the output of our noise-shaping (NS), modulator-based ADCs oron the input of a NS DAC in Ch. 32. Since the delay elements are continuously clocked,we discuss the use of dynamic circuits in this section. Dynamic elements are used becausethey result in lower power and smaller-layout area than static CMOS circuits. Low powerand small-layout area become extremely important when we realize that a filter mayemploy hundreds, or even thousands, of delays.

Figure 33.43 shows a basic cascade of pass-transistors and inverters first shownand discussed in Ch. 14. When clk goes high, the output of the master is transferred to theslave. When clock goes back low, the input capacitance of the slave inverter remainscharged and the output is unchanged. We can think of this circuit as a rising-edgetriggered D flip-flop. The pass-transistors don't pass a logic high well so the input voltageto the inverters will be at most VDD − VTHN (with body effect). This can result in theinverter having a significant cross-over current and large power dissipation. The averagecurrent pulled from VDD by the circuit of Fig. 33.43 while clocked at 100 MHz andhaving equally sized devices (both 10/1) is 50 µA. To avoid excess current draw, theswitching point of the inverter can be decreased towards ground by making the PMOSdevice weak. The output rise-time, with a weak PMOS device, can become very long.

Figure 33.44 shows a positive edge-triggered delay using clocked-CMOS logic.The problem of having excess power-supply current because of marginal logic levels isabsent in this configuration. However, the layout area will be larger than the delay in Fig.33.43. When the delay of Fig. 33.44 is clocked at 100 MHz, the average current pulledfrom VDD is well below 10 µA. It is easy to implement a reset using this delay cellbecause we have a high-impedance node, that is, the node connecting the master and theslave is never connected directly to ground or VDD. We can implement a reset, or set, inthe circuit in Fig. 33.43 by adding an additional switch in series with the input and twoadditional switches on both inverters' inputs.


clkclk

Figure 33.43 Simple delay element using pass transistors and CMOS inverters.

In Out Out

In

Master Slave

clk

Both cells in Figs. 33.43 and 33.44 require the use of two clock signals. Figure33.45 shows a delay element [7] that functions as an edge-triggered D flip-flop with asingle clock signal. The circuit technique used to implement this delay is termed truesingle-phase clocking (TSPC). As seen in Fig. 33.45 both true and complement outputsare available (the true output being buffered). The current pulled by this delay cell, whenclocked at 100 MHz, is below 10 µA. The layout area is comparable to the layout areaused by the clocked CMOS delay in Fig. 33.46.

By having a complementary output available, and requiring only a single-phaseclock signal, a divide-by-two can be implemented, Fig. 33.46, using TSPC. We used clockfrequency dividers in the implementation of both decimating and interpolating filters (seeFig. 31.63 for example). A divide-by-four is implemented by cascading two divide-by-twocircuits. In the general case, we can implement up- or down-ripple counters by cascadingTSPC delays as seen in Fig. 33.47. Also shown in this figure is a synchronous up counter.


Figure 33.45 Delay element using TSPC.

Out

In

In

Out

Out

(D)

(Q)clk clk

clk

clk

clk

Figure 33.44 Simple delay element using clocked CMOS logic.

In Out

Reset

In

Out

Master Slave

clkclk

clk clk


Figure 33.46 Divide-by-two using TSPC

D

Qclk clk

clk

clk

clk/2clk/2

Figure 33.47 Counters using edge-triggered latches.

D

clk

Q

Q

D

clk

Q

Q

D

clk

Q

Q

Ripple up counter

D

clk

Q

Q

D

clk

Q

Q

D

clk

Q

Q

Ripple down counter

In

D

clk

Q

Q

D

clk

Q

Q

D

clk

Q

Q

TSPC cell in Fig. 33.46

Synchronous up counter

D

clk

Q

Q

D

clk

Q

Q

D

clk

Q

Q

bo

bo

b1

b1

b2

b2

bo

b1

b2

Example 33.5Sketch the implementation of a synchronous up/down counter. Discuss itsoperation.

Figure 33.48 shows the basic block diagram of the counter. An adder is used toeither add or subtract one from the contents of the register. Two's complementnumbers are used in the adder to avoid overflow problems (see Ex. 31.22). TheMUX selects either +1 (= 0000...1) if UP is high or −1 (= 1111...1) if UP is low toadd to the contents of the register.

33.2.3 An Adder

The last digital building block we will look at in this chapter is the adder. An adder wasused in all of our digital filters discussed in Chs. 31 and 32. While there are many ways toimplement adders, here we discuss ripple adders using dynamic logic. Again these designsresult in low power and a small layout area. If the delay through the adder is too long, fora specific application, we use pipelining, Fig. 33.49, to segment the adder's internal delays.Note that using pipelining results in a delay in series with the adder. The adder in Fig.33.49 would have a z−3 delay in series with the output signal. In a practical circuit wewould segment 4-, or more, bit adders instead of the single bit adders shown in the figure.

The output of a 1-bit adder can be written as

(33.16)sout = ain ⋅ bin ⋅ cin +(ain + bin + cin) ⋅ cin

where ain and bin are the adder's inputs while cin is the carry input. The carry output can bewritten as

(33.17)cout = ain ⋅ bin + cin ⋅ (ain + bin)


MUX

000...1

111...1

D

clk

Q

D

clk

Q

D

clk

Q

select, UP

UP

UP

clk

Figure 33.48 Synchronous Up/Down counter using an adder.

bo

b1

bn

Figure 33.50 shows the implementation of a dynamic adder. The first stage generates thecarry out and is implemented in NMOS precharge-evaluate (PE) logic. The second stage isimplemented using PMOS PE logic. The overall gate can be thought of as a domino gate.The output of the adder is valid when clk is high.


Latch

Latch

Latch

Latch

Latch

Latch

Latch

Latch

Latch

Latch

Latch

Latch

0

A 4-bit pipelined adder. The latches (clocked) behave as delay elements.Figure 33.49

1-bit

1-bit

1-bit

1-bit

carry in

carry out

a1

a4

a3

a2

b1

b4

b3

b2

c2

c1

c3

c4

cout

s4

s3

s2

s1

Figure 33.50 Full-adder bit implemented using dynamic logic.

sout

ain

ain

bin

bin

cin

cout

ain

bin cin

cout

clk

ain

bin

cin

clk

33.3 Analog Circuit Design

In this section we discuss analog circuit design using a submicron CMOS process. Weassume the reader is familiar with the fundamentals of analog design presented in Chs.20-25 of [1]. The first subsection presents a discussion of biasing concerns, the second-section discusses op-amp design and the third-section covers circuit noise.

33.3.1 Biasing

When starting an analog design we begin by selecting the excess gate voltage, ∆V, alsoknown as the overdrive voltage, and the biasing current level. Selecting these twoparameters sets the width and length of the MOSFETs. While using large area devices (L⋅W) that are placed close together results in the best device matching [8], our focus herewill be on speed and power.

Selecting the Excess Gate Voltage

Figure 33.51 shows the basic source cross-coupled diff-amp first discussed in Ch. 24. Forthe moment we will assume the minimum voltage across the drain and source of aMOSFET, VDS,sat , is ∆V. Further, we know that the gate-to-source voltage of a MOSFET,VGS , can be written as ∆V + VTHN . In our 0.15 µm process the NMOS and PMOS devices


Vob1

VDD VDD

VDD

VDD

VDD

VDD

Figure 33.51 Op-amp input diff-amp without slew-rate limitations.

M1 M2

M3M4

M5 M6

M7 M8

Vbiasp Vbiasp

VbiasnVbiasn

Vinp Vinm

Vot1Vot2

Vob2

have the same threshold; 0.4 V at room temperature in a typical process run. We willdesign our circuits so the PMOS and NMOS devices have the same gate-to-sourcevoltage. Writing a KVL from VDD to ground through M8, M2, M3, and M5 results in

(33.18)VDD = VSG8 + VDS2 + VSD3 + VGS5

or

(33.19)VDD =

VSG8

∆V + VTHP +

VDS2

∆V +

VSD3

∆V +

VGS5

∆V + VTHN

noting, in Fig. 33.51, we've eliminated the body effect in M3 and M4 by placing them intheir own well. Because VDD = 1.5 and VTHP = VTHN = 0.4, we can set our ∆V to at most175 mV. We know that the threshold voltage will change with process runs and withtemperature so we will select our ∆V as 100 mV to provide some margin for these shifts.This means our nominal VGS (or VSG for the PMOS) in the designs presented here is 0.5 Vand the drain-to-source voltages are 250 mV.

Selecting the Channel Length

The small-signal output resistance decreases with decreasing channel length. Because ofthis we might just select a channel length, for analog applications, ten times the minimumlength and be finished. However, as we'll show in a moment, the speed of the MOSFET isinversely proportional to the channel length and so long L equates to slow speed. Also,layout area is always premium real-estate and so using the smallest possible devices isusually desirable.

Consider the test circuit shown in Fig. 33.52. We've applied 0.5 V DC to the gateof the NMOS device and swept the drain-to-source voltage of the MOSFET. This circuitwas simulated for four different device sizes, 40/4, 30/3, 20/2, and 10/1. Figure 33.52ashows how the drain current changes with changing VDS . More interesting is the plot in33.52b showing the MOSFET's output resistance, ro. Notice, as we would expect, theoutput resistance increases with increasing L. The key point here is that we can increasethe output resistance and thus gain by increasing L. Unfortunately, this results in adecrease in speed. For the designs presented here we will use an L of 2 (a 20/2 NMOSdevice) as a reasonable trade-off between gain and speed. The nominal drain current thatflows in a 20/2 NMOS device with a VGS of 0.5 V is 20 µA. Also note from 33.52b thatthe MOSFET appears to enter the saturation region at approximately 250 mV (not the100 mV we assumed earlier for VDS,sat ).

Figure 33.53 shows the output resistance plots for the PMOS device. Because ofthe weaker drive of the PMOS, we used 20/1, 40/2, 60/3 and 80/4 device sizes in anattempt to match the PMOS and NMOS drive strengths. Note that the gate of the PMOSdevice is connected to a 1 V supply to set the VSG of the PMOS device to 0.5 V. We use a40/2 PMOS device for the designs presented here.

It should be clear, after looking at Figs. 33.52 and 33.53, that we will often not beoperating our devices deep in saturation (and so our gain will suffer). If our device'sdrain-to-source voltage is 100 mV, we will be operating our amplifiers in the triode



Figure 33.52 NMOS curves for 40/4, 30/3, 20/2, and 10/1 devices.

0.5 V

(a) Drain current vs drain-source voltage (b) Output resistance vs drain-source voltage

10/1

20/2

40/4

40/4

30/3

20/2

10/1

VDS

Figure 33.53 PMOS curves for 80/4, 60/3, 40/2, and 20/1 devices.

1.0

(a) Drain current vs drain voltage (b) Output resistance vs drain voltage

1.5 V

S

20/1

40/2

80/4

80/4

60/3

40/2

20/1

VSG = 0.5

VD

region. The circuit design techniques that we use for submicron circuit design shouldallow reasonable gains even if our transistors move into the triode region with temperatureor process variations.

Small-Signal Transconductance, gm

Figures 33.54 and 33.55 show the test circuits and simulation results used to determineeach device's small-signal transconductance, gm. Note how we adjusted the DC drain-to-source voltage so that the devices are operating in the triode region (see Figs. 33.52 and33.53). Note also how we've tried to size the PMOS device to have similar characteristicsas the NMOS but the gm is still half that of the NMOS device.

MOSFET Transition Frequency, fT

The MOSFET's transition frequency, fT , is defined as the frequency where the AC gatecurrent is equal to the AC drain current, or, . This figure-of-merit wasid/ig = 1 = 0 dB


0.5 V

0.1 V

Figure 33.54 NMOS small-signal transconductance.

20/2

id = gmvgs

vgs

gm, µA/V

1.5 V

Figure 33.55 PMOS small-signal transconductance.

1.0 1.4

40/2

id = gmvsg

vsg

gm, µA/V

discussed back in Chs. 9 and 25. Figures 33.56 and 33.57 show how fT is determined fromsimulation results. Large fT indicates high-speed. From a circuit point-of-view

(33.20)fT ∝ VGS

L

Using minimum-length devices with large gate-to-source voltages results in high-speedoperation with low gain (because of the small output resistance, as seen in Figs. 33.52 and33.53) and reduced output swing (using a large VGS results in devices that enter the trioderegion with relatively large drain-to-source voltages).

The Beta Multiplier Self-Biased Reference

Figure 33.58 shows the schematic diagram of a beta-multiplier, self-biased referencedesigned to provide nominally 10 µA of current through a 20/2 NMOS or 40/2 PMOS.We select the beta-multiplier because of its robust temperature characteristics. Theincrease in the resistor with temperature is compensated for by the decrease in the


1.5 V

Figure 33.57 PMOS transition frequency.

1.0

40/2

vsg

id

ig

id

ig

fT

0.5 V

1.5 V

Figure 33.56 NMOS transition frequency.

20/2

fT

id

ig

id

ig

vgs

MOSFET's threshold voltage. The 80/1 device, M2, is large relative to M1 so that its VGS

is approximately 0.4 V (the threshold voltage). Because M2's VGS is 0.5 V, there is 100mV dropped across the 10k resistor (and this sets the current). In a practical circuit,subject to process variations, we can adjust the resistor value by adding series-shorted andparallel resistors to the source of M2. This makes adjusting the current to a specific valuepossible. Note, as discussed in the homework problems of Ch. 21, adding a capacitance toground at the source of M2 can result in an unstable circuit. The reference can actuallyoscillate. This may be a problem if the resistor is bonded out to set the current value.Adding capacitors to ground or VDD at Vbiasn and Vbiasp , however, can often be useful toreduce coupled noise to the bias voltages.

The temperature behavior of the beta-multiplier reference self-biased circuit of Fig.33.58 is shown in Fig. 33.59. The temp-co of the resistor is set to 2,400 ppm/C. VDD isswept on the x-axis while the current flowing in M2/M4 is shown on the y-axis. While wemight think that we can get better power-supply rejection by cascoding the MOSFETs, wewould find that many of the MOSFETs would operate in the triode region.

Figure 33.60 shows a general biasing circuit for analog design. The voltages Vbiasn

and Vbiasp are the inputs to the bias circuit and are supplied by the beta-multiplier of Fig.33.58. The reader who doesn't understand the origin of this circuit is referred back to Ch.20. Note, in this biasing circuit, how we have made an effort to reduce the number ofMOSFET gate-source voltages in between VDD and ground. This is necessary forlow-voltage operation. In the general design, as discussed back in Ch. 20, the size of the

device can be reduced (to, say, ) to bias the device closest to the power supply14 ⋅ W

L15 ⋅ W

L

rails further into the saturation region. This will, generally, provide higher gains at the costof slightly reduced output swing. Figure 33.61 shows the output current through bothNMOS and PMOS cascode current mirrors biased with Vbias1 through Vbias4.


VDD

M5

M6

M7

M3 M4

M1 M2

10/20

10/5

10/1

40/240/2

20/280/1

Start-up circuit

Figure 33.58 Beta-multiplier self-biased reference circuit.

10k

Vbiasn

Vbiasp


Figure 33.59 Temperature behavior of the reference of Fig. 33.58.

Ref

eren

ce c

urre

nt

T = 0 C

T = 100 C

T = 25 C

VDD VDD VDD VDD

40/8

VDD VDD

20/8

All unlabeled PMOS are 40/2All unlabeled NMOS are 20/2

Figure 33.60 General biasing circuits for analog design.

Vbias3

Vbiasn

Vbiasp Vbiasp

Vbiasn

Vbiasn2

Vbiasp2

Vbias2

Vhigh

Vbias1

Vbias4

Vlow

Figure 33.62 shows how the currents in each leg of the diff-amp of Fig. 33.51change as we sweep Vinp with Vinm held at 0.75 V. Note how, with Vinp = Vinm = 0.75 V, thecurrent in each leg of the diff-amp is 6 µA or less than the current in the biasing circuits.This is the result of the body effect experienced by the MOSFETs in the diff-amp.


VDD

40/2

40/2

vtest

Figure 33.61 Using the general purpose biasing circuit of Fig. 33.60.

vtest20/2

20/2

Cur

rent

thro

ugh

vtes

t.C

urre

nt th

roug

h vt

est.

Vbias1

Vbias2

Vbias4

Vbias3T = 100 C

T = 0 C

T = 100 C

T = 0 C

Figure 33.62 DC sweeps showing the currents in each leg of the diff-amp of Fig. 33.51.

T = 100 C

T = 0 CT = 25 CT = 50 CT = 75 C

33.3.2 Op-Amp Design

In this section we present the design of general-purpose, mixed-signal op-amps. Onceagain we assume the reader is familiar with the material in Ch. 25. In particular,compensating two-stage op-amps, floating current sources, output buffers, and fully-differential op-amps. We use the biasing circuits developed in the last section in thedesigns presented in this section. The goals of the designs presented here are robustoperation over wide process variations and temperatures.

Output Swing

Let's begin our op-amp development by considering the inverter shown in Fig. 33.63. Inorder for our op-amp to have the widest possible output swing we must use this structureon the output of the op-amp. (Sometimes this output structure is called a push-pullamplifier because it can both source [push] and sink [pull] a current from the load.) Noticehow we've increase the size of the MOSFETs used in this structure from our standard40/2 and 20/2 devices. This was to both increase the output drive of the op-amp and toincrease the output stage's input capacitance. This capacitance will be used to compensatethe op-amp. Also, because op-amp open-loop gain, AOL , is always important, using anoutput stage with gain increases the op-amp's AOL.

Looking at the transfer curve shown in Fig. 33.63 we see that the gain of theinverter (the slope of the curve) is largest when the output falls between 0.25 and 1.25 V(an output swing of 1 V). Throwing away 0.5 V, or 33%, of the power-supply voltage ona MOSFET operating in the triode region is, of course, highly undesirable. Thinking aboutthis for a moment we may realize that if this (second) stage is preceded by a high-gain(first) stage the op-amp may still function within specifications when the second stage gainis dropping. (Though the distortion introduced into the output stage may be too highbecause of this nonlinearity.) A more important concern then is the quiescent currentpulled through this stage. For the inverter in Fig. 33.63 this current is > 1 mA. For bothgain and power reasons we need to modify this basic output circuit.


400/2

200/2

VDD

voutvin

Figure 33.63 Using an inverter on the output of an op-amp.

vin

vout

= 1.5 V

To lower the quiescent current pulled from VDD and to increase the linear outputswing of the output stage consider adding batteries to the circuit as seen in Fig. 33.64.We've selected the batteries so that when vin is 0.75 V the gate-source voltages of theMOSFETs are 0.5 V. From Figs. 33.52 and 33.53 we can estimate the quiescent current inthe output stage as 150 µA (simulation results verify this estimate). Clearly, increasing thebattery voltages will make the output swing approach the power supply rails before theMOSFETs enter the triode region. This increase in linear output swing comes at the costof speed as indicated by Eq. (33.20).

The next question becomes, "How do we implement the batteries in Fig. 33.64?"The batteries must track both process and temperature changes. What we want issomething like what is seen in Fig. 33.65. Using Vbiasn2 from the circuit of Fig. 33.60, wecan precisely set the current in the output stage. Looking at this figure for a moment, we


400/2

200/2

VDD

voutvin

Figure 33.64 Biasing a push-pull amplifier.

vin

vout

= 1.5 V

0.25

0.25

400/2

200/2

VDD

vout

Figure 33.65 Conceptual biasing of a push-pull amplifier with current mirrors.

= 1.5 V

VDD

Two gate-source voltages.

MC1

MC2Vbiasn2

Vbiasp2

see that we need to somehow couple our input signal to the gates of the output MOSFETsand we need to provide a path for current flow in the added transistors. As drawn MC1and MC2 are off.

Figure 33.66 shows the use of a floating current source (discussed in Ch. 25) to setthe bias current in the output stage. Note that since the current in the cascoded transistorssplits between MC1 and MC2 we have reduced their size by one-half in order to set thecurrent in the output MOSFETs to precisely ten times the current in the remainingMOSFETs. By further reducing the size of MC1 and MC2 (reducing W or increasing L)we can choke off the current flowing in the output transistors. While this will push thefrequency of the pole located on the output of the op-amp downwards making stabilityquestionable it may be used to reduce the quiescent power of the op-amp. The inputsignals, Vot1 and Vob1, come from the diff-amp shown in Fig. 33.51. The cascode transistorsprovide the "first stage gain" so that the circuit show in Fig. 33.66 is an op-amp minus thediff-amp. The structure is biased so that it can function with very low power supplyvoltages. The limitation on how low the power supply voltages can go is set by thediff-amp of Fig. 33.51.

Example 33.5Consider the AC small-signal simplification of the floating current source shown inFig. 33.67. Assuming the NMOS cascode output resistance is labeled Rncas , what isthe small-signal resistance seen by the test voltage, vtest?


400/2

200/2

Figure 33.66 Biasing a push-pull output stage with floating current source.

VDD

VDD

10/2

20/2

All unlabeled PMOS are 40/2.All unlabeled NMOS are 20/2.

MC1MC2

M11

M12

Vbiasn2

Vbiasp2

Vbias3

Vbias2

Vob1

Vot1

What we are going to show is that the floating current source will not load, ordecrease, the resistance seen by the cascode structures. Writing a KVL from vtest toground results in

vtest = (itest − idmc1 − idmc2) ⋅ ron rop + itest ⋅ Rncas

where the drain currents of MC1 and MC2 are idmc1 and idmc2 respectively and theiroutput resistances are ron and rop. The drain currents can be written as

idmc1 = gmn ⋅ vgs = gmn ⋅ (−itest ⋅ Rncas)

and

idmc2 = gmp ⋅ vsg = gmp ⋅ vtest

Combining these equations

vtest⋅

≈ gmp ⋅ron rop

(1 + gmp ⋅ ron rop) = itest⋅

≈ gmn ⋅ron rop ⋅Rncas

(1 + gmnRncas ⋅ ron rop + Rncas)

or

vtest

itest≈ Rncas

This shows that adding the floating current source to our cascode stack in Fig.33.66 will not affect the gain of the circuit.

Slew-rate Concerns

We know from our discussion in the last chapter that slew-rate can be a big concern whendesigning a mixed-signal system. For example, the drain of the NMOS device, M11, at thebottom of Fig. 33.66 will be at a voltage of approximately 150 mV. If the voltage Vob1

increases the maximum amount this device (M11) can turn on is very limited. If we wereable to hold its drain voltage constant then an increase Vob1 would result in an increase in


MC1MC2

S

S

To PMOS cascode

Figure 33.67 Small-signal AC circuit for Ex. 33.5.

vtest

itest

itestRncas

idmc1

idmc2

ron rop

drain current. Now, however, the current through M12 is constant (its gate is held at Vbias3

while its source is held at a fixed potential). What we need to add to this basic circuit is acircuit that will hold the drain of M11 at a fixed potential while at the same time adjust thegate voltage of M12 so that it can turn on.

Figure 33.68 shows adding N and P diff-amps to help with adjusting the biasing sothat slewing isn't a concern. Figure 33.69 shows the circuit implementation of theamplifiers. The source-followers were added in Fig. 33.69 so the inputs can go to thepower supply rails and to reduce the input capacitance. Adding the N and P amplifiers tothe amplifier of Fig. 33.66 (called gain-enhancement back in Ch. 25) also increases theoutput resistance of the cascode stack. This is important because we want the poleassociated with this node (the output of the first stage or the input to the second stage) tobe dominant so that it compensates the op-amp. The voltages Vhigh and Vlow are generatedwith the bias circuit of Fig. 33.60 for, once again, the widest possible operating range. Asdiscussed in Ch. 25, we can increase the gain of the op-amp by increasing the gains ofthese added amplifiers.

Reviewing Fig. 33.62 we see that the current sourced by our diff-amp is verylimited. Let's say that there is 5 µA of current available to charge the output transistors inFig. 33.68. We can estimate the input capacitance of these two transistors using


Figure 33.68 Adding amplifiers to our op-amp to boost gain and help slew-rate.

VDD

VDD

Device sizes as seen inFig. 33.66.

N

P

Vbiasn2

Vbiasp2

Vlow

Vhigh

Vob1

Vot1

Vout

C1 =

Wp

400 +

Wn

200

⋅L

2 ⋅(scale)2⋅

Cox

εox

tox= 1, 200 ⋅ (0.15 µ)2 ⋅

35.13 aF/µm0.004 µm

= 237 fF

(33.21)

The rate we can charge this input capacitance is

(33.22)5 µA

237 fF= dV

dt= 21 mV/ns

At first glance this may appear to be a significant limitation if the output of our op-amphas to change by 1 V or more during a 10 ns clock cycle. However, after reviewing Fig.33.64 we see that well under 50 mV change on the input of these output transistors isneeded to cause the output to change from rail-to-rail. One final comment; to balance thedrive to the output transistors, a capacitor can be added in between each of the gates of


Pout

VDDVDD VDD

out

Nout

VDD

VDD VDD

out

Figure 33.69 Diff-amps with source-follower level shifters for use in Fig. 33.68.

Vbiasn

Vbiasp

the two transistors. This capacitor doesn't affect the compensation or the speed, it simplymakes the biasing appear more battery like, as seen in Fig. 33.64. We also addedcapacitors in the diff-amp of Fig. 33.51 so that the source-followers used for biasingappear more battery like (as discussed in Ch. 24).

Now that we've calculated the capacitance on the output of the first stage, C1, wecan estimate the location of the dominant pole. The voltage gain of the cascode section isapproximately (gmro)

2. When the gain enhancement amplifiers (N and P in Fig. 33.69) areadded the voltage gain increases to (gmro)

3 noting this is the gain to the output of the firststage and not the final gain of the op-amp. If we pull the transconductance of the diff-ampout of this equation, we estimate the cascode output resistance as (= R1). Using Figs.gm

2 ro3

33.52 - 33.55 we can estimate R1 as 150 MΩ. The location of the dominant pole is thenestimated as . This pole can be pushed lower inf1 = 1/(2π ⋅150MΩ ⋅ 237 fF) = 4.4 kHzfrequency, further compensating the op-amp, by adding capacitance from the gates of theoutput MOSFETs to AC ground (ground or VDD).

The observant reader may ask "If we can get away with only 5 µA of bias currentin our amplifier and avoid slew-rate limitations, why use the diff-amp of Fig. 33.51?". Aswe discussed earlier this diff-amp represents the weak link in the minimum power supplyvoltage we can use with our op-amp and it dissipates more power than an equivalentlybiased regular diff-amp. Also, the input common-mode range of this diff-amp is verylimited. We won't be able to use the op-amp as a simple voltage follower. Because ofthese concerns/reasons we won't use this topology for our basic op-amp design. (Thenoise performance, discussed in the next section, is also poorer for this diff-amp mainlybecause the source followers used for biasing are in series with the input signal.)

Figure 33.70 shows one possible mixed-signal op-amp topology. We used diodeconnected, cascoded, MOSFETs to generate Vot1 and Vob1 in the diff-amp in an effort toequalize all drain-source voltages. The minimum supply voltage, because of the diff-ampused, can be significantly less than 1.5 V (approaching 1 V for a typical process run). Onepotentially important concern is the negative common-mode range of the diff-amp. If theinputs are held at 0.75 V, with the gate-source voltage of the diff-amp pair at 0.5 V, therewill be only 0.25 V left to drop across the diff-amp's current sink. The result is thediff-amps biasing current may decrease (and so will the common-mode rejection ratio).Using a single MOSFET to bias the diff-amp or increasing the widths of the diff-pair canimprove this situation.

The gain of this topology is very high. This can lead to simulation problems (whichhas lead us to use HSPICE in the following simulation results). Figure 33.71 shows theoutput of the op-amp as a function of the noninverting input voltage of the op-amp withthe inverting input held at 0.75 V. The systematic offset voltage is approximately 3 mV.Not cascoding the diode-connected loads of the diff-amp can result in a significantly largeroffset voltage. Increasing the widths of the diff-amp pair reduces the systematic offset,and, if laid out properly, reduces the random offsets.

Figure 33.72 shows the open-loop gain of the op-amp (approximately 110 dB atDC). As is, the op-amp will be unstable if used in a unity gain configuration. The dominant


pole, as discussed above, is at the output of the first stage (input to the second stage). Wemight think that using different N and P diff-amps (or some other operationaltransconductance amplifier) with a higher gain will help improve the stability. Whileincreasing the gain of these amplifiers will push the dominant pole to a lower frequency, itwill also increase the low-frequency gain having little effect on the stability.

Figure 33.73 shows how adding two 250 fF capacitors to the output stage pushesthe dominant pole downwards and makes the op-amp stable. The unity gain frequency ofthe op-amp is approximately 70 MHz. Unfortunately, the settling time of the op-ampincreases. Figure 33.74 shows a test configuration where the op-amp, driving a relativelylarge 5 pF capacitor, has a settling time of approximately 50 ns. (Figures 33.72 and 33.73were generated without a load; so the unity gain frequency with a load will be less thanwhat is shown in these figures.)

While reducing the capacitive load decreases the settling time, we may not havethis option available. Let's discuss the design of an op-amp and the trade-offs if we use thebasic topology of Fig. 33.70 to implement a mixed-signal op-amp.

1) The load is purely capacitive. We may consider eliminating the floating currentsource and the push-pull output stage (and note that the inverting and noninverting input


Figure 33.70 Mixed-signal op-amp.

VDD

N

P

VDD VDDVDD

VDD

400/2

200/2

20/2

All unlabled PMOS are 40/2.All unlaeble NMOS are 20/2.

40/2

40/2

10/2Vbiasn2

Vbiasp2

Vlow

Vhigh

Vout

Vbias4

Vbias3

Vbias2

Vob1

Vot1


Figure 33.71 DC behavior of the op-amp of Fig. 33.70

1.5 V

0 V

122 nV

VDD

0.75

Vin

Vout

Figure 33.72 Showing open-loop response of the op-amp of Fig. 33.70.

600 MHz

0.75

1 100MEG

Unstable!

Vout

∠ Vout

Vout

Vout

Vin


VDD

250 fF

250 fF

Figure 33.73 Compensating the op-amp of Fig. 33.70.

Adding capacitors tothe output stage.

70 degree phase margin

Out

Figure 33.74 Showing settling-time of the op-amp in Fig. 33.70 with the compensationcapacitors shown in Fig. 33.73.

0.75

10k

0.51.0

10k

Out

In

In

Out

5 pFCload

terminals switch places). While the output range is reduced when not using the push-pulloutput buffer, the stability is almost guaranteed with a reasonable-sized load capacitance.The biasing current is increased so that it can drive the capacitive load in the timerequired. A scaling increase in the biasing currents is followed by an increase in the size ofthe devices. For example, if we increase our biasing current from nominally 15 µA (seeFigs. 33.52 and 33.53) to 150 µA, then our NMOS size is increased to 200/2 and thePMOS size is increased to 400/2. Not scaling devices, as discussed earlier, can result intoo small of an fT or too large of a ∆V.

2) We use the circuit as seen in Fig. 33.70 but the settling time is too long. Byreducing the lengths of the push-pull output stage the frequency of the second pole getspushed out (increases) and the gain of the output stage decreases (both helping withstability). However, the current in the output stage increases, resulting in higher powerdissipation. This, in most situations, isn't enough alone to guarantee a stable op-amp.

3) Increasing the biasing current lowers the gain and improves the speed (and thusdecreases the settling time). The linear output range decreases (perhaps by too modest anamount to be a concern because of the large first-stage gain) and the input diff-ampminimum common-mode range may become too large, causing the diff-amp to shut offwhen VDD/2 is applied to the op-amp input. This latter concern was discussed earlier.This fix for the settling time is trivial to simulate by changing the resistor value in thebeta-multiplier biasing circuit used in the op-amp.

4) Increasing both the biasing current and the size of the devices in Fig. 33.70 sothat a given load capacitance becomes, effectively, less difficult to drive. This is the samefix as 1), above, except that we still have the floating current source and output buffer(and so the current needed to charge the load is supplied by the push-pull amp and is notdirectly related to the biasing current in the diff-amp).

Before listing number 5), let's review from Ch. 27, how the op-amps unity gainfrequency, fu , is related to settling time. Assuming no slew-rate limitations, the op-ampstime constant can be written (assuming the op-amp has only a single dominant pole) as

(33.23)τ = 12πfu ⋅ β

β is the feedback factor. Here we assume β = 1, where all of the output is fed back to theinput. For our op-amp response of Fig. 33.73 τ = 2.3 ns. The output signal for oursingle-time constant dominant pole op-amp circuit can be written as

(33.24)Vout = Voutfinal(1 − e−t/2.3ns)

For 0.1% settling accuracy (Vout /Voutfinal = 99.9%) it takes

(33.25)t = 15.9 ns

While we used 70 MHz for fu , including the 5 pF load drops the unity gain frequency andincreases the bandwidth-limited settling time.


5) Use minimum channel lengths for any high-speed design. This increases thedevice's fT while also increasing the drive current strength of the MOSFETs. Usingminimum channel lengths with a larger biasing current can push the settling time down tounder 10 ns. The decrease in the gain resulting from using minimum length devices and alarger biasing current (larger ∆V) in the topology of Fig. 33.70 shouldn't be too much of aconcern since we are starting with 110 dB gain.

Differential Output Op-Amp

Let's build on our basic op-amp of Fig. 33.70 to implement a high-speed, low-powerfully-differential op-amp. Consider the gain and output stage shown in Fig. 33.75 and theassociated simplified schematic representation. Notice how the inputs labeled "Top" and"Bottom" are low-impedance, cascode-connected current mirrors (with node voltagelabels, Vot1 and Vob1). Using the simplified model, Figure 33.76 shows the schematic of afully-differential op-amp (minus the common-mode feedback circuit).


Figure 33.75 Mixed-signal op-amp building block.

VDD

N

P

VDD

VDD

Top

Bottom

Top

Bottom

Out

Simplified schematic symbol

Vbias3

Vbias2

Vbiasn2

Vbiasp2

Vlow

Vhigh

Vout

Vob1

Vot1

Vout

Vob1

Vot1

An important component of any fully-differential op-amp is the common-modefeedback circuit as discussed back in Ch. 25. While we won't repeat the material in Ch. 25here, we will comment on two additional methods to balance the op-amp outputs.

Figure 33.77 shows the addition of two weak transistors to the input of thediff-amp of the op-amp. If the op-amp's inputs are not at the common-mode voltage, VCM ,the additional transistors either conduct more or less current causing the average of theoutputs of the op-amp to move upwards or downwards. This, of course, assumes theoutput of the diff-amp is single-ended. This would require connecting the "Bottom" inputnode in the building block stage to Vbias4 and removing the diode connected MOSFETs onthe input of this stage.

Earlier we discussed using common-mode noise elimination to balance the outputsof a digital input buffer, Fig. 33.39. We can use the same technique to balance the outputof our op-amp, Fig. 33.78. We will use inverters to illustrate the technique; however, wemust ensure that whatever inverting amplifier we place on the output of the op-ampdoesn't load the op-amp's outputs. Adding resistors in series with the inverter outputs willhelp ensure loading isn't a problem. Since our op-amp outputs are buffered, the op-ampcan drive the resistors directly. Using diff-amps in place of the inverters may be necessaryto precisely set the common-mode output voltage to VCM . The inverters, as shown in Fig.33.78, will try to balance the outputs to their switching point voltage, VSP . When adiff-amp is used in place of the inverters one input is tied to the resistors and the otherinput is tied to VCM. Also note, for high-frequency operation, the averaging resistors


Top

Bottom

Out

Top

Bottom

Out

VDD VDD

Figure 33.76 Fully-differential op-amp.

Vout+Vout−

Vbias3

Vbias4

Vbias2

should have small shunt capacitors placed across their terminals to compensate for theinverters' input capacitance.

We can analyze the operation of the circuit shown in Fig. 33.78 using the stepsshown in Eqs. (33.5) − (33.12). Assuming the output resistance of the inverter is largecompared to the resistors R, we get

(33.26)idiff = gm ⋅ vo+ + vo−

2+ vo+ − (vo+ − vo−)/2

R+ iCM

and

(33.27)−idiff = gm ⋅ vo+ + vo−

2+ vo− − (vo+ − vo−)/2

R+ iCM

Taking the difference in these equations shows, once again,

(33.28)2idiff = vo+ − vo−

R

and that the common mode component of the signal is removed (set to VSP).


VDD VDD

Figure 33.77 Adding auxilary input to the diff-amp to balance the op-amp's outputs.

Long L devices

Adjust current as needed.

Vbias3

Vbias4

VCM

Figure 33.78 Using common-mode noise elimation to balance the outputs of an op-amp.

R

R

vo+

vo−

vo+ + vo−

2

33.3.3 Circuit Noise

In this section we discuss and review circuit noise. We will repeat discussions of some ofthe topics we've already covered in Chs. 7, 9, and 22 to provide further, intuitive,understanding of random processes (such as the quantization noise and clock jitterdiscussed in Chs. 30 and 31).

Thermal Noise

Consider the voltage divider shown in Fig. 33.79a. In this figure the ideal voltage out, Vout,is 0.75. However, because of the random motion of the electrons making up the currentflowing in the circuit (because of lattice vibrations or heat), the voltage Vout has a randomvariation. The effects of this variation are termed thermal noise. As seen in Fig. 33.79b thevariation in the output voltage can be characterized with a Gaussian probability densityfunction (PDF). Notice that time is not indicated in this figure. We can't determinedirectly, from the information shown in the figure, the spectral characteristics of the noiseunless we make some assumptions (like we did with the quantization noise in the previouschapters where we assumed it was bandlimited to the Nyquist frequency). Reviewing Figs31.12 and 31.13 and the associated discussions in Ch. 31 we can make the followingcomments:

1) The RMS value of the thermal noise in Fig. 33.79 is 1 µV. We could also saythat the standard-deviation, σ, is 1 µV since the RMS value and the standard deviation areequal when the noise has a Gaussian PDF.


0.75 V

0.749997

0.750003

Volts

Figure 33.79 (a) A voltage divider and (b) the variation of the output voltage because of thermal noise (an example PDF).

VDD = 1.5 V

R

R

(a)(b)

RMS Voltage = σ ≈ 1 µV

6σ ≈ 6 µV σ2σ

Vout

2) The mean-squared value (squaring the RMS value) indicates the average powerof the thermal noise. We could also say that the variance, σ2, indicates the average powerof the noise. Sometimes this is more correctly called the total average normalized powerbecause we assume a 1 Ω resistor when converting from RMS voltage or current to powerand we sum the total power in the spectrum, see Eq. (31.37).

3) The power (variance) in uncorrelated noise sources (random variables) can beadded directly but the RMS voltage or current values (standard-deviation) cannot. Forexample, if we have an RMS thermal noise voltage, σtherm , an RMS quantization noisevoltage, VQe,RMS , and a sampling error power due to jitter of PAVG,jitter (see Ex. 31.15)corrupting a sinewave signal with a peak amplitude of Vp , then we would determine thesignal-to-noise ratio of the signal using

(33.29)SNR = 20 ⋅ logVp/ 2

σtherm2 + VQe,RMS

2 + PAVG,jitter

The numerator is, of course, the RMS value of the desired signal while the denominator isthe square-root of the total error power from each error source, i.e., thermal noise,quantization noise, and clock jitter. It's interesting to note that averaging K samples of arandom variable, say thermal noise, results in a reduction of its RMS value

(33.30)σK,therm = σtherm

Kor σK,therm

2 =σtherm

2

K

The shape of the Gaussian PDF gets taller and narrower as we average the random signal.The area, however, remains constant and equal to one. Rewriting Eq. (33.29) andincluding the effects of averaging the signal and noise results in

(33.31)SNR = 20 ⋅ logVp/ 2

σtherm2 + VQe,RMS

2 + PAVG,jitter

+ 10 ⋅ log K

which shows, once again, that averaging can be employed to increase SNR.

The Spectral Characteristics of Thermal Noise

Examine Fig. 33.80 where we've eliminated the DC bias and have shown the randomcurrent sources used to model each resistor's thermal noise contributions to Vout. The RMSnoise current has a value (as given in Ch. 7) of

(33.32)i2 = 4kTR

⋅ B

where k is Boltzmann's constant (1.38 x 10−23 Watt ), T is the temperature in⋅sec / KKelvin, and B is the bandwidth over which the noise is measured. For the circuit shown inFig. 33.80, the RMS output noise voltage is

(33.33)σtherm = Vout,RMS = (R1 R2) ⋅ 4kTR1

⋅ B + 4kTR2

⋅ B


As indicated in Ch. 7 to perform a noise analysis we 1) add RMS noise voltages to thecircuit, 2) determine the RMS output noise from each contribution using superposition(i.e., with only one noise source in the circuit at a time), and 3) square each contributionfollowed by summing and taking the square-root to get the output noise (as a function ofthe bandwidth B).

Note that even with both sides of a resistor connected to ground (no DC current) anoise current (electrons) will move back and forth from the ground to the resistivematerial at each connection as long as T > 0 . In other words, a noise current will stillKbe present in the circuit.

Reviewing Eq. (33.32) for a moment would reveal that if we reduce the bandwidthof a measurement (pass the signal plus noise through a narrowband filter) we get acorresponding reduction in the RMS noise present in the signal. Spectrum analyzers usenarrow band filtering for this reason: in order to get extremely large dynamic range. Thepower spectral density (PSD) of the thermal noise voltage specified by Eq. (33.33) isplotted in Fig. 33.81. The output noise power is given by

(33.34)PAVG = σtherm2 = Vout,RMS

2 = ∫fL

fH

Ptherm( f ) ⋅ df = 4kT ⋅ (R1 R2) ⋅ B

where

(33.35)B = fH − fL

We now need to discuss how to determine the bandwidth, B.


Figure 33.80 Modeling thermal noise in a resistor.

RMS noise sources

Vout

4kTR1

⋅ B R1 R24kTR2

⋅ B

Figure 33.81 Thermal noise power spectral density for Eq. (33.33).

f

Ptherm( f ), V2/Hz

4kT ⋅ (R1 R2)

Noise Equivalent Bandwidth (NEB)

Any real circuit will not operate over the infinite bandwidth indicated in Fig. 33.81.Consider the simple RC low-pass filter shown in Fig. 33.82. The noise circuit, after usingsuperposition (shorting the input voltage source, Vin , to ground) is also seen in this figure.Note that a capacitor doesn't generate noise (although, as we'll see in a moment, it doesset the output noise in the circuit).

The output noise power for the circuit of Fig. 33.82 can be determined using

(33.36)Vout,RMS2 = ∫

0

∞

4kTR ⋅ 11 + (2πf ⋅ RC)2

⋅ df

Knowing

(33.37)∫ dua2 + u2

= 1a tan−1 u

a + C

then

(33.38)Vout,RMS2 = 4kTR ⋅

f3dB

12π ⋅RC

⋅[tan−12πf ⋅ RC] 0∞

or

(33.39)Vout,RMS2 = 4kTR ⋅ f3dB ⋅ π

2

The NEB is then

(33.40)NEB = f3dB ⋅ π2

Figure 33.83 shows the interpretation of this equation. The area from DC to the NEB isequal to the area under the actual response. Note that Eq. (33.39) reduces to

(33.41)Vout,RMS2 = kT

C

which is our familar result for the RMS thermal output noise power of an RC circuit (KayTee over Cee noise).


4kTR

Figure 33.82 Circuit used to determine NEB.

R C

R

C

Noise circuit

VoutVoutVin

As an example of where we can use NEB consider the dominant pole compensatedop-amp in a unity follower configuration shown in Fig. 33.84a. It's important to note thatnoise is always measured on the output of a circuit and then referred back to the input,Fig. 33.84b. Also note that we are assuming the op-amp can drive the, possibly, low inputresistance of the spectrum analyzer. If not, as we'll see when characterizing the noiseperformance of MOSFETs, we'll need to introduce a low-noise amplifier (LNA) inbetween the circuit-under-test and the spectrum analyzer for isolation.

To calculate the RMS input-referred noise voltage, we can remember that the unitygain frequency of an op-amp, fu , is related to the op-amp's 3 dB frequency and open loop


f

Figure 33.83 Showing the same area in the NEB and the actual spectrum.

same area

NEB = f3dB ⋅ π2

f3dB

4kTR ⋅ 11 + (2πf ⋅ RC)2

V2/Hz

SpectrumAnalyzer

(a)

(b)

Input-referred noise spectrum

Figure 33.84 (a) Measuring op-amp output noise spectral density and(b) noise model where output noise is referred back to the input.

f

Assuming a white noise spectrum.0.75

Measured output noise spectrum,

Vin( f )

V( f )

Here V( f ) = Vin( f )

V( f )

gain, AOL , using . The RMS input-referred noise, assuming the op-amp is thef3dB = fu/AOL

limiting bandwidth factor in the circuit, is given by

(33.42)Vin,RMS = V( f ) ⋅

NEB

fu

AOL⋅ π

2

This assumes is a constant magnitude number (white noise) vs. frequency. (WhiteV( f )noise being analogous to white light where the spectrum of white light is occupying allfrequencies of interest with equal amplitude.)

In a CMOS op-amp we'll be able to use NEB to get an idea for the circuit noise,especially if the circuit bandwidth is wide. However, because of flicker noise (1/f noisediscussed in Ch. 9) present in MOSFETs we will need to use Eq. (33.34) to get an exactidea for the output RMS noise. Equation (33.34) is rewritten as

(33.43)Vout,RMS2 ( f ) = ∫

fL

fH

V2( f ) ⋅ df

where now the measured noise output spectrum, , is not a constant but changes withV( f )frequency. The RMS input-referred noise can be determined, for a particular circuitconfiguration using

(33.44)Vin,RMS2 ( f ) = ∫

fL

fHV2( f )H( f ) 2

⋅ df

where is the transfer function of the circuit. H( f )

MOSFET Noise

The noise mechanisms present in MOSFETs (thermal and 1/f ) were discussed back in Ch.9. Figure 33.85 shows how a low-noise amplifier (LNA) keeps the spectrum analyzer fromloading the MOSFET-under-test and to set the drain voltage of the MOSFET. In order tosimplify the calculations in the following discussions, we will write the total noise power


1/f noise dominates

Figure 33.85 Determining MOSFET noise.

LNA SpectrumAnalyzer

Sets drain current

Sets drain voltage and provides isolation

f

MOSFET noise

1/f noise corner

-10 dB/decade

10k1k 100k

Thermal noise dominates

itherm2 + i1/f

2 , A2/Hz

of both contributions from thermal noise and 1/f noise (flicker) in a MOSFET's draincurrent as orinoise

2

(33.45)inoise2 = itherm

2 + i1/f2

Because noise is always measured on the output of a circuit and referred back tothe input for comparison with the input signal we can use either of the circuits shown inFig. 33.86 for performing simple noise analyses in our CMOS circuits.

Noise Performance of the Source Follower

Examine the source-follower configuration shown in Fig. 33.87. The input-referred noisevoltage (the noise added to the input signal) is

(33.46)Vin2 ( f ) = (inoise1

2 + inoise22 ) ⋅

1gm1

2+ ro

2

By increasing gm1 (making the gain of the source-follower approach one) theinput-referred noise can be minimized (ultimately approaching the measured output noise

). This statement alone isn't too useful because increasing the biasing[inoise12 + inoise2

2 ] ⋅ ro2

current flowing in M1 (and M2) will increase gm1 but not necessarily decrease the


Figure 33.86 Modeling MOSFET noise.

inoise2

inoise2 /gm

2gmvgs = id

Figure 33.87 Noise performance of the source follower.

VDD

Bias

In

Out

VDD

Bias

In

Out

M1

M2

M1 inoise12

inoise22

input-referred noise. Increasing the biasing current will also cause the noise currents toincrease (as discussed in Ch. 9). To increase gm1 without changing the noise currents wemust increase the width of M1. While increasing the width improves the noiseperformance, it slows down the inherent speed of the circuit because of the drop in ∆V(and thus fT ). However, speed is usually not a concern with a source-follower (under lightto reasonable load conditions) because its bandwidth approaches fT . The point here is thatincreasing the width of the MOSFET whose gate is connected to an input node can beused in any amplifier to reduce the input-referred noise.

An important use of the source-follower is in small-input capacitance amplifiers(such as charge amplifiers used in charge-coupled devices, CCDs). Because the AC inputvoltage is ideally equal to the AC output voltage, the voltage change across the gate-source capacitance is zero. This means that the input capacitance of the source-follower inFig. 33.87 is set by the gate-drain capacitance of M1 (and, compared to a common-source amplifier, is considerably smaller). However, because the voltage gain of thesource-follower is one the input-referred noise contributions from the amplifier connectedto the output of the source-follower is referred directly back to the source-follower's inputwithout any amplitude reduction. To understand this statement in more detail, let'sconsider the noise performance of a cascade of amplifiers.

Noise Performance of a Cascade of Amplifiers

Consider the cascade of amplifiers shown in Fig. 33.88. Here we are assuming theamplifiers have infinite input resistance (the amplifier input is the gate of a MOSFET; theamplifiers amplify an input voltage). If this isn't the case, then we need to model theinput-referred noise with both voltage and current generators to account for the loadingon the amplifier output. As seen in the figure referring all three stage's noise contributionsback to the overall amplifier input results in

(33.47)Vin2 ( f ) = V1

2( f ) +V2

2( f )A1

2+

V32( f )

A12A2

2


Figure 33.88 Noise performance of a cascade of amplifiers.

First stage Second stage Third stage

OutIn

OutIn

A1

A1

A2

A2

A3

A3

V12( f ) V2

2( f ) V32( f )

V12( f ) + V2

2( f )/A12 + V3

2( f )/A12A2

2

Stage two's input-referred noise, , is referred back to the overall amplifier's input byV22( f )

dividing by the first stage's gain, . If the first stage's gain is one then the second-stagesA12

input-referred noise appears directly on the overall amplifier's input (which is the casewhen using a source-follower as the first amplifier). However, if the first stage has a largegain, then the contributions from the following stages are negligible. The point here is thatto minimize the input-referred noise the gain of the first stage should be large.

For the basic op-amp shown in Fig. 33.70 the noise performance is dominated byboth the first-stage diff-amp and the second-stage amplifier made up of the cascodedtransistors and floating-current source. The voltage gain of the diff-amp will be close toone making the second stage's input-referred noise reflect directly back to the input of theop-amp. Again, for low-noise design, we want large first-stage gain.

To minimize a diff-amp's input-referred noise (see Ch. 24), we can increase thewidths of the diff-pair. This, as discussed earlier, also minimizes both the systematic andrandom offsets in an op-amp and increases the input common-mode range. The cost ofthese benefits, again, is the lowering of the parasitic poles (ultimately affecting op-ampstability) that the diff-pair introduces into the op-amp's overall transfer function. The fT ofthe two MOSFETs used in the diff-pair decreases.

It's interesting to note that an amplifier's offset voltage can be thought of as aspecial case of noise at DC. This means that Eq. (33.47) can be applied to determine theimportance of amplifier offset in a cascade of amplifiers. (Replace with VOS in Eq.V( f )33.47.) Note that because of the small voltage gain of the diff-pair used in ourmixed-signal op-amp of Fig. 33.70 the topology can have a relatively large systematicoffset voltage (e.g. 5 mV). The noise and offset performance of this op-amp, however, isno worse than that of the folded-cascode amplifiers presented in Ch. 25. Folded cascode-based op-amps also use a low-voltage gain in the input diff-pair. For circuit techniques toreduce both noise and offsets (chopper stabilization, offset storage, and correlated doublesampling) the reader is referred to reference [9].

DAI Noise Performance

Figure 33.89 shows the DAI (see Fig. 31.78) with noise sources shown. The input-kT/Creferred noise is given by

(33.48)Vin,RMS2 = kT

CI

in series with both v1 and v2. A total of is sampled onto CI during each clock cycle.2kT/CI

If the input signal can swing from VDD to ground then we can estimate the SNR using

(33.49)SNR = 20 logVDD/ 2 2

2kT/CI

If VDD = 1.5 V, T = 300K, and CI = 100 fF then the maximum SNR, is 68 dB (roughly11-bits of resolution.) Equation (33.49) is useful in determining the minimum value ofcapacitors used in a DAI for a specific application.


REFERENCES

[1] R.J. Baker, H.W. Li, and D.E. Boyce, CMOS: Circuit Design, Layout, andSimulation, IEEE Press, 1998. ISBN 0-7803-3416-7

[2] Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, CambridgeUniversity Press, 1998. ISBN 0-521-55959-6

[3] C. Enz, F. Krummenacher, and E. Vittoz, "An analytical MOS transistor model valid inall regions of operation and dedicated to low-voltage and low-current applications,"Journal on Analog Integrated Circuits and Signal Processsing, Kluwer AcademicPublishers, pp. 83-114, July 1995

[4] M. Bucher, C. Lallement, C. Enz, F. Théodolz, and F. Krummenacher, ElectronicsLaboratories, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland.Available at http://legwww.epfl.ch/ekv/index.html

[5] D.P. Foty, MOSFET Modeling with SPICE: Principles and Practice, Prentice-Hall,1997. ISBN 0-13-227935-5

[6] D.I. Hariton, Floating MOS Capacitor, U.S. Patent 5,926,064, July 20, 1999.

[7] J. Yuan and C. Svenson, "High-Speed CMOS Circuit Technique," IEEE Journal ofSolid State Circuits, Vol. 24, No. 1, pp. 62-70, February 1989.

[8] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, "Matching Properties ofMOS Transistors," IEEE Journal of Solid State Circuits, Vol. 24, No. 5, pp. 1433-1440,October 1989.

[9] C.C. Enz, and G.C. Temes, "Circuit Techniques for Reducing the Effects of Op-AmpInperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization,"Proceedings of the IEEE, Vol. 84, No. 11, pp. 1584-1614, November 1996.


Figure 33.89 Noise performance of the DAI.

φ1

CF

CIVCM

v1

v2

Vout

kT/CI kT/CI

Sampled onto CI when φ1 switches close.

Sampled onto CI when φ2 switches close.

φ2

QUESTIONS

33.1 Regenerate the plots shown in Fig. 33.1 using an L of 5 µm and a W of 15 µm. Dothe curves look similar? Could we use the Level 1 model with long L devices?

33.2 Can we use a native MOSFET in an application where we need a small thresholdvoltage? What are the limitations?

33.3 Sketch the implemenation of a floating capacitor that uses a MOSFET switch toconnect the source/drain/bulk to ground. Show the capacitor used in a DAI, Fig.31.78. Assume the switch connected to the capacitor is clocked with the φ1 clock(why?). Explain the operation of the circuit.

33.4 Sketch the practical layout of a 10k n+ poly resistor using a silicide block.

33.5 Verify the error in Fig. 33.18 is due to differing device drain-source voltages.Show that using an even longer length device can result in less error.

33.6 If the drawn area of a source implant is 100 m2 what is the actual area if a scalefactor of 0.15 µm is used.

33.7 Using Eqs. (33.3) and (33.4) estimate the high-to-low and low-to-high delays inthe circuits shown in Fig. 33.90.

33.8 Using WinSPICE results tabulate the output amplitude of the circuit in Fig. 33.32against capacitive load.

33.9 Show kickback noise on the inputs of the comparator shown in Fig. 33.34 usingsimulations. Show adding the circuit of Fig. 33.91 (a source-follower) to eachinput of the comparator will drastically reduce kickback noise.

33.10 Modify the design of the digital input buffer shown in Fig. 33.39 using thetopology shown in Fig. 33.78. Show that the circuit still functions as expectedusing simulations.

33.11 Show, using simulations, that the circuits in Fig. 33.47 do indeed behave ascounters.

33.12 Verify the operation of the element in Fig. 33.50 as a 1-bit adder.


Figure 33.90 Circuits used in problem 33.7.

In Out In

1 pF

40/20 40/20

33.13 Do the capacitors in Fig. 33.51 slow down the operation of the diff-amp? Why?

33.14 Estimate the input common-mode range of the diff-amp shown in Fig. 33.51.

33.15 Regenerate the plots shown in Figs. 33.54 and 33.55 if the drain-source voltagesof the MOSFETs are increased to 1.5 V. Why did the transconductance increase?

33.16 Show, using simulations, that a MOSFET's transition frequency does increase withincreasing gate-source voltage and decreasing length.

33.17 Do any of the MOSFETs in Fig. 33.58 move into the triode region if the resistor'svalue is decreased to 1k? Verify your answers with simulations.

33.18 Compare the cascode current mirror performance shown in Fig. 33.61 to a singleMOSFET current mirror. Show the output resistance of the single mirror increaseswhile the minimum voltage required across the mirror decreases.

33.19 What happens in Fig. 33.65 to the current flowing in the push-pull amplifier if weincrease the lengths of MC1 and MC2?

33.20 Estimate the minimum VDD allowed for proper operation of the diff-amps shownin Fig. 33.69.

33.21 If, in Fig. 33.70, and what is theVGS = VSG = 0.5 V ∆V = VDS,min = VDS,max = 0.1 Vminimum allowable power supply voltage, VDD, for proper op-amp operation.

33.22 Sketch the implementation, based on the topology of Fig. 33.70, of a wide-swingop-amp with rail-to-rail input common-mode range. Assume the tail currents usedin the diff-amps use 20/2 (NMOS) and 40/2 (PMOS) devices (half the currentflowing each MOSFET of the diff-pair) so that summing the currents in the circuitof Fig. 33.75 at the top and bottom nodes doesn't cause any MOSFET to enter thetriode region.

33.23 Resketch Fig. 33.79 for the cases when the thermal noise is averaged. Show thecases with K = 1, 2, 4, 8, and 16.


Figure 33.91 A source follower used to reduce kickback noise.

VDD

In

Out

20/1

10/50

33.24 Suppose a MOSFET is used as a switch connecting an input signal to a capacitor.The MOSFET can be modeled, for noise purposes while the switch in on, as asimple resistor, Fig. 33.82. When the capacitor is charged zero current flows in theMOSFET. Is the noise in the circuit due to thermal or 1/f (flicker) noise? Why?Note that each time the MOSFET turns on we can think that an RMS noisevoltage of is sampled on the capacitor.kT/C


Implementing Data Converters

Minimum gate lengths in CMOS (complimentary metal oxide semiconductor) technologyare falling below 100 nm [1]. This feature size reduction is driven mainly by the desire toimplement digital systems of increased complexity in a smaller area. This natural trend infeature size reduction, with accompanying reduction in supply voltage, can presentchallenges for the mixed-signal design engineer. The accompanying lower supply-voltageresults in an inherent reduction in dynamic range, signal-to-noise ratio (SNR), andchallenges for the implementation of analog circuitry with little, ideally zero, voltageoverhead. This chapter focuses on these issues, and others, related to the implementationof data converters in a digital, submicron, CMOS technology.

Data converters are fundamental building blocks in mixed-signal systems. Thischapter presents, and discusses, methods and tradeoffs for designing CMOS dataconverters in submicron CMOS. For digital-to-analog converter (DAC) design we focuson converters implemented with resistors using R-2R networks. The benefit of, and reasonwe are focusing on, using R-2R networks over other methods for DAC implementation,such as charge redistribution [2] or current steering topologies [3], are the absence ofgood poly-poly capacitors in a digital CMOS process, the desire for small layout area,and/or the ability to drive an arbitrary load resistance. R-2R based DACs can be laid out ina small area while achieving resolutions in excess of 12-bits. Charge scaling DACs requirelinear capacitors. The layout area required for these capacitors can often be quite large andpractically limit both the resolution and accuracy of the DAC. Similarly, implementation ofcurrent steering topologies can result in very large layout area with limited resolutions,generally less than 8-bits if integral nonlinearity (INL) is a concern and, more importantly,limited output swing and the requirement of known, fixed, load resistances.

The first section of this chapter reviews current and voltage mode R-2R basedDACs. The second section of the chapter discusses the use of op-amps in data converterswhile the third section presents an overview of general ADC implementations in

Chapter

34

submicron CMOS process. While we briefly discuss the future direction of ADCs weconcentrate our discussion on the implementation of pipeline data converters.

The goal in this chapter is not to provide an exhaustive overview of data converterdesign but rather to provide discussions and some practical insight. We assume the readeris familiar with data converter fundamentals (Ch. 28) and data converter architectures (Ch.29). For example, the reader knows the difference between differential nonlinearity (DNL)and integral nonlinearity (INL) or the difference between a two-step flash ADC and apipeline ADC.

34.1 R-2R Topologies for DACs

We begin this section by discussing R-2R DAC topologies. The problems encountered inthe traditional R-2R topologies with low-voltage overhead are illustrated. Also, concernsrelated to the performance of the op-amps used in data converters (both ADCs and DACs)are discussed. Finally, matching and accuracy concerns are presented along withtechniques to remove these imperfections using calibration.

34.1.1 The Current-Mode R-2R DAC

The R-2R DAC can be classified into two categories voltage-mode and current-mode [4].A current-mode R-2R DAC is shown in Fig. 34.1. The branch currents flowing throughthe 2R resistors are of a binary-weighted relationship caused by the voltage division of theR-2R ladder network, and are diverted either to the inverting input of the op-amp (actuallythe feedback resistor) or the non-inverting input of the op-amp (actually VREF−). Thevoltage on the R-2R resistor string at the X th tap (where X ranges from 0 to N – 1), in Fig.34.1, can be written as

(34.1)VTAPX = 2X

2N⋅ (VREF+ − VREF−) + VREF−

where VREF+ and VREF− are the N-bit DAC’s reference voltages. The current that flowsthrough the 2R resistor at the X th tap is then

(34.2)ITAPX = VTAPX − VREF−

2R= 1

2R⋅ 2X

2N(VREF+ − VREF−)

This current is summed at the inverting input of the op-amp and flows through thefeedback resistor to the DAC output, Vout. The output voltage of the DAC can be writtenas

(34.3)Vout = VREF− − R ⋅ ΣX=0

N−1

(bX ⋅ ITAPX) for VREF+ > VREF−

where bX is either a 1 or 0, or

(34.4)Vout = VREF− + R ⋅ ΣX=0

N−1

(bX ⋅ ITAPX) for VREF+ < VREF−


Using these equations we can see the main problem with the basic current mode topologyof Fig. 34.1 in a submicron CMOS process using low power supply voltages, namely,limited output swing. If VREF− is set to 0V, with VREF+ > 0 , then the output of the DACmust be negative which, of course, can't happen when the only power supply voltage isVDD. If VREF− is set to VDD then we can see from Eq. (34.4) that this would require Vout >VDD. After reviewing Eqs. 34.1-34.4 we see that the range of output voltages, associatedwith the current mode R-2R DAC, is limited to VDD/2, e.g., 0 to VDD/2, VDD/2 to VDDor 0.25VDD to 0.75VDD, etc. Giving up half the power supply range in a DAC, and thecorresponding reduction in dynamic range, is usually not desirable.

Chapter 34 Implementing Data Converters 313

VDD

1 0

1 0

1 0

1 0

to resistor

1 0

detail

MOSFET channel resistance should be << 2R

TapN-1

TapN-2

Tap0

Under most circumstances only either NMOSor PMOS devices need be used.

Figure 34.1 Traditional current mode R-2R DAC.

(output swing limited to VDD/2)


2N+1

2R

2R

2R

Rb0

bN−3 bN−3

VREF−

2R

2R

R

R

RbN−1

bN−2

bN−3

VREF+

R

By removing the requirement that the noninverting input of the op-amp be tied toVREF− and that the feedback resistor be R (the same value used in the R-2R string) we canincrease the output range of the DAC. The output of the op-amp is level shifted by thevoltage on the noninverting input of the op-amp and by increasing the closed-loop gain ofthe op-amp. Similarly, we could add an additional gain stage to the output of the DAC(two op-amps would then be used) to achieve wider DAC output swing. We don't coverthese options any further here because they either put more demand on the op-amp design,such as increased op-amp open-loop gain and speed, or won't, in a practicalimplementation, result in a rail-to-rail output swing.

34.1.2 The Voltage-Mode R-2R DAC

Figure 34.2 shows the schematic of a voltage-mode DAC. The voltage on thenon-inverting input of the op-amp can be written as

(34.5)V+ = bN−1 ⋅ VREF+ + bN−1 ⋅ VREF−

21+ bN−2 ⋅ VREF+ + bN−2 ⋅ VREF−

22+ ... + VREF−

or, in general terms,

(34.6)V+ = Σk=1

N bN−k ⋅ VREF+ + bN−k ⋅ VREF−

2k+ VREF−

The output of the N-bit voltage-mode DAC can be written as

(34.7)Vout = 1 + RF

RI

⋅ Σ

k=1

N bN−k ⋅ VREF+ + bN−k ⋅ VREF−

2k+ VREF−

If the input code is all zeros with VREF−= 0, VREF+ = VDD, and the op-amp is in the followerconfiguration, then Vout = VREF−. If the input code is all ones then the output of the DAC isVREF+ − 1 LSB.

By using the voltage-mode DAC we would seem to have solved the problem of thelimited output swing associated with the current-mode DAC of Fig. 34.1. However,consider how the finite common-mode rejection ratio (CMRR) of the op-amp in Fig. 34.2can affect the linearity of the overall DAC design. We know the effects of finite CMRRcan be modeled as an offset voltage, , (see Ch. 25) in series with the non-inverting∆VOS

input of the op-amp that is a function of the op-amp common mode voltage, , or∆VC

(34.8)∆VOS = ∆VC

CMRR

We should see the problem at this point, that is, is in series with the R-2R resistor∆VOS

string and will ultimately limit the linearity of the DAC. To further illustrate the problem,let's assume the CMRR of the op-amp in Fig. 34.2 is 20 dB at 1 MHz. Since thecommon-mode voltage on the input of the op-amp, again assuming VREF+ = VDD, VREF− =0, and the op-amp in the unity follower configuration can range from zero toapproximately VDD the change in the offset voltage, used to model finite CMRR when theDAC input is at 1 MHz, is 10% of VDD. At first glance we might simply consider the


resulting offset as a nonlinear gain error affecting only the large-signal linearity (INL).However, it is unlikely, in any practical op-amp design, that the CMRR will vary linearlywith changes in the input common-mode voltage and so the small-signal linearity (DNL)will be affected as well. Since, for this example, 1 LSB = VDD/2N the resolution of theDAC, because of the finite CMRR and assuming 1 LSB > , is limited to 4-bits!∆VOS

Performing DC or audio-frequency tests on the voltage-mode DAC made with an op-ampwith a CMRR of, for example, 120 dB at DC results in no practical resolution limit


VDD

detail

MOSFET channel resistance should be << 2R

1

0

to resistor

Figure 34.2 Traditional voltage mode R-2R DAC.

(assuming op-amp is in thefollower configuration)

2R

2R

2R

R

b0

bN−2

2R

2R

2R

R

R

bN−1

bN−2

bN−3

VREF+

b1

RI

RF

VREF+

VREF−

VREF−


2N

(indicating that if DAC speed isn't a concern the voltage-mode configuration may still beused for reasonable resolutions.) Note how CMRR isn't a concern with the current-modeR-2R DAC (assuming no secondary effects, such as common mode substrate noise, arepresent on the input of the op-amp.) For precision, high-speed, data converter design wemust use an inverting op-amp topology where the inputs of the op-amp remain at a fixedvoltage.

34.1.3 A Wide-Swing Current-Mode R-2R DAC

We've shown that it is desirable to have a wide output swing, as is provided by thevoltage-mode R-2R DAC, while at the same time having a fixed input common modevoltage, as is provided by the current-mode R-2R DAC. Figure 34.3 shows a wide-swingcurrent-mode R-2R DAC configuration that has a rail-to-rail output swing while keepingthe input common-mode voltage of the op-amp fixed at the common mode voltage, VCM ,or . (VREF+ + VREF−)/2

Like traditional current-mode R-2R DACs the DAC scheme shown in Fig. 34.3operates on currents. Using superposition and assuming VREF− is the reference forcalculations, we can show that the current flowing in the feedback resistor, RF , is given by

(34.9)IF = −VREF+ − VREF−

2R+ VREF+ − VREF−

2R⋅ 1 ⋅ bN−1 + 1

2⋅ bN−2 + ... + 1

2N−1⋅ b0

noting the inversion used in the control logic of Fig. 34.3. The output voltage of the DACis then given, assuming R = RF , by

(34.10)Vout = VREF− + VREF+ − VREF−

2+ IF ⋅ R

or

(34.11)Vout = VREF− + (VREF+ − VREF−) ⋅ 1 −

12

⋅ bN−1 + 14

⋅ bN−2 + ... + 12N

⋅ b0

From this equation we see that as the digital input code is sequenced through 0...0 to 1...1the output of the DAC changes in steps of (= 1 LSB) from VREF+ (when(VREF+ − VREF−)/2N

the input code is 000000...) to VREF− + 1 LSB (when the input code is 11111...). SettingVREF− to ground and VREF+ to VDD allows the DAC output to swing from rail to rail.

In practice, since any rail-to-rail output op-amp has high non-linearity close to itspower supply rails, a slightly “shrunk” output range from power rails is often desired. Forexample, we can set VREF+ = 0.9·VDD and VREF− = 0.1·VDD. The output will changebetween 10% to 90% of VDD centered at VDD/2. Another way to shrink the output rangeis to make feedback resistance RF smaller than R (as seen in Eq. [34.10]) by eithertrimming or programming the value of the feedback resistor RF.

The matching between the resistors of the R-2R ladder is one of the mostimportant and limiting factors that determine the linearity (e.g., DNL and INL) of theentire DAC. It is helpful, when designing any type of resistor string DAC, if we canestimate the resistor matching requirements based on a desired resolution.


DNL Analysis

It was shown back in Ch. 29 that for a binary-weighted DAC the worst case DNLcondition tends to occur at midscale when the code transitions from 01…11 to 10…00.Let's assume in a worst case scenario the 2R resistance of the MSB input in Fig. 34.3 has amaximum positive mismatch of ∆R, and all other resistors have a maximum negativemismatch of –∆R. In this case, the current provided by the MSB has to match with thesum of currents provided by all other lower input bits plus one LSB. Again using thesuperposition principle we can verify that the step error of the current flowing through thefeedback resistor RF , caused by the resistor mismatch at the midscale transition, isapproximately equal to


VDD

to resistor

Figure 34.3 Wide-swing current mode R-2R DAC.

detail

1

0 MSB

LSB

1

0

1

0

1

0

bN−2

VREF−

VREF+

VREF−

b0

2R

2R

R

2R

2R

2R

2R

R

R

bN−1

bN−2

bN−3

VREF+

b1

VCM = VREF+ + VREF−

2

R = RF


2N

(34.12)∆I = VREF+ − VREF−

2(R − ∆R) ⋅ 1 − 1

2N−1

− VREF+ − VREF−

2(R + ∆R)

Assuming RF = R, the final output step error (DNL) is approximately

(34.13)DNL = ∆I ⋅ R ≈ (VREF+ − VREF−) ⋅ ∆RR

− 12N

For the DNL to be within 1 LSB (1 LSB equals to ) the matching[VREF+ − VREF−]/2N

required of the resistors is

Resistor mismatch = (34.14)∆RR

≤ 12N−1

For a 10-bit data converter to have a DNL of less than 1 LSB requires the MSB resistor tomatch within 0.2% of the lower resistors (which were assumed to have the same(= ∆R/R)value, i.e. the maximum mismatch from the MSB resistor) in the R-2R string. Equation(34.14) results in a pessimistic estimate for the matching required of the resistors becausethe variation in resistance along the string does not vary abruptly at the MSB resistor butrather, in most cases, varies linearly from LSB to MSB. As we'll see in the experimentalresults discussed in the next section the matching requirements results in a practical limitof 10-bits for an R-2R based converter with no special layout or circuit techniques (forexample, averaging process gradients by using multiple resistor strings or usingsegmentation).

INL Analysis

Since any change of the 2R resistance in the MSB has the largest influence on the ladderoutput current among that of all the branch resistors (2R), the worst case INL tends tooccur when the input code is 01…11 (The gain error is nulled from the INL calculationhere, and therefore there is no INL error, but a gain error instead, if all the resistors have amaximum mismatch). Assuming the 2R resistance of the MSB has a maximum positivemismatch of ∆R/R, the error in the current flowing through RF from its ideal value causedby the resistance mismatch is

(34.15)∆I = VREF+ − VREF−

2(R + ∆R) − VREF+ − VREF−

2R≈ −VREF+ − VREF−

2⋅ ∆R(R + ∆R) ⋅ R

The worst case INL tends to occur, assuming RF = R, when

(34.16)INL = −∆I ⋅ R ≈ VREF+ − VREF−

2⋅ ∆R

R + ∆R

For the INL to be within 1 LSB, this also approximately yields

Resistor mismatch = (34.17)∆RR

≤ 12N−1

Again, as was mentioned in the DNL analysis, this is a pessimistic estimate if the sheetresistance varies linearly with distance. Equations (34.14) and (34.17) indicate that aresistance matching to within 1/2N is required for less than ½ LSB of DNL and INL for theDAC scheme in Fig. 34.3. Layout of R-2R resistors was discussed in Ch. 33.


Switches

The switches (MOSFETs) used in the R-2R DAC should have an effective switchingresistance (see Eqs. [33.3] and [33.4]) much less than the resistors used in the R-2Rladder. The inherent switching time of the switches is extremely fast (speeds comparableto logic gate delays). Since the switches are in series with the branch resistances of theR-2R ladder, the R-2R relationship is broken if the switch resistance is not negligible andthis affects both the INL and the DNL. Also note that we can try to compensate for theswitch effective resistance by making the length of the 2R resistor slightly shorter than thelength of the R resistor. However, if not careful, this may lead to problems over theprocess corners and temperature.

Experimental Results

The wide-swing current-mode R-2R DAC, based on scheme in Fig. 34.3, was fabricated ina 0.21µm/1.8V CMOS process (single poly, up to five layers of metal) for resolutions of8-, 10-, and 12-bits. The cell dimensions of the 12-bit DAC are 150 µm by 300 µm. Thegoal of the experimental results was to verify the topology of Fig. 34.3 would indeedperform as predicted by Eqs. (34.14) and (34.17) and to generate a low-power, small areaDAC cell for general purpose, mixed-signal circuit designs. Unsilicided n+ poly was usedfor the R-2R resistances as discussed earlier, see Table 33.1. The mismatch indicated inTable 33.1 for an unsilicided n+ poly resistor is 0.005 . Using Eqs. (34.14) and(= ∆R/R)(34.17) we would estimate that our resolution is limited to 8.6 bits if we want both INLand DNL less than 1 LSB. The results in Table 34.1, however, show that the resolution isbetter than estimated. This may be because of our pessimistic assumption of how theresistor values change with position as discussed in the derivation of these equations. Thenominal resistor value used in these experimental DACs is 10k. To enhance the resistancematching, dummy resistors are implemented at both ends of the R-2R ladder (see Fig.33.13). The output range of the DAC is programmable by choosing the value of thefeedback resistance or by the setting of the reference voltages VREF+ and VREF−.

8-bit 10-bit 12-bit

DNL (LSB) 0.150 0.450 2.000

INL (LSB) 0.200 1.000 3.000

Settling time 200 ns

Power 3.88 mW (driving a 1k load)

Area (mm2) 0.045

fclk,max 4 MHz

Output swing 0 < Vout < VDD (= 1.8 V )

Table 34.1 - Summary of experimental results.


The measured INL and DNL profiles of the three DACs with resolutions of 8-, 10-,and 12-bits are shown in Fig. 34.4. The outputs of the DACs are configured to swing toboth rails (VREF+ = VDD and VREF− = 0). The first several points, adjacent to the two rails,are not shown in Fig. 34.4 due to the high non-linearity of the op-amp in those regions.Major performance results are maximum DNLs of 0.15 LSB, 0.45 LSB and 2 LSB for8-bit, 10-bit and 12-bit resolutions, respectively, with no special circuit techniques (laidout as shown in Fig. 33.13), or trimming (adjustments). The corresponding maximumDAC INLs are 0.2 LSB, 1 LSB and 3 LSB, respectively. Notice that the LSB of the 8-,10-, and 12-bit DACs are 7.03 mV, 1.75 mV, and 439 µV respectively. The DNL/INL canbe written in terms of a voltage as 1.05 mV/1.4 mV for the 8-bit DAC, 0.788 mV/1.75mV for the 10-bit DAC, and 0.878 mV/1.31 mV for the 12-bit DAC. The measurementswere taken while the DAC was driving a 1k load. The power dissipated by the DAC, with1.8V output, while driving a 1k resistor is 3.88 mW. The unloaded power dissipation ofthe DAC is approximately 500 µW. The DACs were designed using op-amps withsimulated unity-gain frequencies of 10 MHz. The measured DAC settling time wasapproximately 200 ns.


-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0 50 100 150 200 250

LSB DNL Profile (8-bit)

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 50 100 150 200 250

LSB INL Profile (8-bit)

-0.5-0.4-0.3-0.2-0.1

00.10.20.30.40.5

0 200 400 600 800 1000


-1.2-0.9-0.6-0.3

00.30.60.91.2

0 200 400 600 800 1000


-2

-1.5

-1

-0.50

0.5

1

1.5

2

0 500 1000 1500 2000 2500 3000 3500 4000


-3

-2

-1

0

1

2

3

0 500 1000 1500 2000 2500 3000 3500 4000


Figure 34.4 Experimental results for the wide-swing DAC of Fig. 34.3.

Improving DNL (Segmentation)

After reviewing the DNL plots in Fig. 34.4 we see that the worst case DNL occurs whenthe input code transitions from 01111... to 10000... (midscale) where the current in the top2R should be 1 LSB (equivalent in current) greater than the sum of all of the currentscontributed by the lower resistors. As an example, consider the 12-bit R-2R ladder in Fig.34.5 where we have used 1 µA to indicate an LSB of current contribution to the feedbackpath. When the input digital code is 0111 1111 1111 the feedback current is 2047 µA.When the code changes to 1000 0000 0000 the feedback current becomes (ideally) 2048µA. If a 1/2 LSB error (0.5 µA) is the maximum error allowable then the accuracyrequired of the currents when transitioning is 0.5/2048 or 0.0244%. If we use fewer bits,say 8, then the accuracy required when transitioning from 255 µA to 256 µA is 0.5/256 or0.2%.

Let's consider segmenting the upper 4-bits in Fig. 34.5 so that the four bits control16 segments each contributing 256-µA to the feedback current. This (segmentation)


10 MSB

LSB

Figure 34.5 Showing how currents sum into the feedback current.

Contribution to thefeedback currentwhen bit is high.1

0

1

0

1 µA

2 µA

512 µA

1024 µA

1 LSB = 1 µA

b11

b10

2048 µA IF

VREF+

b0

b1

b9

makes attaining good DNL with less accurate components possible [5]. A segmentedwide-swing DAC is shown in Fig. 34.6. In this figure we've taken the upper 4-bits andsegmented their current contributions to the feedback resistor. If we use the numbers fromFig. 34.5 then when the code 0000 1111 1111 (255 µA) transitions to 0001 0000 0000(256 µA) the 1 output of the decoder goes high and the bottom resistor connected to theoutput of the decoder contributes 256 µA to the feedback path. When the code changesfrom 0001 1111 1111 (511 µA) to 0010 0000 0000 (512 µA) both lower outputs (1 and2) of the thermometer decoder are high. Since the 1 decoder output continues tocontribute to the output current the step height is set by the difference between the 2decoder output and the contributions from the lower 8-bits. This makes the accuracy


VDD

Dec

oder

1

14

15

Segmentation in a wide-swing R-2R DAC.Figure 34.6

1

0

1

0

1

0

1

0

1

0

10

The

rmom

eter

0000111

0011111

0111111

1111111

1111111

0111111

0011111

0001111

0000111

0001111

0011111

0111111

0011111

0001111

0000111

0000011

0000001

0000000

3-bit thermometer decoder output

1234567

Out

puts

011 101 101 000Inputs

011

b0

2R

2R

R

2R

b1 VCM = VREF+ + VREF−

2

VREF−

2R

R

R

R

b8

b7

VREF+

RF = R/16

Vout

b9

b10

b11

requirements for 1/2 LSB DNL in a 12-bit converter set by 8-bit matching. Note thatwhile segmentation reduces DNL error it does nothing for INL. Segmentation can also beused to reduce the glitch area associated with the changing DAC output.

Trimming DAC Offset

Figure 34.7 shows how the op-amp's offset voltage shifts the DAC's output. It may bedesirable in some situations to trim or remove this offset. The offset may be the result ofan inherent systematic offset in the op-amp or the result of random variations in thecharacteristics of the MOSFETs used in the op-amp. An offset may also result because ofthe voltage dependence of the resistors used to generate the common-mode voltage, VCM.

Figure 34.8 shows one possible method to generate a common-mode voltage thatis adjustable with a digital code. Here again we are assuming VCM is ideally 0.75 V. Weshould recognize the R-2R ladder from Fig. 34.2. The output voltage of this ladder, asseen in Eq. (34.6), is an analog voltage (assuming the voltage divider made up of Rbig andthe two R resistors connected to the output in Fig. 34.8 doesn't load the circuit) related tothe digital input word. Figure 34.9 shows the output of this circuit for all possible digitalinput words when R is 10k and Rbig is 100k. The inset in Fig. 34.9 shows the adjustabilityof the output is approximately 1 mV. To decrease this value we can either increase Rbig

(resulting in a decrease in the output swing) or increase the number of bits in the R-2RDAC. Decreasing the R resistors on the output can be used but can result in an increase inpower dissipation.

Note that the accuracy required of the 5-bit DAC can be very loose. N-wellresistors can be used to implement the offset trimming circuit to reduce area and power.The main concerns are the possibility of substrate noise injection and making sure that thesame resistive material is used for the entire circuit. We wouldn't want the temperaturebehavior of an n-well resistor used in a circuit with a poly resistor since the temperaturedependencies are different (the offset trimming would only be effective at the temperatureit was performed). Finally note that in a practical circuit it is a good idea to add capacitors


digital input code

(a) Showing offset voltage in an op-amp.(b) DAC transfer curves showing offset

Figure 34.7 Showing how an op-amp offset affects the DACs transfer curves.

±VOS

+VOS

−VOSVCM

Vout

Vout


Figure 34.9 Output of the circuit in Fig. 34.8 for all possible digital codes.

Ideal output

VDD = 1.5 V

To op-amp + input

Adjustable voltage.

VDD

Figure 34.8 Trimming circuit for DAC offset.

Voltage mode R-2R DAC.

Selected large so it doesn't load the R-2Rladder and so we get a large attenuationto the output.

2R

2RR

R

R

R

2R

2R

2R

2R

b0

b1

b2

b3

b4

1 LSB ≈ VDD2N

⋅ R/2R/2 + Rbig

centered around VCM.

R

R

Rbig

from the output of the circuit to both VDD and ground to ensure the + op-amp input isconnected to a good AC ground.

Trimming or calibrating out the offset can be performed at a time prior topackaging the chip or it can be performed with some autocalibration sequence after thechip has been fabricated where the output of the DAC is compared to a known voltagereference. The concern, as with any calibration, is to adjust only one known error at a time(known as orthogonal tuning in filter design). For example, the DAC may not have anyoffset but does have an INL error for a given input code, Fig. 34.10a. If we were only tolook at this one input code, say 10000... (VCM in binary offset) we wouldn't know if theerror is an INL error or an offset error. After the offset is calibrated out, Fig. 34.10b, wewould then perform an INL calibration to pull the end-points of the transfer curve back tothe ideal straight line transfer curve.

Trimming DAC Gain

We assumed in Fig. 34.10 that the gain of the DAC was one, in other words, there wasn'tany gain error in the DAC's transfer function. If there is a gain error the offset calibrationcan lead to poorer INL. Consider Fig. 34.11a showing gain and INL errors without anyoffset. Performing an offset calibration, Fig. 34.11b, can result in significant INL error.We can avoid this situation by calibrating out the gain error by trimming the op-amp'sfeedback resistor prior to offset calibration. A reference voltage close to the ends of thetransfer curve is used while adjusting the gain of the op-amp used in the DAC. If VREF+ isless than VDD (to avoid op-amp saturation as its output approaches the supply rails) thenit can be compared directly to the output of the DAC (keeping in mind the maximumoutput of the DAC may be ). Having gone through all of this discussion itVREF+ − 1 LSBstill would be nicer if we could simply perform two calibrations, offset calibration and INLcalibration effectively using the INL calibration to remove the gain error. The drawback ofthis two calibration method is the requirement that an INL calibration circuit be capable ofremoving very large INL errors.


digital input code

(b) DAC transfer curves after offset cal.

Figure 34.10 Showing how INL can be seen as an offset error.

digital input code

(a) DAC transfer curves before calibration

INL error

Ideal curve

Vout Vout

Improving INL by Calibration

We can calibrate out errors in our wide-swing DAC in two basic ways as seen in Fig.34.12. The method shown in (a) adds or subtracts a current from the feedback path toadjust the DAC output to the correct value. In (b) the noninverting input of the op-amp isvaried to force the DAC output to the correct value. The offset calibration describedearlier uses the method shown in (b). Note that the resistance looking from the invertingop-amp terminal back through the ladder to AC ground is simply R so using the method in(b) results in a noninverting op-amp configuration with a gain of two. (A variation of 1mV on the + op-amp terminal causes an output variation of 2 mV.) Because we alreadyhave a circuit, Fig. 34.8, to make adjustments to the DAC output and the topology of (b)doesn't provide any DC load to the calibrating voltage source and the least interactionwith the main R-2R ladder we will use this topology to illustrate how we can calibrate outINL errors.

Consider the calibration circuit shown in Fig. 34.13. In this figure the five mostsignificant bits of a 12-bit DAC, that is, b11, b10, b9, b8, and b7 are applied to the 12-bitDAC and to the address input of a 32 to 1 MUX with 5-bit input and output words. TheMUX drives the R-2R circuit of Fig. 34.8. The 5-bit register feeding each MUX input isused to store the calibration values. Again the calibration can be performed after the DACis manufactured or during its use by employing a self-calibration sequence. In this schemethe DC offset calibration shown in Fig. 34.10 is simply one case of the 32 calibrationsperformed. (The top five bits of the input word are 10000 for the DC calibration.) Thistechnique can be used to precisely set the linearity of the DAC, perhaps up to 16-bits.Note that segmentation must still be employed to keep the DNL small. Also note thatadding a large capacitance, C, to the noninverting input of the op-amp can result in a long

time constant slowing the settling of the circuit and affecting the high-frequency ≈ R

2 ⋅ C

SNDR.


digital input code

(b) DAC transfer curves after offset

Figure 34.11 Showing gain error and how it can cause problems in an offset calibration.

digital input code

(a) DAC transfer curves with gain error

Ideal gain (slope)

Actual gain

calibration with gain error.

INL

Vout Vout


Figure 34.12 Trimming the output of the DAC using (a) current and (b) voltage.

Variable current

(a)

R-2RLadder

Variable voltage

R-2RLadder

Fig. 34.3

Fig. 34.3

VCM

R-2RCircuit

Fig. 34.8

5

Out

0

Address

12Digitalinput (12)

5Upper five bits

12

30315-bit Register

5-bit Register

5-bit Register5-bit Register5-bit Register

00000 (upper 5-bits all zeroes)

00010

Figure 34.13 Calibration scheme for 12-bit DAC.

MUX

R-2RLadder

Fig. 34.3 Vout

34.1.4 Topologies Without An Op-Amp

We discuss the requirements of op-amps used in data converters in detail in the nextsection. In this section we present an overview of topologies using voltage and currentmode DACs based on both R-2R and W-2W topologies (see Fig. 33.17). The benefit ofusing a DAC with an op-amp is that an arbitrary load impedance (within reason) can beconnected to the DAC's output. Without the op-amp the load impedance must either beknown, capacitive, or very large since it will load the DAC's output and affect INL, DNL,and, ultimately, the SNR. The benefit of not using an op-amp are faster-speed (with lightloads) and guaranteed stability.

The Voltage-Mode DAC

The simplest voltage mode DAC is the R-2R string shown in Fig. 34.14. We shouldrecognize this circuit from both Figs. 34.2 and 34.8. For the moment we assume the loadis purely capacitive so that errors resulting from sourcing a DC current are not present inthe DAC. Here, through several examples, we discuss settling time, resistor voltagecoefficient, matching, and the effects of a DC load.

Example 34.1Suppose a 10-bit voltage-mode DAC with the topology given in Fig. 34.14 isimplemented where R = 10k and CL = 10 pF. Estimate the maximum clocking


VDD

Figure 34.14 Voltage-mode (5-bit) DAC without an op-amp.

2R

2RR

R

R

R

2R

2R

2R

2R

b0

b1

b2

b3

b4

1 LSB = VDD2N

CLRL

Vout

frequency we can use to clock the register supplying the input words to the DAC.Verify your answer using SPICE.

For complete settling we require the DAC be 10-bit accurate to within 0.5 LSBsover its full-scale range,

Accuracy = 0.5 LSBFull scale range (VDD) = VDD/2N+1

VDD= 1

211= 0.04883 %

The time constant associated with the DAC and capacitive load is

RCL = 10k ⋅ 10p = 100 ns

We can use this time constant to relate the final ideal output voltage, Voutfinal , to theactual output voltage, Vout , using

Vout = Voutfinal(1 − e−t/RCL )

or, relating this to the required accuracy,

12N+1

= 1 − Vout

Voutfinal= e−tsettling/RCL

The required settling time is then

(34.18)tsettling = RCL ⋅ ln2N+1

Using the numbers from this example results in tsettling = 762 ns. The SPICEsimulation results are shown in Fig. 34.15. The maximum clock frequency is thenestimated as

(34.19)fclk,max = 1tsettling

= 1RCL ⋅ ln 2N+1

For this example fclk,max= 1.3 MHz. Note that the fundamental way to decrease thesettling time is to decrease the resistance in the R-2R ladder (assuming we have nocontrol over the load capacitance). The practical problem then becomesimplementing the switches (MOSFETs) with a resistance small compared to R.


Figure 34.15 Example output for the 10-bit DAC in Ex. 34.1 showing settling time limitations.

Example 34.2Suppose that the 2R MSB resistor in the DAC described in Ex. 34.1 experiences a0.5 % mismatch. Estimate the resulting DACs INL and DNL. Use SPICE to verifyyour answer.

The 0.5 % mismatch ( or 1 σ [standard deviation]) is the mismatch specified∆R/Rfor the unsilicided n+ polysilicon resistors specified in Table 33.1. Again it isdesirable to use poly resistors because they sit above the substrate on the fieldoxide and are more immune to substrate noise. Note that the voltage coefficientcan (will) also cause nonlinearities. However, instead of the worst case situation ofan abrupt mismatch between the lower resistors and the MSB 2R resistor as usedin this example, a first-order voltage coefficient error will cause a linear variationof the resistor values from the LSB resistor up to the MSB resistor (and so theeffects of the voltage coefficient, for reasonably small values, are generally notsignificant compared to the random mismatch effects).

Rewriting Eqs. (34.14) and (34.15) to estimate the maximum number of bitspossible with 1 LSB INL or DNL results in

(34.20)N = 1 − 3.3 ⋅ log ∆RR

Using this equation with results, again, in N = 8.6 bits. For a 10-bit∆R/R = 0.005DAC we would estimate both the INL and DNL as 2.4 bits.

To verify these results using SPICE let's input a code of 01 1111 1111 (ideally748.5 mV) and then step the input code to 10 0000 0000 (ideally, 750 mV). Withthe MSB 2R resistor changed to 20.1k (a 0.5 % mismatch from its ideal 20k value)the simulation results are shown in Fig. 34.16. With this mismatch the output ofthe DAC is 750.4 mV when the input is 01 1111 1111. The INL with this inputcode is 1.25 LSBs (roughly 1.9 mV). The INL when the input digital code is 100000 0000 is −1.25 LSBs. The DNL at this worst-case point is −2.5 LSBs. Note


Ideal response

Figure 34.16 Output if MSB resistor in Fig. 34.14 experiences a 0.5 % mismatch.

Actual DAC output

1 L

SB

01 1111 1111 10 0000 0000

INL

= 1

.25

LSB

s

INL

=

1.25

LS

Bs

DNL = 2.5 LSBs

that the DAC is nonmonotonic (DNL < −1 LSB). An increase in the digital inputcode results in a decrease in the output voltage. Nonmonotonic DACs can result incircuits that don't function properly (an example being a successive approximationADC). A DNL of −1 LSB would indicate the output voltage of the DAC doesn'tchange when the input code changes.

To improve the DNL the upper bits of the DAC must be segmented as seen in Fig.34.6. Improving the INL relies on calibrating out the mismatch errors, Figs. 34.12and 34.13. Also note, again, that mismatch can be improved by layout techniqes(e.g. common-centroid) and by averaging the outputs of multiple resistor strings.

We can characterize the effects of a DC load resistance, RL as seen in Fig. 34.14,by noticing that RL forms a divider with the R-2R ladder. The LSB with a load can bewritten as

(34.21)1 LSB = VDD2N

⋅ RL

R + RL

Notice that if this equation reduces to the LSB value given in Fig. 34.14. TheRL → ∞time constant associated with driving an output capacitance can now be written as

(34.22)τ = R RL ⋅ CL

Two Important Notes Concerning Glitches

Note that we have assumed the RC delay through the resistors used in the R-2R ladder isnegligible. This may not be the case in many practical situations (especially if diffused orimplanted resistors are used) resulting in a DAC output glitch. Also, we have beensimulating with perfectly aligned digital signals, that is, signals that change at the exactsame moment. When the digital signals are slightly misaligned a significant glitch canoccur in the DAC's output. This means that the inputs to the DAC should be provided bythe same digital hold register. Using segmentation, with the required thermometerdecoder, can result in the digital signals driving the R-2R ladder seeing differing delays.Care must be excersied when designing the DAC input clocking circuit (e.g. add smalldummy delays).

Example 34.3Repeat Ex. 34.2 if a 200 ps skew is experienced by the lower 9-bits in the digitalinputs with relation to the MSB.

The simulation results are shown in Fig. 34.17. When comparing this result to Fig.34.16 the magnitude of the glitch in relation to the much smaller final step in theoutput voltage should be obvious. The small 200 ps skew in the digital inputscauses a code of 00 0000 0000 to be applied to the DAC for 200 ps. For this veryshort period of time the output begins to discharge from 750 mV down to ground.Note in this figure and in Fig. 34.16 the load capacitance was reduced to 0.1 pF todecrease the settling time.


The Current-Mode (Current Steering) DAC

Figure 34.18 shows the two basic cells used in the implementation of a current-modeDAC. In this section we focus on the use of the current source based cell. The advantageof the current source cell is the fact that the value of the current can be adjusted, via thebias voltage, to compensate for process variations while the value of the resistor, in theresistor based cell, is fixed. The advantages of the resistor based cell are wider outputswing (the MOSFET current source must remain in the saturation region), better voltagecoefficient (no channel length modulation or other finite MOSFET output resistanceeffects), and better substrate noise immunity (assuming the resistors are integrated on thetop of the field oxide and not down in the substrate with the MOSFETs). Notice, in thisfigure, that we've implemented the cells with two, complementary outputs. Havingcomplimentary outputs is useful, for example, in a DAC used with a video monitor(driving two complimentary 75 Ω loads). The load resistors are labeled the left loadresistor, RLL , and the right load resistor, RRL.


Figure 34.17 Showing glitch if the lower 9-bits are skewed by 200 ps in Ex. 34.2.

VDD

Bias

VDD

Figure 34.18 Basic cell used in a current-mode DAC.

VDD VDD

This simplified to This simplified to

Current source based cell. Resistor based cell.

RLLRLL RLLRLLRRL

RRLRRL

RRL

IbiasRdac Rdac

b

b

b

b

Glitch area ≈ 125 mV ⋅ 2 ns = 250 V ⋅ ps

Figure 34.19 shows the block diagram implementation of a current-mode DAC.The output voltages depend on both IREF and the load resistors. The current sources areimplemented using both the cells in Fig. 34.18 and a PMOS W-2W mirror (see Fig. 33.17in the last chapter) to improve layout area. The combination of binary weighted currentsources must be used together with the required segmentation of the upper bits to reduceDNL. Although not drawn so in Fig. 34.18, the current sources can be cascoded toincrease their output resistance (decrease their voltage coefficient). Again the switchesconnected to the loads should be controlled by signals from the same register to avoidsignificant glitches in the outputs.

While the matching requirements of current-mode (current steering) DACs werediscussed in Ch. 29 we should comment on ways to improve matching before leaving thissection. The layout of the W-2W ladder should follow the basic techniques discussed inCh. 20, i.e. devices oriented the same way, use of dummy poly and diffusions, attempt tokeep the source-drain voltages constant, use long L devices, etc. The layout of the W-2Wmirror should look similar to the layout of the R-2R string in Fig. 33.13 but it can alsoemploy two or more W-2W segments to average variations. The upper bits segmented bits


VDD

Segm

ents

W-2

W c

urre

nt m

irro

r (s

ee F

ig. 3

3.17

)

1

6

7

1234567

The

rmom

eter

Dec

oder

Figure 34.19 Implementation of a current-mode DAC.

b0

b1

b2

b3

b4

RLL RRL

IREF

IREF

IREF

2−1IREF

2−16IREF

2−8IREF

2−4IREF

2−2IREF

b5

b6

b7

Vout+

Vout−

can be laid out adjacent to the W-2W and can also benefit from averaging the outputs ofseveral DAC layouts. In some cases the number of bits used in the W-2W ladder equalsthe number of bits used for the upper segments. For example, a 10-bit DAC would use a5-bit W-2W ladder (whose MSB is IREF /2) and 31 segments with values of IREF (a total of36 outputs see Fig. 34.20a). To improve INL the layouts are connected (see the examplecommon centroid layout in Fig. 34.20b) together to, hopefully, average the randommismatch effects and increase the linearity of the DAC. Of course the current output in thecircuit of 34.20b is four times the current in 34.20a for the same reference biasing levels.

34.2 Op-Amps in Data Converters

The open-loop magnitude and phase responses of a typical op-amp are shown in Fig.34.21. In this section we discuss the gain and bandwidth requirements of op-amps used ineither a DAC or an ADC. We assume that the op-amp is designed to have a phase marginof 90 degrees under full load conditions and over process variations. (We should point outthat this assumption is easily met using an OTA that is compensated by a load capacitanceas discussed in Ch. 25.) It's important to understand why having a 90 degree phase marginis important, namely, to avoid a second-order step response with the associated ringing. Ifthe phase margin is 90 degrees we get an RC like settling response shape as seen in Fig.34.15. Figures 33.73 and 33.74 show the AC responses and step response of a basic


Figure 34.20 Layout of a current-mode DAC.

31

Segm

ents

and

W-2

W m

irro

r.

123

(a) layout block

Segm

ents

and

W-2

W m

irro

r.

Segm

ents

and

W-2

W m

irro

r.

Segm

ents

and

W-2

W m

irro

r.

Segm

ents

and

W-2

W m

irro

r.

Segm

ents

W-2

W

Outputs

(b) averaging the outputs ofseveral layout blocks to improve linearity.

mixed-signal op-amp. The phase margin of this op-amp was 70 degrees. The step responseshows a moderate amount of ringing. Decreasing the phase margin increases the peakamplitude of the ringing and can lengthen the settling time (the time it takes the op-amp'soutput to settle to within 1/2 LSB of the ideal final value). Note that the settling time, inFig. 33.74, was measured using an inverting op-amp topology. While we concluded, inSec. 34.1.2, that we must use an inverting op-amp (or a fully-differential topology wherethe input common-mode voltage remains constant) it is still useful to look at the basicspeed (bandwidth) differences between noninverting and inverting topologies.

Gain Bandwidth Product of the Noninverting Op-Amp Topology

Figure 34.22 shows the basic topology of a noninverting op-amp amplifier. The voltage onthe inverting op-amp input can be written as

(34.23)v− = Vout⋅

β

R1

R1 + R2

where β is the feedback factor for this series-shunt feedback amplifier (the ideal closedloop gain, ACL , is 1/β or 1 + R2/R1). The output of the amplifier is

(34.24)Vout = (Vin − v−) ⋅ AOL( f )

Solving these equations for the closed-loop bandwidth of the amplifier, fCL,3dB , gives

(34.25)fCL,3dB ≈ β ⋅ AOLDC ⋅ f3dB = β ⋅ fu


f

Phase margin

Gain margin

Figure 34.21 Magnitude and phase responses of an op-amp.

Assumes a dominant poleop-amp (phase margin of90 degrees)

AOL( f ) = AOLDC

1 + j ⋅ f

f3dB

AOLDC

f3dB

−180

−450

−90

fu ≈ f3dB ⋅ AOLDC

= 90 here.

20 log [AOL( f )]

The gain bandwidth product of the noninverting amplifier is then

(34.26)Gain ⋅ Bandwidth = fu

Gain Bandwidth Product of the Inverting Op-Amp Topology

Figure 34.23 shows the schematic diagram of an inverting op-amp topology using anop-amp. Summing the currents at the inverting input node gives

(34.27)Vin − v−

R1= v− − Vout

R2

The output of the amplifier is related to the op-amp's input terminals using

(34.28)Vout = (−v−) ⋅ AOL( f )

Solving these two equations for the closed-loop bandwidth, once again, results in Eq.(34.25) with β defined as indicated in Eq. (34.23). This can be confusing because thefeedback factor, β, for the inverting amplifier is not the same as for the noninvertingamplifier. The inverting op-amp is an example of a shunt-shunt amplifier (current input andvoltage output). The feedback factor for this amplifier is −1/R2 where(= β)

(34.29)Vout

iin= −R2

If we assume the input current source (Norton equivalent) has a source resistance of R1 sothat we can writeVin = iin ⋅ R1

(34.30)ACL = Vout

Vin= R2

R1

Keeping in mind that closed loop bandwidth of the inverting amplifier is still, from Eq.(34.25),

(34.31)fCL,3dB ≈ R1

R1 + R2⋅ fu

we can write

(34.32)Gain ⋅ Bandwidth = R2

R1 + R2⋅ fu


Figure 34.22 Noninverting op-amp topology.

Vin

R1

R2

v−

v+

Vout = AOL( f ) ⋅ (v+ − v−)

Example 34.4Compare the bandwidth of a +1 gain amplifier implemented using a noninvertingop-amp topology (Fig. 34.22) to the bandwidth of a −1 gain amplifier using theinverting op-amp topology (Fig. 34.23).

Using Eq. (34.26) the bandwidth of the +1 gain amplifier is fu. This amplifier iscommonly known as a unity voltage follower and has (an open) and R1 = ∞ R2 = 0(a short). The bandwidth of the inverting, −1, gain amplifier can be determinedusing Eq. (34.32) with R1 = R2 and is 0.5fu. This result is important because itshows that for the fastest speed the noninverting op-amp topology offers the bestchoice. Practically, however, the nonlinearities related to the finite CMRR (see Eq.[34.8]) force the use of inverting op-amp topologies. As discussed earlier, theinput common-mode voltage must remain constant in any precision application.Note that a fully-differential op-amp topology is also a shunt-shunt amplifier with again bandwidth product given by Eq. (34.32).

Example 34.5Comment on the derivations of Eqs. (33.23) - (33.25) in the last chapter.

The equations are still valid, however, it would be more correct to use the value ofβ given by the resistive divider in Eq. (34.23) instead of β = 1. For the test setupshown in Fig. 33.74 β = 0.5 and so the settling time would more accurately beestimated as 31.8 ns.

34.2.1 Op-Amp Gain

In this section we answer the question of how large the DC open-loop gain of the op-amp,AOLDC , must be in a data converter with a resolution of N bits. We know the op-amp mustamplify signals to within 1/2 LSB of the ideal value. Further we know the closed-loop gainof an amplifier can be written as

(34.33)ACL =AOL( f )

1 + β ⋅ AOL( f )

The feedback factor can be written, after reviewing Figs. 34.23 or 34.24, as


Figure 34.23 Inverting op-amp topology.

R1

R2

v−

v+

VinVout = AOL( f ) ⋅ (v+ − v−)

(34.34)β = R1

R1 + R2or

CF

CF + CI

=

1/jωCI

1/jωCI + 1/jωCF

where the capacitive dependence, or second term in this equation, is used when estimatingthe feedback factor present in a discrete-analog integrator (DAI).

As we discussed in Ch. 29 the output of the amplifier will be equal to its idealvalue minus some maximum deviation, ∆A. We can write the gain of the DAI over oneclock cycle (treating the integration, , as an initial DC condition on thez−1/[1 − z−1]feedback capacitor) as

(34.35)ACL = CI

CF

Then we can write

(34.36)ACL = CI

CF− ∆A = AOLDC

1 + AOLDC ⋅ CF

CF+CI

If the maximum value of ∆A is at most 1/2 LSB of the ideal gain, or,

(34.37)∆A = CI

CF⋅ 1/2 LSB

Fullscale output= CI

CF⋅ 1/2 ⋅ (VREF+ − VREF−)/2N

(VREF+ − VREF−) = CI

CF⋅ 1

2N+1

then we can estimate the minimum required DC open-loop gain as

(34.38)AOLDC ≥ 1β ⋅ 2N+1

If , as in the R-2R DAC of Fig. 34.3 or in a DAI with , then this equationβ = 1/2 CI = CF

can be reduced to

(34.39)AOLDC ≥ 2N+2

A 12-bit ADC or DAC requires the use of an op-amp with a gain greater than 16k while a16-bit converter must have . Clearly this estimate can present a real designAOLDC ≥ 256kconcern. Note that Eq. (34.38) is optimistic. For a general design, an error of 1/2 LSB duejust to op-amp gain is not desirable (so a larger value of AOLDC must be used).


Figure 34.24 Inverting op-amp topology.

CI

CF

Vin

Vout

34.2.2 Op-Amp Unity Gain Frequency

The speed of a data converter is mainly limited by the op-amp used. In general, theminimum op-amp gain-bandwidth product ( fu ) required for a specific settling time t(where t is less than 1/fclk , within a dead band of ) can be estimated, assuming no±1/2 LSBslew-rate limitations (see also Eqs. [34.18] and [34.19]), by

(34.40)Vout = Voutfinal 1 − 1

2N+1 = Voutfinal(1 − e−t/τ)

where, once again,

(34.41)τ = 12π ⋅ β ⋅fu

The minimum required op-amp unity-gain frequency is then given by

(34.42)fu ≥fclk ⋅ ln2N+1

2π ⋅ β

or, again assuming β =1/2,

(34.43)fu ≥ 0.22 ⋅ (N + 1) ⋅ fclk

If we design a 12-bit ADC that is clocked at 100 MHz we need to use op-amps with unitygain frequencies, fu , of 286 MHz (and a DC gain of at least 16k). Again, this estimate forthe unity-gain frequency is optimistic. A good design would use a larger fu than what isspecified by Eq. (34.43).

34.2.3 Op-Amp Offset

A critical characteristic of any op-amp used in a data converter is its offset voltage. Weintroduced the concept of reducing the offset voltage of an op-amp back in Ch. 27. Herewe provide additional comments and possibilities for offset reduction.

Adding an Auxiliary Input Port

A simple method of nulling the offset voltage of an op-amp is shown in Fig. 34.25 [6]. Inthis figure the added MOSFETs, M1 and M2, (which operate in the triode region) areused to essentially balance the current flowing in the current mirror load. We can think ofthe added MOSFETs as providing an auxiliary input port for offset calibration.


Figure 34.25 Trimming offset using an auxiliary input port.

Adjust the voltage hereto trim offset voltage.

VDD VDD

To diff-amp

M1 M2

Figure 34.26 shows how we would use the auxiliary input port to remove (lower)the offset. When zeroing out the offset the op-amp is removed from the circuit by openingS1 (and possibly a switch [not shown] in series with the op-amp's output). This is followedby closing S2 and S3 so that a control voltage is stored on C. Note that we have assumedthe op-amp is used in an inverting configuration (that is, the noninverting input of theop-amp, +, is tied to VCM). The offset removal is dynamic and will have to be performedperiodically. We could also use a simple R-2R DAC with a topology similar to what isseen in Fig. 34.8 to calibrate out the offset (eliminating the dynamic nature of the method).The output of the DAC would be connected to the auxiliary input port. Note that anincrease in voltage on the auxiliary input port must result in a decrease in output voltage(there must be negative feedback when connecting the output of the op-amp to the inputport).

The practical problem with the topology of Fig. 34.26 is the charge injection andcapacitive feedthrough resulting from shutting off (opening) S3. This "glitch" of chargecauses a change in the auxiliary port's input voltage and can place a significant limitationon the minimum possible offset voltage attainable after calibration. The amplitude of theglitch can be reduced by increasing C or by increasing the length of the MOSFET used inthe op-amp (M2 in Fig. 34.25). Increasing the length results in a decrease in theMOSFET's transconductance (keeping in mind the MOSFET is operating in the trioderegion) making the amplitude of the glitch less harmful. The drawback of increasing theMOSFET's length is that the range of offset voltages we can remove is reduced.

Example 34.6Suppose perfect switches are available for the circuit of Fig. 34.26. Estimate theresidual offset voltage in terms of the op-amp's gain AG from the auxiliary port tothe op-amp output.

If the offset voltage before reduction is VOS then the offset voltage after reductionis VOS/AG. For reasonable values of AG the final inherent offset voltage is negligible.The point of this example is that the charge injection and capacitive feedthroughfrom the switches is the dominant source of offset error using this technique.


Auxilary input port

Figure 34.26 Using an auxiliary input port to lower offset.

S1 S2

S3

C

VCM Vout

We've seen the problem of charge injection and capacitive feedthrough before. Themost common technique for reducing its effect is to use a fully-differential topology.Figure 34.27 shows a modification of Figs. 34.25 and 34.26 to compensate for chargeinjection. The idea is that when S4 and S3 turn off (open) the variation in voltages on thegates of M1 and M2 are equal resulting in a common change in each MOSFET'sresistance. Ideally then the current will remain balanced in the diff-amp. Note that whilewe've showed the use of triode operating MOSFETs M1/M2 in Figs. 34.25 and 34.27 inseries with the load of a diff-amp on the input of an op-amp we could also use this conceptin later stages of the op-amp.

Figure 34.28 shows another possible topology for offset removal using an auxiliaryinput [7]. An additional diff-amp is added in parallel to the main input diff-amp stage of anop-amp to balance the currents and zero-out the offset voltage. Again, long lengthMOSFETs are used in the added input so that the glitches resulting from the imperfectionsin the MOSFET switches (S4 and S3 in Fig. 34.27) have the least effect on the operationof the circuit.


Figure 34.27 Using an auxiliary input port to lower offset (two terminals).

S1 S2

S3

C C S4

VDD VDD

To diff-amp

M1 M2 VCM Vout

Figure 34.28 Using an auxiliary diff-amp for balancing current in an op-amp's input.

Auxiliary input portMain input diff-amp

Long L devices

We can estimate the maximum offset voltage we can zero-out using the techniqueof Fig. 34.28 by writing the imbalance in the main diff-amp's currents because of its offsetvoltage as

(34.44)gm ⋅ VOS,max = id

The auxiliary input must sum the opposite of this current in the main diff-amp's load tobalance the currents in the main diff-amp (and hence eliminate the offset voltage). If welabel the transconductance of the diff-amp used in the auxiliary input gmaux and themaximum allowable differential voltage on the auxiliary input for linear operation Vaux,max

then we can write

(34.45)gm ⋅ VOS,max = gmaux ⋅ Vaux,max

Because we are using long length devices in the auxiliary input for the samegmaux << gm

biasing current levels. If (a differential voltage of will causeVaux,max = 200 mV ± 200 mVall of the diff-amp tail current to flow through one side of the diff-amp) and gm/gmaux = 10then we can zero-out at most 20 mV of op-amp offset.

The offset storage technique shown in Fig. 34.27 relies on the removal of theop-amp from the circuit while autozeroing the offset. The scheme in Fig. 34.29 showshow the technique can be extended to remove the offset while leaving the main op-amp,O1 in the circuit at all times. When S2, S3 and S4 are closed the offset of O2 is zeroedout. At this time switches S1 and S5 are open. After O2's offset is stored S2, S3 and S4are then opened. Next S1 and S5 close. O2 is used to precisely set the inverting input ofO1 to VCM through the feedback around O1 (not shown). When O2 goes back to zeroingout its own offset (S2 - S4 close) the capacitor connected to the auxiliary port of O1retains the charge, and thus voltage, needed to keep O1's offset nulled out to zero. Againthis capacitor should be large to avoid problems from the imperfections of S5.


S1

S2

S3

S4

Figure 34.29 Continuous-time offset removal.

S5

O1

O2

VOS

VCM

VCM Vout

34.3 Implementing ADCs

In this section we continue to discuss implementing data converters with design concernsfor sample-and-holds (S/H), cyclic ADCs, and pipeline ADCs.

34.3.1 Implementing the S/H

We assume the reader is familiar with the fundamental implementation of a CMOS S/Hdiscussed in Ch. 27. Figure 34.30 shows the more general implementation of a S/H. Notethat if CI goes to 0 (an open) this topology reduces to the basic S/H given in Ch. 27(repeated in Fig. 34.31 for convenience).

We can determine the relationship between the input of the S/H and its output bywriting the charge stored on CI and CF when the φ1 and φ2 switches are closed (the φ3

switches are open) as

(34.46)QIφ1 = CI,F ⋅ (Vin + VCM − VCM ± VOS) = QF

φ1

where VOS is the offset voltage of the op-amp and the input (and output) voltages arereference to VCM. Note the reason why the φ2 switches turn off slightly after the φ1

switches was shown in Figs. 30.31 and 30.32 and the associated discussion (bottom platesampling). When φ3 goes high the charge on CI is

(34.47)QIφ3 = CI ⋅ (VCM − VCM ± VOS)


Figure 34.30 Data converter sample-and-hold building block.

Indicates plate closest to the substrate.

φ1

t3t2t1to

φ2

φ3

CF

CF

φ1

φ1

φ2

φ3

φ3

φ3φ3

CI

CIVCM

CL

CL

Vout+

Vout−

Vin+

Vin−

The difference between and is transferred to QF when φ3 goes high. The outputQIφ1 QI

φ3

voltage is then determined knowing charge must be conserved

CF ⋅ (Vout + VCM − VCM ± VOS) =

QFφ1

CF ⋅ (Vin + VCM − VCM ± VOS) +

QIφ1

CI ⋅ (Vin + VCM − VCM ± VOS) −

QIφ3

CI ⋅ (VCM − VCM ± VOS)

(34.48)

or

when φ3 is high. (34.49)Vout = 1 + CI

CF

⋅ Vin

Notice how the op-amp offset is auto-zeroed out. The ideal residual offset is VOS/AOL.Practically the residual offset is limited by the imperfections in the switches (which, onceagain, forces us to use fully-differential topologies). Also note, in Fig. 34.30, that we havedrawn the input capacitance of the next stage as a load, CL. This was so that the output ofthe S/H will appear to change only on the rising edge of φ3 (plus the output settling time).Finally, if the S/H is clocked at fclk = 1/Tclk the output of the S/H must settle to < 1/2 LSB,worst case, in a time of Tclk/2. This means that the value of op-amp unity gain frequencygiven by Eq. (34.42) should be doubled.


Sample-and-hold using differential topology from Ch. 27.Figure 34.31

φ1

φ1

φ1φ2

φ3

φ3

φ3

φ3

φ2t3t2t1to

φ2

φ3

CF

CF

Vout+

Vout−

Vin+

Vin−

A block diagram for the S/H of Fig. 34.30 is shown in Fig. 34.32. The use of blockdiagrams, as we saw in Ch. 32 when discussing noise-shaping, can be very useful todescribe data converters architectures.

A Single-Ended to Differential Output S/H

Note how we have assumed in the S/H of Fig. 34.30 that the input voltage was fully-differential. In most practical situations, at the input of an ADC, this isn't the case. Whilewe can connect Vin− to VCM in an attempt to change the single-ended input into afully-differential, sampled, output the practical problem is the variation of the op-amp'sinput common-mode voltage. As we've already discussed, precision data converters mustuse op-amp configurations where the input common-mode voltage is constant. Also, andperhaps more practically, the range of allowable common-mode voltages can be veryrestricted when doing low-voltage circuit design. As we saw with our basic mixed-signalop-amp in the previous chapter, Fig. 33.70, the minimum input common-mode voltage canbe very close to VCM when only an NMOS diff-pair is used.

A technique to force the op-amp's input common-mode voltage to VCM when asingle-ended input is applied to the S/H is seen in Fig. 34.33 [8]. The error amplifiersenses the op-amp's input common-mode voltage. It adjusts the value of the voltageapplied to the top plates of the input capacitors, when φ3 is high, until the common-modevoltage is approximately VCM. We say approximately to indicate that we don't want thegain of the error amplifier to be too large so that stability is a concern. The settling time ofthis circuit is not too important because any variation in its output simply represents adeviation from VCM on the op-amp inputs. As long as the deviation is small and falls withinthe common-mode range of the op-amp the single-ended to differential S/H functionsproperly. The addition of this error amplifier will increase the CMRR and thus reduceop-amp distortion (see Eq. [34.8]). Of course, when the φ1 and φ2 switches are on theop-amp's input common-mode voltage is . Figure 34.34 shows a possible designVCM ± VOS

for the error amplifier. The error amplifier is simply an operational transconductanceamplifier.

A common-mode feedback circuit (CMFB) is still required to precisely balance theoutputs of the op-amp. Figure 34.35 shows one possible design. In this figure we assumethe reader is familiar with the designs and notation used in the last chapter for op-ampdesign in a submicron process. When the φ1 switches are closed the outputs are connectedto the CMFB amplifier, Fig. 34.35a. Also when the φ1 switches are closed, from Figs.


Figure 34.32 Block diagram for the S/H of Fig. 34.30.

S/HVin Vout

1 + CI

CF

34.30 or 34.33, the op-amp is placed in the unity feedback configuration. Because the gainof the op-amp is large the inputs must be at the same voltage. The CMFB circuit is used toinsure this voltage is VCM . A typical mixed-signal op-amp is seen in Fig. 34.35b.(±VOS)This op-amp is derived from the topology given in the last chapter without the outputbuffers. The benefit of removing the output buffers when driving purely capacitive loads isthe ease of attaining a 90 degree phase margin (and so clean settling behavior). The


Figure 34.34 Schematic of the error amplifier.

VDD

OutW/2

W/2

W

Bias

Figure 34.33 Single-ended to differential sample-and-hold.

Error amplifier

VCM

CF

CF

φ1

φ1

φ2

φ3

φ3

φ3φ3

CI

CI

CL

CL

Vout+

Vout−

Vin+

VCM

vo+

vo−

drawbacks of not using an output buffer are the reduced gain and the need to increase thebiasing currents and devices sizes to drive a given load capacitance. Again, thegain-boosting amplifiers labeled N and P in (b) can be compensated, if needed, usingcapacitors at their outputs to ground (or VDD). If a basic diff-amp, as seen in Fig. 33.69,is used then in most situations no additional capacitance is needed. The CMFB amplifier isseen in Fig. 34.35c. It is simply a PMOS diff-amp with diode loads. The gain of thisamplifier should be similar to the gain of the diff-amp used in the main op-amp so that thesame load capacitances can be used for compensating both the op-amp and the CMFBloop. Note that when the φ1 switches are open in Fig. 34.35a the capacitors essentiallyaverage the outputs maintaining a balanced condition.


Figure 34.35 Mixed-signal op-amp for use in a S/H with CMFB.

op-amp detail

Common-mode feedback circuit

VDDVDD VDD

N

P

VDD

N

P

CMFB ampdetail shown

(a)

(b)

in (c) on the

2W

2W

next pageVCMFB

φ1

vo+

vo−VCM

Vlow

Vhigh

vo+

Vbias3

Vbias2

Vhigh

Vlow

vo−

VCMFB

Vbias4

34.3.2 The Cyclic ADC

Cyclic or Algorithmic DACs were first discussed back in Ch. 29. Here we present theconcept of a Cyclic ADC. A Cyclic ADC is seen in Fig. 34.36 assuming an 8-bit (N = 8)converter. The input signal is sampled on the rising edge of every eighth (N) clock pulse.On the rising edge of every clock pulse the comparator determines if the S/H input isabove or below the common-mode voltage. If it is below VCM nothing is subtracted fromthe S/H output. If it above VCM then VCM is subtracted from the S/H output. In either casethe resulting output is multiplied by two and cycled back to the S/H input. Each time thecomparator output goes high the value is stored in a shift register. When the conversion iscomplete the digital word stored in the shift register, which corresponds to the analoginput voltage, is shifted into a hold register. The next conversion then begins on thefollowing clock pulse starting with sampling the input voltage, Vin. Note that it takes Nclock cycles for one conversion.

Example 34.7Determine the output of the ADC in Fig. 34.36 if the input voltage is 1.5 V.

1. Sample the input voltage of 1.5 V, the output of the comparator is a logic 1(MSB). VCM (= 0.75 V) is subtracted from the S/H output resulting in 0.75 V. Thisoutput is multiplied by 2 resulting in 1.5 V. This 1.5 V output (the output of themultiplier) is cycled back to the S/H input.

2. Sample the fed back voltage of 1.5 V, the output of the comparator is, again, alogic 1 (MSB − 1). VCM (= 0.75 V) is subtracted from the S/H output resulting in


VDD

Out

Figure 34.35 (cont'd) CMFB amplifier circuit.

(c)

W/2

W/2

2W

2W

Vbias1

Vbias2

Vbias3

0.75 V. This output is multiplied by 2 resulting in 1.5 V. This 1.5 V output (theoutput of the multiplier) is cycled back to the S/H input.

3. This continues and the final output of the ADC hold register is 1111 1111(binary offset format).

Example 34.8Repeat Ex. 34.7 if the Cyclic ADC input is 1.1 V.

1. Sample the 1.1 V input voltage. The comparator output goes high (MSB, b7 , =1). The output of the multiply by 2, after subtracting VCM (= 0.75) from the S/Houtput, is 0.7 V.

2. Sample 0.7 V fed back voltage. Comparator output goes low ( b6 = 0). Outputof the multiplier is 1.4 V.

3. Sample 1.4 V. Comparator output goes high (b5 = 1). Output of the multiplier is1.3 V.

4. Sample 1.3 V. Comparator output goes high (b4 = 1). Output of the multiplier is1.1 V.

5. Sample 1.1 V (b3 = 1) output of the multiplier is 0.7 V.

6. Sample 0.7 V (b2= 0) output of the multiplier is 1.4 V.


Vin

VCM

VCMfclk

Figure 34.36 Block diagram of a cyclic ADC.

S/H

2 MUX

0

01

N-bit shift register

Hold register

MSBLSB

clk/N

select

(assuming N = 8)

(assuming N = 8)Move switch to input when high.

Input

clocked comparator

clock pulses

in

clk

÷ N



9. Sample new input voltage and begin conversion again. The output word in thehold register is 1011 1011 (binary offset).

Comparator Placement

We showed the inverting input of the comparator in Fig. 34.36 connected to the common-mode voltage. In practice, however, we know that the input signal may be single-ended orthe fed back signal may have a common-mode voltage slightly different than the idealvalue. If the common-mode voltage of the fed back signals was, for example, 10 mVdifferent than the ideal value the comparator can make a wrong decision. Further, if thecommon-mode voltage is varying because of power supply, noise or temperature changeswe can make a wrong decision even if some calibration scheme is employed. To avoid awrong decision the comparator is most often used in a fully-differential configuration, asseen in Fig. 34.37, with offset storage.


Figure 34.37 Implementation of the comparator with a S/H for use in a cyclic ADC.

Clocked comparator,see Fig. 33.34 where

digital

the NAND gates arenot used.

VCM

CF

CF

φ1

φ1

φ2

φ3

φ3

φ3φ3

CI

CI

CL

CL

Vouta+

Vouta−

Vin+

VCM

vo+

vo−

Voutd+

Voutd−

φ3

φ3

φ1

φ1

In Fig. 34.37 the clocked comparator shown in Fig. 33.34 is used without theNAND gates on the output. This comparator can have significant kickback noise. Byadding the φ2 switches in series with the comparator input we ensure the kickback noisedoesn't corrupt the S/H input voltage. Note that since φ3 and φ2 are nonoverlapping weguarantee the comparator and S/H are disconnected with the comparator is clocked (andthe kickback noise is generated). Note that when the φ1 switches are closed the offsetvoltage of the comparator or the op-amp is zeroed out. The performance requirements ofthe comparator (gain and offset) can be greatly reduced (offset storage is not required) ifwe use 1.5 bits per clock cycle instead of the 1 bit per cycle used here [9]. We discuss thisfurther at the end of the section.

Implementing Subtraction in the S/H

Notice in Fig. 34.36 how we can implement the S/H and the multiply by two by simplysetting in Fig. 34.30. Reviewing Fig. 34.36 we see that it would also be nice toCF = CI

implement the subtraction in the S/H too. In Fig. 34.36 we see that if the output of theMUX is 0 nothing needs to be changed in Fig. 34.30. However, if the MUX output is VCM

then the S/H output must be reduced by VCM. Consider what happens if, when φ3 goeshigh, instead of connecting the bottom plate of CI to VCM in Fig. 34.30 we connect it toVDD (= 1.5 V or 2VCM here). Doing this, after reviewing Eqs. (34.46) to (34.49) results in

(34.50)QIφ3 = CI ⋅ (VDD − VCM ± VOS)

or

(34.51)Vout = 1 + CI

CF

⋅ Vin − CI

CF⋅ VCM

If , a requirement for a gain of 2, then when the bottom plates of CI are connectedCF = CI

to VDD (when φ3 is high) we will subtract VCM from the S/H output.

REFERENCES

[1] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, CambridgeUniversity Press, 1998.

[2] R. E. Suarez, P. R. Gray, and D. A. Hodges, “All-MOS Charge RedistributionAnalog-to-Digital Conversion Techniques - Part II,” IEEE Journal of Solid-StateCircuits, Vol. 10, No. 6, pp. 379-385, December 1975.

[3] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, andSimulation, IEEE Press, 1998.

[4] S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits,Second Edition, McGraw-Hill, 1998.

[5] J. A. Schoeff, An Inherently Monotonic 12-bit DAC, IEEE Journal of Solid-StateCircuits, Vol. SC-14, No. 6 Dec. 1979, pp. 904-911.


cmos mixed signal circuit design by jacob baker continuation

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