cmos metal gate

8/8/2019 Cmos Metal Gate

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PMOS & NMOS


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NMOSSilicon

gate


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NMOS

Silicon

gate


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COMPLEMENTARY METAL OXIDE

SEMICONDUCTOR (CMOS)

It is The Combination Of Both

PMOS & NMOS in a Single Chip


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ADVANTAGES

1. Minimum feature size2. Low static power consumption

3. Gate propagation delay in the order of nanoseconds

4. Consumes very low power, particularly, at low

frequency.

5. The large logic voltage swing, with the high-state

output voltage being very close to +VDD

6. The low-state output voltage dropping is very closeto either ground potential or the negative supply

voltage.

7. CMOS provides lower delay and lower dc power

dissi ation


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APPLICATIONS

1. Prime choice for high speed, high density

applications.

2. The prime choice in applications requiringminimum power.


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Disadvantages1. Greater process complexity and increased chip area

(about 10 to 30 % compared to NMOS).2. CMOS design is to have both p-channel and n-

channel transistors on the same wafer.

3. This leads to two different approaches to CMOS

Both have their on advantages and disadvantages

1. p-well approach where n-channel transistors are

created.

2. The n-well approach, produces the n-channel

transistors in p-type substrate and the n channel

transistors in an n-well


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P WELL APPROACHThe starting substrate is n-type, which contains the p-

channel transistors and, deep p-type doped areascalled the "p-well", where n-channel transistors arecreated

Advantages

The p well approach produces balancedperformance of the p- and n-channel transistorsbecause of two opposite factors. The n-channeldevices have higher conductivity (about twice the

conductivity of p-channel devices) and transistors ofany type produced in a well have less speed thanthose built into a clean substrate by doping. It isalso easier to produce a p-well in an n-substraterather than an n-well in a p-substrate

The p well approach is proven and high reliability


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n-well approachThe n-well approach produces the n-channel transistors

in p-type substrate and the n channel transistors inan n-well, which actually increases the performancedifference between the p-and n channel transistors.

n-well approach is compatible with the NMOS processusing about 20% more processing steps.

Advantage

The NMOS and CMOS processes can shareprocessing steps and substrate material, which is anadvantage for high-volume production.

The n-well process also provides reduced latch-upsensitivity

Improved n-channel performance

Low cost.


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F

ABRIC

ATION PROC

ESS1. METAL GATE

2. SILICON GATE

1. P WELL(SUBSTRATEN TYPE)

2. N WELL(SUBSTRATE P TYPE)

3. OXIDE ISOLATION

4. SILICON ON SAPPHIRE (SOS)

5. TWIN WELL CMOS PROCESS


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CMOS METAL GATE (Pwell process)

Similar to metal gate N MOS


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CMOS

METAL

GATE

P wellprocess


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Drawbacks of the metal- gateprocess

1. A separate mask is used for the gate region.2. To allow for tolerances, the gate area is deliberately

overlapped with the drain and source areas. This not

only uses more area, but also increases the gate

capacitance due to overlapping. The gatecapacitance makes the device slow.

3. The metal gate process provides only one layer,

namely metal, for all terminal interconnects, this

increases the total area of chip.


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Silicon

gate

processing

employingp well


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Silicongate

processingemploying

p well


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Silicongate

processing

employing

p well


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Silicon

gate

processing

employing

p well


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Silicon

gate

processing

employing

p well


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A typical n-well process

follows exactly the stepsdescribed above, except

that the substrate isp-type, in which an initial

n-well is started first.


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Advantages of Si Gate over Metalgate

1. The silicon-gate process is self-aligned, i.e., asingle mask region can be used to define the gate

as well as the drain and source regions.

2. A silicon-gate process has two layers of

interconnect, and a special structure called buriedcontact to connect between polysilicon and diffusion

wire.

3. CMOS also provides better scalability and

"ratioless" logic circuits.

4. CMOS process technology has undergone

extensive experimentation and there are large

variations in processing steps and parameters


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OXIDE ISOLATION CMOSPROCESS

The oxide-isolation CMOS process, also

referred to as

ISOPLANAR or SELECTIVELY

OXIDIZED CMOS process,

is a self-aligned silicongate process withHIGH DENSITY, SPEED, AND YIELD.


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OXIDE

ISOLATION

CMOS

PROC

ESS


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SILICON ON SAPPHIRE CMOS PROCESS The silicon-on-sapphire (SOS) CMOS

structure is a heteroepitaxial CMOS structurein which a thin (~1 m) single crystal siliconepitaxial layer is deposited on a highlypolished single-crystal sapphire substrate.Thesilicon film is doped n+ and p+ by phosphorusand boron ion implantation, followed by anannealing or drive-in diffusion step, asrequired. The thin silicon film is then etchedinto many separate NMOS and PMOS devicesand interconnected by the metallizationpattern.


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SILICON ON SAPPHIRE (SOS)The starting wafer is sapphire (aluminium oxide, Al203) onwhich silicon, whose crystal lattice is compatible with that of

sapphire, is grown


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SILICON ON SAPPHIRE (SOS)n-type or p-type by implantation


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polysilicon is deposited on top of it

to form the gate terminals


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SILICON ON SAPPHIRE (SOS)source and drain regions


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SILICON ON SAPPHIRE SOS final structur


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SILICONON

SAPPHIRE

CMOS

PROCESS


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Drawbacks of the SOS process

(i)The dielectric constant of sapphire is highcompared with that of silicon. This results in a

higher coupling capacitance in the adjacent wires,

which gets worse with scaling (offsetting the

reduced junction capacitance). This affects thespeed adversely.

(ii)Sapphire is an expensive raw material which may

be more suitable for jewelry than for transistors.


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TWIN WELL CMOS PROCESS

The twin-well employs two separate wellsCMOS structure which are implanted intovery lightly doped silicon.

This allows the doping profiles in each well

to be tailored independently so that neithertype of device will suffer from excessivedoping effects.

The lightly doped silicon is usually an

epitaxial layer grown on a heavily dopedsilicon substrate.

The substrate can be either n-type or p-type.


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n well ion implant



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TWIN WELL CMOS PROCESSp well implant


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twin well drive in



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TWIN WELL CMOS PROCESSnon selective source/drain implant



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TWIN WELL CMOS PROCESSselective source/drain implant



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TWIN WELL CMOS PROCESSp glass deposition


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TWIN

WELL

CMOS

PROCESS


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A CMOS Fabrication SequenceTwo-Level Metallization and via Holes

2 levels of metal results in the minimuminterconnection delays but requires the mostprocessing steps.

The first level of metal is placed on the chipafter the polysilicon gates and is insulated fromthe polysilicon gate (below)

Second-level metal (above) by SiO2.

The desired connections between level 1 andlevel 2 metal are made by means of openingcalled via holes which are etched beforedeposition of level 2 metal.

A CMOS Fabrication Sequence


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A CMOS Fabrication SequenceTwo-Level Metallization and via Holes Electrical connections between metal

layer with polysilicon or diffusion layerare referred to as contactcuts.

The contact cuts are established

between level 1 metal and also betweenlevel 1 metal and diffusion layer.

Electrical connections established

between polysilicon and diffusion layersare referred to as buried or buttingcontacts.


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CMOS

CIRC

UITFOR

VLSI

on ro o res o o age or


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on ro o res o o age or Structure.

To maximize the performance of the devices,

the threshold voltages of the n-and p-channel

devices of CMOS structure should be

comparable, and ideally, of equal magnitude.

The threshold voltages should be as low as

possible without introducing excessive off

currents.


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Structure. Different methods are:-

1. Heavily n-doped polysilicon is suitable for gatematerial. This is usually combined with a silicide layerto lower the sheet resistance.

2. The work function of n+

polysilicon is ideal for an n-channel MOSFET since it will yield VTh < 0.7 V forreasonable values of channel doping and oxidethickness.

3.The threshold voltage is easily adjusted from 0 to +1V with a substrate doping rang of 1015 to 1017 cm-3,which is the proper doping range to be compatible withother device constraints (such as short channeleffects .

Structure


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Structure. 4.Implant a shallow boron layer into the channel

region.

5. A single boron implant dose can be used to

set the threshold voltage of both the n- and p-

channel transistors. If the background dopingsare chosen correctly.

6. Choices of gate material, such as, MoSi2,have metal work functions that are between

those of n+ and p+ polysilicon


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Latch up problems

cmos metal gate

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