Lecture 4Lecture 4

CMOS Inverter

Professor Sunil BhaveCU School of Electrical and Computer p

Engineering

February 8, 2010

I tInverters

DC AnalysisDC AnalysisOperating regions and voltage transfer curveLogic levels and noise marginsLogic levels and noise margins

Transient Analysis - delayPPower

Obj tiObjectivesWe have studied how a transistorWe have studied how a transistor can be viewed as a switch (switch-view)We have derived the I-V model for a transistora transistorNow with this simple model, we analyze the “electrical” properties of a CMOS inverter

Noise MarginDelayPower

Two outcomes:Analysis abilityUnderstand concepts (intuition)

Reliability―Noise in Digital Integrated Circuits

i(t)v(t) VDD

( )

Inductive coupling Capacitive coupling Power and groundnoise

DC OperationVoltage Transfer CharacteristicVoltage Transfer Characteristic

V(out)

VOH fV(y)=V(x)

VOH = f(VOL)VOL = f(VOH)VM f(VM)

VMSwitching Threshold

VM = f(VM)

VOL

M

V(in)VOHVOL

Nominal Voltage Levels

Mapping between analog and digital signals

VoutVSlope = -1V OH

out

VIH

VOH“ 1”

UndefinedRegion

Slope = -1VIL

V IL V IH V in

V OL“ 0” VOL

D fi itiDefinitions

VMVMVILVOLVIHVOH

D fi itiDefinitions

VM Vout=VinVM – Vout=VinVIL – Slope = -1VOL – Vout @ VIHVIH – Slope = -1VOH – Vout @ VIL

Regenerative PropertyRegenerative Property

outout

finv(v)v3

out

f (v)v3

out

v1

v3 f (v)

v1

finv(v) f (v)finv(v)

v0 v2 inRegenerative Non-Regenerativev2 v0 in

Regenerative PropertyRegenerative Property

A chain of inverters

v0 v1 v2 v3 v4 v5 v6

5

V (V

olt) v0

v11

3

2 4

v1v2

02 1

1

6 8 10Simulated responset (nsec)

Simulated response

N i M iNoise MarginsHow much noise can a gate input see before it doesHow much noise can a gate input see before it does not recognize the input?

N i B d tNoise Budget

Allocates gross noise margin to expectedAllocates gross noise margin to expected sources of noiseS l i t lkSources: supply noise, cross talk, interference, offsetDiff ti t b t fi d d ti lDifferentiate between fixed and proportional noise sources

Key Reliability PropertiesKey Reliability PropertiesAbsolute noise margin values are deceptiveAbsolute noise margin values are deceptive

a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)

Noise immunity is the more important metric – the capability to suppress noise sourcesK t i N i t f f ti O t t i d f thKey metrics: Noise transfer functions, Output impedance of the

driver and input impedance of the receiver;

F i d F tFan-in and Fan-out

NM

N

Fan in MFan-out N Fan-in M

The Ideal Gate

V out

Ri = ∞

out

i

Ro = 0Fanout = ∞NMH = NML = VDD/2 g = ∞

V in

An Old-time Inverter

NM

5.0

NM L

3.0

4.0

out(V)

V2.0

3.0

NM HVout V M

1.0

V (V)0.0 1.0 2.0 3.0 4.0 5.0

V in (V)

CMOS I tCMOS Inverter

DC Analysis:DC Analysis:Operating regions and voltage transfer curve (VTC)Logic Levels and Noise MarginsLogic Levels and Noise Margins

VIH, VOH, VIL, VOL

Transient AnalysisTransient AnalysisDelay (tHL and tLH)

Power Analysis and PDP (Power Delay Product)Power Analysis and PDP (Power Delay Product)Power Dissipation

DC RDC ResponseDC Response: Vout vs VinDC Response: Vout vs. Vin for a gateEx: CMOS Inverter

First order analysis: switchFirst order analysis: switch model

When Vin = 0 -> Vout = VDDWhen Vin = VDD -> Vout = 0When Vin = VDD -> Vout = 0

Real analysis: transistor equations

In between, Vout depends onIn between, Vout depends on transistor size and currentBy KCL, must settle such that Idsn = |Idsp|W l tiWe solve equations

CMOS I t P tiCMOS Inverter PropertiesHigh and low levels = VDD GNDHigh and low levels VDD, GND

Voltage swing = supply voltage -> high noise marginsLogic levels *not* dependent on device sizes

ratio lessratio-lessIn steady state, there is a path from either VDD or GND to the output

Low output impedanceLow output impedanceLess sensitivity to noise

Extremely high input resistanceSteady state power is very lowSteady state power is very lowFanout = ∞ (if you don’t care about speed!)

No direct path between supply rails => no static power

T i t O tiTransistor Operation

Current depends on region of transistor behaviorCurrent depends on region of transistor behaviorFor what Vin and Vout are nMOS and pMOS in

C ff?Cutoff?Linear?S t ti ?Saturation?

MOS O tinMOS OperationCutoff Linear SaturatedCutoff Linear SaturatedVgsn < Vgsn > Vgsn >

Vdsn < Vdsn >

MOS O tinMOS OperationCutoff Linear SaturatedCutoff Linear SaturatedVgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn - Vtn Vdsn > Vgsn - Vtn

MOS O tinMOS OperationCutoff Linear SaturatedCutoff Linear SaturatedVgsn < VtnVin < Vtn

Vgsn > VtnVin > Vtn

Vgsn > VtnVin > Vtn

Vdsn < Vgsn - VtnVout < Vin - Vtn

Vdsn > Vgsn – VtnVout > Vin - Vtn

Vgsn = Vin

Vdsn = Vout

MOS O tipMOS OperationCutoff Linear SaturatedCutoff Linear SaturatedVgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

Vtp < 0

MOS O tipMOS OperationCutoff Linear SaturatedCutoff Linear SaturatedVgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp - Vtp Vdsp < Vgsp - Vtp

Vtp < 0

MOS O tipMOS OperationCutoff Linear SaturatedCutoff Linear SaturatedVgsp > VtpVin > VDD + Vtp

Vgsp < VtpVin < VDD + Vtp

Vgsp < VtpVin < VDD + Vtp

Vdsp > Vgsp - VtpVout > Vin - Vtp

Vdsp < Vgsp – VtpVout < Vin - Vtp

Vtp < 0

Vgsp = Vin – VDD

Vdsp = Vout - VDD

DC T f CDC Transfer CurveRevisit transistor operating regionRevisit transistor operating region

Region nMOS pMOSq

A

B

C

DD

E

DC T f CDC Transfer CurveRevisit transistor operating regionRevisit transistor operating region

Region nMOS pMOS

A Cutoff Linear

B Saturation Linear

C Saturation Saturation

D Linear SaturationD Linear Saturation

E Linear Cutoff

Now we are ready to derive VM, VIL, VOL, VIH and VOH

CMOS Inverter Load Ch t i ti

I

Characteristics

IDnVin = 2.5Vin = 0

Vin = 2Vin = 0.5 NMOSPMOS

Vin = 1.5Vin = 1

Vin = 1Vin = 1.5

V 1V = 1 5

Vin = 0

Vin = 0.5Vin = 2

Vin = 2.5

Vin = 1Vin = 1.5

Vout

CMOS I t VTCVout NMOS off

CMOS Inverter VTC

2.5

NMOS offPMOS res

NMOS satPMOS res

52

NMOS sat

PMOS res

11.

5

PMOS sat

NMOS res

0.5 NMOS res

PMOS off

NMOS resPMOS sat

Vin0.5 1 1.5 2 2.5

D i VDerive VM

Assume velocity saturation for both devices ignoreAssume velocity saturation for both devices, ignore channel length modulation, set VM=Vin=Vout

Solving for VM yields:g y

D i VMDerive VMSimplification for large VDD (compared to threshold and saturation voltages)

For long channel devices, or for low VDDs

VM P tiVM PropertiesFor max noise margins want Vm to be ~= Vdd/2For max noise margins, want Vm to be Vdd/2

Want r=1: (W/L)p=(W/L)n(VDSATpk’n)(VDSATnk’p)For given Vm, what transistor ratios?

VM relatively insensitive to device ratioUse PMOS slightly smaller than needed to get exactly Vdd/2Vdd/2

Device ratios only change transition regionTo move VM higher size PMOS largerTo move VM lower size NMOS largerTo move VM lower size NMOS larger

D i VILDerive VILAccurate derivation: ∂Vout/ ∂Vin=-1Accurate derivation: ∂Vout/ ∂Vin=-1

Not so insightfulSimplifying assumption: Piece-wise linear w/ gain at VmCalculate gain at Vm

Differentiate VTC at VmCan not ignore channel length modulation VoutVoutVoutCan not ignore channel length modulation

VOH

out

VOH

outout

V

VM

VV

VM

VOL

Vin

VIL VIHVOL

VinVin

VIL VIHVIH

Y D i VIHYou Derive VIH S t i I tSymmetric InverterSymmetric Inverter: k’ / k’ =1Symmetric Inverter: k p / k n =1

Why Wp/Wn = 2.5? (PMOS transistor is weak)If k’p / k’n ≠ 1, switching point will move from VDD/2If k p / k n ≠ 1, switching point will move from VDD/2Called skewed gateDifficult to skew gate very much robustness!cu o s e ga e e y uc obus ess

CMOS I tCMOS Inverter

DC Analysis:DC Analysis:Operating regions and voltage transfer curve (VTC)Logic Levels and Noise MarginsLogic Levels and Noise Margins

VIH, VOH, VIL, VOL

Transient AnalysisTransient AnalysisDelay (tHL and tLH)

Power Analysis and PDP (Power Delay Product)Power Analysis and PDP (Power Delay Product)Power Dissipation

T i t RTransient ResponseDC analysis tells us Vout if Vin is constantDC analysis tells us Vout if Vin is constantTransient analysis tells us Vout(t) if Vin(t) changeschangesRequires solving differential equationsInput is usually considered to be a step or rampInput is usually considered to be a step or rampFrom 0 to VDD or vice versa

D l D fi itiDelay DefinitionsVinin

50%

t t

t

50%

Vout

tpHL tpLH

90%

t10%

50%

tf trt10%

Ri O ill tRing Oscillator

v1 v2v0 v3 v4 v5

v v v

v1 v2v0 v3 v4 v5

v0 v1 v5

T = 2 × tp × N

D l D fi itiDelay Definitions

tpdr:tpdr:tpdf:tpd:tr:tf:

D l D fi itiDelay Definitionstpdr: rising propagation delaytpdr: rising propagation delay

From input to rising output crossing V DD/2tpdf: falling propagation delaytpdf: falling propagation delay

From input to falling output crossing VDD/2tpd: average propagation delay

tpd = (tpdr + tpdf)/2tr: rise time

From output crossing 0.1 V DD to 0.9 V DDtf: fall time

From output crossing 0 9 V DD to 0 1 V DDFrom output crossing 0.9 V DD to 0.1 V DD

D l D fi itiDelay Definitions

tcdr: rising contamination delaytcdr: rising contamination delayFrom input to rising output crossing V DD/2

t df f lli t i ti d ltcdf: falling contamination delayFrom input to falling output crossing VDD/2

t d t i ti d ltcd: average contamination delaytpd = (tcdr + tcdf)/2

I t C iti L dInverter Capacitive Load

Many caps between different nodesMany caps between different nodesReplace with single cap to GND

Mill ff !Miller effect!Linearize non-linear caps

I t C iti L dInverter Capacitive Load

Miller effectMiller effectA capacitor experiencing identical, but opposite voltage swings at both its terminalsvoltage swings at both its terminalsReplace with a cap to GND of twice the capacitance

I t L d C itInverter Load CapacitanceCapacitor Expressionp p

2Cgd1 2CGD0nWn

2Cgd2 2CGD0pWp

Cdb1 K AD CJ+K PD CJSWCdb1 KeqnADnCJ+KeqswnPDnCJSW

Cdb2 KeqpADpCJ+KeqswpPDpCJSW

Cg3 (CGD0n+CGSOn)Wn+CoxWnLn

Cg4 (CGD0p+CGSOp)Wp+CoxWpLp

Cw From extraction

CL Σ

J ti it diff t• Junction capacitances are different value low to high than high to low• Almost even split between intrinsic capacitance (diffusion and overlap cap)capacitance (diffusion and overlap cap)and extrinsic load capacitance (wire and next gate)

Si l t d I t D lSimulated Inverter DelaySPICE simulator solves the equations numericallySPICE simulator solves the equations numerically

Uses more accurate I-V models too!

Here we focus on how you can drive a simple y pexpression (to gain design insight)