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CMOS Inverter:Power Dissipation and Sizing

Professor Chris H. Kim

University of MinnesotaDept. of ECE

chriskim@umn.edu

CMOS Inverter Power Dissipation

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Where Does Power Go in CMOS?• Switching power

– Charging capacitors• Leakage power

– Transistors are imperfect switches• Short-circuit power

– Both pull-up and pull-down on during transition

• Static currents– Biasing currents, in e.g. memory

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Dynamic Power Consumption

( ) ( ) ∫∫ ∫ ====→

DDV

DDLoutLDD

T T

DDDDDD VCdvCVdttiVdttPE0

2

0 010

( ) ( ) ∫∫ ∫ ====DDV

DDLoutoutL

T T

LoutCC VCdvvCdttivdttPE0

2

0 0 21

iL 210 DDLVCE =→

Vin VoutCL

VDD

2

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Dynamic Power Consumption

• One half of the energy from the supply is consumed in the pull-up network and one half is stored on CL

• Energy from CL is dumped during the 1→0 transition

210 DDLVCE =→

2

21

DDLR VCE =iL

Vin VoutCL

VDD

2

21

DDLC VCE =

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Circuits with Reduced Swing

C L

V dd

V dd

V dd -V Th

( )ThDDDDL VVVCE −=→10

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Dynamic Power ConsumptionPower = Energy/transition • Transition rate

= CLVDD2 • f0→1

= CLVDD2 • f • P0→1

= CswitchedVDD2 • f

• Power dissipation is data dependent –depends on the switching probability

• Switched capacitance Cswitched = CL • P0→1

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Transition Activity and Power• Energy consumed in N cycles, EN:

EN = CL • VDD2 • n0→1

n0→1 – number of 0→1 transitions in N cycles

fVCN

nfNEP DDLN

NNavg ⋅⋅⋅⎟

⎠⎞

⎜⎝⎛=⋅= →

∞→∞→

210limlim

fN

nN

⋅= →

∞→→10

10 limα

fVCP DDLavg ⋅⋅⋅= →2

10α

3

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Short Circuit Current

• Short circuit current is usually well controlled0 20

−0.5

0

0.5

1

1.5

2

2.5

40 60

I sc (A

)

x 10−4

CL = 20 fF

CL = 100 fF

CL = 500 fF

time (s)

VinVout

CL

VDD

Isc ∼ 0

VinVout

CL

VDD

Isc = IMAX

Large load Small load

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Transistor Leakage• Transistors that are supposed to be off - leak

Input at VDD Input at 0

VDD 0V

VDD

ILeak

VDD0V

VDD

ILeak

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Np+ p+

Reverse Leakage Current

+

-Vdd

GATE

IDL = JS × A

JS = 10-100 pA/mm2 at 25 deg C for 0.25um CMOSJS doubles for every 9 deg C!Much smaller than transistor leakage in deep submicron

Diode Leakage

Sizing of an Inverter Chain

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Inverter Chain

If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?May need some additional constraints.

In Out

CL

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Inverter Delay• Minimum length devices, L=0.25um• Assume that for WP = 2WN =2W

• same pull-up and pull-down currents• approx. equal resistances RN = RP• approx. equal rise tpLH and fall tpHL delays

• Analyze as an RC network

WNunit

Nunit

unit

PunitP RR

WWR

WWRR ==⎟⎟

⎠

⎞⎜⎜⎝

⎛≈⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−− 11

tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):

2W

W

unitunit

gin CWWC 3=Load for the next stage:

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Inverter with Load

Load (CL)

Delay

Assumptions: no load -> zero delay

CL

tp = k RWCL

RW

RW

Wunit = 1

k is a constant, equal to 0.69 for step input

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Inverter with Load

Load

Delay

Cint CL

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL/Cint)= Delay (Intrinsic) + Delay (Load)

CN = Cunit

CP = 2Cunit

2W

W

5

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Delay Formula

( )

( ) ( )γ/1/1

~

0int ftCCCkRt

CCRDelay

pintLWp

LintW

+=+=

+

Cint = γCgin with γ ≈ 1f = CL/Cgin - effective fanoutR = Runit/W ; Cint =WCunittp0 = 0.69RunitCunit

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Apply to Inverter Chain

CL

In Out

1 2 N

tp = tp1 + tp2 + …+ tpN

⎟⎟⎠

⎞⎜⎜⎝

⎛+ +

jgin

jginunitunitpj C

CCRt

,

1,1~

LNgin

N

i jgin

jginp

N

jjpp CC

CC

ttt =⎟⎟⎠

⎞⎜⎜⎝

⎛+== +

=

+

=∑∑ 1,

1 ,

1,0

1, ,1

1=γ

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Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay

1,1,, +−= jginjginjgin CCC

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Optimum Delay and Number of Stages

1,/ ginLN CCFf ==

When each stage is sized by f and has same eff. fanout f:

N Ff =

( )Npp FNtt += 10

Minimum path delay

Effective fanout of each stage:

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Example

CL= 8 C1

In Out

C11 f f2

283 ==f

CL/C1 has to be evenly distributed across N = 3 stages:

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Optimum Number of StagesFor a given load, CL and given input capacitance CinFind optimal number of stages, N, and optimal sizing, f

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+=+=

fffFt

FNtt pNpp lnln

ln1/ 0/1

0γ

γγ

0ln

1lnln2

0 =−−

⋅=∂

∂

fffFt

ft pp γ

γ

For γ = 0, f = e, N = lnF

fFNCfCFC in

NinL ln

ln with ==⋅=

( )ff γ+= 1exp

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Optimum Effective Fanout fOptimum f for given process defined by γ

( )ff γ+= 1exp

fopt = 3.6for γ=1

0 0.5 1 1.5 2 2.5 32.5

3

3.5

4

4.5

5

γ

f op

t

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Impact of Loading on tpWith self-loading γ=1

1 1.5 2 2.5 3 3.5 4 4.5 50

1

2

3

4

5

6

7

f

No

rmal

ized

del

ay

7

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Normalized Delay Function of F

( )γ/10N

pp FNtt +=

( ) 1with ,10 =+= γNpp FNtt

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Buffer Design

1

1

1

1

8

64

64

64

64

4

2.8 8

16

22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3