cmos inverter design using tanner 180nm technology
DESCRIPTION
In this document there is a design steps of a CMOS Inverter.TRANSCRIPT
Designing of CMOS Inverter using Ledit
Rajesh Yadav
12ECP01p
M1 vout vin gnd gnd NMOS L=9u W=11.5u
* M1 DRAIN GATE SOURCE BULK (57 22 66 33.5)
M2 vout vin vdd vdd PMOS L=9u W=9.5u
* M2 DRAIN GATE SOURCE BULK (3.5 23.5 12.5 33)
.include "C:\tanner\2u-model-files\ml2_20.md"
vdd vdd gnd 5
vin vin gnd 5
.dc lin source vin 0 5 .1
.print dc v(vin) v(vout)
M1 vout vin gnd gnd NMOS L=9u W=11.5u
* M1 DRAIN GATE SOURCE BULK (57 22 66 33.5)
M2 vout vin vdd vdd PMOS L=9u W=9.5u
* M2 DRAIN GATE SOURCE BULK (3.5 23.5 12.5 33)
.include "C:\tanner\2u-model-files\ml2_20.md"
vdd vdd gnd 5
*vin vin gnd 5
vin vin gnd SIN (0 5 1000)
*.dc lin source vin 0 5 .1
.tran/op .1m 10m method=bdf
*.print dc v(vin) v(vout)
.print tran v(vin) v(vout)
M1 vout vin gnd gnd NMOS L=9u W=11.5u
* M1 DRAIN GATE SOURCE BULK (57 22 66 33.5)
M2 vout vin vdd vdd PMOS L=9u W=9.5u
* M2 DRAIN GATE SOURCE BULK (3.5 23.5 12.5 33)
.include "C:\tanner\2u-model-files\ml2_20.md"
vdd vdd gnd 5
vin vin gnd SIN (2.5 2.5 1000)
.tran/op .01m 2m method=bdf
.print tran v(vin) v(vout)
M1 vout vin gnd gnd NMOS L=9u W=11.5u
* M1 DRAIN GATE SOURCE BULK (57 22 66 33.5)
M2 vout vin vdd vdd PMOS L=9u W=9.5u
* M2 DRAIN GATE SOURCE BULK (3.5 23.5 12.5 33)
.include "C:\tanner\2u-model-files\ml2_20.md"
vdd vdd gnd 5
*vin vin gnd 5
*vin vin gnd SIN (2.5 5 1000)
vin vin GND PULSE (0 5 0 1n 1n 2.5m 5m)
*.dc lin source vin 0 5 .1
.tran/op .1m 10m method=bdf
*.print dc v(vin) v(vout)
.print tran v(vin) v(vout)
M1 vout vin gnd gnd NMOS L=9u W=11.5u
* M1 DRAIN GATE SOURCE BULK (57 22 66 33.5)
M2 vout vin vdd vdd PMOS L=9u W=9.5u
* M2 DRAIN GATE SOURCE BULK (3.5 23.5 12.5 33)
.include "C:\tanner\2u-model-files\ml2_20.md"
vdd vdd gnd 5
*vin vin gnd 5
*vin vin gnd SIN (2.5 5 1000)
vin vin GND PULSE (0 5 0 1n 1n 2.5u 5u)
*.dc lin source vin 0 5 .1
.tran/op .1u 10u method=bdf
*.print dc v(vin) v(vout)
.print tran v(vin) v(vout)
