Introduction toCMOS VLSI

Design

Elementary Logic Design

andFabrication

bySUVAYAN SAMANTA

STREAM-ECE-2ROLL-111

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INTRODUCTION

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip.

VLSI began in the 1970s

Integrated circuits: many transistors on one chip.

Metal Oxide Semiconductor (MOS) transistor Fast, cheap, low-power transistors Complementary: mixture of n- and p-type leads to less

power

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Silicon Lattice

Si SiSi

Si SiSi

Si SiSi

Silicon is a Group IV material

Transistors are built on a silicon substrate

Forms crystal lattice with bonds to four neighbors

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Dopants

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

Silicon is a semiconductor

Pure silicon has no free carriers and conducts poorly

Adding dopants increases the conductivity

Group V: extra electron (n-type)

Group III: missing electron, called hole (p-type)

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N-type P-type

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p-n Junctions

p-type n-type

anode cathode

A junction between p-type and n-type semiconductor

forms a diode.

Current flows only in one direction

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Current flow direction

Electron flow directionElectron flow direction

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NMOS PMOS CMOS

CATEGORIES

MOSFET

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MOSFET

Metal Oxide Semiconductor Field Effect Transistor

Source (Arsenic, Phosphorous, Boron)

Drain (Arsenic, Phosphorous, Boron)

Gate (Aluminium, Polysilicon)

Drainsource

Gate

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nMOS Transistor Four terminals: gate, source, drain, body

Gate – oxide – body stack looks like a capacitor

Gate and body are conductors

SiO2 (oxide) is a very good insulator

Called metal – oxide – semiconductor (MOS) capacitor

Even though gate is no longer made of metal

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n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+Body

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nMOS Operation Body is commonly tied to ground (0 V)

When the gate is at a low voltage:

P-type body is at low voltage

Source-body and drain-body diodes are OFF

No current flows, transistor is OFF

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n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S

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nMOS Operation When the gate is at a high voltage.

Positive charge on gate of MOS capacitor

Negative charge attracted to body

Inverts a channel under gate to n-type Now current can flow through n-type silicon from

source through channel to drain, transistor is ON

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n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S

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pMOS TransistorSimilar, but doping and voltages reversed

Body tied to high voltage (VDD)

Gate low: transistor ON

Gate high: transistor OFF

indicates inverted behavior

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SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

Bubble

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Power Supply Voltage

GND = 0 V

In 1980’s, VDD = 5V

VDD has decreased in modern processes

High VDD would damage modern tiny transistors

Lower VDD saves power

VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

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Transistors as Switches

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFF ON

ON OFF

We can view MOS transistors as electrically controlled

switches

Voltage at gate controls path from source to drain

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What is CMOS?

Complementary metal–oxide–semiconductor (CMOS) Has many different uses:

Integrated Circuits Data converters Image sensors Logic circuits

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CMOS Inverter

A Y

0

1

A Y

VDD

A Y

GND

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CMOS Inverter

A Y

0

1 0

VDD

A=1 Y=0

GND

ON

OFF

A Y

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CMOS Inverter

A Y

0 1

1 0

VDD

A=0 Y=1

GND

OFF

ON

A Y

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CMOS Fabrication

CMOS transistors are fabricated on silicon wafer

Lithography process similar to printing press

On each step, different materials are deposited or etched

Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

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Fabrication Steps Start with blank wafer

First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide)

Remove layer where n-well should be built

Implant or diffuse n dopants into exposed wafer

Strip off SiO2

p-substrate

P-TYPE si WAFER

Slide view

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Oxidation Grow SiO2 on top of Si wafer

900 – 1200 ºC with H2O or O2 in

oxidation furnace

SiO2

P-substrate

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PhotoresistSpin on photoresist

Photoresist is a light-sensitive organic polymer

Softens where exposed to light

p-substrate

SiO2

Photoresist

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Lithography

Expose photoresist through n-well

mask

Strip off exposed photoresist

p-substrate

SiO2

Photoresist

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Etch

Etch oxide with hydrofluoric acid (HF)

Only attacks oxide where resist has been exposed

p-substrate

SiO2

Photoresist

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Strip Photoresist

Strip off remaining photoresist

Use mixture of acids called piranah etch

Necessary so resist doesn’t melt in next step

p-substrate

SiO2

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n-well n-well is formed with diffusion or ion implantation

Diffusion

Place wafer in furnace with arsenic gas

Heat until As atoms diffuse into exposed Si

Ion Implanatation

Blast wafer with beam of As ions

Ions blocked by SiO2, only enter exposed Si

n-wellp-substrate

SiO2

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Strip Oxide

Strip off the remaining oxide using HF

Back to bare wafer with n-well

Subsequent steps involve similar series of steps

p-substrate n-well

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N-diffusion Historically dopants were diffused

Usually ion implantation today

But regions are still called diffusion

p-substrate

n-welln+ n+n+

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N-diffusion Strip off oxide to complete patterning

step

n+ n+ n+n-well

p-substrate

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P-Diffusion Similar set of steps form p+ diffusion

regions for pMOS source and drain and

substrate contact

n+ n+ n+

p-substraten-well

p+ p+ p+

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Summary

MOS Transistors are stack of gate, oxide, silicon

Can be viewed as electrically controlled switches

Build logic gates out of switches

We became familier with the fabrication process

of CMOS

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Bibliography

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web.ewu.edu/groups/technology/Claudio/ee430/Lectures/L1-print.pdf

users.ece.utexas.edu/~adnan/vlsi-05-backup/lec23Concl.ppt

en.wikipedia.org/wiki/CMOS

www.cmosvlsi.com/www.cmosvlsi.com/

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