class2 20 board block diagram

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12/4/2002

Lab Board

A description of the board youwill do measurements on



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12/4/2002Introduction

Lab Board Description

Code name is ¶King·s Canyon·Referred to hereafter as ¶KC·You will do measurements on this board in the lab

Background for KCLow-end server board

Inexpensive board for customers who wantservers Server

Computer which serves data to othersSupports more memory, more processing power,and more I/O (i.e., network bandwidth, harddrives) than desktop computersMore reliable (crashes less and recovers better)than desktop computers



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Server in a network



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Inside the Server



12/4/2002

Circuit Board Block Diagram Front

Side Bus(FSB)

Hub Interface

SS

SS

SS

SS

SSSS

SS Source Synchronous

CC- Common Clock

CC

CC

CC

CC

CC

4 PCI-X busses

Low speed 33MHzPCI bus

CPU 0 CPU 1

MCHMemory

Memory

Two (2) DDR(Double DataRate) MemoryBusses

ICH Video

P64H2 HI toPCI bridge

P64H2 HI toPCI bridge

Details to Follow «.



12/4/2002

Components on KC

¶the chips·




CPU

CPUs ²Central Processing Units

The brains of the computer that ¶run· your programRuns the Operating System (e.g. windows) and all the softwareSpeed of CPU has large effect on speed of system

Currently measured in GHz (e.g., 3.0 GHz)Consumer pc·s typically have 1 cpu inside the box ² called ¶UP·

KC has 2 cpus ² this is called ¶DP·, i.e. dual processor

Some boards have4+

cpus, they are called ¶MP

·, i.e. multi-processorKC uses Intel Xeon CPU·sCurrently at 3GHzSimilar to Pentium 4

Bigger cache (superfast memory inside CPU) Can operate with other CPUs on same bus

The Silicon die (2) is under this metal heat

spreader (1). The die is significantly smallerthan the heat spreader. A Fansink mountsto the heat spreader to keep die cool.



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MCH

MCH ² Memory Controller HubHelps CPU communicate with rest of system

The ¶gatekeeper· to the outside world from perspective ofCPU

Talks to memory, CPU, and I/O I/O means busses and chips and boards which ultimately connect

to things like hard drives, networks, keyboards, monitor, etc..Maintains memory

tells it when to refresh, etc.. (dynamic memory has to berefreshed or it forgets the data it holds)

Detects errors in what is stored in memory (ECC) and

periodically corrects these errorsKC uses Intel E7501 MCH

http://www.intel.com/design/chipsets/e7501/index.htm?iid=ipp_srvr_proc_xeon+e7501&

Actual Die: Passive (no fan)Heatsink mounts on top.

Package decouplingcapacitors. Try tohold voltage rails(vcc) steady. Closerto the die the better.



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ICH

ICH ² Input/Output Controller HubI/O device that deals with critical but slow speeddevices

Video controller (basic 2-d video on servers, not meant for 3-d graphics)

Talks to Keyboard, mouse via ¶Super IO· chip

BIOS (contains software which computer runs when it·s firstpowered on. BIOS gets computer up and running and thenpasses control to the OS)

IDE Hard drive (slow hard drive that OS boots off of. Thebig capacity hard drives do not connect to ICH)

Helps with initial bootup of system

Talks to mch over a slow version of the Hub Interfacebus

KC uses Intel 82801CA ICH

Still uses wire-bond technology.Doesnt require heatsink.



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Memory Modules Memory ² High speed storage place for code and data used by

CPUMuch faster than hard drive storage, but not as massive inquantity

2-16 Gigabytes vs. 100·s of GigabytesSlower than CPU cache (small amount of memory internal to CPU)

Memory die·s are inside wire-bond packages called ¶DRAMs·

Dynamic Random Access MemoryMany DRAMs solder to a memory board called the ¶DIMM·

Dual In-line Memory ModuleAnywhere from 9 to 36 DRAMs on one memory board2 types of memory boards: Unbuffered and Registered. Unbuffered isused in desktop. KC (and most servers) only uses Registered DIMMs.

Memory board plugs into KC board via a connector.KC can support up to 8 DIMMs

Many different DIMM manufacturersMicron, Samsung, Elpida,Infineon, « DRAM

2 DIMMshttp://www.micron.com/products/modules/ddrsdram/index.html



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PCI-bridge P64H2 ² PCIX 64-bit to Hub Interface 2 bridge

Gateway to High Speed I/O devices such as hard drivearrays adapters or ethernet adaptersTalks to MCH on one side

Via high speed variey of ¶Hub Interface· BusTalks to 2 separate pci-busses on other side

Several connectors connect to each pci busUser can slide a card into each of these connectorsTypically Hard Disk Controller Cards

Each Provides several SCSI or SATA connection to hard drive Can end up with quite a few hard drives and large storage

capacityOr Network Adapater Cards

P

rovide several 100Mb/s ethernet connections, which go to aswitch or router Servers tend to read data from the hard drive into memory,

process the data with the CPUs, and then send it out to therequesting computer via the network (e.g., web server)

¶P64H2· is the code name for the Intel 82870P2

P64H2 die, may requirepassive heatsink



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Identifying parts on the board CPUs

there are two of them and they have really huge fansinks.NOTE: If the fansink doesn·t run, and the system is on, the heatsink will getVERY hot (burn skin) and system will eventually shut itself off.

Memorymemory consists of 8 wide connectors all in a row.

At least 2 DIMMs must be plugged in (¶populated·) for system to boot up. Thereare rules regarding what kind of dimms to use and which order to plug them intothe connectors.

MCHIt·s the chip between the cpus and the memoryProbably has a passive heatsink (a small heatsink w/ no fan)

ICH & P64H2·sHard to find, but it looks like the chip pictured in the above slideThere is one ICH and 2 P64H2·s (second one not always populated, i.e.sometimes it·s missing)

PCI SlotsLarger connectors on opposite side of board from DIMM connectors.One slot is from ICH and is slow speed legacy PCI bus (33MHz, 32-bit)The rest are high speed (66-133MHz, 64-bit ² i.e. 64 data bits wide)



12/4/2002

Interconnects on KC

¶the wires that connect thechips together·



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Front Side Bus (FSB) Function: CPUs talk to each other and to the MCH. This is how

the CPUs get data and code from memory, and communicatewith rest of the system.

Technology: Source synchronous533MBit/second/wire (266MHz signals)

This means each data wire on this bus can send 533 million bits of datain one second

64 data bits wideSo the whole bus can transfer 64*533 million bits of data per second

Topology: Multi-drop bus. CPU1 has to listen to when CPU0acceses memory because CPU1 may have that memory data in it·scache

¶Cache Coherency· Each cpu has a small superfast memory inside it

called the ¶cpu cache·. The cache holds recently accessed memorydata. If one cpu holds the data for a memory address that anothercpu needs, it has to let it know not to get that data from main memory.

Termination: Parallel termination at both ends of bus (MCH andCPU0)



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FSB Topology



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FSB Signal Groups Data Signal Group

HD[63:0]# ² 64 bits of dataDINV[3:0]# - dynamic inversionHDSTBP[3:0]# - P strobesHDSTBN[3:0]# - N strobes

Example, HDSTBP[0]# & HDSTBN[0]# are used to strobe in HD[0-16]# & DINV[0]#

E.g., two strobe signals are used to clock in a set of data bits, more on this

later Address Signal Group

Switches at ½ the rate of the FSB Data SignalsHAB[35:3]# - Address Bits. E.g., what memory address is beingrequestedHADSTB[1:0]# - Strobes for address signal group

HADSTB[0]# strobes A[16:3

]#, HADSTB[1]# strobes the rest Common Clock SignalsThere a whole lot of common clock signalsHCLKINP, HCLKINN ² Common clock for all signals in the ¶HostClock Domain·, i.e. all common clock signals, and outer loop timingsfor strobes (also called BCLK)



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FSB Timings ² 4X Source Synchronous

Timings not published for 533 MHz FSB,400 MHz timing diagrams shown



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FSB Timings ² 2X Source Synchronous

Timings not published for 533 MHz FSB,400 MHz timing diagrams shown



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DDR (Double Data Rate) Memory Bus Function: MCH reads and writes data from memory over this

high speed bus. Signaling Technology: Source Synchronous

266Mbit/sec/wire (133Mhz signals)A DDR bus is 64 data bits wideKC·s MCH uses 2 DDR busses in parallel, so it likes having a 128-bitwide bus

Bandwidth is 128*266 Million bits per secondTopology:Multi-Drop Bus.

Each of the two separate instances of this bus on this system go tofour (4) DIMM slots.

Each DIMM can have up to 2GBytes of memory, for a max total of 16GB.

Topology and Timings

The subject of the next class



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Memory speed and size within a system

Wh n w tudyign ling nd

timing , it will bcl r thov rh d nd

l t ncy th t m inm mory xhibit ,nd thu th n d

for loc l 1-

c ch .

rd riv



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HI (Hub Interface) Bus Function: Intel proprietary bus to provide flexible high speed

data transfer from MCH to various downstream components Signaling Technology: Source Synchronous

HI1: From MCH to ICH: 266Mbit/sec/wire (133Mhz signals)8 data bits wide, bandwidth = 8*266 Million bits per second

HI2: From MCH to P64H2·s: 533Mbit/sec/wire (266Mhz signals)16 data bits wide, bandwidth = 16*533 Million bits per second

Topology: Point to Point.Termination: There are parallel terminations at both ends of thebus



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Hub Interface Topology



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Hub Interface Signal Groups

Data BitsHI[15:0] ² Data Signals

PSTRB_[1:0], PSTRB_[1:0]# ² Strobe SignalsPSTRB_[0] & PSTRB_[0]# strobe in HI[0:7]

PSTRB_[1] & PSTRB_[1]# strobe in HI[15:8]

OtherHI[18:16] ² Command SignalsCommon Clock signals

GCLKIN66MHz common clock for HI[18:16] and outer loops of thePSTRB·s

Timings not published for Hub Interface



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PCI and PCI-X Function: Industry standard bus for plug-in peripherals

In servers, quite often plug-in hard drive adapters or networkadapters are connected to the pci bus Technology: Common Clock

PCI-X: From P64H2 ² 133Mbit/sec/wire, clocks are 133MHzsignals, data is 66MHz

64 data bits wide, bandwidth = 64*133 Million bits per secondPCI: From ICH ² 33Mbit/sec/sire, clocks are 33MHz, data is16MHz

32 data bits wide, bandwidth = 32*33 Million bits per secondThis speed and width are common in current desktop pc pci slots

Topology: Multi-Drop Bus.The bus consists of devices soldered down on the board and slots forplug-in devices. They all dangle off the PCI bus.

Termination:Series terminated inside the transmitting agent.This signaling technolgy depends on a doubling of the waveform at theend of the bus (due to open-circuit) in order to function.



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PCIX-133 2-slot Topology

x

xx



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PCI-X Signal Groups

Data and Address use same signals:AD[63:0]

Common Clocked

Control SignalsDEVSEL, TRDY, « a bunch more

Common Clocked Asynchronous Signals

REQ, GNT ² Arbitration signals

Interrupt Signals

ClocksPCLK[6:0] ² goes to every device that hangs off the pci busincluding the bridge itself



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PCI-X Data to Common Clock Timings

ns

ns



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PCI-X Common Clock



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Magic Decoder Ring Names for Signals given so far are from the device sheets

KC Board uses it·s own namesBoard·s have to name signals clearly and uniquely across the wholeboardDevices only have to name then uniquely across the device

Decoder Ring:FSB: HD[63:0]# FSB_HD63 _N

Rule is append FSB_ in front and replace ¶#· with ¶_N· in the devicesignal name

HI: HI[15:0] P64H2 _1_HI[15:0]Rule is append P64H2 _1_ before the device signal nameNote that the ¶1· in P64H2 _1_ may be a ¶1· or a ¶2· because KC has twoP64H2 devices

PCI-X: AD[63:0] P64H2 _1_ PB_AD[63:0]Rule is append P64H2 _1_ PB to beginning of device signal nameNote that the ¶1· in P64H2 _1_ PD.. Can be a ¶2· or ¶3· « depending onwhich pci bus the signal belongs too

DDR: Given Later

class2 20 board block diagram

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