circuits, systems, and signal processing volume 30 issue 4 2011 [doi 10.1007_s00034-011-9303-z] bo...

8/12/2019 Circuits, Systems, And Signal Processing Volume 30 Issue 4 2011 [Doi 10.1007_s00034-011-9303-z] Bo Shi; Michae

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Circuits Syst Signal Process (2011) 30:741753

DOI 10.1007/s00034-011-9303-z

C O G N I T I V E R A D I O - B A S E D W I R E L E S S C O M M U N I C A T I O N D E V I C E S

Design of a Noise-Canceling CMOS Wideband Receiver

Front-End with Inherent Active Balun

Bo Shi Michael Yan Wah Chia

Received: 31 December 2009 / Revised: 20 December 2010 / Published online: 6 May 2011

Springer Science+Business Media, LLC 2011

Abstract This paper presents the design of an ESD-protected noise-canceling

CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-

based wireless communications. Designed in a 0.13-m CMOS technology, the RF

front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-

conversion mixer. While having ESD and package parasitics absorbed into a wide-

band input matching network, the LNA exploits a combination of a common-gate

(CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage andto provide a well balanced differential output for driving the double-balance mixer,

which has a merged quadrature topology. A variable-gain method is developed for the

LNA to achieve a large factor of gain switch without degrading the input impedance

match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the

proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz

up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure

of 4.36.7 dB over the entire band.

KeywordsReceiver front-end

RF integrated circuit

Wideband receiver

Low-noise amplifier (LNA) Mixer Noise cancellation Active balun

1 Introduction

As a precious nature resource, there is fierce competition for the use of radio spec-

trum which is licensed by governments. However, actual measurements show that

B. Shi () M.Y.W. ChiaInstitute for Infocomm Research, A*STAR, 1 Fusionopolis Way, #21-01 Connexis, Singapore

138632, Singapore

e-mail:[email protected]

M.Y.W. Chia

e-mail: [email protected]
mailto:[email protected]:[email protected]:[email protected]:[email protected]


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742 Circuits Syst Signal Process (2011) 30:741753

most of the licensed spectrum is typically underutilized. To greatly improve spectral

efficiency, the Federal Communications Commission (FCC) recently proposed the le-

gal operation of unlicensed devices that can access a spectrum hole unoccupied by the

primary users. Cognitive Radio (CR), built on a Software Defined Radio (SDR) plat-

form, has emerged as an environment-aware intelligent wireless communication sys-tem to accomplish the coexistence mechanism [10]. There are two frequency bands

where the cognitive radios might operate: 400800 MHz (UHF TV bands) and 3

10 GHz, where the FCC has authorized unlicensed use of ultra-wideband (UWB)

devices and underlay networks [6]. The 310 GHz is of particular interest as this fre-

quency band has very low spectral utilization and might be opened for opportunistic

use in addition to UWB [10].

Ultra-wideband (UWB) is a radio technology for transmitting information spread

over a large portion of the radio spectrum (>500 MHz) at very low energy levels thatshould, in theory and under the right circumstances, be able to share spectrum with

other users [1]. This provides an efficient use of scarce radio bandwidth while en-

abling a high data rate personal-area network (PAN) wireless connectivity featuring

hundreds of megabits of data per second as well as longer-range, low data rate appli-

cations such as sensors, precision locating and tracking, radar and imaging systems.

Both CR and UWB radios may operate in the 310 GHz frequency band. In fact,

the concept of CR can be introduced to UWB communications to minimize harm-

ful interference and realize harmonic coexistence. Thus, a wideband RF front-end

covering 310 GHz is very much desired from both CR and UWB point of view.To increase integration level and reduce system cost, CMOS is the preferred tech-

nology for these implementations. It is, however, quite challenging for a CMOS de-

sign to cover the entire 310 GHz band at moderate power consumption [4,1113].

In this paper, we present the design of a 0.13-m CMOS noise-canceling wideband

receiver front-end that achieves a 3-dB gain bandwidth of around 10 GHz spanning

from 1.8 GHz up to 11.8 GHz. Comprising a wideband single-in-differential-out low-

noise amplifier (LNA) and a quadrature double-balanced down-conversion mixer, the

proposed design exploits noise cancellation in combination with inductive peakingtechniques to extend the circuit bandwidth and to lower the noise figure (NF) over the

entire frequency band. A variable-gain method is developed for the LNA to switch

between high-gain and low-gain mode when desired, without degrading the input

impedance match. To obtain a robust design, parasitic effects of the chip package and

electrostatic discharge (ESD) protection devices are modeled and embedded in the

RF front-end circuit. Together with a merged topology proposed for the quadrature

mixer driven by a differential voltage buffer, this RF front-end achieves a very wide

operating bandwidth with good gain and noise figure.

This paper is organized as follows: Sect.2starts by describing the architecture ofthe wideband receiver RF front-end. Then, the circuit design of the noise-canceling

wideband single-in-differential-out LNA and the merged quadrature mixer is dis-

cussed in detail. Section3 presents the results obtained from simulations, while the

conclusions are drawn in Sect.4.


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Circuits Syst Signal Process (2011) 30:741753 743

2 Architecture and Circuit Design

The proposed receiver front-end uses a direct-conversion architecture, which is suit-

able for a high level of integration to achieve a low-cost design. A block diagram

of the front-end architecture is shown in Fig. 1, comprising a wideband LNA and aquadrature mixer for down-conversion of the RF signal to zero-IF for further signal

processing.

The LNA has a single-ended input to avoid the need for an off-chip wideband

balun at the RF input, which adds both signal loss and cost. On the other hand, differ-

ential signaling in the receiver front-end is preferred in order to reduce second-order

distortion and to reject power supply and substrate noise. For this purpose, a double-

balanced topology is chosen for the down-conversion mixers. In order to drive the

fully differential mixers, a broadband active balun is naturally embedded in the LNA

design to provide the desired single-to-differential conversion. By avoiding the use of

a separate on-chip balun, this topology has the advantages in reducing overall noise

and dc power consumption. It further benefits from the noise canceling technique to

achieve a low NF for the overall design [2]. Below, the proposed circuit topology will

be discussed in detail, together with the principle of noise cancellation.

2.1 Single-In-Differential-Out Noise-Canceling LNA

The LNA needs to feature matched input impedance, flat broadband gain, good linear-

ity, and minimum possible NF over the entire UWB band, yet at relatively low power

consumption. Figure 2 shows the simplified schematic of the developed single-in-differential-out broadband LNA, which combines a common-gate (CG) device M1and a common-source (CS) deviceM2 to produce a pair of differential outputs from

a single RF input. Besides providing single-to-differential conversion, this circuit

topology is further exploited to cancel the channel thermal noise ofM1 [3]. Same as

for a simple common-gate based LNA a well defined impedance at the RF input port

for wideband matching is easily accomplished by setting 1/gm1 to the 50 source

impedance, wheregm1is the transconductance ofM1. However, it is well known that

such a design has relatively high NF since CG device M1 is fixed for the purpose of

impedance matching and thus cannot be optimized for low noise. To solve this in-herent problem, additional circuitry can be added to cancel the noise of the CG-stage

[3,9]. It is shown below that, by employing the CS-stage M2, the output noise con-

tribution from M1 can be fully canceled with properly designed circuit parameters.

Consequently, for the LNA design in Fig.2 the input match is effectively decoupled

from the NF so that it is now possible to optimize the overall NF independently.

Fig. 1 Block diagram of the

wideband receiver front-end


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Fig. 2 Circuit schematic of the single-in-differential-out noise-canceling LNA

To analyze the principle of single-to-differential conversion and noise cancella-

tion as well as to derive the conditions for simultaneous balancing and noise cancel-

ing, a simplified low-frequency AC equivalent circuit of the LNA is drawn in Fig.3.

A current sourceIn,M1models the channel thermal noise of the MOSFET M1, which

is assumed to be the dominating noise source. A portion of the noise current In,M1flows into the source impedance RSbut out ofM1s load impedance RL1, creating

two fully correlated noise voltages at the source and drain terminals ofM1, i.e. node

A and node B, with opposite phases. In contrast, the signal voltages at these two

nodes are in phase. The voltage at nodeA is further amplified by the common-source

device M2 to produce a voltage in opposite phase at its drain terminal, i.e. node C.

Thus, at nodeB and C the noise voltage is in common-mode, while the signal voltage

is in differential-mode. With properly designed circuit parameters, the subtraction of

these two node voltages results in that the noise contributed by M1 is canceled while

the signal voltages are added constructively. The condition for complete noise can-

cellation is derived as

Vn,B Vn,C =In,M1

1 + gm1RSRL1

In,M1

1 + gm1RSRSgm2RL2 = 0

RL1 = RSgm2RL2 (1)

where gm2 is transconductance of the CS device M2. Further, the signal voltages at

nodeB andC are derived as

vs,B =gm1RL1

1 + gm1RSvs; vs,C =

gm2RL2

1 + gm1RSvs (2)


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Fig. 3 Noise canceling

principle

Taking the noise canceling condition ofRL1 = RSgm2RL2 and the input impedance

matching condition of RS= 1/gm1 into (2), it can be shown that the signal volt-

age gain of the CG- and CS-stage are both equal to RL1/(2RS), but have opposite

sign. Thus, balancing of the balun and cancellation of the noise are simultaneously

achieved.

Under conditions for noise canceling and input impedance matching, the total

noise factorFat low frequencies is approximated as

F= 1 +RS

RL1+

1

g2m2RSRL2+

1

gm2RS(3)

Note that in the above derivation only the channel thermal noise is taken into account,

which has a power spectral density of 4K T gm with being a noise parameter.The last three terms in (3) are the noise factors contributed by RL1, RL2, and M2,

respectively.

Equation (3) provides the design insights for sizing circuit parameters. By apply-

ing the noise canceling technique, the noise of the input matching device in the design

has no contribution to the final noise factor. Thus, the overall NF is fully decoupled

with the input matching condition. The NF is now dominated byRL1, RL2, andM2.

It is shown in[2] that using identical CG and CS devices with equal load and bias

cannot bring the desired low-noise benefit of noise cancellation although the noise of

the CG-transistor is fully canceled and the output signal is perfectly balanced. This isbecause the noise generated by the CS-stage is significant due to its low transconduc-

tance,gm2. To reduce the NF, gm2 need to be maximized under the constraint of dc

power consumption. Whilegm2 is chosen to be n times bigger than gm1, the load re-

sistorRL2 need to ben times smaller thanRL1 in order to maintain output balancing

and noise canceling. As long asgm2 is sufficient large,RL2will not affect the overall

NF much even it has a relatively small value. However, RL1 does have a major im-

pact on the NF and, to reduce its noise contribution, a large value with respect to RSshould be used. On the other hand, bandwidth demand limits the maximum resistor

value. This limitation is somewhat relaxed by introducing shunt peaking through in-

ductors L3 and L4 as well as driving the mixer through a differential voltage buffer

discussed below, which extend the circuit bandwidth effectively.

When a strong level of received signal is detected, the LNA need to be switched

to low-gain mode in order to avoid excessive nonlinearity caused by overdriving the

mixer and subsequent stages. Since the LNA also functions as a broadband active


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balun, one additional challenging demand for the gain-control technique here is to

maintain the performance of the single-to-differential conversion while the LNA gain

is largely varied. Current-splitting [8] and resistor-chain [7] are the widely used gain-

control techniques. The resistor-chain variable-gain technique obtains gain control by

steering the signal current through a resistive load having more or less resistance. It is,however, not well suited to the inductive shunt-peaking load network structure used in

this design. As shown in Fig.2, the load network combines a resistor and an inductor

in series connection to achieve the desired impedance characteristics with frequency

and thus to obtain the flat broadband gain. Consequently, the change of only resistive

load to switch gain may largely affect the circuit bandwidth and the gain flatness. The

gain-control technique used here is developed from the conventional current-splitting

scheme and is somewhat similar to the solution in [5].

Referring to the LNA circuit in Fig. 2, gain reduction is obtained by using addi-

tional cascode devicesM4 andM6 to steer part of the signal current produced byM1andM2 to the supply instead of the load impedances so that they will not contribute

to the output. This is same as the conventional current-splitting technique. However,

as we will see in the next section, it is found that a large factor of gain switch disturbs

the input matching and the balun performance significantly. One factor responsible

for the effects is due to that the impedance loading of the amplifying devices M1and

M2 are largely changed when cascode devices M4 and M6 are switched on to pro-

vide gain reduction. For the CG-transistorM1, by taking into account its drain-source

conductance,gds1, the input impedance at the source node is derived as

zin =1 + gds1ZL1

gm1 + gds1. (4)

If the transistor has an infinite drain-source resistance, i.e. gds1 is zero, we have

zin = 1/gm1. However, in reality the drain-source resistance of a nanometer CMOS

transistor is rather low and consequently the inductive loading impedance, ZL1, will

have an impact on the input impedance as shown by (4). Thus, the input matching of

the circuit will be affected by any variation ofZL1. Similarly, we can derive equa-

tions for the signal voltages at drain nodes of CG-transistorM1and CS-transistorM2

related to the input voltage,vi :

vd1 =gm1 + gds1

1 + gds1ZL1ZL1vi; vd2 =

gm2

1 + gds2ZL2ZL2vi (5)

Besides the direct effect of loading impedance ZL, with finite drain-source resistance

the gdsZL term in (5) will also have some effect on the amplitude and phase ofvd1and vd2. In this case, the amplitude and phase change ofvd1 and vd2 caused by the

variation ofZL1andZL2 are not exact same due to unequal nature of the device size,

bias, and inductive loading impedance used forM1and M2. Consequently, amplitude

and phase balance of the balun are affected.

To solve the problem, the cascode transistors M3 andM5 are split into two parts,

i.e. M3a and M3b as well as M5a and M5b , which at high-gain mode are all turned

on to steer the entire signal currents to the load impedances to produce the output

voltage. At low-gain mode, M3b and M5b are switched off while M4 and M6 are


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Fig. 4 Amplitude and phase difference ofM1s loading impedance between high-gain mode and low-gain

mode

turned on. Since the sizes of M4 and M6 are designed to be the same as that of

M3b andM5b, respectively, the portion of signal currents original carried byM3b and

M5b are now steered byM4 andM6 away from reaching the load and dumped to the

supply through dummy resistors R3 and R4 so that the gain is effectively reduced.

Thus, the size ratios ofM3a to M3b and M5a to M5b will determine the amount ofgain reduction. Further, their ratios are designed to be the same so that the condi-

tion for both balun balancing and noise canceling is still kept at the low-gain mode.

In this way, the loading impedance and the circuit operating condition for M1 and

M2 is effectively maintained when switched from high-gain mode to low-gain mode.

This is confirmed by the simulation results presented in Fig. 4for both the conven-

tional current-splitting and the developed scheme, where the loading impedance vari-

ation for the CG-transistor M1 caused by a 12 dB gain switching is characterized by

their magnitude and phase differences between high-gain mode and low-gain mode.

Note that the circuit topology used in all the simulations for the conventional current-

splitting scheme differs from the circuit shown in Fig. 2in: (1) the current steering

transistorsM4 and M6 are directly connected to the supply without using the dummy

resistorsR3 and R4; (2) both M3 and M5 function as a single transistor by keeping

M3b and M5b always on with the same gate bias as M3a and M5a ; (3) the width of

current steering transistors M4 and M6 are increased accordingly so that they pro-

vide the same amount of gain reduction. In Fig. 4, the dash dot lines plot the results

for the developed circuit while the solid lines give the results for the conventional

current-splitting circuit. The amplitude and phase variation of the loading impedance

for the developed circuit shown in Fig. 2are within around 1.5 dB and 1 over the

310 GHz band. In contrast, for the conventional current-splitting circuit the loading

impedance changed close to 10 dB in amplitude and between 3 to more than 10 in

phase. With much smaller impedance change by using the proposed gain-switching

method, it is expected that the input matching and the wideband balun function will

not be significantly disturbed by the large factor of gain switch. Furthermore, it also


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results in a better NF and wider bandwidth since by switching off part ofM3 andM5relatively smaller device sizes are now needed for M4 and M6 to provide the same

amount of gain reduction, leading to reduced parasitic capacitances. In Sect.3, simu-

lation results are presented to compare the performance of this gain-control technique

with the conventional current-splitting technique in terms of their effects on the in-put matching as well as amplitude and phase imbalance of the single-to-differential

conversion.

Electrostatic discharge (ESD) at I/O pins can cause damage to the RF front-end

chip. To divert the discharge current away from the main circuitry, a double-diode

ESD protection circuit is placed at the RF input port as shown in Fig.2. The diodes

are sized to provide 2-kV ESD protection on Human Body Model (HBM). The major

concern regarding the ESD diodes is their parasitic shunt capacitances added to the

signal path. Together with the bondpad capacitance, they are accounted as Cpad+ESD

in Fig.2, with an estimated value of around 290 fF. Such large a shunt capacitancewill degrade the input match at the upper UWB band and, thus, must be taken into

consideration in the design. Further, package parasitics especially the bond wire in-

ductanceLbw also need to be accounted. To maintain good input matching over the

entire UWB band, they are absorbed into the wideband LC matching network de-

signed along with an on-chip spiral inductor L1 and an off-chip capacitor Cin .

2.2 Merged Double-Balanced Quadrature Mixer

Doubled-balanced mixers are used in the design for their superior performance of-fered by the fully differential circuit topology. The mixer schematic is shown in

Fig.5, which is based on a merged quadrature topology. A single common-source

transconductor pair ofM3 and M4 perform voltage-to-current conversion of the RF

input signal and inject the differential RF signal current into two double-balanced

quadrature commutating quads, which are switched by the LO voltage to produce

frequency conversion. The parasitic capacitances, Cpar, loading the quadrature quad

source nodes limit the communication bandwidth. The inductors L2 and L3 tunes

out these parasitic capacitances, with benefits to conversion gain, noise, and linearity.

When compared to the conventional solution adopting two separate transconductor

pairs, this merged topology allows a higher switching quad current gain. Further, for

the same transconductance gain the parasitic capacitance loading the LNA is mini-

mized. Another advantage is that this design only uses two parasitic tuning inductors

instead of four inductors in the conventional design, resulting a reduced chip size.

In the original form of this type of mixers, there is a trade-off between linearity and

noise performance. Clearly, for the transconductance circuit to achieve high linearity

a large gate-source overdrive voltage is required for M3 and M4, leading to a large

DC biasing current. On the other hand, a fairly low current is required for the LO

switching quad to realize better noise performance. To break this trade-off, current

bleeding technique is employed in the design by adding two DC current sources at the

common-source nodes of the LO switching pairs to supply part of the biasing current

for the transconductance circuit. In this way, the DC current flowing through the LO

switching pairs is reduced and, therefore, a lower NF can be achieved. At the same

time, the linearity is not degraded since the biasing current of the transconductance


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Fig. 5 Double-balanced mixer with a merged quadrature topology

circuit need not to be lowered. Furthermore, with this approach the load resistance of

the mixer can be increased to obtain a higher conversion gain.

The quadrature mixer is driven by a differential source follower composed by

transistorsM1 and M2 as well as a center tapped spiral inductor L1, which buffers

the LNA outputs to reduce the loading parasitic capacitances and thus to increase the

circuit bandwidth. Further, the high-pass effect produced by the voltage buffer also

largely filter out the low-frequency second-order distortion generated by the LNA.

3 Simulation Results

The proposed wideband receiver front-end design is implemented in a 0.13-m

CMOS technology. The layout of the chip is shown in Fig. 6. Total die area including

pads is 2.4 mm2 where the active area occupies less than 1 mm2. All I/O pads are de-

signed with ESD protection circuits. Multiple pads are given to the chip ground and

supply pins to minimize parasitic inductance of bonding wires. Large MIM capacitors

are used to provide on-chip decoupling of the supply line. As is discussed in Sect. 2,

the bond wire inductance and the parasitic capacitances at the RF input pin are taken

care in the wideband input matching circuit design. To accurately control and model

parasitic effects, on-chip transmission lines are used for all long interconnections in

the RF path.

For this implementation the gate width ratio ofM3a to M3b and M5a to M5b in

Fig. 2 is designed to be 1:3, providing a LNA gain switch of around 12 dB. The

receiver front-end chip is powered by a 1.5 V supply with a simulated dc current

consumption of 24 mA. Below the RF performance of the chip are presented. For the

high-gain mode results obtained from both schematic and post-layout simulations are

plotted to show the parasitic effects introduced by the chip layout. Since the effects


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Fig. 6 Chip layout

Fig. 7 Input return loss versus frequency

are quite similar, for the low-gain mode only results from schematic simulations are

plotted for the sake of clarity of the figures.

Figure7characterizes the input impedance matching by plotting the simulated S11under both high-gain and low-gain mode. In the figure, the solid line and the dot line

show the input return loss at high-gain mode from schematic and post-layout simula-

tions, respectively. The input in both cases is well matched with a return loss below

10 dB from 1.611 GHz, covering the entire UWB band. At low-gain mode the

result from schematic simulation is plotted by the dash dot line in Fig. 7. As shown,


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Fig. 8 Voltage conversion gain and noise figure versus frequency

while the frequency band for an input return loss of below 10 dB stays roughly

the same, S11 at low-gain mode deviates somewhat from that at high-gain mode.

Nevertheless, it does confirm that with the developed variable-gain method a well

matched input can be maintained for a large factor of gain switch. For comparison,

for the same factor of 12 dB gain reduction the input return loss with the conventional

current-splitting scheme is shown by the dot line in Fig. 7. It is noticed thatS11in this

case is much more affected by the change of gain with the input matching bandwidth

somewhat reduced.

Figure8plots the overall voltage conversion gain and double-sideband (DSB) NF

of the RF front-end versus frequency under both high-gain and low-gain mode. The

solid lines are results from schematic simulations. Over the entire 310 GHz UWB

band, this design at high-gain mode achieves a voltage gain of 28.330 dB and a

NF of 4.35.6 dB, respectively. The voltage gain response is fairly flat with a gain

variation of only 1.7 dB. The 3-dB voltage gain bandwidth covers around 10 GHz

spanning from 1.8 GHz up to 11.8 GHz with a NF of 4.36.7 dB. At low-gain mode

the voltage conversion gain is 16.819 dB and the NF is 1213.1 dB. The amount

of gain switch obtained is just a bit smaller than the calculated value of 12 dB. At

high-gain mode the results from post-layout simulations are also plotted in Fig. 8

using dot line. Both conversion gain and NF are closely matched to the schematic

simulations up to around 9 GHz. Above that, the performance starts to degrade with

the conversion gain reduced by around 1.5 dB and the NF increased by around 0.7 dB

at 12 GHz.

For in-band third-order nonlinearity characterization, a two-tone test under high-

gain mode was simulated at 3.4 GHz with tone spacing of 20 MHz. The results ob-

tained from schematic and post-layout simulations are about same. Figure9shows

the obtained output levels of the fundamental tone and the third-order intermodula-

tion product with the input power level swept. An input third-order intercept (IIP3)

of around 11 dBm is extrapolated, while an input 1-dB compression point (ICP-


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Fig. 9 Two-tone test for extrapolation of IIP3 at high-gain mode

Fig. 10 Amplitude and differential phase error of the inherent active balun

1 dB) is observed near 20.5 dBm. When switched to low-gain mode, the IIP3 and

ICP-1dB are increased to 1.5 dBm and 10 dBm.

The performance of the inherent active balun is characterized by its amplitude

and differential phase imbalance. Plotted in Fig. 10, the solid lines and the dot lines

show the simulated imbalances of this design at high-gain and low-gain mode, re-

spectively. At high-gain mode over 112 GHz band the amplitude imbalance is less

than 0.35 dB and the phase imbalance is less than 5. For the 310 GHz UWB band,

the differential phase error is improved to better than 1, which indicates a good

single-to-differential conversion. Expected from the discussion in Sect.2, the balun

performance is affected when the LNA is switched to low-gain mode. With the devel-

oped gain-switching technique, however, over the UWB band a very good single-to-


13/13


differential conversion is still achieved at low-gain mode with amplitude and phase

error comparable to the high-gain mode as is indicated by the dot lines in Fig.10. To

compare, the performance results with the conventional current-splitting technique

are also plotted in Fig. 10using dash dot lines. It is observed that in that case the

large factor of gain-switching severely degrades the amplitude and phase error toaround 0.9 dB and 3 at higher UWB band.

4 Conclusions

The design of an ESD-protected noise-canceling CMOS wideband receiver front-end

for applications in UWB radios and cognitive radio-based wireless communication

has been presented. A single-in-differential-out wideband LNA with gain control that

can achieve simultaneous noise canceling and balun balancing is designed to providedirect interface to the double-balanced mixer, which has a merged quadrature topol-

ogy. The variable-gain method developed for the LNA achieve a large factor of gain

switch without degrading the wideband input impedance match and the balun func-

tion. For a robust design, package and ESD parasitics are taken care in the design

and embedded into the wideband input matching network. With relatively a moder-

ate power consumption, the proposed RF front-end achieves a simulated maximum

voltage conversion gain of 30 dB and a simulated noise figure of 4.36.7 dB over the

3-dB gain frequency band of 1.811.8 GHz, combined with good linearity.

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