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Circuits for Time and Frequency Domain
Characterization of Jitter
by
Antonio Chan, B. Eng. 1999
Department of Electrical Engineering
McGill University, Montréal
July 2002
A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfilment of
the requirements for the degree of Master of Engineering
© Antonio Chan, 2002
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Circuits for Time and Fregeuency Domain Characterization of Jitter
Abstract
Antonio Chan
Jitter characterization has become significantly more important for systems
running at multi-gigahertz data rates. Time and frequency domain characterization of jitter
is thus a crucial element for system specification testing. Time domain jitter measurement
on a data signal with sub-gate timing resolution can be achieved using two delay chains
feeding into the dock and data lines of a series of D-Iatches known as a Vernier Delay
Line (VDL). An important drawback to the VDL structure is that its measurement
accuracy depends on the matching of the various delay elements. Although carefullayout
techniques can help to minimize these mismatches, it cannot eliminate them completely.
As well, due to the nature of the design, a relatively large silicon area is required for
silicon implementation. In this work, a novel technique is developed which reduces the
silicon area requirements by two orders of magnitude, as well enables the measurement
device to be synthesized from a register transfer level (RTL) description. A custom IC was
designed and fabricated in a 0.18 Ilm CMOS process as a first proof of concept. The
design requires a silicon area of 0.12 mm2 and measured results indicate a timing
resolution of 19 ps. The synthesizable nature of the design is demonstrated using a FPGA
implementation. In addition, another custom IC was designed and fabricated in a 0.35 I-tm
CMOS process as a frequency characterization circuit to process and extract information
from the data obtained from the VDL. This design occupies a silicon area of 1.83 mm2. As
test time is an important consideration for a production test, an extension to this
component-invariant VDL technique is provided that reduces test time at the expense of
ii
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
more hardware. Finally, a method for obtaining the frequency domain characteristics of
the jitter using the VDL will also be given.
iii
Circuits for Time and Fregeuency Domain Characterization of Jitter
Résumé
Antonio Chan
La caractérisation du phénomène de jitter est devenue de plus en plus importante
pour des systèmes électroniques à des vitesses de plusieurs Gigahertz. La caractérisation
en temps et en fréquence du jitter est donc un élement critique pour le test et l'évaluation
des systèmes. La mesure du jitter en temps avec une résolution inférieure au délai d'une
porte logique peut être accomplie grâce à deux chaînes de délai qui alimentent les entrées
'horloge' et 'donnée' d'une série de bascules D. Le tout est connu comme la Ligne de
Délai Vernier (LDV). Un inconvénient de la structure LDV est que sa précision dépend du
matching des élements de délai, c'est-à-dire du niveau auquel ces élements sont
identiques. Bien que ces différences peuvent être minimisées avec un layout aussi précis
que possible, elles ne peuvent pas être complètement éliminées. De plus, l'espace de
silicon éxigé pour le layout de ces élements de délai est en géneral relativement grand.
Cette thèse propose une nouvelle technique qui réduit le volume de silicon nécessaire par
deux ordres de grandeur, et permet de synthétiser le circuit à partir de d'une description
Register Transfer Level (RTL). Pour démontrer le concept, un circuit integré (CI) a été
conçu et fabriqué dans une technologie de CMOS 0.18 f.lm. Le prototype occupe une
surface de 0.12 mm2 et les résultats de l'expérience montrent une résolution en temps de
19 ps. Le fait que le circuit peut être synthetisé est démontré par une réalisation FPGA.
De plus, un autre CI a été conçu et fabriqué dans une technologie CMOS 0.35 f.lm. Celle
ci permet la caractérisation en fréquence des données obtenues à partir de la LDV. Ce
deuxième CI occupe une surface de 1.83 mm2. Comme le temps éxigé par des tests de
production est une considération importante, une extension à cette architecture LDV est
iv
Circuits for Time and Freqeuency Domain Characterization of Jitter Antonio Chan
présentée afin de réduire le temps de test au prix d'une augmentation de la surface du
silicon. Enfin, une méthode est présentée pour obtenir les caractéristiques frequentielles
du jitter en utilisant le LDY.
v
Circuits for Time and Fregeuency Domain Characterization of Jitter
Acknowledgments
Antonio Chan
It has been a long process and sometimes tedious and frustrated but mostly fun,
exciting and rewarding. 1 can say it is not strict forward to come to this point. Without the
support from various people and groups, it could have been much harder. Therefore, 1
would like to acknowledge them for their support during this process.
First, 1 would like to acknowledge the following organizations for their support of
this research: Natural Sciences and Engineering Research Council of Canada, the Cana
dian Microelectronics Corporation and Micronet, a Canadian network of centers of excel
lence dealing with microelectronics devices, circuits, and systems.
1 would also like to thank my supervisor Professor Gordon Roberts for his patient
guidance both technically and personally throughout my degree. His enthusiasm and dedi
cation in research is what brings the fun and exciting part of research.
1would like to thank the MACS group and the ECE system administrators for their
support in the various aspect of research as well as their presence to make this a very fun
group. In particular, 1 would like to acknowledge Bardia for his he1p in the French transla
tion of my abstract.
Finally, 1 would like to thank my family for their personal and emotional support
throughout the process. Without their support, things would have messed up midway
through. The final important person that 1 would like to thank is someone who has been
very patient with me for the past years. 1 would not have come to this point without her
beside me. My special dedication to AAA •
vi
Circuits for Time and Fregeuency Domain Characterization of Jitter
Table of Contents
Antonio Chan
1.1 - Motivation 1
1.2 - Thesis Outline 4
2.1 - Introduction 5
2.2 - Jitter Statistics and Characterization 52.3 - Unit Gate Delay Resolution 82.4 - Sub-Gate Delay Resolution Circuit 10
2.5 - Drawbacks 122.6 - Surnmary 14
3.1 - Introduction 15
3.2 - A Component-Invariant VDL Structure 15
3.3 - Circuit Implementation 18
3.3.1 _ Edge Detector 18
3.3.2 - Triggered Ring Oscillator Circuits 19
3.3.3 - Phase Detector 20
3.3.4 - Complete Circuit 21
3.4 - Calibration And Measurement Processes 223.5 - Test Time Comparison 26
3.6 - Reducing Test Time Using A Spatial Arrangement of Component-InvariantVDLs 27
3.7 - Experimental Results 31
3.7.1 - CMOS Implementation ofA Component-Invariant VDL .31
3.7.2 - Calibration for systematic error .443.7.3 - A Three-Oscillator Component-Invariant VDL in a FPGA 49
3.8 - Limiting Factors 543.8.1 - Metastability in the D-Latches 54
3.8.2 - Resolution limited by noise 553.8.3 - Noise free clock 56
3.9 - Surnmary 56
vii
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
4.1 - Introduction 574.2 - Frequency Characterization Method 574.3 - Experimental Result Using VDL Circuit.. 594.4 - Exploiting Hardware Requirement.. 61
4.4.1 - Discrete Fourier Transform Algorithm 61
4.4.2 - Circuit Implementation 62
4.4.3 - Experimental Resultfrom DFT IC 66
4.5 - Limiting Factors 694.5.1 - Effective Sampling Rate 694.5.2 - Silicon Sizing 70
4.6 - Summary 705.1 - Conclusion 715.2 - Future Works 72
viii
Circuits for Time and Fregeuency Domain Characterization of Jitter
List of Figures
Antonio Chan
Figure 1.1 SoC Example 2
Figure 1.2 SoC with TMU 2
Figure 1.3 TMU Architecture 3
Figure 2.1 Sampling instances of signal.. 6Figure 2.2 Jitter CDF and PDF 7Figure 2.3 VDL with unit gate resolution implementation 9
Figure 2.4 VDL with sub-gate timing resolution 11
Figure 2.5 VDL in 0.35mm CMOS technology 13Figure 2.6 VDL with mismatched elements 14
Figure 3.1 Obtaining a timing measurement directly from a VDL 16
Figure 3.2 Replacing VDL by a component-invariant VDL structure 17
Figure 3.3 Edge detector 18Figure 3.4 Triggered ring oscillator 19Figure 3.5 Voltage-controlled delay circuit 20
Figure 3.6 Phase detector 21Figure 3.7 The circuit implementation of the component invariant VDL structure 22
Figure 3.8 Timing diagram for the calibration and measurement modes of operation23
Figure 3.9 An array of component-invariant VDLs 29
Figure 3.10 Timing relationship for VDL array 30
Figure 3.11 Controller for VDL array structure 30
Figure 3.12 A chip monograph of component-invariant VDL implemented in a 0.181lmCMOS process 32
Figure 3.13 Experimental setup 33
Figure 3.14 Teradyne Tester 34Figure 3.15 Four-layer PCB 35
Figure 3.16 Phase measurement of VDL set to the 54.5 ps timing resolution 36Figure 3.17 Histograms for Gaussian distributed jitter for 54.5 ps
timing resolution 37
ix
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Figure 3.18 Histograms for sinusoidal distributed jitter for 54.5 pstiming resolutionfrom 40
Figure 3.19 Phase measurement ofthe VDL set to a 18.9 ps timing resolution .41
Figure 3.20 Histograms for Gaussian distributed jitter for 18.9 pstiming resolution 42
Figure 3.21 Histograms for sinusoidal distributed jitter for 18.9 pstiming resolution 43
Figure 3.22 Mean Value 45
Figure 3.23 RMS measurement before calibration .45
Figure 3.24 RMS measurement after calibration .46
Figure 3.25 Difference in RMS measurement before calibration .46
Figure 3.26 Difference in RMS measurement after calibration 47
Figure 3.27 Peak to Peak measurement before calibration .47
Figure 3.28 Peak to Peak measurement before calibration .48
Figure 3.29 Difference in Peak to Peak measurement before calibration .48
Figure 3.30 Difference in Peak to Peak measurement after calibration .49
Figure 3.31 Altera FPGA Board 50
Figure 3.32 Test setup 51
Figure 3.33 Histograms for 0.566 ns VDL 52
Figure 3.34 Histograms for 1.22 ns VDL 53
Figure 3.35 Delay versus power supply 56
Figure 4.1 Phase modulation by noise 58
Figure 4.2 Effect of various sampling rates 59
Figure 4.3 A comparison of the frequency spectrum of a sinusoidal distributed jitterbefore and after the VDL 60
Figure 4.4 Main Blocks 62
Figure 4.5 RAM Block 63
Figure 4.6 Mult/Add Block 64
Figure 4.7 FFf Chip Micrograph 66
Figure 4.8 DPI algorithm from MATLAB 68
Figure 4.9 DPI algorithm from chip 68
x
Circuits for Time and Fregeuency Domain Characterization of Jitter
Chapter 1 - Introduction
1.1 - Motivation
Antonio Chan
Timing accuracy is one of the required criteria for high-speed data communication
System-on-Chip (SoC) which operates at gigahertz data rate. However, signal integrity is
often degraded due to noise coming from the system itself and other external sources.
These noise corruptions introduce reliability uncertainty to the timing accuracy which is
often referred to as timing jitter. As such, certain measures of jitter are to be used to
characterize the system to ensure performance reliability. Although sorne existing
instrumentation provides such characterization, an on-chip measurement technique is
often preferred due to reduction in signal path from Device Under Test (DUT) to the
measurement device which provides more accurate measurement. Moreover, an on-chip
measurement technique often has advantage over external instrumentation due to the
inherit accessibility limitation to the DUT which is often an integrated part of the Soc.
This is very common in the case of jitter characterization of Phase Locked Loops (PLLs)
within an SoC as shown in Figure 1.1. In order to characterize the PLL within each
Intellectual Property (IP) block of the SoC, an integrated test approach is required as
shown in Figure 1.2. Here a timing measurement unit (TMU) consisting of a jitter
excitation circuit (JEe), a jitter analyzing circuit (JAC) and a synchronization circuit (SC)
as shown in Figure 1.3 is added to each IP block to provide testability for the DUT or PLL
in this case. The research focus for this thesis is on the design of the JAC.
Introduction
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
IP Core IP Core IP Core
,-----_..: ADC :1 1.._-----~
j------.: DAC!1 1..------~
i---------ï1 11 11 11 1
: Memory :1 11 11 11 1L J
ï----------,1 11 11 11 1
: Memory :1 11 11 11 1L J
,-------,: IIP 11 r :.._-----~
.-------.: DAC:1 1..------~
j---------ï1 11 11 11 1
1 Memory :1 11 11 11 1L J
-------,1 1
: IlP 1l J
I-------~
: ADC :1 1..------~
,-------.1 IIP 11 r- :.._-----~
j------.1 11 IlP 1L J
i---------j1 11 11 11 1
: Memory :1 11 11 11 1L J
j---------j1 11 11 11 1
: Memory 11 11 11 11 1L -'
IP Core
IP Core
IP Core
Figure 1.1 SoC Example
IP Core
IP Core
IP Core
-j------.11 ADC:1 1.._-----~
-,-------:: DAC:1 1.._-----~
i----------,1 11 11 11 1
1 Memory :1 11 11 11 1L -'
i---------j1 11 11 11 1
: Memory :1 11 11 11 1L J
-,-------,: IlP 1l J
-,-------.: DAC:1 1.._-----~
j----------,1 11 11 11 1
: Memory :1 11 11 11 1L -'
·-------i: ADC 11 1.._-----~
-,-------.1 IlP :1 1.._-----~
-,-------,: IlP :1 1L •
i---------ï1 11 11 11 1
1 Memory :1 11 11 11 1L -'
i----------,1 11 11 11 1
: Memory :1 11 11 11 1L -'
IP Core
Introduction
IP Core
Figure 1.2 SoC with TMU
IP Core
2
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Jitter Excitation DUT ~ Jitter Analysis
Il
Synchronization
Figure 1.3 TMU Architecture
It should be noted that the lAC has to fulfi1 sorne important criteria:
(1) Since the DUT runs at high speed, the amount of jitter that the DUT can tolerate has to
be small. In order to provide accurate measurement, timing resolution of the lAC is one of
the key requirements. For gigabit data rate, the required timing resolution will be in the
order of picoseconds.
(2) The lAC has to occupy a relatively small area of silicon since it is designed to be
inserted in each IP block of the Soc.
(3) Since minimizing test time is an important requirement for cost-effective design, the
lAC has to provide the shortest possible test time.
(4) Due to scalability and tum-over rate of digital circuits, the design should be
synthesizable.
In recent years, researchers have devised various schemes in which to perform on
chip timing measurements. Time-to-Digital Converter (TDC) using a Delay Locked Loop
(DLL) [1], Vernier Delay Line (VDL) [2] and multiple phase ring oscillator [3] [4] are
methods used to provide high-resolution on-chip timing measurements. For jitter
measurement in particular, an on-chip circuit consisting of a ring oscillator and a
calibration circuit was reported to be able to perform jitter measurements with a resolution
as low as a single gate delay [5]. Moreover, the circuit was fully synthesizable from an
Introduction 3
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
RTL description, as the design does not depend on matched elements. In fact, due to the
scalability of digital circuits and turn-over rate of synthesizable circuits, the design in [5]
is more preferable. A significant improvement to sub-gate resolution [6] jitter
measurement device was also reported using a VDL. In this case, the timing resolution
was derived from the difference of two gate de1ays. Unfortunately, the design depends
largely on the matching of pairs of delay elements [7] and due to the nature of the design,
it occupies relatively large silicon area. In order to remove the dependency on element
matching while maintaining synthesizability, a component-invariant VDL structure based
on a single-stage VDL is proposed in this research in arder to tackle the design
requirements described previously.
1.2 - Thesis Outline
A description of the thesis is as follows. In Chapter 2, we shall describe the
fundamentals of jitter statistics and the motivation from conceptual design to sorne
existing designs and the evolvement from existing design to this novel design. In Chapter
3, we shall describe the theory of operation of the component-invariant VDL, the circuit
details used to perform RMS and Peak-to-Peak jitter measurement as well as sorne
experimental results obtain from an FPGA and IC implementations. In Chapter 4, we shall
describe the technique for frequency characterization of jitter using additional circuit as
well as sorne experimental result from this le. Finally, we conc1ude the thesis in Chapter
5.
Introduction 4
Circuits for Time and Fregeuency Domain Characterization of Jitter
Chapter 2 - Background
2.1 - Introduction
Antonio Chan
The principles of a basic jitter measurement are described in this chapter. This
includes various statistical concepts applied to jitter, as well as a practical method for
characterizing jitter. Various circuits used to measure jitter will be described, highlighting
their advantages as weH as their disadvantages.
2.2 - Jitter Statistics and Characterization
To illustrate the basic principle of a jitter measurement, consider uniformly
sampling a noiseless clock signal with, say for sake of explanation, 16 points per period.
Next, stack consecutive periods of this sampled clock signal one above the other as shown
in Figure 2.1(a), taking care to line up each sampling point relative to the start of each
clock cycle. As expected for a noiseless clock signal, in aH three cases shown, the
transition from logicallow to logical high occurs at the same point, somewhere between
sampling instances 8 and 9. However, if the clock signal is jittery, as shown in Figure
2.1 (b), the rising edge of the dock signal will vary over the period of the dock.
Statistically, we can characterize this variation by computing the Cumulative Density
Function (CDF) of the jittery clock signal. This is simply done by counting the number of
times the clock signal is logically high at each sampling instance. For the 3-period
example given in Figure 2.1(b), at the first sampling instance the count is O. The count
Background 5
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
remains at 0 for the next three sampling instances then increases to 1 at the 6th sampling
instance, remains at 1 until the 9th sampling instance where it increases to 2. The count
remains at 2 until the llth sampling instance and then increases to 3 at the 12th sampling
instance. The count remains at 3 for the remaining four sampling instances. Although the
granularity of this particular example is rather course, a smoother positive-increasing
monotonie function would result if a larger number of dock periods are used in the
calculation.
FirstClockEdge
No UncertaintyLogical '1' , , , , ,,""""
• 1 1 l ,oh.1 1 1 l ":.•1 1 1 1 • 1 1 • ",,-, 1 1 • 1 1 1 1
• ,,' 1 1 l , 1 • .,~~;,' 1 1 1 1 • , 1Loglcal 0 ••••••••;} , , , , , , ,
Logical '1' , , , , , , , ,::""", , S d, , , , , , , ,", , , , , , " econ, , , , , , , '" , , , , , , , Clock1 1 1 1 • 1 l ':';:;::1 1 1 1 1 1 1 1
L . 1'0' , , , , , , , ".'." , , , , , " Edgeoglca ••••••••. ' , , , , . , .
Logical '1' , " , , , , , , ,1 I?'H:I• ~~L", , , , , , , ,ffl , , , , , , ,
• ,,1 1 1 1 • 1 1 1,::::,' 1 • 1 1 1 • 1Loglcal 0 ••••••••. , , , , , . ,
1 2 3 4 5 6 7 8 9 10 1112 13141516
ThirdClockEdge
(a)
Logical '1' , First,, Clock,Logical '0' , Edge
Logical '1', , Second,, Clock,Logical '0' , Edge
Logical '1' , Third,, Clock,Logical '0' , Edge
1 234 5 678 9 10 11 12 131415 16
(b)
Figure 2.1 Sampling instances of (a) jitter-free signal (b) jittery signal
Background 6
Circuits for Time and Fregeuency Domain Characterization of Jitter
Cumulative Density Function
Antonio Chan
J!!c::::Jo
C,)-o...8E::::JZ
Sampling Instances
Derivative
Probability Density Function
LLCQ.
Sampling Instances
Figure 2.2 Jitter CDF and PDF
The resulting CDF would then take on a shape similar to that shown in Figure 2.2(a).
Interesting enough, if the derivative of the CDF is computed, then one would obtain the
probability density function (PDF) or histogram of the jittery dock signal as shown in
Background 7
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Figure 2.2(b) [8]. Subsequently, we can extract farniliar statistical measures of the jitter,
such as the RMS and Peak-to-Peak values, based on these results.
2.3 - Unit Gate Delay Resolution
The algorithm described above can be implemented using the circuit shown in
Figure 2.3(a) consisting of a series of ND-type flip-flops or D-Iatches, counters and a
delay line with N taps. The signal under test, herein referred to as the data signal, is
simultaneously applied to the input of each D-Iatch whose dock inputs are slightly delay
with respect to one another to correspond to the appropriate sampling instance described
in the previous sub-section. The clock signaIs for the various D-Iatch are generated by
passing a master clock signal through a chain of buffers, delaying the clock by 't second as
is shown Figure 2.3(b). Assurning that the master clock signal is jitter-free, the size of the
delay 't establishes the timing resolution of the measurement. If the data signal is leading a
particular clock signal, the output of the corresponding flip-flop will go high and cause the
counter connected to its output to increment its content by 1. However, if the data signal is
lagging the clock signal, the flip-flop williatch to a logic low value and the counter will
maintain its current value. For example, consider the timing relationship between Data,
Clock_l, Clock_2 and Clock_3 shown in Figure 2.3(b). In this case, the data signal is
sampled by three delayed version of the same clock signal simultaneously. Countecl
keeps its current value while Countec2 and Countec3 increment their contents by 1. This
process is repeated for a large number of clock cycles. The values stored in the counter is
then processed to obtained a CDF and, in turn, a PDF [8].
Background 8
Counter_1
Circuits for Time and Fregeuency Domain Characterization of Jitter
Data ILn.-n
Clock_1
Antonio Chan
MasterILn.-n ln-kCounte,-N
Clock
-B>--lY Clock_N
(a)
Data ~111
Clock_1 ~ '- 1 Counter_1 keeps its1 current count value1 It -'tl1111
Clock_2 -' F 1Countec2 increments
1 its count by 11 1t -2't111111 F 1
Counter_3 incrementsClock_3 ~1 its count by 11 1t -3't1
(b)
Figure 2.3 VOL with unit gate resolution implementation(a) circuit diagram (b) timing diagram
Background 9
Circuits for Time and Fregeuency Domain Characterization of Jitter
2.4 - Sub-Gate Delay Resolution Circuit
Antonio Chan
It should be obvious that a smaller unit delay in the delay chain will result in a
finer timing resolution in which to collect the signal statistics. However, the smallest gate
delay available is technology dependent, as summarized in Table 1.
Table. 1 - Intrinsic delay of different CMOS technology
Technology Buffer Delay
O.351lm 52.3 ps
O. 18 1lm 25.1 ps
To circumvent this limitation, an additional delay chain can be added to the data path as
shown in Figure 2.4(a). The resolution is no longer dependent on the intrinsic gate delay,
but rather the delay difference between two gates. If the gates delays are made slightly
different, sub-gate timing resolution is possible. Such a structure has come to be known as
a VDL. Here it is assumed that the dock signal is jitter-free. The symbols "Cf and "Cs are the
respective propagation delays of the buffers interconnecting each stage of the VDL. As the
propagation delays of the dock and data paths differ by an amount ilt ="Cs - "Cf, the time
difference between the rising edges of the data and dock signaIs will decrease by ilt after
each stage of the VDL. The phase relationship between these two rising edges after each
stage is detected and recorded by a corresponding D-latch. A logicallow will result when
the dock signal leads the data signal, whereas a logical high will result when the data
signalleads the dock signal. The output of the D-latch is passed to a counter circuit,
which simply counts the number of times the data signalleads the dock signal (i.e., the
number of 10gica11 's) with a delay difference set by its position in the VDL.
Background 10
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
'>-.-..---..-...1- ... 00 •• 0 •••
Clock
Data
JUlJL
JUlJL
countec1 countecN
Clock_1
(a)
1It -'tsl
-----1
~....--4-!-- lt_-_'tf_l_Countec1 keeps itscurrent count value
---~ !-Counter_2 keeps itscurrent count value
--1-iF
Countec3 incrementsits count by 1
(b)
Figure 2.4 VOL with sub-gate timing resolution(a) circuit diagram (b) timing diagram
By design, the data signal will be made to always lead the dock signal at the input
of the VDL by placing an additional delay block in series with the dock input.
Subsequently, as the dock input signal propagates along the VDL, we come to a point
Background 11
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
where the data signal will go from a leading to lagging situation that is detectable. This
will result in aIl the D-Iatches prior to this point to register logical high levels, whereas aIl
D-Iatches after this point will register logicallow levels. The counter in each stage then
registers the corresponding state of each D-Iatch. As the phase between the data and dock
signaIs at the input of the VDL is a random variable, each time the measurement is
performed, a different set of D-Iatches are set to a logical high level and the corresponding
counters begin to register different values. In the case of the first counter, its count value
reflects the number of times the rising edge of the data signal is ahead of the rising edge of
the dock signal with a delay greater than ~t. Likewise, the counter in the next stage will
correspond to the number of times the rising edge of the data signalleads the rising edge
of the dock signal with a delay greater than 2ôt. Subsequently, the following stages
correspond to the number of times the data signal leads the dock signal by 3ôt, 4ôt, and
so forth. As an example, the timing relationship between the data and dock signal is
shown in Figure 2.4(b). In this case, three delayed version of the data signal is sampled
simultaneously by three delayed version of the dock signal, resulting in sub-gate timing
resolution. StatisticaIly, the various count values can be collected and used to create a
CDF of the jitter riding on the data signal. Subsequently, a PDF can then be obtained.
2.5 - Drawbacks
To see the drawback of this design, let us take a look at the design implemented
previously in [6]. This design was implemented in a 0.35 /lm CMOS technology
consisting of 101 buffer stages in the VDL. The chip micrograph taken from [6] is shown
in Figure 2.5 The respective sizes of the VDL and the counter is summarized in Table 2.
An important drawback of this design is large number of counters that is required. Not
only is size a drawback to this design, the measurement accuracy of this VDL structure is
dependent on the matching of delay elements in the various stages, as symbolically
illustrated in Figure 2.6. These mismatch errors lead to differential non-linearity timing
errors. Although careful layout techniques can help to minimize these mismatches, it
cannot eliminate them completely.
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Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Figure 2.5 VOL in 0.35J.Lm CMOS technology
Table. 2 - Silicon area for VOL in CMOS 0.35 J.Lm
Component Area occupied
VDL 2.4 mm2
Counter 3.1 mm2
Background 13
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
JUUlData
JUUlClock
........--+f--------
countec1
Figure 2.6 VOL with mismatched elements
countecN
2.6 - Summary
Sorne basic jitter statistics and rnethod of characterization as well as sorne existing
circuits and their drawbacks have been discussed in this chapter. It is clear that a new
technique is required to overcorne these problerns. Chapter 3 will introduce the concept of
a cornponent-invariant VDL circuit that gets around both of these problerns.
Background 14
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Chapter 3 - Jitter Characterization for
lime Domain Parameter
3.1 - Introduction
In the previous chapter, the problems with the existing state-of-the-art in jitter
measurements was described. In particular, the component matching requirement in the
VOL and the excessive number of counters required. In this chapter we shaH outline a new
VOL circuit that is component-invariant and requires a single counter. Implementation
details in a 0.18 !lm CMOS process from TSMC will be described, together with
experimental results. In addition, an FPGA implementation will also be provided
illustrating the synthesizable nature of the technique. FinaHy, we will look at sorne of the
design limitations such as latch metastability issues and dock and power supply noise.
3.2 - A Component-Invariant VOL Structure
If one assumes that the period of the data and dock signal, denoted as T, is larger
than the total propagation de1ay through an M-stage VDL, then the outputs of all the D
latches can be combined into one bit-stream whose total count of logical high levels
represents the actual time difference between the edge of the data and dock signal taken at
a particular instant in time. This is easily achieved by üRing the outputs of aH the 0
latches together and counting the number of logical high levels over the time period T, as
Jitter Characterization for Time Domain Parameter 15
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
shown in Figure 3.1. Repeating the measurement N times enables a histogram of the jitter
signal to be constructed. This eliminates the problem of having to use a large number of
counters.
"1propagation delay = M 'tf
T» M 'tf 1"1" ..,
Jl 11. --1'~~>----r'~>--+--- .Data
Jl 11.Clock
Figure 3.1 Obtaining a timing measurement directly fram a VOL
As noted previously in section 2.5, the original VDL design is sensitive to
component mismatches in the delay elements. However, by utilizing the same delay
elements in each stage, mismatches can be completely eliminated. Such an approach is
achieved by modifying the circuit in Figure 3.1 to obtain the component-invariant VDL
structure shown in Figure 3.2 [9][10]. This novel circuit is the main focus of this research
and will be discussed in sorne detail in the next subsection. In this circuit, inverters instead
of buffers are used to create the delay difference between the data and clock input signaIs
to the D-Iatches. In addition, the output of each inverter is fed back to its corresponding
input, depending on the state of the switch in its feedback path. When the switches are
closed, the inverters are configured with regenerative feedback, hence will oscillate with a
period of 2'ts or 2'tf seconds, depending on the propagation delay of the inverter in the
feedback loop. More importantly, each inverter circuit will delay the leading edge of the
data signal with respect to the leading edge of the clock signal by an amount 2(ts-'tf) or
2d't seconds every cycle of the input clock signal. Altematively, one can envision this to
Jitter Characterization for Time Domain Parameter 16
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
be equivalent to having two ring oscillators running simultaneously with different
frequencies to produce a constant delay difference during every cycle of oscillation.
To ensure an accurate time measurement, switch A in the feedback path of the
inverter controlling the clock of the D-Iatch shown in Figure 3.2 must be closed on the
rising edge of the dock signal, whereas switch B must be closed on the rising edge of the
data signal. Simultaneously, the output of the single D-Iatch is passed to a counter, which
simply determines how many dock cycles the D-Iatch remains in the high state. Once the
edge of the data signal goes from a leading to lagging situation with respect to the clock
signal (or vice versa), the counter is stopped. The time difference between the data and
dock edges can then be computed. The process is then repeated and a histogram of the
jitter is derived.
Counter
TriggeredRing Oscil/ator
1----1------1
1 nnn Switch B 1I~ 11 Data s____L 1
1 DQ~~~1 Phase Detector
EdgeDetector
1
1 1
1 -C-Iock- -r- 't- - - - 1
Edge 1-(>--. f )04..----.-...:..I-J Triggered
Detector 1 Switch A 1 Ring Oscil/ator
1 ~ 1
Figure 3.2 Replacing VOL by a component-invariant VOL structure
Jitter Characterization for Time Domain Parameter 17
Circuits for Time and Fregeuency Domain Characterization of Jitter
3.3 - Circuit Implementation
Antonio Chan
In this section we shaH describe the circuit details of the three main circuit
components of the component-invariant VDL circuit: the edge detector, the ring oscillator
and the phase detector. We shaH also outline the calibration and measurement process, and
the time it takes to complete a single measurement.
3.3.1 - Edge Detector
The main function of the edge detector is to catch the rising edge of the data or
dock signal. This can be implemented using a single D-type flip-flop with the D and reset
inputs connected together as shown in Figure 3.3(a). With the enable signal set high, the
D-type flip-flop output willlatch its output high on the subsequent rising edge of the dock
or data signal. The D-Iatch will be reset when the enable input is set low and another dock
or data edge occurs. These two situations are illustrated in Figure 3.3(b).
Enable R--.-1 D QClockl Data
(a)
Clockl Data
Edge
Enable
Clock/ Data
Clock/ DataEdge
·~
·J1JU1··--r-
.~.
.............~
~
(b)
Figure 3.3 Edge detector (a) circuit diagram (b) timing diagram
Jitter Characterization for Time Domain Parameter 18
Circuits for Time and Fregeuency Domain Characterization of Jitter
3.3.2 - Triggered Ring Oscillator Circuits
Antonio Chan
At the heart of the component-invariant VDL are the two triggered ring-oscillator
circuits highlighted in Figure 3.2. Note that "Cf and "Cs are the respective propagation delays
around the loop of each ring oscillator. In order to maintain a predictable phase
relationship for detection, "Cs is set to be greater than "Cf. (Here the subscript 's' indicates a
slow oscillation and of' for a fast oscillation.) This, in tum, establishes the ring oscillator
triggered by the dock signal to ron at a higher frequency than the oscillator triggered by
the data signal. To trigger each oscillator on a logical high level, the circuit of Figure 3.4
was chosen. The delay in the ring oscillator circuit can be designed to be tunable using the
voltage-controlled delay cell [7] shown in Figure 3.5 or as a fixed-delay buffer using
several inverter circuits in cascade.
r-------iClock/Data
Edge
(a)
Clock / Data Edge J
Oscillator Output
(b)
OscillatorOutput
Figure 3.4 Triggered ring oscillator (a) circuit diagram (b) timing diagram
Jitter Characterization for Time Domain Parameter 19
Circuits for Time and Fregeuency Domain Characterization of Jitter
VDD
~~ln ~
OCControlVoltage
Figure 3.5 Voltage-controlled delay circuit
3.3.3 . Phase Detector
Antonio Chan
JU1JLSignal
Out
The phase detector circuit is used to keep track of the history of the phase
difference between the two oscillators, thus providing information on a phase change. As
mentioned in the previous section, by design, the edge of the data signal is always set to
lead the dock signal at the start of the measurement process. It is when the data signal
begins to lag the dock signal that the measurement process is to stop. To accomplish this,
the phase detector is implemented using the two D-Iatches shown in Figure 3.6(a). The
output of the AND gate will switch from a logicallow level to logical high level when an
input sequence of '10' is detected as shown in Figure 3.6(b).
Jitter Characterization for Time Domain Parameter 20
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Data-triggeredoscillator
Clock-triggeredoscillator
o a1----1----f 0 01------1OB OB
(a)
Phase detected 1LData-triggered Il Il Il Il
oscillator -.J LJ L --.-J LJ L
CIO~~~~~:~;o~red 5lSL 5lSL(b)
Figure 3.6 Phase detector (a) circuit diagram (b) timing diagram
3.3.4 • Complete Circuit
By combining the edge and phase detector, the two triggered oscillators and the
counter circuit, the complete component-invariant VDL circuit is shown in Figure 3.7. It is
interesting to note that this circuit can be synthesized using entirely digitallogic.
Jitter Characterization for Time Domain Parameter 21
Circuits for Time and Freqeuency Domain Characterization of Jitter Antonio Chan
1---1-------------- 1 ---------,1 Edge 1 1 1
Detector S Triggered 1 1
:: Ring Oscil/ator 1 Phase Detector 1
Enable 1 1
Oma 1 1 .----,1---1------------- 11 Edgel f 1
1 Detector 1 Triggered 1
1 1 Ring Oscil/ator 1
Enable 1
Clock 1 1 1l -l 1 1
Figure 3.7 The circuit implementation of the component invariant VOL structure
3.4 - Calibration And Measurement Processes
There is an intrinsic delay difference between the signal path of the clock and the
data lines, which includes the intentional delay added between the clock-triggered
oscillator and the edge detector, the setup time and propagation de1ay difference between
the D-Iatches in the two edge detectors, as well as that of the XOR gate in the ring
oscillators. Since all these delays are process sensitive, the measured delay will be
different from the actual delay difference between the clock and the data edges. AIso, note
that the difference in oscillation frequencies determines the measurement resolution,
which also becomes process sensitive due to the unpredictable delay of each loop in the
ring oscillator. Therefore, in order to make the design fully synthesizable, i.e. no element
matching is required, a calibration sequence is necessary to determine the frequency of
oscillations and the difference between the delay path of the data and clock signal.
Ta achieve a calibration, the dock and data lines are first connected together to
determine the delay difference between the two signal paths. Because the two inputs are
tied together, jitter on the input calibration signal will have little effect. As the enable
signal goes high, the two oscillators start to oscillate and the counter starts to record the
number of clock cycles that the rising edge of the clock signal is leading the data signal.
Jitter Characterization for Time Domain Parameter 22
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Once the clock signallags the data signal, the counter will have counted to a value of No
corresponding to a time delay of To as shown in Figure 3.8.
1--- - ------- ----------------, ï- --------- ---..,: .T0 =No.1T Calibration : : Measurement1 -: :-- Mode 1 Mode1 :: 1 :
Enable JJ:: :1 1
1 :: Tp 1. ·1 Il Il. . -.i !- T = N.1TPhase detected : •• ~ I:! : n 1
1 : 1 1 : : 1
1 :: n r:J : h n 1
Data-trig. osc. ~"'"'':SU1::''' J1SL.....~ U!Ll.--J :U L· ......JlSLI1 : : 1: :
Clock-trig.osc. -.LM ·JUL JUl~ JlfL :1 1 1 1: No counts Np counts 1: N counts 1
i l' '" -, i : 1· -1 i___________________________ ~ L ~
Figure 3.8 Timing diagram for the calibration and measurement modes of operation
After a certain period of time Tp' the rising edge of the clock-triggered oscillator
will move across one complete cycle of the data-triggered oscillator, corresponding to Np
counts as also shown in Figure 3.8. The timing resolution, ôT is defined as
(3.1)
where Ts is the oscillation period of the data-triggered oscillator and Tf is the oscillation
period of the clock-triggered oscillator. Tf is related to Tp and Np according to
(3.2)
As the clock-triggered oscillator completes Np cycles in the time Tp' the data-triggered
oscillator must complete Np -1 cycles. Rence, the fundamental relationship that govems
the coherence of this design is
T = N . Tf = (N - 1) . Tppp s
Jitter Characterization for Time Domain Parameter
(3.3)
23
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
We shal1 refer to Tp as the coherency period. By rearranging (3.3), the period of the data
triggered oscillator can be then determined in terms of the measured data as fol1ows
(3.4)
Final1y, the timing resolution ilT can be determined by substituting (3.2) and (3.4) into
(3.1), to obtain
TliT = p
N . (N -1)p p
(3.5)
The time value of Tp is usual1y very large compared to Tf, thus, depending on
measurement equipment, measuring an accurate Tp may be difficult, especial1y in the case
of a smal1 time step over a large measurement range. An alternative approach is to
measure Tf indirectly through the counter output. As shown previously in Figure 3.7, the
counter is used to count the number of the clock-triggered oscillator cycles during
calibration and during a phase measurement. Therefore, when the oscillator is running, Tf
can be obtained by measuring the cycling time of one bit of the counter. Thus, Tf is related
as fol1ows:
(3.6)
where n is the bit position with respect to the least significant bit of the counter and Tc is
the cycling time of the nth counter bit. Therefore, Tp can be determined from (3.3) as
fol1ows
(3.7)
Of course, once Tp is known, Tg can be calculated using (3.4).
Now that the calibration phase is complete, we are ready to perform a time
measurement. Assuming that the calibration and measurement modes experience the same
Jitter Characterization for Time Domain Parameter 24
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
intrinsic delay along the dock and data paths, we can compute the measured phase
difference by subtracting off the intrinsic delay To' according to
T = f:..T·No 0(3.8)
Similarly, denoting the counter output during the measurement mode as N (shown in
Figure 3.8), the total measured time Tn is given by
(3.9)
Since this time includes the intrinsic delay To' the actual time difference between the data
and clock signal is given by
(3.10)
Substituting (3.8) and (3.9) into (3.10), Tm can be written more directly in terms of the
measured parameters as follows
(3.11)
The accuracy of our measured time interval Tm is directly dependent on the
accuracy of the calibration factors, Tp and the counts, No and Np. To a first-order
approximation and assuming Np - l "" Np, the relative accuracy of Tm can be expressed as
(3.12)
With count errors of ±l count, the accuracy of the time measurement becomes
(3.13)
Here we c1early see that Np, N-No' and Tp should be as large as possible in aIl situations to
maximize the relative accuracy of the measurement. Of course, N-No is outside of our
direct control, as it varies with each measurement. However, as evident from (3.13), in
order for Tp and Np to be maximized, the periods of both the data and dock triggered
oscillators (i.e., Tf and Tg) must be maximized. In general, to increase the oscillation
Jitter Characterization for Time Domain Parameter 25
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
period of a ring oscillator requires additional delay stages to be added in the feedback loop
of the oscillator. However, incorporating additional delay stages increase the noise
introdueed into the circuit and adds to the randomness in any particular measurement.
Nonetheless, measurement averaging can be exploited to reduce this variation at the
expense of more test time.
3.5 - Test Time Comparison
Since test time is one of the criteria to quantify the performance of a measurement deviee,
the required test time of the component-invariant VDL is compared with the original VDL
circuit shown in Figure 2.4. For the VDL circuit of Figure 2.4, the test time to collect aIl
the CDF data is roughly equal to
(3.14)
where Ttest is the total test time, TcIk is the clock period and Nsample is the total number of
samples taken. For clock period of TcIk = 1 ns and 5000 samples collected, the total test
time would be approximately T rest "'" 5f.ts .
For the component-invariant VDL, assuming jitter is uncorrelated with the clock
signal, the average test time per sample can be estimated by taking the mean of the
maximum and minimum test time per sample. Test time per sample is at a maximum when
the clock and data signal is different by almost one clock cycle Tf. This is determined
during the calibration phase to be equal to TP' Test time per sample is at a minimum when
the data and clock signal is aligned such that it only requires one oscillation cycle to obtain
a phase change. Henee, the maximum test time per sample is estimated to be
Tmax-test-per-sample"'" T p
Therefore, the average test time per sample is
TpTtest-per-sample"'" "2
and the average overall test time becomes
Jitter Characterization for Time Domain Parameter
(3.15)
(3.16)
26
Circuits for Time and Fregeuency Domain Characterization of Jitter
where Nsample is the total number of samples coHected.
Antonio Chan
(3.17)
With 5000 samples coHected, a timing resolution of 10 ps, a result of dock and
data oscillators having periods of 0.2 ns and 0.21 ns, respectively, and a coherency time Tp
of 4.2 ns, we find from above that the average test time is expected to beTtest "" lOJls.
The component-invariant approach typicaHy requires longer test times than the
original VDL approach of Figure 2.4. One way to reduce the test time is through the
application of additional component-invariant VDL stages.
3.6 - Reducing Test Time Using A SpatialArrangement of Component-Invariant VOLs
An array of component-invariant VDLs can be configured as shown in Figure 3.9.
Here a single dock-triggered ring oscillator is shown driving the dock input of each D
flip-flop. AH the data-triggered ring osciHators are designed to have the same nominal
oscillation frequency but aH are triggered by a progressively increasing one-gate delayed
data signal. With the data-trigger oscillation frequency set below the dock-triggered
oscillation frequency, a time-grid of data-triggered oscillation will result as shown in
Figure 3.10. Therefore, as soon as the rising edge of the dock-triggered oscillator passes
through any one of the rising edges of the data-triggered oscillators, the result will be
known. For jitter measurement applications, this structure has the advantage that the
measurement time is significantly reduced. Since jitter is assumed to be random and,
hence, does not correlate with the time that the sample is taken, a non-uniform sampling of
data will also lead to a good estimation of the jitter statistics.
Note that the phase difference between any data-triggered oscillator does not have
to be matched, since calibration can be performed on each component-invariant VDL
circuit. For the same reasons, the frequency of oscillations of these data-triggered
osciHators does not have to be made exactly equal.
Jitter Characterization for Time Domain Parameter 27
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Since there are multiple phase detectors, a controHer will be required to select the
earliest phase detection. This can be easily implemented using sorne simple combinational
logic such as that shown in Figure 3.11. The calibration process is exactly the same as the
single component-invariant structure, provided one calibrates each data-triggered
oscillator with respect to the clock-triggered oscillator. During calibration mode, the
control signal q will be set to a logical high level to enable the ith data-triggered
oscillator, and aH other Cj's (i::t. j) will be set to a logicallow level to disable the other
data-triggered oscillators. During measurement mode, aH C's will be set to a logical high
level.
Jitter Characterization for Time Domain Parameter 28
Circuits for Time and Fregeuency Domain Characterization of Jitter
.................. "[)éit~iCièiàyèd' ...by P buffers
.-----111' .......---'---,
...................bàta 'delayeèf ...by two buffers
.-----111· .......---=-....,
~ Dat"éi'ëfëfayëë:i .. ':: b one buffer ~L.-_-.L...,
__---l-~
~ "[iéità trfggérs' .._ .......__+--..: switch B to close
Antonio Chan
counter
JUUlData
.................. .................................
C~J1J1Jl.: Clock triggers
. switch A to close .1 :
Figure 3.9 An array of component-invariant VOLs
Jitter Characterization for Time Domain Parameter 29
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Data (delayed by 1 buffer)
Data (delayed by 2 buffers)
Data (delayed by 3 buffers)
Clock
Figure 3.10 Timing relationship for VOL array
CoDo
C10 11111111111
Counter
Figure 3.11 Controller for VOL array structure
Since the efficiency of the time reduction depends on the time grid location, if P
component-invariant VDLs are added to provide the optimal time-grid, the average test
time per sample is now reduced to
TpTtest-per-sample:=:: 2 . P
Therefore, the total test time becomes
Jitter Characterization for Time Domain Parameter
(3.18)
(3.19)
30
Circuits for Time and Fregeuency Domain Characterization of Jitter
where Nsample is the number of samples collected over the test period.
Antonio Chan
For a VDL with 4 additional oscillators (each with an oscillation period of Tf =0.21 ns), 5000 samples collected over the test time and a timing resolution of ~T =10 ps,
the expected test time becomes 2.5 ilS (compared to 10 ilS in the single oscillator VDL
case).
Note that an OR gate with a large number of inputs is necessary if a large number
of data-triggered oscillators are used. Practically speaking, however, only a few are
required to produce a "time grid" fine enough to reduce the test time significantly. In
addition, circuitry for decoding which data-trigger oscillator is responsible for the phase
detect must also be added. This is necessary to know which calibration factors should be
used to compute the appropriate measurement time. Latching the state of the outputs of
each phase detect at the time of the first phase detect will enable the user to know which
oscillator is taking part in the time measurement.
3.7 - Experimental Results
3.7.1 - CMOS Implementation of A Component-Invariant VDL
In this section we shall describe the experimental results of a single-stage
component-invariant VDL implemented in a 0.18 Ilm CMOS process. The schematic of
the circuit that was used is shown in Figure 3.7, with the addition of two 12-bit shift
registers. These two registers shown in boxed area on dotted line were included for
scanning digital data off the chip. The buffers in the feedback path of the two triggered
oscillators was implemented using the voltage-controlled delay circuit shown in Figure
3.5 with the DC control node of each delay cell brought off the chip for external control.
The layout of the experimental chip is shown in Figure 3.12. In the center of the chip
monograph are four white boxes on solid lines containing four component-invariant
VDLs. Each cell occupies an area of 0.12 mm2.
Jitter Characterization for Time Domain Parameter 31
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Figure 3.12 A chip monograph of component-invariant VOL implemented in a 0.18/lm CMOS process. The boxed region on solid line iIIustrates one component
invariant VOL circuit consuming approximately 0.12 mm2 of silicon area.
Several experiments were run using the experimental setup shown in Figure 3.13.
This setup consists of a Teradyne A567 (shown in Figure 3.14) mixed-signal tester
configured as a pseudo jittery clock stimulus and a Wavecrest DTS-277ü jitter analyzer for
eomparing the results of the VDL. The circuit was eonneeted to the test-head through a
Device Interface Board (DIB). A user computer was used to control the test sequence and
test setup. A software program was written to coordinate these test procedures. Through a
mathematical analysis in MATLAB, the edges of the jittery clock signal were assigned a
specifie statistical distribution and stored in the memory of the Teradyne A567 tester. Eaeh
number corresponds to an edge placement of a digital signal. These edge placements have
Jitter Characterization for Time Domain Parameter 32
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
a maximum timing resolution of 78 ps [11]. The jittery clock signal was then applied
simultaneously to the VDL and the Wavecrest instrument from which the actual phase
error of the test signal relative to a reference clock signal could be measured. The
Wavecrest instrument has 0.8 ps timing resolution, ±25 ps single-shot accuracy and ±10 ps
average accuracy [12].
On-Chip VDL
JUUl Data .~ 1
A567 Vc
.~ r-counter :TeradyneTester JUUl Vd
~1Clk
Wavecrest DTS-2770
CounterOutput
Figure 3.13 Experimental setup
Since high resolution timing measurement is very sensitive to noise, in order to
have quality measurement, a four-layer PCB was designed and fabricated as shown in
Figure 3.15. The four layers were designed to be analog ground, digital ground and two
signallayers. The SMA connector on the PCB were placed very closed to the signal to be
measured since PCB trace can introduce relatively significant picosecond timing delay.
The same reason applies to the IC where it is placed closed to the digital pins as opposed
to the analog pins. As weH, both analog and digital power supplies were regulated by on
board voltage regulators to provide stable DC voltages. The DC control voltages which
control the timing resolution of the two oscillators were filtered by passive RC low-pass
filters to reduce high frequency noise as much as possible. AH power supplies were also
decoupled with capacitors to reduce high frequency noise. These passive filters and
decoupling capacitors were located as close as possible to the IC on the PCB to reduce
Jitter Characterization for Time Domain Parameter 33
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
noise picked up by the PCB trace. A clamp was used to keep the IC in place so that the IC
did not have to be soldered on the PCB for ease of replacement.
With the DC control voltage of the two delay cells set to 0.68 V and 1.8 V,
respectively, the VDL was calibrated using 2000 samples of a 1.56 MHz clock.
Specifically, Tp was measured to be 345 ns, Np was measured to be 80.1 counts and No
was found to be 23.05 counts. Subsequently, according to (3.2) and (3.4), the oscillation
frequency of the clock-triggered oscillator, Tf, was calculated to be 4.307 ns which
corresponds to a frequency of 232 MHz and Ts was calculated to be 4.362 ns which
corresponds to a frequency of 229 MHz. Therefore, according to (3.5), a timing resolution
of 54.5 ps was achieved.
Figure 3.14 Teradyne Tester
The VDL circuit was then characterized by sweeping its input with a 1.56 MHz
clock signal whose phase was linearly varied over its clock period. Simultaneously, the
same signal was sampled by the Wavecrest DTS-2770 jitter analyzer. Five thousand
Jitter Characterization for Time Domain Parameter 34
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
samples of the input signal was measured. The results are displayed in Figure 3.16(a) with
the VDL results plotted as a function of the Wavecrest results. As is c1early evident, there
is a strong linear correlation between the two results. In the phase range 0 - 1000 ps, the
correlation is nearly perfect as evident from the expanded view shown in Figure 3.16(b).
Above this leve1, the measurement correlation seems to decrease. We believe this
deviation is due to excessive noise induced on the power supply by the triggered oscillator
pair and the counter. Since the delay cens and the counter share a common power supply
and that the ring oscillator pair draws different amount of current from the power supply
depending on the relative position of the rising edges of the ring oscillator pair - the power
supply level varies with the input signal conditions. Better layout and improved on-chip
power supply decoupling is expected to improve this situation.
Digital Pins
Voltage Regulators
Passive Filters
Figure 3.15 Four-layer peB
Analog Pins
Jitter Characterization for Time Domain Parameter 35
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Resolution = 54.5 ps3500...----r----,-----,.--,...---...,...---r--.....,...,
'Vi' 3000Q.-...J~ 2500
>-~ 2000G)L.:;,
~ 1500G)
E
~ 1000~
c.500
OCF----L._----JL....-_-'--_----L__..L--_---'-_----J
o 500 1000 1500 2000 2500 3000 3500Phase measured by Wavecrest (ps)
(a)
Resolution = 54.5 ps1000...----...,...----r------,..---,--------"
,
~ Ideal (dotted line)
Experimental (solid line)
~
~ BOO-...J~>- 600,g
"C
~:;,
~ 400G)
EG)
~~ 200c.
1000200 400 600 BOOPhase measured by Wavecrest (ps)
(b)
o<l'--_--L. "---__--'- .L...-__......
o
Figure 3.16 Phase measurement of VOL set to the 54.5 ps timing resolution(a) full view (b) zoom view
Jitter Characterization for Time Domain Parameter 36
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
0.5 r---~---'--"----r"-----r--~----'
0300 400 500 SOO 700 800 900 1000
lime {psec)
(a)
7370 -
60 -
50 -
~ 40a..
30
20
10
0332.6ps 645.7ps 967.4ps
Time
(b)
0.3
0.1
0.2
0.4
IJ...CIa..
Figure 3.17 Histograms for Gaussian distributed jitter for 54.5 pstiming resolution from (a) VOL (b) Wavecrest
Jitter Characterization for Time Domain Parameter 37
Circuits for Time and Freqeuency Domain Characterization of Jitter Antonio Chan
The next experiment was one that involved generating a 1.56 MHz dock signal
with a jitter component having gaussian statistics. The jitter variation was made to stay
within the linear range of the VDL (i.e., < 1000 ps). The De control voltages of the VDL
circuit were adjusted to 0.68 V and 1.8 V, respectively, whereby a 54.5-ps timing
resolution was achieved. Two thousand samples were simultaneously collected by the
VDL and Wavecrest instrument. The captured histograms are shown in Figure 3.17(a) and
Figure 3.17(b), respectively. The resolution is clearly higher with the Wavecrest
instrument (finer Hne widths), however, the overall shape has very similar behavior. The
RMS and peak-to-peak values of the two distributions are summarized in Table 3. The two
sets of statistics show excellent correlation.
Table. 3 • Jitter measured using 54.5 ps timing resolution VOL
Jitter MeasurementVDL
WavecrestDistribution Type (54.5 ps timing
(as reference)resolution)
Gaussian RMS 92.8 ps 98.79 ps
Gaussian Peak ta peak 599 ps 634.8 ps
Sinusoidal RMS 168.3 ps 185.6 ps
Sinusoidal Peak to peak 707.9 ps 606.6 ps
Another experiment was run in a manner similar to that just described, however,
this time a 1.56 MHz clock signal with a jitter component having a sinusoidal distribution
was created and applied to the VDL and Wavecrest instrument simultaneously. The
captured histograms are shown in Figure 3.18(a) and Figure 3.18(b). The RMS and peak
to-peak values of the two distributions are summarized in Table 3. As is evident, the two
sets of statistics show very good correlation.
By adjusting the control voltages associated with the two delay blacks inside the
VDL circuit, we were able to fine-tune the time resolution of the component-invariant
VDL to 18.9 ps. The histogram results for both a Gaussian and sinusoidal jitter
distribution for both the VDL and the Wavecrest instrument are shown in Figure 3.19,
Figure 3.20 and Figure 3.21. Furthermore, Table 4 summarize the statistics of each these
Jitter Characterization for Time Domain Parameter 38
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
experiments. Once again, we conc1ude that the results of the VDL correlate very weIl with
the Wavecrest instrument.
Table. 4 - Jitter measured using 18.9 ps timing resolution VOL
Jitter MeasurementVDL
WavecrestDistribution Type
(18.9 ps timing(as reference)
resolution)
Gaussian RMS 21.1 ps 18.68 ps
Gaussian Peak ta peak 158.2 ps 124.5 ps
Sinusoïdal RMS 32.5 ps 41.94 ps
Sinusoidal Peak ta peak 234.5 ps 197.8 ps
Jitter Characterization for Time Domain Parameter 39
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
1000800600lime (psec)
400a200
0.04
0.08
0.02
0.1
0.12.-------
IJ..CI 0.06"-
(a)
42
35
30
25LL.CQ. 20
15
10
5
o L.....T==========rI========·j-375.4ps 676.5ps 982.1 ps
Time
(b)
Figure 3.18 Histograms for sinusoidal distributed jitter for 54.5 pstiming resolutionfrom (a) VOL (b) Wavecrest
Jitter Characterization for Time Domain Parameter 40
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Resolution = 18.9 ps2500 r------r---...---~---.------,---,
-[2000-..JCl>~ 1500"0E::::l:g 1000QI
EQI(Il
.! 500a.
500 1000 1500 2000 2500 3000Phase measured by Wavecrest Cps)
(a)
Resolution = 18.9 ps
Ideal (dotted line)
Experimental (solid line)
\" '\01lL..- .1....- 1....-__---I ---1_....::I
o 100 200 300 400Phase measured by Wavecrest (ps)
_250(IlQ"-....J~ 200>J:l
'Z 150L.::::l
lQË 100ClJIII~
if 50
(b)
Figure 3.19 Phase measurement of the VOL set to a 18.9 ps timing resolution(a) full view (b) zoom view
Jitter Characterization for Time Domain Parameter 41
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
0.45
0.4
0.35
0.3
LI. 0.25CIa. 0.2
0.15
0.1
0.05
0850 900 950 1000 1050
lime (psec)
(a)
226220
200
180
160
140
u.1200
Q.
100
80
60
40
20
0892.3ps 957.3ps 1017ps
Time
(b)
Figure 3.20 Histograms for Gaussian distributed jitter for 18.9 pstiming resolution from (a) VOL (b) Wavecrest
Jitter Characterization for Time Domain Parameter 42
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
0.4
0.35
0.3
0.25
LI.0.2Cl
c.
0.15
0.1
0.05
0BOO B50 900 950 1000 1050 1100
lime (psec)
(a)
192180
160
140
120ILc
1000-
80
60
40
20
0
819.1ps 909.6ps 1017ps
Time
(b)
Figure 3.21 Histograms for sinusoidal distributed jitter for 18.9 pstiming resolution from (a) VOL (b) Wavecrest
Jitter Characterization for Time Domain Parameter 43
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
3.7.2 - Calibration for systematic error
To exploit the limitation of the design, a set of pseudo random gaussian jitter was
generated from the tester and the results were compared. The mean values of the
measurement obtained by VDL and Wavecrest are shown in Figure 3.22. As expected, it
shows relatively linear behaviour. However, the RMS jitter of the same measurement
shown in Figure 3.23 shows sorne systematic deviations. This is due to the change in noise
level for different phase input as discussed in the previous section. However, this
systematic error can be corrected by having a lookup table that maps the RMS values
obtained by the VDL to that of the Wavecrest. Therefore, the RMS values obtained by the
VDL can be corrected in software to obtain the actual RMS value taken from a particular
measurement. The corrected RMS values are shown in Figure 3.24. This lookup table
optimizes the error across aH the measurements. The difference between the measured
values from the VDL and Wavecrest before and after calibration are shown in Figure 3.25
and Figure 3.26. The error after calibration shows a ±25 ps error which is within the
timing resolution of 54.5 ps. However, better optimization can be obtained by localizing
the measurement range and optimizing only the measurement range of interest.
The peak-to-peak jitter of the same measurement are shown in Figure 3.27. The
corrected peak-to-peak values are shown in Figure 3.28. The difference between the
measured values from the VDL and Wavecrest before and after calibration are shown in
Figure 3.29 and Figure 3.30. The error after calibration shows a ±150 ps error.
Jitter Characterization for Time Domain Parameter 44
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Resolution = 54.5 ps2500,.....-----r---,-------,..------.----.-------,
'[2000-...JCl
t. 1500~
"CGlC
! 1000~oCIIIGl 500::E
500 1000 1500 2000 2500 3000Mean obtained by Wavecrest (ps)
Figure 3.22 Mean Value
Resolution =54.5 ps
..250r;:::;:::::;:;;::;;:::ç:;:::==~,-----,-----,-----,----,
__ VOL (0 ps nns)"0" Wavec,est (0 ps nns)__ VOL (44.5 ps ,ms)"0" Wavecrest (44.5 ps ,ms)__ VOL (81.2 ps ,ms)"0" Wavec,est (81.2 psrms)__ VOL (201 B ps nns)"0" Wavec,est (201B ps nns)
200
! 150...al-=.ri)
::i!:1ooc::
""""""""."'"'''''''''''''''0'''''''''''''''''''''''''''''''''''''''''''',,0 '"'''''''''''',0''''''' "',",0
°o'-------'-----"-----'------L----.l..---~
500 1000 1500 2000 2500 3000Mean obtained by Wavecrest (ps)
Figure 3.23 RMS measurement before calibration
Jitter Characterization for Time Domain Parameter 45
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
200
Resolution =54.5 ps250~~::;;;::2::=:;:::==:::::;'-----'-----=---'------'--~
- VDL (0 ps nns),. o·, Wavecrest (0 ps rms)..... VDL (44.5 ps nns).. o·· Wavec,esl (44.5 ps nns)_ VDL (812 ps nns).. 0" Wavec,esl (812 ps nns)-+- VDL (201.8 ps ,ms)o· Wavec,est (201.8 ps ,ms)
150Iii"~...Q)- 100:=..
CI)
::Ec::
.,,'0' ", .. ",.",
."",,,,,,,
-50 '--__--'- "---__---'- -'--__---'-__-----J
o 500 1000 1500 2000 2500 3000Mean obtained by Wavecrest (ps)
Figure 3.24 RMS measurement after calibration
Resolution =54.5 ps60.-----,-----,----,-----'----,-------,-----,
50
~ 20Cl:C
QIUC
~ 0.!!-15-10
-20
__ Opsrms__ 44.5 ps rms__ 81.2 ps rms___ 201.8 ps ,ms
500 1000 1500 2000 2500 3000Mean obtained by Wavecrest (ps)
Difference in RMS measurement before calibration
-30'-------''-------'---------L-----L------'--------'o
Figure 3.25
Jitter Characterization for Time Domain Parameter 46
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Resolution =54.5 ps25
20
15.....IIIC. 10--...a>-:!: 5.-
CI)
::!:0ex:
ca> -5uca>...
-10a>--15_ Opsrms_ 44.5 ps rms_ 81.2 ps rms___ 201.8 ps rms
_25L----l.-----L---l.----l.-----L-------'o 500 1000 1500 2000 2500 3000
Mean obtained by Wavecrest (ps)
Figure 3.26 Difference in RMS measurement after calibration
Resolution =54.5 ps
".
1200
1400~::;;::;~~=:;-r----;;-------r-------'--~..... VDL (0 ps rms)"0" Wavecrest(O ps nns)..... VDl (44.5 ps rms)"0" Wavecrest (44.5 ps nns).... VDl (812 ps nns)"0" Wavecrest(U12 ps rms)..... VDl (2OlB ps rms),0" Wavecrest (201.8 ps nns)
....
500 1000 1500 2000 2500Mean obtained by Wavecrest (ps)
3000
Figure 3.27 Peak to Peak measurement before calibration
Jitter Characterization for Time Domain Parameter 47
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Resolution =54.5 ps
'0,·,
a."',
o
500 1000 1500 2000 2500 3000Mean obtained by Wavecrest (ps)
Peak to Peak measurement before calibration
1200
1400r-;:;:::;;;;;:::;~=.=:=:::;-~-----;r~ --..,.-------r-~... VOL (0 ps nns)"0,, Wavecrut (0 ps nns)... VOL (44.5 ps nns).0" Wavecrest(44.5 ps rms)... VOL (812 ps rms)"o·· Wavecrest (812 ps rms)__ VOL (201.8 ps rms)
Wavecrest (201.8 ps nns)
Figure 3.28
°1000e..alE 800
Resolution =54.5 ps300..----.--------,-------,----'-----,-------,-----,
3000
"iil 200Q,...al-:=~CIlalQ,
6 0
~CIl
rf. -100c:al
g -200al...al--15 -300
_ Opsnns_ 44.5 psrms_ 81.2 ps rms..... 201.8 psrms_400L_ ___.l...___~_ ___.l...___L--~~===::.J
o 500 1000 1500 2000 2500Mean obtained by Wavecrest (ps)
Figure 3.29 Difference in Peak to Peak measurement before calibration
Jitter Characterization for Time Domain Parameter 48
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Resolution =54.5 ps200~---.-------,--------;~--'--.-------.-------,
150Cil.e...~ 100:=.~
lB 50Co1o
]; 0III
8!..5alc.J
5i -100...al--15 -150
___ Opsrms...- 44.5 ps rms___ 81.2 ps rms___ 201.8 ps rms
-2000 500 1000 1500 2000 2500 3000Mean obtained by Wavecrest (ps)
Figure 3.30 Difference in Peak to Peak measurement after calibration
3.7.3 - A Three-Oscillator Component-Invariant VDL in a FPGA
To demonstrate the synthesizable nature of the proposed design, in this section we
shall implement a three-oscillator component-invariant VDL circuit using a FPGA as
shown in Figure 3.31. This section will also demonstrate the test time saving of the
multiple array approach.
A three-oscillator component-invariant VDL structure was implemented on an
Altera FPGA as a first proof of concept of the synthesizable nature of the VDL design.
The entire design was capable of fitting into a 128 macrocell FPGA. The circuit was
calibrated by collecting 1500 samples, resulting in the following parameters: Npl =143.2
counts, Nol = 57.4 counts, N p2 = 66.1 counts, N o2 = 99.2 counts. In this design, the
oscillation period of the c1ock-triggered oscillator was found to be 81.6 ns, corresponding
to a frequency of 12.3 MHz, which is deduced from the cyc1ing time of one bit of the
counter. In this situation, the oscillation period of the c10ck is larger than that of the data.
This is a result of our inability to precisely control the location of our cells. As a result, the
Jitter Characterization for Time Domain Parameter 49
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
clock-triggered oscillator completes Nf cycles in the time Tp while the data-triggered
oscillator completes Nf +1 cycles. Renee, the coherency equation becomes
(3.20)
Figure 3.31 Altera FPGA Board
This is slightly different than what we saw before in (3.3). ConsequentlY' the formulas for
Tg and dT in (3.4) and (3.5) are slightly modified by replacing Np - 1 by Np + 1.
Subsequently, the oscillation periods of the two data-triggered oscillators were calculated
to be 81.03 ns and 80.38 ns, giving rise to timing resolution of 0.566 ns in one case and
1.22 ns in the other. These particular results are strongly dependent on the physical
location of the macroeells in the FPGA. If one were to exercise greater control over the
eell placement, then we would expect a higher timing resolution.
To test this circuit, we made use of a Teradyne A567 mixed-signal tester to
generate a 2 MHz repetitive data signal with ajitter component having Gaussian statistics.
The experimental setup is shown in Figure 3.32. Subsequently, the RMS and peak-to-peak
values of the histogram are derived. The jittery signal was designed to have zero mean, an
RMS value of 1.03 ns and an 8 ns peak-to-peak value. The theoretical historgram is shown
in Figure 3.33(a). The component-invariant VDL with a 0.566 ns timing resolution was
Jitter Characterization for Time Domain Parameter 50
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
then used ta measure the characteristics of this signal with 1500 samples. The resulting
histogram is displayed in Figure 3.33(b). Here the RMS value was found ta be 1.27 ns and
the peak-ta-peak value was found ta be 9.05 ns. In the case of the RMS value, the
experimental error was 0.24 ns, which is within the timing resolution of the VDL, i.e.,
0.566 ns.
Pseudo Random x (n) Jitter y(n)Number generated Excitation On-Chip VDL DSP
trom MATLAB trom Tester
Figure 3.32 Test setup
A second test was run, but this time we made use of the component-invariant VDL
that had a 1.22 ns timing resolution. In this case, the jitter was designed ta have an RMS
value of 2.06 ns and a 16 ns peak-ta-peak value. The histogram of the Jitter input is shawn
in Figure 3.34(a). Fifteen hundred samples of this jitter were then gather by the VDL and
the results are shawn in Figure 3.34(b). The measured distribution has an RMS value of
2.64 ns and a 19.8 ns peak-ta-peak value. In the case of the RMS value, the experimental
error was 0.58 ns which is again within the timing resolution of the VDL, i.e., 1.22 ns.
Deviations of the experimental results from the theoretical are speculated ta be
caused by the internaI jitter of the tester and by the jitter generated by the VDL.
Nonetheless, the measurements correlate very well with each other.
Ta illustrate the test time reduction that is possible when an array of VDL are
utilized, we summarize in Table 5 the test time required for two VDLs tuned ta a 0.5466
ns and 1.22 ns timing resolution, and when both are utilize during the time measurement.
As is c1early evident in the case cited, when the two VDLs are combined, a significant
reduction in test time is achieved. Since the efficiency of the time reduction depends on
the time grid location of the VDLs, if one were ta exercise greater control over the cell
placement, then we would expect even a greater improvement in test time reduction.
Jitter Characterization for Time Domain Parameter 51
Circuits for Time and Fregeuency Domain Characterization of Jitter
0.2 r----.....-----.--------..----r---...,
Antonio Chan
0.15
u..o 0.1a.
0.05
01-----o 2 4 6
lime (nsec)
(a)
8 10
0.25 r--.--,--.---,--.,..---r--.,..--.,.-----,-_
0.20
LI.. 0.15oa..
0.10
0.05
oo 1 2 3 4 5 6 7 8
lime (n5)
(b)
9 10
Figure 3.33 Histograms for 0.566 ns VOL (a) theoretical (b) experimental
Jitter Characterization for Time Domain Parameter 52
Circuits for Time and Fregeuency Domain Characterization of Jitter
0.2 r----....-------,-------,------,
Antonio Chan
0.15
u.Cl 0.1c.
0.05
01...----o 5 10
lime (nsec)
(a)
15 20
0.2
0.16
0.12ILClc..
0.08
0.04
00 5 10 15 20 25
Time (ns)
(b)
Figure 3.34 Histograms for 1.22 ns VOL (a) theoretical (b) experimental
Jitter Characterization for Time Domain Parameter 53
Circuits for Time and Fregeuency Domain Characterization of Jitter
Table. 5 - Test time reduction (peak-ta-peak jitter of 45 ns)
VDL Used Test Time
0.566 ns-resolution VDL 196635 clock cycle
1.22 ns-resolution VDL 96235 clock cycles
Both VDLs 81960 clock cycles
3.8 - Limiting Factors
Antonio Chan
Although very high timing resolution can be obtained by tuning the oscillation
periods of the clock and data delay lines, the maximum resolution is limited by sorne basic
characteristics of the VDL circuit. In this design, we saw significant detection errors when
the timing resolution was driven below 15 ps. Henee, we limited our timing resolution to
be no less than 19.5 ps. Below are several reasons for this error.
3.8.1 - Metastability in the D-Latches
As resolution increases, the probability that the setup time between clock and data
signaIs in the phase detector is violated becomes higher. This results in exponentially
increasing propagation delay and may drive the circuit into a metastable state. Although,
careful design and layout of the D-Iatches can be used to minimize this effect, it cannot be
eliminated entirely [13]. The probability of failure is usually characterized by a Mean
Time-Between Failure (MTBF) measure which can be approximated in terms of the VDL
design parameters as follows:
(3.21)
Here Tf is the period of the clock triggered oscillator, "C, td and tsu is the time constant,
maximum propagation delay and setup time of the D-Iatch, respectively, Ris the rate at
which the data changes and Tw is the metastability window parameter expressed in
seconds [14][15]. Here Tw is defined as the minimum time difference between the rising
edge of the clock and data signals such that no metastability effect occur. In the case of our
Jitter Characterization for Time Domain Parameter 54
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
component-invariant VDL, R can be expressed as ;T since the metastability event can
only occur within the time ~T. Therefore, (3.21) can be written as
(3.22)
(3.23)
One can observe from (3.22) that the MTBF will improve with a larger Tf and smaller
metastability window Tw' Unfortunately, the MTBF decreases with finer timing resolution
~T.
As a first-order approximation, the change in MTBF can be expressed as
IÙMTBFI ::::: ù(~T)MTBF ~T
For a change of ~T =20 ps to ~T =15 ps, we expect to see I~MTBFI::::: 25% . ThisMTBF
supports, at the very least, what we have experimentally observed.
3.8.2 . Resolution Iimited by noise
Another limiting factor is the internaI noise from the power supply and substrate
that couples in from the analog and digital grounds of the circuit [16]. The variation in the
delay for a single buffer due to a change in power supply is summarized in Figure 3.35.
Although the sensitivity of a single delay cell to a power supply variation is quite small,
this error will accumulate as more stages are incorporated into the design. Clearly in order
to obtain high resolution, the power supply must be relatively clean during the test phase.
In practice, this can be achieved by limiting the electronic activity to only those cells that
are under test.
Jitter Characterization for Time Domain Parameter 55
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
27.5Q---,------,--~-.....,..--r_-_r_-___,
1.B21.B1.72 1.74 1.76 l.7BPower supply voltage M
1.725 '---_--'-__...1....-_---'-__-'-__'---_--'-_------'
1.6B
27
25.5
";ilQ.
;: 26.5iC'c$
~
~
~
~ 26C:I
Figure 3.35 Delay versus power supply
3.8.3 - Noise free clock
Although this design does not require a jitter-free dock during calibration, it does
require a dean dock in order to perform a measurement during its measurement phase.
This is a fundamental constraint of this design.
3.9 - Summary
ln this chapter, a novel circuit technique was described which can overcome the
drawbacks of the present state-of-the-art circuit techniques for measuring jitter. As a first
proof of concept, the design was implemented and tested using a 0.18 ~m CMOS IC as
weIl as an Altera MAX7000 FPGA. However, like aU circuits, this particular design is
limited by latch metastability and dock and power supply noise issues.
Jitter Characterization for Time Domain Parameter 56
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
Chapter 4 - Jitter Characterization for
Frequency Domain
Parameter
4.1 - Introduction
As described in the previous chapter, jitter is typically described in terms of its
time domain characteristics. Another way of characterizing jitter is to describe its
frequency domain distribution. In this chapter, the method and the algorithm for frequency
domain characterization will be described. Using time-domain measurements made with
the prototype IC of the previous chapter, an example phase spectrum will be provided.
Subsequently, a prototype FFf core was designed and fabricated in a 0.35 ~m CMOS
process to aid on-chip signal processing. Circuit details will be provided in this chapter.
Finally, design limitations will be described.
4.2 - Frequency Characterization Method
Timing jitter can be modelled as a noise signal phase-modulating a perfect digital
signal as shown in Figure 4.1. Here a single sinusoidal signal is seen modulating a jitter
free digital signal. The deviation of the edge position of the digital signal from its ideal
position is based on the instantaneous value of the modulating signal. In other words,
Jitter Characterization for Frequency Domain Parameter 57
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
samples of the modulating waveform give rise to the phase modulated or jittery signal.
Assurning that the average test time per sample is Ttest-per-sample, as described by (3.15),
the component-invariant VDL can sample the input signal at a frequency of
F s "'"TI. Further assume that the highest frequency component in the jittertest - per- sample
signal is less than Fs/2, then a Discrete Fourier Transform (DFT) or Fast Fourier
Transform (FFT) [17] of the jitter signal can be used to approximate the frequency
spectrum of the jitter. As shown in Figure 4.2(a), the sampling rate is high enough so that
no frequency aliasing will occur. However, if this condition is not met as shown in Figure
4.2(b), aliasing effects will occur and distort the spectral distribution. It is therefore
important to have sorne idea of the spectral distribution of the jitter that one is
investigating in order for this approach to be effective.
Phase Modulation
---.1 X 1-----.
Input Signal(Jitter-free)
-Modulated Signal '(Jittery Signal)
~Modulating Signal
(noise)
Figure 4.1 Phase modulation by noise
Jitter Characterization for Frequency Domain Parameter 58
Circuits for Time and Fregeuency Domain Characterization of Jitter
(a)
(b)
Antonio Chan
Figure 4.2 Effect of (a) higher sampling rate (b) lower sampling rate
4.3 - Experimental Result Using VOL Circuit
To demonstrate the ability that frequency domain characterization can be
performed, an FFI can be performed on the time domain data obtained from the
component-invariant VDL circuit. In Figure 4.3 we compare the spectral distribution of a
sinusoidal phase-modulated dock signal synthesized by a Teradyne A567 mixed-signal
tester and sampled with a component-invariant VDL circuit with its ideal spectral
distribution. Specifically, a 1.56 MHz dock signal was generated from the tester with an
equivalent phase modulation from a 90.3069 Hz sinusoidal signal having a 1 V amplitude.
Jitter Characterization for Frequency Domain Parameter 59
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
The resulting spectrum X(n) is shown with a dotted line in Figure 4.3 as a function of the
FFI bin index. This signal was then synthesized using the A567 tester and applied to the
input of a component-invariant VDL tuned to a time resolution of 18.9 ps. Subsequently,
4096 samples were captured at an effective sampling rate of 16.0825 kHz and an FFI was
then performed on the sample set. The resulting spectrum yen) represented by a solid line
is also shown in Figure 4.3. As is evident, the results agree reasonably well. The difference
between the actual and expected outputs is due to the jitter contributed by the tester and
the on-chip VDL.
FFT on Phase DataOr:-----,-----,-----r----r----,.------,-----.-----.
-10
-20 ~X(n)
-30 ...--- yen)
-40
QJ -50
" -60
-70
-00
-90
-100
50 100 150 200Bin
250 300 350
Figure 4.3 A comparison of the frequency spectrum of asinusoidal distributed jitter before and after the VOL
Jitter Characterization for Frequency Domain Parameter 60
Circuits for Time and Fregeuency Domain Characterization of Jitter
4.4 - Exploiting Hardware Requirement
4.4.1 . Discrete Fourier Transform Aigorithm
Antonio Chan
As shown from the previous section that FFf can be used to extract the frequency
characteristics of a jittery signal, let us exploit the hardware requirement of this signal
processing by first looking at a simple way of implementing the FPI' algorithm on
hardware. For a discrete time signal x(n), X(k), the DPI' of x(n), can be described as
N-l~ -j2rcknlN
X(k) = ~ x(n)e ,k = 0, 1,2, .... , N-1
n=O
In general, for x(n) = xR(n) + jx](n) ,X(k) = XR(k) + jX](k) can be expressed as
For real signal x(n) = xR(n), X(k) can be simplified as
N-l
[2nkn]XR(k) = L x(n)· cosN"'
n=O
N-l
[. 2nkn]X](k) =- L x(n)· smN"'
n=O
(4.1)
(4.2)
(4.3)
(4.4)
(4.5)
By comparing (4.4) and (4.5), the DPI' algorithm can be easily implemented in hardware.. 2nkn . 2nkn
Smce cos-y,r- and smN"' are always the same for the same k, n and N, these can be
easily implemented using lookup table in sorne memories. The main hardware that is
required is a single adder and a single multiplier.
Jitter Characterization for Frequency Domain Parameter 61
Circuits for Time and Fregeuency Domain Characterization of Jitter
4.4.2 • Circuit Implementation
Antonio Chan
Figure 4.4 shows the block diagram of the circuit implementation of a 64-point
DFf algorithm. The circuit can be divided into five blocks: ROM, RAM, Control,
Multipler/Adder and Output.
clk
resel
binnum
oulmode
clk
resel
dalain
clk
resel
inmode
16/ romdalaROM
/
13/v selrom
6// lalchoul
MULT/ADD2~
OUTPUTclearsum /CONTROL
6/ selsigclk resel clk resel
16/selmux
RAM/ ramdala
Figure 4.4 Main Blacks
synbil
realdata
imgdala
a) ROM Circuit
The sine and cosine coefficients shown in (4.4) and (4.5) are pre-calculated using
MATLAB and stored on the 16 bit x 8192 word ROM which can be synthesized using
standard logic. Selrom is the address select lines controlled by the controller that selects a
particular sine or cosine coefficient (labelled as 'romdata') as shown in Figure 4.4.
Jitter Characterization for Frequency Domain Parameter 62
Circuits for Time and Fregeuency Domain Characterization of Jitter
b) HAM Circuit
The detail of the RAM circuit is shown in Figure 4.5.
Antonio Chan
clk
reset
datain
inmode
selsig
clk
reset
ParallelSERIAL·TO·PARALLEL 16 Data
/
SHIFT REGISTER /
16RAM /
addr 6/
/
6/ read_enable/ RAM
CONTROLLER write_enable
clk_
dataout
Figure 4.5 RAM Block
The internaI RAM is from a celllibrary while the rest of the circuit is synthesized from
standard logic. The input data is first loaded through a 16-bit serial-to-parallel shift
register into a 16 bit x 64 word RAM after a reset condition. The serial-to-parallel
conversion is to minimize the Input/Output (1/0) pin counts on the chip. The small
controller is used to control the read and write action to avoid read-write conflict. The
following table summarizes the read-write action:
Table. 6· Input Mode Configuration
inmode ramfull input enable output enable
o(write) o(not full) 1 (write data to RAM) 0
1 (read) o(not full) 1 (write data to RAM) 0
o(write) 1 (full) 0 0
1 (read) 1 (full) 0 1 (read data from RAM)
When 'reset' and 'inmode' is low (i.e. attempting to write data into RAM), the RAM
controller checks to see if the RAM is empty. If the RAM is empty (i.e. "ramfull" is low),
'write_enable' becomes high (i.e. write action is active) and the serial-to-parallel shift-
Jitter Characterization for Frequency Domain Parameter 63
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
register starts shifting the 16-bit word into the RAM. The addressing of the RAM ('addr')
is incremented automatically from 0 to 63. This addressing is controlled by the RAM
controller. The write action will continue until the RAM is full (i.e. write action is
completed). When write action is completed, 'ramfull' will go high and "write_enable"
will go low (i.e. write is deactivated until another reset is triggered).
When 'inmode' is high (i.e. attempting to read data from RAM), the controller checks to
see if the RAM is full. If the RAM is full, 'read_enable' becomes high (i.e. read is
activated). The RAM address lines ('addr') now takes the addressing from 'selsig' which
is the address of the data to be read. If RAM is not full and read is requested, read action
will not start until the write action is completed.
c) Multiplier and Adder Circuit
After the data are loaded into the RAM, DPI' algorithm can be performed through the
multiplier and adder. In order to preserve arithmetic precision, the multiplier and adder
have 24-bit data width output instead of 16-bit. The internaI data path of the
Multiplier/Adder is shown in Figure 4.6. The 'Addbits' block first patches zeros to widen
the data widths to ensure precision during arithmetic operation. The small controller
controIs the 'c1earsum' signal which c1ears the content of the registers of the adder and the
'reset' signal. The calculated result is then latched out as a 24-bit wide data. The data
representation is summarized as shown in Table 7.
16 32
clk clk
reset reset
Figure 4.6 MultlAdd Black
Jitter Characterization for Frequency Domain Parameter 64
Circuits for Time and Fregeuency Domain Characterization of Jitter
Table. 7· Data Representation
Antonio Chan
Data Width Format
16 bits _20 + 2-1+ 2-2+ ........ + 2-14 + 2-15
24 bits 20 2-1 2-2 T 14 2-15 T 30 T 31- + + + ........ + + + ........ + +
40 bits 28 27 20 2-1 2-2 2-14 2- 15 2-30 2-31- + + ........ + + + + ........ + + + ........ + +
24 bits 28 27 20 2-1 2-2 2-14 2-15- + + ........ + + + + ........ + +
d) Main ControUer Circuit
A main controller (shown in Figure 4.4) is used to control the addressing of the ROM and
RAM during input and output condition. 'outmode' controls the output mode of the design
as summarized in Table 8. 'binnum' specifies the frequency bin to be calculated (when
outmode is set to 0). 'selmux' specifies whether the output is the real or imaginary part of
the bin. When 'selmux' is low, the output data is the real part of the bin and when 'selmux'
is high, the output data is the imaginary part of the bin. 'selsig' is the required address
location for the RAM during a read action. 'selrom' is the required address location for the
ROM during read and write action. 'clearsum' clears the content of the multipler/adder.
'latchout' latches data to the output module.
Table. 8 • Output Mode configuration
outmode 0 1
Action Calculates the real and imaginary Calculates aIl the real and imagi-values of one bin based on binnum nary values of aIl the bins
e) Output Circuit
The result is presented serially as the real and imaginary part described in (4.4) and (4.5).
As a feature of the design, the output can be in an increasing value of 'k' from 1 to 64
described in (4.4) and (4.5) or a selected value of 'k'. The latter is controlled by setting an
external input 'binnum' . The incoming data is shifted serially out to either
Jitter Characterization for Frequency Domain Parameter 65
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
'realdata'(selmux is low) or 'imgdata' (selmux is high) while 'synbit' is low during valid
output data.
4.4.3 - Experimental Result from DFf leFigure 4.7 shows the chip rnicrograph of the implementation fabricated on a 0.35
!lm CMOS process. Most of the layout of this design is generated using automatic place
and-route tool using standard cells. The relative size of the component is summarized in
Table 9. The design is mostly occupied by interconnects.
Figure 4.7 FFT Chip Micrograph
Jitter Characterization for Frequency Domain Parameter 66
Circuits for Time and Fregeuency Domain Characterization of Jitter
Table. 9 • Component Size for DFf Chip
Component Size
ROM 0.46 mm:l
Output 0.02mm2
Mult/Add 0.99mm2
Input 0.06mm2
RAM 0.17 mm2
Controller 0.13 mm2
Total 1.83 mm2
Antonio Chan
The algorithm used was first simulated on MATLAB under lirnited precision
condition. A two-tone signal generated from MATLAB and passed through the algorithm.
Figure 4.8 shows the simulated result. The noise floor is the limited precision of the
arithmetic operation. The circuit was also simulated with the same two tone signal
generated from MATLAB. The result shown in Figure 4.9 correlates with the MATLAB
simulation. The fabricated IC was also tested with the same two tone signal as the input.
The same plot as shown in Figure 4.9 was obtained.
Jitter Characterization for Frequency Domain Parameter 67
Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
FFf on 16-bit signal using designed FFf algorithmo .
-20 , ;. .; , ..· . . .· . . .· . . .· . . .· . . .· . . .· . . .· . . .-40 . . ~ ; ' ~ .· . . .· . . .· . . .· . . .· . . .· . . .· . . .· . . .-60 . · .,..............................................
-80 : ~ ~ : ~ '" .
. .-100 : , ; : : ... . . . ... ... .
" .
70605040302010
-140 L-__-'-__---1 ...1..-__--L. ~__-'-__----'
oSin
Figure 4.8 DFT algorithm from MATLAB
FFf result from Chip: Seriai ln - Seriai OutOr-------,----,..-------,----r-------,----,..-----,
-20 " .
-40 ; ;. ;. .:.. . .· . . .· . . .· . . .· . . .· . . .· . . .· . . .· . . .· . . .!g -60 : : : : : ..
-80 .
-100 ..: : .. .. .
70GO5040302010
-120 L...-___'_ L-___'_ ~___'_ L-__--'
oSin
Figure 4.9 DFT algorithm from chip
Jitter Characterization for Frequency Domain Parameter 68
Circuits for Time and Fregeuency Domain Characterization of Jitter
4.5 - Limiting Factors
4.5.1 • Effective Sampling Rate
Antonio Chan
As stated in the previous section, the sampling rate of the modulating signal (i.e.
the jitter) is set by the frequency at which the phase of the digital signal are being taken.
The highest sampling rate one can obtain is to collect aIl the phase samples from cycle to
cycle. However, due to test time requirement, this may not be the case. Test time of each
sample is
(4.6)
where Tf is the period of the clock oscillator and N is the number of oscillations for the
data oscillator before phase detect. For maximum test time,
(4.7)
where i1T is the timing resolution. Therefore, the maximum sampling rate depends on N.
However, if one can predict or limit the amount of jitter (i.e. the size of N), the maximum
number of oscillations before phase detect occurs can be predicted. Henee, the effective
sampling rate can be increased. Table 10 summarizes the relationship between effective
sampling rate and test time.
Table.l0· Effective Sampling Rates
Max. Peak-to-Peak Jitter Test Time Equivalent Max. Sampling Rate
2 ns 145 ns 6.9 MHz
1 ns 73 ns 13.8 MHz
500 ps 36ns 28 MHz
250ps 18 ns 55 MHz
Jitter Characterization for Frequency Domain Parameter 69
Circuits for Time and Fregeuency Domain Characterization of Jitter
4.5.2 - Silicon Sizing
Antonio Chan
As the design space is mainly constraint by interconnect, the same design using a
0.18 J..lm standard CMOS process has 61ayers ofmetal will be much sma11er as opposed to
0.35 J..lm standard CMOS process which has only 3 layers of metal.
4.6 • Summary
ln this chapter we developed an algorithm for capturing the frequency-domain
description of jitter from a set of time samples obtained from the component-invariant
VDL. In addition, another IC was implemented that executed a 64-point DFf algorithm to
aid in the post-processing of the time samples.
Jitter Characterization for Frequency Domain Parameter 70
Circuits for Time and Fregeuency Domain Characterization of Jitter
Chapter 5 - Conclusion
5.1 - Conclusion
Antonio Chan
A high-resolution timing measurement circuit based on a component-invariant or
single-stage VDL structure is developed. This circuit is synthesizable whereby precise
element matching is not required. The design was implemented on an FPGA as well as a
eustom IC as a first proof of concept. Experimental results confirm the validity of this
approach. In the case of the FPGA implementation, the design requires about 128
macrocells. In the case of an IC implementation in a 0.18 micron CMOS process, the
circuit occupies a total silicon area of 0.12 mm2, while achieving a 18.9 ps timing
resolution. Although the design is not limited by precise element matching, the frequency
characteristics of the D-type flip-flop limits the maximum timing resolution acheivable.
Frequency characterization method and additional circuit was also implemented
on a 0.35 pm CMOS process which occupies a silicon area of 1.83 mm2. If this design
were to be imported to 0.18 pm CMOS process, it would occupy a much smaller space.
The two circuits together show the validity of the Jitter Measurement Unit
whereby pico-second timing and frequency measurements can he achieved with a small
silicon size using synthesizable logic.
Conclusion 71
Circuits for Time and Fregeuency Domain Characterization of Jitter
5.2 - Future Works
Antonio Chan
Since both the DPI and component-invariant VDL designs are synthesizable, it
would appear that one element of the future work would include integrating the two
designs together into a single le. In addition, it would be useful to have the ability to
provide RMS, peak-to-peak and frequency-domain extraction capability aIl on-chip in
order to have a complete Jitter Analyzing Circuit.
Conclusion 72
Circuits for Time and Fregeuency Domain Characterization of Jitter
References
Antonio Chan
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
M. Mota, J. Christiansen, "A four-channel self-calibrating high-resolutiontime to digital converter", IEEE International Conference on Electronics,Circuits and Systems, pp 409-412, 1998
M.S. Gorbics, 1. Kelly, K.M. Roberts, R.L. Sumner, "A high resolutionmultihit time to digital converter integrated circuit", IEEE Transactions onNuclear Science, vo1.44 no.3, pp 379 -384, 1997
Y. Arai, M. Ikeno, M. Sagara and T. Emura, "Time memory cell VLSI forthe PHENIX drift chamber", IEEE Transaction on Nuclear Science, VoIA5no.3, pp 735-739, 1998
E.Raisanen-Rnotsalainen, T. Rahkonen, J. Kostamovaara, "Time intervaldigitization with an integrated 32-phase oscillator", IEEE InternationalSymposium on Circuits and Systems, vo1.5, pp 673 -676, 1994
S. Sunter, A. Roy, "BIST for phase-Iocked loops in digital applications",Proc. IEEE International Test Conference, pp. 532 -540, 1999
N. Abaskharoun and G. W. Roberts, "Circuits for on-chip sub-nanosecondsignal capture and characterization," Proc. IEEE Custom IntegratedCircuits Conference, pp. 251 -254,2001
P. Dudek, S. Szczepanski, 1.y. Hatfield, "A high-resolution CMOS time-todigital converter utilizing a vernier de1ay Hne" IEEE Journal ofSolid-StateCircuits, vol.35 no.2, pp. 240 -247, 2000
B.D. Kulp, "Testing and characterizing jitter in 100BASE-TX and 155.52Mbit/s ATM devices with a 1 Gsamples/s AWG in an ATE system", Proc.IEEE International Test Conference, pp. 104 -111, 1996
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Circuits for Time and Fregeuency Domain Characterization of Jitter Antonio Chan
[9] A. Chan and G.W. Roberts, "A synthesizable, fast and high-resolutiontiming measurement device using a component-invariant vernier delayline", Proc. International Test Conference, pp 858 -867, 2001
[10] A. Chan and G.W. Roberts, "A Deep Sub-Micron Timing MeasurementCircuit Using a Single-Stage Vernier Delay Line", Proc. IEEE CustomIntegrated Circuits Conference, pp 77-80,2002
[11] Teradyne Inc., "High-Speed Digital Programming", Tester Manual,Version 6.2, 1996
[12] WAVECREST Corporation, "User's Guide and Reference Manual forDTS-2079, DTS-2077, DTS-2075", 207900-01 REV A, 2000
[13] T.A. Jackson and A. Albicki, "Analysis of metastability operations in Dlatches", IEEE Transaction on Circuits and Systems, Vo1.36 no. 11, pp1392-1404, 1989
[14] T.C. Tang, "Experimental studies of metastability behavior of sub-micronCMOS ASIC flip flops", Proc. IEEE International ASIC Conference andExhibit, pp P7 -4/1-4, 1991
[15] C. Foley, "Characterizing Metastability", Proc. IEEE InternationalSymposium on Advanced Research in Asynchronous Circuits and Systems,pp 175 -184,1996
[16] F. Herzel and B. Razavi, "A study of oscillator jitter due to supply andsubstrate noise", Proc. IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing, Vo1.46 no.1, pp 56-62, 1999
[17] J. Proakis and D. Manolakis, "Digital Signal Processing: Principles,Algorithm, and Applications", Prentice Hall, 3rd Edition, 1996
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