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Page 1: circuitos translineares

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Page 2: circuitos translineares

Analysisand Synthesisof Static Translinear Cir cuits

Bradley A. Minch

Schoolof ElectricalandComputerEngineeringCornell University

Ithaca,NY 14853-5401

[email protected]://www.ee.cornell.edu/˜minch

March 25,2000

Cornell UniversityIthaca,NY

Page 3: circuitos translineares

©2000Bradley A. Minch

All RightsReserved

Page 4: circuitos translineares

Analysis and SynthesisofStatic Translinear Cir cuits

Bradley A. Minch

Schoolof Electrical and Computer EngineeringCornell University

Ithaca,NY 14853–5401

[email protected]

March 25,2000

AbstractThisreport describestheclassof static translinearcircuits, which arecapableof accuratelyimplementinga wide rangeof static nonlinearrelationships in thecurrent signal domain,such asproducts, quotients, fixedpower-law relationships, vectormagnitude,andrationalfunctions. After a brief historical accountof the emergenceof the class of translinearcircuits, we examinetherepresentationof informationin translinear circuitsandsystems.Then,wedescribethetranslinear principleanditsapplicationto theanalysis andsynthesisof translinear-loop circuits, illustrating the processes with several examplecircuits. Wethendescribetheoperation andimplementationof a translinear-circuit primitivecalledthemultiple-inputtranslinearelement(MITE). From such elements, we build MITE networks,a class of low-voltagetranslinear circuitsthat is equivalentto theclassof translinear-loopcircuits. We describe intuitively the operation of MITE networks. We also describe howto analyze and synthesize such circuits, illustrating these processes with several examplecircuits.

1 Translinear Cir cuits: What’s in a Name?

I¦n1975,BarrieGilbert coinedtheword translinear todescribeaclassof circuitswhoselarge-signal

behavior hingeson the extraordinarily precise exponentialcurrent–voltagecharacteristic of thebipolartransistor andtheintimatethermalcontactandclosematchingof monolithicallyintegrateddevices [1]. The functionsperformed by these fundamentallylarge-signal circuits—includingmultiplication[2–7], widebandsignalamplification[3,8],andvariouspower-law relationships[9]—were utterly incomprehensible from the customary linear-circuit picture of the bipolar transistor

1

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2

asa linearcurrent amplifierwhose key property is its forward current gain, § . At thesametime,Gilbert also succinctlyenunciateda general circuit principle, the translinear principle (TLP), bywhichwecananalyzethe(steady-state)large-signalcharacteristicsof suchcircuitsquickly, usuallywith only a few linesof algebra,by considering only thecurrentsflowing in thecircuits.

Theword translinear derives from acontractionof onewayof statingtheexponentialcurrent–voltagecharacteristic of thebipolartransistor thatiscentralto thefunctioningof thesecircuits—thatis, thebipolartransistor’s transconductanceis linear in its collectorcurrent.Gilbert also meanttheword to convey thenotion of analysis and design techniques(e.g., the translinear principle) thatbridgethegapbetweenthewell-establisheddomainof linear-circuitdesignandthelargelyuncharteddomainof nonlinear-circuitdesign, for whichpreciouslittle canbesaid in general[10–12]. Asweshall seein Section4, thetranslinearprincipleis essentially a translation throughtheexponentialcurrent–voltagerelationship of a linear constraint on the voltagesin a circuit (i.e., Kirchhoff ’svoltagelaw) into a product-of-power-law constraintoncollectorcurrentsflowing in thecircuit.

SinceGilbert coined the word translinear, the translinear principle has beenthe basis of aplethora of useful nonlinearcircuits, includingwidebandanalogmultipliers [13–15], translinearcurrentconveyors[16–18], translinearfrequency multipliers[19–22], operationalcurrentamplifiers[23–26], RMS–DC converters [27–32], and vector-magnitudecircuits [28,33–36]. In the 1980s,Evert Seevinck [37,38] madesignificantcontributionsto thestateof theart of translinear-circuitdesign by developingsystematictechniquesfor theanalysis andsynthesis of these circuits.

Sincethemid-1990s, therehasbeenagrowing interest in translinearcircuits, primarily becauseof thedevelopmentof the class of dynamictranslinear circuits, which hadits origins in 1979inthework of Robert Adams[39]. Althoughhedoesnotappearto have madea connectionbetweenhis own ideasandthegrowing bodyof work on translinearcircuits, Adamsproposeda methodofimplementinglarge-signal–linear, continuous-time filters using linearcapacitors, constantcurrentsources, and translineardevices, which hecalledlog-domainfiltering, because all of thefilteringoccurred on log-compressed voltagestatevariablesusing translineardevices. Theconceptof log-domainfilteringremainedin obscurity for over adecade,only to beindependentlyrediscovered bySeevinck. In 1990,Seevinck presentedafirst-orderfilter, whichhedubbedacompandingcurrent-modeintegrator [40]. Unfortunately, it appearsthatneitherSeevinck norAdamshadaclearideaofhow to generalizetheir ideasto implementfilters of higherorder. In 1993,encouragedby Adamsto pursuetheideaof log-domainfiltering,DougFrey introducedageneral methodfor synthesizinglog-domainfiltersof arbitrary orderusingastate-spaceapproachandhepresentedahighly modulartechniquefor implementingsuchfilters [41].

Jan Mulderetal. coinedthephrasedynamictranslinearcircuitsandhavemadetheclearest con-nectionbetweentranslinearcircuitsandlog-domainfilters[42–45]. They haveextendedSeevinck’stranslinearanalysis andsynthesis methodologyto encompass dynamicconstraintsbasedon whatthey have calledthedynamictranslinear principle, with whichwe canexpress capacitive currentsembeddedwithin translinear loopsdirectly in terms of productsof the currents flowing throughtranslinear devicesandtheir time derivatives. Dynamic translinear circuit techniqueshave beensuccessfully appliedto thestructureddesign of both linear dynamicalsystems(e.g., log-domainfilters [41,46–53]) and nonlineardynamicalsystems(e.g., RMS-DC converters [30–32], oscilla-

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3

tors[54–57], phasedetectors[58], andphase-lockedloops[59,60]). Althoughdynamictranslinearcircuits are beyondthescopeof this report, theprinciplesthatwe shall develop directly extendtoandform afoundationfor theanalysis and synthesis of thisemerging class of circuits.

2 The Ideal Translinear Element

Figur¨

e1a shows a circuit symbol for an idealtranslinear element(TE). This symbol,which hasagate,an emitter, anda collector, is commonlyused in powerelectronicsto representan insulated-gatebipolar transistor (IGBT), whichisahybrid bipolar/MOSdevicethatcombinesthehigh inputimpedanceof an MOS transistor andthe larger current-handlingcapabilitiesof a power bipolartransistor. Althoughit may be possible to build translinear circuits with IGBTs, that possibilityis not what we arepresently considering. Instead,we use the circuit symbol shown in Fig. 1afor two reasons. First, the idealTE shouldhave thenearly inviolateexponentialcurrent–voltagerelationship of the bipolar transistor andthe infinite input impedanceof the MOS transistor; thehybrid symbolof Fig.1aishighlysuggestiveof precisely thismixtureof bipolarandMOSqualities.Second,eventhoughtranslinearcircuits were originally implementedwith bipolartransistors, wecanalso implementsuchcircuitsusing subthreshold MOS transistors. By using a symbol for theidealTE thatresemblesbothtypesof transistors, weremindourselvescontinuallyof this fact.

We shall assume that the idealTE producesa collector current, I , that is exponentialin itsgate-to-emittervoltage,V , and is given by

I ©~ª Is« e¬ V ­ UT , (1)

where Is isapre-exponentialscalingcurrent, ª is adimensionlessconstantthatscalesIs« pr® oportion-ally, ¯ is adimensionless constantthatscalesthegate-to-emittervoltage,V , and UT is thethermalvoltage,kT° q. To demonstratethattheidealTE is translinear in thefirst senseof thewordthatwediscussed in Section1, we cancalculateits transconductanceby simply dif ferentiatingEq. 1 withrespectto V to obtain

gm± © ²I²V

© ª Ise¬ V ­ UT ³UT

© ¯ I

UT´Bµ

Figures1b through1e show five practicalcircuit implementationsof the idealTE. The firstof these TEs is thepn junctiondiode,shown in Fig. 1b. Althoughtheforward-biased diodedoeshaveanexponentialcurrent–voltagecharacteristic, it isatwo-terminaldeviceanddoesnot,strictlyspeaking,haveatransconductance.Moreover, diodesseldomactuallyappearin translinearcircuits;instead,for thesakeof device matching,we almost invariably use diode-connectedtransistors inplaceof diodes. Nonetheless, for simplicity, many presentationsof thetranslinearprinciplebegin

Page 7: circuitos translineares

I

V

·

I

V

I

V

V

I

V

(a)(b)

(c) (d)

(e)

Figure 1: Translinearelements(TEs). (a) Circuit symbol for an idealTE. Suchadeviceproducesa current, I , that is exponentialin its controlling voltage,V . Parts b throughf show five practicalTE implementationscomprising(b) adiode,(c) annpnbipolartransistor, (d) asubthresholdMOStransistor with its sourceandbulk connectedtogether, and (e) a compoundTE comprisingannpnandapnpwith theiremittersconnectedtogether. Of course, for theTEsshown in partsc andd, theappropriatecomplementarytransistorsarealso TEs.

by considering aloopof diodes. For thediode,¹ correspondsto therelativeareaof thepn junctionand º is typically very nearlyunity.

The bipolar transistor, shown in Fig. 1c, biased into its forward–active region is consideredby most peopleto be the quintessential TE. The bipolar transistor commonlyexhibits a preciseexponentialrelationship betweenits collector current and its base-to-emittervoltageover morethaneightdecadesof current. For thebipolar transistor, ¹ correspondsto therelative area of theemitter–basejunctionand º is typicallyclosetoone.Themainlimitationof thebipolartransistorasaTE is theexistenceof afinite basecurrent, which is oftenwhatlimits therangeof usablecurrentlevels in bipolartranslinearcircuits.

The subthreshold MOS transistor with its source and bulk connectedtogether, as shown inFig. 1d,biased into saturation also hasanexponentialcurrent–voltagecharacteristic. In this case,¹ correspondsto theW» L ratioof theMOStransistor and º is equalto ¼ , which is theincrementalcapacitive-dividerratiobetweenthegateandthechannel.Therequirementthatthesourceandbulkbeshortedtogetherstemsfrom thefactthatthegateandsourcedo nothave thesameeffecton theenergy barrier(i.e., thesource-to-channelpotential)thatcontrols theflow of current in thechannel.The sourcepotentialdirectlyaffectsthis barrierheight,whereasthegatecouplescapacitively into

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5

thechannelandonly partially determines(i.e., with a weightof ½ ) thechannelpotential.Thebulkalso couplesinto thechannelcapacitively andpartially determinesthechannelpotential(i.e., withaweightof 1 ¾U½ . By connectingthesourceandbulk together, wecanusethebulk in opposition tothesourcetoreducethesource’sneteffectivenessat controllingthebarrierheighttomatchpreciselytheeffectiveness of thegate.

In themajority of bulk CMOStechnologies, wefabricateonetypeof MOStransistor (i.e., eithernMOS or pMOS ) in a global substratethatwe maintainat a singlecommonpotential,while wefabricatetheothertypeinsideof isolatedlocalsubstrates, calledwells thatwemayhaveat dif ferentpotentials. In such technologies, we canonly connectthe source andbulk togetherfor the typeof transistor that is fabricatedinsideof thewell; for instance,in ann-well CMOS technology, thepMOS transistors are fabricatedin n-wells. By fabricatingpMOS transistors in separatewells,we canconnecttheir sourcesandbulks togetherandsimultaneously have differentTEs operatingwith different source potentials. In such a technology, we fabricateall of the nMOS transistorsinsidea global p-typesubstrate;hence,if we must short all of thesourcesandbulks together, wecannotoperatedifferentTEs with their sourcesat differentpotentials. Fortunately, as we shall seein Section4, for certain translinear-looptopologies, wedo notneedto connecttogetherthesourceandbulk of all of theMOStransistors within thetranslinearloops.

We canconstruct a variety of compoundTEs by combiningtwo or more transistors in variousways. Figure 1e shows onesuch compoundTE, comprising an npn transistor and a pnp bipolartransistor with theiremittersconnectedtogether. For thisTE, thecontrolling voltageis thevoltagedifferencebetweenthe base of thenpn andthatof thepnp andtheoutputcurrent is availableatthecollectorof eithertransistor. Also, ¿ correspondsto thegeometric meanbetweenthe relativeemitterareaof thenpnandtherelativeemitterareaof thepnpand ÀÂÁ 1

2.

3 Translinear SignalRepresentations

ranslinearcircuits are current-modecircuits, which meansthattheir inputandoutputsignalsarerepresentedas currents. Moreprecisely, we represent a dimensionless quantity, z, as theratio of asignalcurrent, IzÄ , to aunit current, Iu. In otherwords, we defineanumber, z, by

z Å Iz

IuÆ .We call Iu the

Çunit current precisely because it is the current level that represents unity in our

numbersystem; that is, z Á 1 if and only if Iz Á IuÆ . The value of the unit currentultimatelydetermines the power dissipation, computationalthroughput,and the precision of a translinearanaloginformation-processingsystem. By allowing theunit current level to changeover time,wecanbuild computingsystemsthatcanadaptively tradecomputationalthroughputandprecision forpowerdissipation[61].

Therepresentationof signalsbycurrentsin translinearcircuitsissomethinglike afloating-pointnumberrepresentationin thedigital domain. For translinearcircuits, current signalsspana large

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dynamicrange(typically several decades), but noise restricts theprecision availableat any givensignal-currentlevel to acertainfinite fractionof thatcurrentlevel (i.e., givenby thenoise-to-signalratio (NSR)). The mannerin which thenoisecurrent scaleswith thesignal current dependson thetypeof noisethatispredominantin thesystem[62]. If whitenoiseispredominant,thenNSRscalesinverselywith thesquarerootof thesignalcurrent,sowecantradepowerconsumptionforprecision.On theotherhand,if 1È f noise dominatesthespectrum, thentheNSRis roughlyindependentofthesignal-current level, so wecannotobtainadditionalprecisionby increasingpowerconsumption.In thedigital domain,floating-pointnumberssimilarly spanalargedynamicrange,but becausethemantissa is representedby a finite numberof bits, theprecision for any given exponentis limitedto a constantfractionof two raisedto thatexponent.

Peoplenormallyeitherdonotconsider thevoltagesin translinearcircuits, whichareimplicitlylogarithmic representationsof thevariousinputandoutputsignals, or at most consider themto beof little importance.However, fromacomputationalpointof view, thevoltagesignalsin translinearcircuitsaredirectlyanalogous, in thedigital domain,to representationscalledlogarithmicnumbersystems [63–66], in which numbers are representedinternally by their binary logarithmsto somefinite precision. Many researchers [67–78]have proposed using logarithmic numbersystemsinspecial-purposedigital signalprocessorsfor applications, suchasdigital filtering,FFTcomputation,andcomputergraphics, whichtypically requirealargedynamicrangeandin whichoperationssuchasmultiplication,division, squaring,andsquare-rootingoccur more frequentlythando additionandsubtraction.

The appealof such logarithmic numbersystemsis that we can implementthe operations ofmultiplicationanddivisionusing onlyfixed-pointaddersandtheoperationsof squaringandsquare-rootingusingonly shifters. However, in such digital arithmeticunits, conversion betweenconven-tional numberformatsandthe logarithmic numberformat is quiteexpensive, typically involvinglarge lookuptables. Also, whereasmultiplicationand division are relatively inexpensive in suchsystems, additionand subtraction can only be approximatedand involve additional lookup ta-bles, making themquitecumbersome. By contrast, in translinear analoginformation-processingsystems, conversion betweenthe logarithmic(i.e., voltage)signal representationand the linear(i.e., current) signal representation is extremely inexpensive, requiring only a single translineardevice. Consequently, with translinearcircuits, operationslike multiplication,division,squaring,andsquare-rootingare inexpensive and theoperationsof additionand subtraction,which we canimplementsimply usingKirchhoff ’scurrent law on a singlewire,arealso inexpensive.

Because of the logarithmic relationship that exists betweenthe controlling voltageand theoutputcurrentof atranslineardevice,wemust ensurethatthecurrentsflowingthroughall translineardevicesremainstrictly positiveatall times. Inordertorepresentbothpositiveandnegativequantitiesby currents, we canfollow oneof two basic approaches. First, we canaddan offset current, IyÉ ,to a signal current, Iz, so thattheir sum, IzÄ'Ê IyÉ , remainpositive at all times, as shown in Fig. 2a.In this case, thesignal currentis a bidirectionalcurrent. Notethat theconditionthat Iz Ê IyÉ�Ë 0impliesthat Iz ËÍÌ IyÉ . Thus, while thereis no restriction on themagnitudeof positive valuesofIz, negative valuesof IzÄ cannotexceedthe magnitudeof the offset current, IyÉ . Second,we canrepresenta quantitythatcanbebothpositive andnegative as a differential current; that is, as the

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7

IzÎ

VzÎ

Ï

ÏVzÎ

IzÎ

VzÎIÐzÎ I

ÐzÎ

VzÎÏ ÑÏ Ñ

inputÒ

output

IÐyÓ

VyÓ Ï zIÐ

zÎ IyÓ Ô IzÎ IÐzÎ

IÐyÓ

IyÓ Ô IzÎVyÓ Ï z

input output

(a)

(b)

Ñ

Ñ

Figure 2: Translinear representationsfor quantitiesthat cantakeon both positive andnegativevalues. (a)The quantity, z, is representedby a bidirectionalcurrent, Iz, offset by anothercurrent,IyÉ , so that Iz Õ IyÉ�Ö 0. (b) Thequantity, z, is representedby adifferential current, Iz × I Øz Ù I Úz ,where I Øz Ö 0 and I Úz Ö 0.

differencebetweentwo strictly positive components, eachof which is representedindependentlyastheratioof asignalcurrent to theunit current,asshown in Fig.2b. In otherwords, werepresenta number, z, as z × zØ Ù zÚ�Û where

zØ × I ØzIÜu

Ö 0 and zÚ × I ÚzIÜu

Ö 0.

4 The Translinear Principle

In¦

thissection,weshall derivethetranslinear principlefor a loopof idealTEs andillustrateits usein analyzingtranslinear circuits. We shall thenconsider a loopof subthreshold MOS transistorswith their bulks all connectedto thecommon substratepotentialto determinehow thetranslinearprinciple ismodifiedfor such devicesby thebodyeffect.

Page 11: circuitos translineares

8

4

V4Þ

ß4

V5

5

I5

Ià6áV6 â

nVn

In

VNäNå

INæ

V3

I 3

3V

22

Iç 2

V1

1

Iè 1

Figure 3: A conceptualtranslinear loop comprising N ideal TEs. The large arrow shows theclockwisedirectionaroundtheloop. If aTE symbol’semitterarrow pointsin thedirectionoppositeto thatof thearrow, thenwe consider theelementa counterclockwise element. If a TE symbol’semitterarrow pointsinthesamedirectionasthelargearrow, thentheelementisaclockwiseelement.The translinear principle statesthat the product of the currents flowing through the clockwiseelementsis equalto theproductof thecurrentsflowing throughthecounterclockwiseelements.

4.1 Translinear Loops of Ideal Translinear Elements

Consider theclosed loopof N idealTEs, shown in Fig. 3. The largearrow shows theclockwisedirectionaroundtheloop. If theemitterarrow of aTE pointsin theclockwisedirection,weclassifytheTEasaclockwiseelement. If theemitterarrow of aTE pointsin thecounterclockwisedirection,weclassify theTEasacounterclockwiseelement.Letusdenoteby CW theset of clockwise-elementindicesandby CCW theset of counterclockwise-elementindices.

As we proceedaround the loop in the clockwise direction, the gate-to-emitter voltageof acounterclockwiseelementcorrespondsto avoltageincrease,whereasthegate-to-emittervoltageofa clockwise elementcorrespondsto a voltagedrop. Onewayof statingKirchhoff ’svoltagelaw isthatthesum of thevoltageincreasesarounda closed loopis equalto thesum of thevoltagedropsaroundtheloop.Consequently, by applyingKirchhoff ’svoltagelaw aroundtheloopof TEsshownin Fig. 3, we have that

n é CCW

Vnê@ën é CW

Vn. (2)

Page 12: circuitos translineares

9

By solving Eq. 1 for V in termsof I andsubstituting theresulting expression for eachVnê inì

Eq. 2,we obtain

n í CCW

UTî logInïnê Is ð n í CW

UTî logInêïn Is

. (3)

Assuming thatall TEs areoperating at thesame temperature,wecancancelthecommon factorofUT ñ î in all of theterms in Eq. 3 to obtain

nê í CCW

logInïnê Is ð n í CW

logInïnê Is

. (4)

Because logx ò log y ð logxy, we canrewrite Eq. 4 as

lognê í CCW

IÜnï

nê IÜs ð log

nê í CW

IÜnï

nê IÜs. (5)

By exponentiatingbothsidesof Eq. 5 we get

nê í CCW

Inïnê Is ð n í CW

Inïn Is« ,

whichwe canrearrangeto obtain

n í CCW

IÜnêïn ð I N

óCCWô õ NCW

ôs

nê í CW

IÜnêïnê , (6)

whereNCCW andNCWö denoterespectivelythenumberof counterclockwiseelementsandthenumber

of clockwise elements. Now, it is easy to seethat,if NCWö ð NCCW, thenEq. 6 reducesto

n í CCW

Inêïn ð n í CW

Inïn

, (7)

which has no remaining dependenceon temperature or device parameters. Equation7 is thetranslinear principle, whichcanbestatedasfollows.

In a closed loopof idealTEs comprising anequalnumberof clockwise andcounter-clockwise elements, theproductof the(relative) current densities flowing throughthecounterclockwise elementsis equal to the productof the (relative) current densitiesflowing throughtheclockwise elements.

If eachTE in theloophasthesamevalue ofï, thenEq. 7 becomes

nê í CCW

In ðï Nó

CCWô õ NCW

ônê í CW

In,

Page 13: circuitos translineares

10

I1

2

I3

(a)

I1 I2I3

Ixø Iyù

1 2

(b)

Figure 4: Two translinear-loopcircuits. (a)A simple circuit with onetranslinearloopcomprisingtwo clockwise elementsandtwo counterclockwise elementsarrangedin a stackedtopology. (b)A circuit with two overlappingtranslinearloopseachof whichcomprisestwo clockwise elementsandtwo counterclockwiseelementsarrangedin astackedtopology.

which, if NCWö ú NCCW, furtherreducesto

n û CCW

Inê ún û CW

In. (8)

Equation8 is animportantspecialcase of thetranslinearprinciple thatcanbestatedasfollows.

In a closed loopof identicalidealTEs comprising anequalnumberof clockwise andcounterclockwise elements, the productof the currentsflowing throughthe counter-clockwiseelementsisequaltotheproductof thecurrentsflowingthroughtheclockwiseelements.

Note that the derivation of the translinear principle just described canbe characterized asatranslation of a linear set of algebraic constraintson the voltagesin thecircuit (i.e., Kirchhoff ’svoltagelaw appliedaroundtheloopof Fig.3) intoaproduct-of-power-lawconstraintonthecurrentsflowingin thecircuit. Thischaracterizationof thetranslinearprincipleisonewaytostatethesecondconnotationof theword translinear originally intendedby Gilbert [1,10–12].

To illustratetheuseof thetranslinearprinciple,weshall analyzethetwotranslinear-loopcircuitsshown in Fig. 4. First, consider the circuit of Fig. 4a. This circuit hasa single translinear loopcomprisingfour identicalTEs, two of which facein theclockwisedirectionand two of which facein thecounterclockwisedirection.Inputcurrent I1 pas® sesthroughbothcounterclockwiseelements.Input current I2 pas® ses throughone of the clockwise elements. The outputcurrent, I3, passes

Page 14: circuitos translineares

11

throughtheotherclockwiseelement.Consequently, toanalyzethiscircuit, weapplythetranslinearprinciple,asstatedin Eq. 8, andwrite that

I 21 ü I2 I

Ü3,

whichwe easily rearrangeto obtain

I3 ü I 21

I2ý .

Thus, thecircuit of Fig. 4a is a squaring–reciprocalcircuit.Next, consider thecircuit shown in Fig. 4b. This circuit hastwo overlappingtranslinearloops,

eachof which comprisesfour identicalTEs with two in the clockwise directionand two in thecounterclockwise direction. By Kirchhoff ’s current law, we have that the outputcurrent, I3, isgiven by

I3 ü Ix þ Iy. (9)

In the first loop, input current I1 pas® ses throughboth counterclockwise elements. Intermediatecurrent Ix pas® sesthroughthefirst clockwiseelementandtheoutputcurrent, I3, (i.e., Ix þ Iy) passesthroughthesecondclockwiseelement.So, by thetranslinearprinciple,we have that

I 21 ü Ix I3,

which impliesthat

Ix ü I 2ý1

I3ÿ . (10)

In thesecondloop,input current I2 pas® ses throughbothclockwise elements. IntermediatecurrentIy� pas® ses throughoneof thecounterclockwiseelementsand theoutputcurrent, I3, passes throughtheothercounterclockwiseelement.So, by thetranslinearprinciple,we have that

I 22 ü Iy I3,

which impliesthat

Iy ü I 22

I3ÿ . (11)

Substituting Eqs. 10 and 11 into Eq. 9, wehave that

I3ÿ ü I 2

1

IÜ3þ I 2

2

IÜ3

,

whichwe canrearrangeto find thatI 23 ü I 2

1 þ I 22 .

By takingthesquare rootof bothsidesof theprecedingequation,we have thattheoutputcurrent,I3ÿ , is given by

I3 ü I 21 þ I 2

ý2 .

Page 15: circuitos translineares

12

I�

4

V4�

�4

V5

5

I5

I�6�V6 �

6�

nVn

In

VN�N

IN

V3

I 3

3V

2

2

I

� 2

V1

� 1

I 1

U1

U0

U 2

U3

U4

U5

Un�1

U6

UnUN��1

I�

n�

Un�Vn�Un��� 1 � n�

clockwise�element

In�

� n� Un�Vn�

Un��� 1

counterclockwise�element

(a) (b)

(c)

Figure 5: A translinear loop of subthreshold MOStransistors with their bulks tied to a commonsubstratepotential.HereVn refersto thegate-to-sourcevoltageof thenth MOS transistor andUn

refersto thevoltageonthenth nodereferencedto thecommonsubstratepotential.(a) A conceptualtranslinear loop comprising N subthreshold MOS transistors with their bulks tied to a commonsubstrate. (b) A clockwise elementis onewhose gate-to-sourcevoltageis a voltagedrop in theclockwise directionaroundtheloop. (c) A counterclockwiseelementis onewhose gate-to-sourcevoltageis avoltageincrease in theclockwisedirectionaroundtheloop.

4.2 Translinear Loops of Subthreshold MOSTransistors

Considertheclosedloopof N saturatedsubthresholdMOStransistorswhosebulksareall connectedto a commonsubstratepotential,shown in Fig. 5a. Here,Vnê representsthegate-to-sourcevoltageof thenth MOStransistor, andUn is thevoltageon thenth noderelative to thesubstratepotential.Again, the large arrow in Fig. 5a, indicatesthe clockwise directionaroundthe loop. As shownin Fig. 5b, we shall consider a clockwise elementto be one whose gate-to-source voltage is avoltagedrop in theclockwise directionaroundthe loop. As shown in Fig. 5c, we shall considera counterclockwise elementto be onewhose gate-to-source voltage is a voltageincrease in theclockwise directionaroundtheloop.

Recallthatthechannelcurrent, I , of an nMOStransistor, operating in subthreshold, is given by

I ��� I0e� Vg��� UT e� Vs� UT � e� Vd � UT , (12)

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13

where Vg! isì

the gate-to-bulk voltage,Vs« isì

the source-to-bulk voltage, Vd" isì

the drain-to-bulkpotential,# is theW$ L ratioof thetransistor, I0 is thesubthresholdpre-exponentialcurrent factor,% is the (incremental)capacitive divider ratio betweenthe gateand the channel,andUT is thethermalvoltage,kT$ q [79]. If the drain-to-source voltage is larger than about4UT, then thetransistor is saturated. Under these conditions, the secondterm in the parenthesis in Eq. 12 isnegligible comparedto thefirst one,which reducesEq. 12 to

I &'# I0( e)+* Vg�-, Vs.0/ UT,

whichhasnoremainingdependenceon thedrain-to-bulk potential.Thus, if thenth MOS transistor isa clockwise element,we have that

Inê &1# n IÜ0e2 * Un354 1 , Un376 / UT

8,

whichwe canrearrangeto find that

eUn3 / UT8 & eUn354 1 / UT

8 * # n I0

IÜnê . (13)

Equation13 expressesarecurrencerelationship betweenthenth nodevoltageto the ) n 9 1. st nodevoltagefor clockwiseelements. On theotherhand,if thenth MOStransistor isacounterclockwiseelement,wehave that

Inê &1# n IÜ0e2 * Un3 , Un354 1 6 / UT

8,

whichwe canrearrangeto find that

eUn3 / UT8 & eUn354 1 / UT

8 1/ * In# n IÜ0

1/ *. (14)

Equation14 likewise expresses a recurrencerelationship betweenthe nth nodevoltageand the

) n 9 1. st nodevoltagefor counterclockwiseelements.Wecanusetherecurrencerelationships, expressed inEqs. 13 and14,to build upthetranslinear-

loop constraint equationfor thesubthreshold MOStranslinear loop,shown in Fig. 5a,asfollows.We begin at oneof thenodesin theloop,say U0, and proceedsequentiallyaroundtheloopin theclockwise direction,recursively applying Eq. 13 or Eq. 14 to get to thenext node,dependingonwhetherthe current elementis clockwise or counterclockwise. Whenwe encountera clockwiseelement,we raise the partially formedtranslinear-loop equationto the % power and multiply itby # n I0

( $ In, as expressed in Eq. 13. Whenwe encountera counterclockwise element,we raisethe partially formedtranslinear-loop equationto the1$ % power and multiply it by ) In $:# n I0. 1/ * ,asexpressed in Eq. 14. Finally, whenwe return to the nodewith which we started,we stop andsimplify theresulting expression.

To illustrate this process, we shall consider two simple subthreshold MOS translinear loops,shown in Fig. 6. Eachof these loopscomprisesfourtransistors, two of whichfacein theclockwise

Page 17: circuitos translineares

14

I;1

I;2 I

;3

I;4<

=1

=2

=3

=4

U0

U1

U2

U3

(a)

I;1 I

;2 I

;3 I

;4<

=1

=2

=3

=4

U1

U2

U3

U0

(b)

F>

igure 6: Two subthresholdMOStranslinearloopscomprisingtwo clockwise transistors and twocounterclockwise transistors. In eachcase, thebulks of all four transistors are tied to a commonpotential.(a)A stackedloop topology. (b)An alternating loop topology.

directionandtwo of whichfacein thecounterclockwisedirection.Thefirst loop,shown in Fig. 6a,hasa stackedtopology;that is, all of thegate-to-sourcevoltagedropsare stackedup, oneon topof theother. Thesecondloop,shown in Fig. 6b hasanalternating topology;that is, we alternatebetweenclockwise andcounterclockwise elements, aswe goaroundtheloop.

First, consider the stackedMOS translinear loop, shown in Fig. 6a. Starting with nodeU0

andproceedingaroundthe loop in the clockwise direction,we encountertwo counterclockwiseelementsfollowed by two clockwise elementsbefore we finish backat nodeU0. Following theprocedure just described,wehave that

eU0?�@ UT

8 1@BA I1C1 IÜ0( 1@�A

eU1@ UT

1@BA I2C2 IÜ0( 1@�A

eU2DE@ UT

8

A C3 IÜ0

IÜ3ÿ

eU3F @ UT

A C4 IÜ0(

IÜ4

G eU0?E@ UT

8,

which we can simplify to get

eU0? @ UT

1@BA I1C1 I0

1@�A I2C2 I0

C3 I0

I3ÿ

C4 I0(

I4

1@BA G eU0? @ UT

1@�A.

By cancelingcommonfactorsandgroupingthecounterclockwisecurrentson theleft-handside oftheequationandgroupingtheclockwisecurrentson theright-handside of theequation,weobtainthefollowing translinear-loopequation:

I1C1

1@�A I2C2

CCW

G I3ÿC3

I4C4

1@BA

CW

, (15)

Page 18: circuitos translineares

15

whichhasnoremainingtemperaturedependenceandnodependenceon I0, but doesdependon thesubthresholdslopefactor, H .

Next, considerthealternatingMOStranslinearloop,showninFig. 6b. Again,startingwith nodeU0 andproceedingaroundtheloopin theclockwisedirection,wefirst encounteracounterclockwiseelementfollowedby aclockwiseelement,followedby anothercounterclockwiseelement,followedby anotherclockwise element. Following theprocedure just described,we have that

eU0?�I UT

1IBJ I1K1 I0( 1I�J

eU1I UT

J K2 I0

I2

eU2D I UT

8

1IBJ I3ÿK

3 I0

1I�J

eU3FEI UT

J K4 I0(

I4

L eU0?EI UT ,

which we can simplify to get

eU0? I UT

8 I1K1 IÜ0

K2 IÜ0

IÜ2ý I3

ÿK3 IÜ0

K4 IÜ0(

IÜ4

L eU0? I UT

8.

By cancelingcommonfactorsandgroupingthecounterclockwisecurrentson theleft-handside oftheequationandgroupingtheclockwisecurrentson theright-handside of theequation,weobtainthefollowing translinear-loopequation:

I1K1

I3K3

CCW

L I2K2

I4K4

CW

, (16)

whichhasnoremainingtemperaturedependence,nodependenceon I0( , andnodependenceon H .

Fromtheseexamples, wecanmakeanumberof observationsaboutsubthresholdMOStranslin-earloops. First, if thenumberof clockwise elementsis equalto thenumberof counterclockwiseelementsin a closed loop,thentheeU0

?�I UT factorwill cancelfrom bothsidesof theequation. Ingeneral, eachtime we traverse a clockwise element,we raise this factorto the H power, andeachtime we traverse a counterclockwise element,we raise this factorto the1M:H power. Thus, if thereare NCW

ö clockwiseelementsand NCCWö elements, thefactorof eU0

? I UT8

will appearontheleft-handside of the translinear-loop equationraised to the H N

óCWôON NCCW

ôpo® wer, which is equal to unity if

NCWö L NCCW

ö . Therefore, this factor, which appears on both sidesof the final translinear-loopequationwill cancel.

Second,if thenumberof clockwise elementsis equalto thenumberof counterclockwise ele-ments, thenthetranslinear-loopequationwill beindependentof I0

( . To seewhy, considerfirst whathappensto the power to which I0

( isì

raised after we traverse a clockwise elementfollowedby acounterclockwise element. Suppose that I0

( appearsin the initial translinear-loop equationraisedto the P power. After traversing a clockwise element,we will have I0 raisedto the HQPSR 1. Then,

Page 19: circuitos translineares

16

after traversing a counterclockwise element,we will have I0( raisT edto the U+VXWZY 1[]\:V_^ 1\:V_`aW

power. Thus, thepower to which I0 is raised in thetranslinear-loopequationremainsunchangedwhenwepass from asequenceof clockwiseelementsto asequenceof counterclockwiseelements.Next, considerwhathappensto thepowerto which I0 is raisedafterwetraverseacounterclockwiseelementfollowedby aclockwiseelement.Again,suppose I0

( appearsin theinitial translinear-loopequationraised to the W power. Af ter traversing acounterclockwiseelement,wewill find I0 raisedto the WQ\:Vb^ 1\:V power. Then, after traversing a clockwise element, we will have I0

( raisT ed tothe VcUdWQ\:Ve^ 1\fVX[gY 1 hW power. Thus, thepower to which I0 is

ìraised in the translinear-loop

equationalso remainsunchangedwhenwepassfromasequenceof counterclockwiseelementsto asequenceof clockwiseelements. Therefore, thepower to which I0 is

ìraisedin thetranslinear-loop

equationremainsunchangedwhenwe pass througha boundary betweena sequenceof clockwiseelementsandasequenceof counterclockwise elements.

Now, if thereareanequalnumberof clockwiseandcounterclockwiseelements, thentherewillbeat least two such boundaries; this lower boundis achieved whentheloop hasa purely stackedtopology. If thereare2N elementsin theloop(i.e., NCW ` NCCW ` N), thentherecanbeatmostN such boundaries; this upperboundis achieved whentheloophasa purely alternatingtopology.Because theelementsat theboundariesbetweenrunsof clockwiseandcounterclockwiseelementsdo not alter the power to which I0 is

ìraised in the translinear-loopexpression, we candrop the

elementsateachof these boundariesfrom thesequencein determiningtheoverall power to whichI0( is raised. However, theelementsadjacentto those thatwe haveomittedthenform anothersuch

boundary. Consequently, if there is a clockwise elementin the loop for eachcounterclockwiseelement,thentheoverall power to which I0 is raisedaswe go aroundtheloopremainsunaltered.Moreover, whenwe begin accumulating thetranslinear-loopexpression, I0

( doesnotappearin theexpression (i.e., it is raised to the zeroth power). Therefore, because the power to which I0

( israisedbeginsatzero and it remainsunaltered for a loopcomprisinganequalnumberof clockwiseand counterclockwise elements, the overall translinear loop expression remainsindependentofI0( . An identicalargumentholds if all of the MOS transistors have the same W\ L ratio (i.e.,i1 `kjljljm` i

Nó ` i

); thatis, if all of thetransistorshave thesameW\ L ratio andif thenumberofclockwiseelementsisequalto thenumberof counterclockwiseelements, thenthetranslinear-loopequationis independentof thetransistors’ commonW\ L ratio.

Finally, consider a purely alternatingsubthreshold MOStranslinear loop comprising anequalnumberof clockwise and counterclockwise elementswith their bulks connectedto a commonpotential. For such a loop, the translinear-loopequationwill be independentof V . To see why,consider the loop-equationconstructionprocedure. If we begin by traversing a counterclockwiseelement,thefirst currentfactorin theequationwill beraisedto the1\:V power. Af tertraversing thesecondelement,which by hypothesis is a clockwise element,thefirst current factorwill beraisedto the V power, cancelingthe initial 1\:V . The secondcurrent factorwill beaddedto theproductraisedto thefirst power. Aftertraversingthethirdelement,thefirst twocurrent factorswill beagainraisedto the1\fV poweras will thethird current factor. Aftergoingthroughthefourth element,weraise thefirst three current factors to the V power, againcancelingthe1\:V power on eachfactorfrom thepreviousstep.A forth current factoris thenaddedto thepartially formedproduct,raised

Page 20: circuitos translineares

17

to thefirst power. Thus, in an alternatingloop,we alternatebetweenraising eachfactorto the1n:opowerandraisingeachoneto the o power, effectivelyremovingthe o dependencefromthepartiallyformedproductafter every otherstep. Moreover, if there are an equalnumberof clockwise andcounterclockwise elementsin such a loop, thenit follows that thefinal translinear-loopequationwill beindependentof o , becausetheremust bean even numberof steps. A similar argumentwouldhold if we begin with a clockwise element.This result hasbeendemonstratedpreviously usingotherargumentsby Vittoz [80] andby AndreouandBoahen[81].

With these considerationsin mind,we cansimplify our translinear-loopequationconstructionprocedurefor loopsthatcompriseanequalnumberof clockwiseandcounterclockwisesubthresholdMOStransistorswhosebulksareall tiedtoacommonpotential.First, wedonothavetowritedowntheinitial and final eU0

?Ep UT factors; instead,we canreplacethemby unity, effectively dividing outthefactorthatwill becommonto bothsidesof theequationaheadof time. Next, we candispensewith keepingtrackof all of the I0 factors, because we have shown thatthefinal expression will beindependentof I0

( . To summarizethis reducedprocedure,we pick a starting point in theloopandbegin thetranslinear loop expression with unity. Then,we proceedaroundtheloopfrom nodetonodein theclockwise direction. If we traverse a clockwise element,we raise thepartially formedexpression to the o power and thenwe multiply it by q n n Inê . If we traverse a counterclockwiseelement,we raise the partially formedexpression to the 1n:o power and multiply by r In nfq nêfs 1p�t .Whenwearrivebackat thestarting node,weequatetheproductthatwehaveaccumulatedto unityandsimplify it as necessary.

5 ABC’sof Translinear-Loop–Circuit Synthesis

I¦n this section,we shall give a brief overview of the basics of translinear-loopcircuit synthesis.

As with all synthesis problems, thetask of constructinga translinearcircuit that implementssomedesired functionalityis underconstrained.For any given function,therewill bea variety of circuitsolutions with design decisions to be madeand many trade-offs to consider. Thus, our briefdiscussion cannot,by any means, be exhaustive. Rather, we shall attempt to make the basicprocedureclearandweshall illustrateit with two simpleexamples. In theprocess, weshall discusssomedesigndecisionsandtrade-offs.

5.1u

Synthesizing Static Translinear-Loop Cir cuits

he basic procedure for synthesizing translinear-loopcircuits canbedescribedas follows. First,we acquire a set of translinear-loopequationsfrom therelationship(s) thatwe wantto implement.Next, we build a translinearloop for eachof thetranslinear-loopequations. Next, we biaseachofthetranslinearloops. Finally, if possible,weconsolidatetheresulting circuitsby merging someofthe loops. We shall discuss eachof these stepsin turn, thenwe shall use themto synthesize twosimpletranslinear-loopcircuits, asquaringcircuit anda two-quadrantmultiplier.

Page 21: circuitos translineares

18

Acquiring a set of translinear-loop equations. The starting point for synthesizing a translinear-loop circuit is a static linear or nonlinearmappingbetweendimensionless variables. The classof translinear circuits is capableof embodyinga wide rangeof useful linear andnonlinearrela-tionships. However, not all functionsare directly implementableby translinear circuits; we candirectly realizeproducts, quotients, power-law relationships, polynomials, rationalfunctions, andvariouscombinationsof such relationships. In many cases, we may needto find an acceptableapproximationfor oneor more nonlinearfunctionsin terms of polynomials, rational functions,continuedfractions, or someothersuitablemathematicalform before we canrealizetherequiredrelationship with translinearcircuits. In his bookon translinearcircuits, Seevinck [38] providesagooddiscussionof suitableapproximationtechniquesandapproximationsof varioustranscendentalfunctions.

Oncewe have obtaineda set of relationshipsthatcanberealizedwith translinearcircuits, wethenrepresenteachof thedimensionlessquantitiesastheratio of asignalcurrent to theunit currentor as the ratio of a dif ferentialcurrent to the unit current,as described in Section3. Then,wedecompose theresulting equationsinto a set of translinear-loopequationsof theformof Eq. 7. Inthe decomposition process, it is sometimesconvenientto introduceintermediatecurrents, whichserve to parameterize someof the relationships, allowing us to furtherdecompose the system ofequations.

Building the translinear loops. Oncewe have a set of translinear-loop equations, we constructa closed loop of TEs for eachone. In general, there will be more thanonetranslinear loop thatimplementsany giventranslinear-loopequation.Ourchoicesof looptopologyandcurrentorderingmust be guidedby experienceandother system-level design considerations. For instance,loopswith an alternating topologyare better thanstackedloopsfor systemsthat require a low power-supplyvoltage.On theotherhand,stackedloopsareeasier to biasin thecase thatthesamecurrentmust pass throughmultiple TEs that facein thesamedirection. In a stackedloop, we only haveto supply a singlecopy of the inputcurrent to thecircuit andwe canpass thesamecurrent fromoneelementto thenext in a stack of TEs. In an alternating loop,there are no runsof clockwiseor counterclockwise TEs, so if we must pass thesamecurrent throughN TEs facingin thesamedirection,we must supply N matchedcopiesof theinputcurrent to thecircuit.

Biasing the translinear loops. The process of biasing a translinear loop involves forcing inputcurrentsinto theemitteror collectorof eachinputTE in theloopandarrangingsometypeof localnegative feedbackaroundit, adjusting its gate-to-emittervoltageso that theTE passes the inputcurrent. Onceagain,there are many possible feedbackarrangementsthatwill properly biaseachTE in any givenloop. In somecases, we may evenuse operationalamplifiers to biasa translinearloop. Here, weshall consideronly thethreesimplest possibilities, whichareshown in Fig. 7.

Figure7ashowstheubiquitousdiodeconnection. Here,weforceacurrentinto thecollectorofacounterclockwiseTE, whichcorrespondsto avoltageincrease,andwefeedthecollectorvoltagebackto thegate. Any mismatchbetweenthe inputcurrent andtheTE’s collectorcurrent causesthe gatevoltageto charge up or down in such a way to reducethe mismatch. If the collectorcurrent is biggerthantheinputcurrent, thegatewill discharge,reducingthegate-to-emittervoltage

Page 22: circuitos translineares

19

Unvxw 1 y VnvVnvUnv�w 1

Iznv

Iznv

Inv { I

InvVnv

Unv�w 1

Unv�w 1 y VnvInv

InvInv

Inv

VnvUnv�w 1

Unv�w 1 { Vnv

(a) (b) (c)

F>

igure7: ThreesimplebiasingarrangementsforTEs. (a)Collectorcurrent forcing with thediodeconnection.(b) Emittercurrent forcing with theemitter-followerconnection.(c) Collectorcurrentforcing with theEnz–Punzenberger (EP)connection.

therebyreducingthecollectorcurrent. If thecollectorcurrent is smaller thantheinputcurrent, thegatewill chargeup,increasing thegate-to-emittervoltage,therebyincreasing thecollectorcurrent.Of course, we canintroduceadditional circuitry betweenthe collector andthe gate,such as oneor more buffer stage,as long aschangesin the collectorvoltageinducelike changesin thegatevoltage. In somecases, we actuallyuse otherTEs in the loopwith their input-current sourcestoformemitter-followerbuffer stagesinmakingadiodeconnection.Insomecases, wemayintroducebufferstagesto eliminatebase-current errors in bipolartranslinear-loopcircuits.

Figure7b showsanemitter-follower connection. Here,we forceacurrentoutof theemitterofa clockwise TE, which correspondsto a voltagedrop. In such anarrangement,for any givengatevoltage,theemittervoltagewill adjust itself up or down so that theemittercurrentjust balancesthe input current. If the emittercurrent is larger thanthe input current, the emittervoltagewillcharge up, reducingthe gate-to-emittervoltage, therebyreducingthe emitter current, until thecurrentsmatcheachother. If theinputcurrent is larger thantheemittercurrent, theemitterwill bedischarged, increasing thegate-to-emittervoltage,therebyincreasing theemittercurrentuntil thecurrentsbalance.

Figure 7c shows a simple alternative to theemitter-followerconnectionfor biasing clockwiseTEs. Here, we force a current into the collector of a clockwise TE and we feedthe collectorvoltagebackthroughanothertransistor to adjust theemittercurrent. An nMOStransistor isshownin Fig. 7c, but a bipolar transistor could be used instead. A similar feedbackarrangement(i.e.,forcing thecollectorcurrentby feedbackto theemitter terminal)involving operationalamplifiershasbeenusedin biasing translinearcircuitsfor many years[10]. Theuseof thisparticularly elegant

Page 23: circuitos translineares

20

implementationof suchafeedbackarrangementin thecontext of translinear-circuitbiasing appearsto have beenfirst proposedby Enz and Punzenberger [82] to biaslow-voltagelog-domainfilters.Consequently, we shall refer to this connectionas theEnz–Punzenberger (EP) connection.For agiven gatevoltage,any imbalancebetweenthecollectorcurrentandtheinputcurrentwill causethefeedbacktransistor to adjust thegate-to-emittervoltagein suchawayasto reducetheimbalance.Iftheinputcurrent is too large,thecollectorvoltagewill increase,causing thefeedbacktransistor topull a largercurrentoutof theemitter. Conversely, if thecollectorcurrentis to large,thecollectorvoltagewill decrease,reducingtheamountof currentflowing throughthefeedbacktransistor. Thisdecreasedcurrent,in turn,will cause theemitterto chargeup,reducingthegate-to-emittervoltage,therebyreducingthecollectorcurrent. Note that if someadditionalcurrent I is injectedinto theemitternode,thecollectorvoltagewill adjust itself so that the feedbacktransistor sinks both thecurrentflowing throughtheTEandtheadditionalcurrent. Thisfeatureof theEPconnectiongreatlyfacilitatesthebiasing of translinearloopswith analternatingtopology.

In general, wecanbiasany translinearloopusing only two of thethreesimplearrangementsofFig. 7; we canuse thediodeconnectionfor biasing counterclockwise TEs andwe canuse eitherthe emitter-followerconnectionor theEP connectionto bias theclockwise TEs. In general, theemitter-follower connectioninvolves only onenode,whereasthe EP connectionis involves twonodes, which cancause more complicatedsettling behavior with theEP connection.On theotherhand,in analternatingtranslinearloop,by using thediodeconnectionto biasthecounterclockwiseelementsandthe EP connectionto bias the clockwise elements, we are always forcing collectorcurrentsand takingoutputsfrom collectorcurrents. This uniform use of collectorcurrentsallowsus to freely use translineardeviceswhose emitter currentandcollectorcurrentarenot nearlythesame,suchas thecompatiblelateral bipolar transistor (CLBT), which is alwaysavailablein anyCMOS process [83]. Suchdeviceshave at least two collectors, a lateralcollectoranda parasiticvertical collector, eachof whichcollectonly a finite fractionof theemittercurrent.

Consolidating thecircuit. In somecases, after we have biasedeachof thetranslinear loopsin thecircuit, we will recognizesomeredundancy betweentheloopsin thecircuit. For example,if twoTEs in differentloopspass thesamecurrent andare at thesamevoltagelevel, thenthese devicesare redundantandmay be sharedbetweenthe loops. Suchconsolidation is usually a goodidea,becauseit usually results in smallercircuitsandfeweropportunitiesforerrorsresulting fromdevicemismatch.

5u.2 Synthesisof a Translinear Squar ing Circuit

Suppose that we want to implementa squaring operation with a strictly positive input usingtranslinear-loopcircuits. That is, we want to find a translinear-loopcircuit that implementstherelationship

x | y2, (17)

where x } 0 and y } 0 are dimensionless quantities. Herey is theindependentvariable(i.e., theinput) and x is thedependentvariable(i.e., theoutput). First, we represent x by Ix~�� Iu andy by

Page 24: circuitos translineares

21

Iy�I�

y�Iu�

I�

x�

Iy�

I�

u�

Iy�I�

y�Iu�

I�

x�

(a) (b)

Figure 8: Synthesis of a translinear squaring circuit based on a stackedtranslinear loop. (a) Astackedtranslinearloop thatimplementsEq. 18. (b) Onepossiblebiasing scheme.

IyÉm� IuÆ , where Iu is theunit current. Then,we substitute these definitionsof x and y into Eq. 17,getting

Ix~IÜuÆc�

IyÉIÜu

2

,

whichwe caneasily rearrangeto obtainthefollowing translinear-loopequation:

Ix~ IuÆCW

� I 2ýy

CCW

. (18)

Next, to implementEq. 18,weneedto selectatranslinearloopcomprisingfourTEs, two facingin thecounterclockwisedirectionandtwo facingin theclockwisedirection.Inputcurrent IyÉ p® assesthroughbothof thecounterclockwiseTEswhile IuÆ pas® sesthroughoneof theclockwiseelementsandIx~ pas® ses throughtheother. Figure8ashows astackedloopthatimplementsEq. 18. Onepossiblebiasing arrangement for thestackedloop is shown in Fig. 8b; here, wehave diodeconnectedeachof thecounterclockwise elementsand we have usedanemitter-followerconnectionfor oneof theclockwiseelements. Because thecounterclockwiseelementscomein sequencein thestackedlooparrangement,wecaneffectively reusetheinputcurrent, IyÉ , by passing thecurrentfrom theemitterof onecounterclockwiseTE intothecollectorof theotherone.Notethattheresulting circuit is thesame as theoneshown in Fig. 4a.

Figure9ashowsanalternatingloopthatalso implementsEq. 18. Weshall considertwopossiblebiasing arrangementsfor the alternating loop. Figure 9b shows an arrangementbased on diodeconnectionsandan emitter-followerconnection.Notethat,becausethecounterclockwiseelements

Page 25: circuitos translineares

22

Iy� Iu� Iy� Ix�

Vref Vref

I�y� I

�y�

I�y� � I

�u�

I�u�

(c)

Iy� Iu� Iy� Ix�

Vref Vref

I�y� I

�y�

Iu� Iy�

(b)

I�y� I

�u� I

�y� I

�x�

Vref Vref

(a)

F>

igure9: Synthesisof atranslinearsquaringcircuit basedonanalternatingtranslinearloop. (a) AnalternatingtranslinearloopthatimplementsEq. 18 (b)A biasingschemeondiode-connectionsandemitter-followerconnections. Note thatwe needto supply threematchedcopiesof IyÉ , includingtwo current sourcesandonecurrent sink. (c) A biasing schemebasedondiodeconnectionsandtheEP connection.By using theEP connection,we only forcecollectorcurrentsandwe only needtosupply two matchedcopiesof IyÉ , bothof which arecurrent sources.

are separatedby a clockwise element,we must now supply a separate copy of IyÉ toÇ

eachone.Also, because IyÉ also flows out of the emitter of the secondcounterclockwise element,to biasthe clockwise element that passes IuÆ pr® operly, we must sink IyÉ out of the central emitternodein additionto Iu. Figure 9c shows a biasing arrangementbased on diodeconnectionsandan EPconnection.Here, while westill have to supply two matchedcopiesof IyÉ to

Çthecircuit, wearenot

required to also supply a matchedcurrent sink; theEP feedbackconnectionwill adjust thegateofthefeedbacktransistor to compensate for theextra IyÉ flowing into thecommon-emitternode.Forbothbiasing schemes, theexactvalue of thevoltageVref is

ìnot critical—it shouldbe high enough

allow an adequateswing on thecommon-emitternodewhile keepingthecurrent-sinking devicesactingproperly.

Page 26: circuitos translineares

23

1 2�

Iz� � Iz� �Ix� � Ix� �Vref

Iu�Iy�

Vref I�x� � I

�u�

I�x� �I

�u�I

�y� I

�x� �

Iu� Iy�

VrefI�

x� � I�u���

I�

u� I�y�

(b)

1 2

I�z� � I

�z� �I

�x� � I

�x� �

Vref

I�

u�I�y�

Vref� I�x� � I

�u�

Ix� �Iu�Iy� Ix� �

�� Ix� �

(c)

1 2

I�z� � I

�z� �I

�x� � I

�x� �

Vref�I�

u�I�y� I

�u� I

�y�

Vref�Vref�

(a)

F>

igure 10: Synthesis of a two-quadranttranslinearmultiplier basedon two alternatingtranslinearloops. (a)A pair of alternatingtranslinear loopsthat implementIu I

Ü��z � IyÉ I

Ü��x and IuÆ IÜ��z � IyÉ I

��x .

(b)A biasingschemebasedoncollector-currentforcingwith diodeconnectionsandEPconnections.(c) Thefinal consolidatedtwo-quadranttranslinearmultiplier circuit. Herewe couldsharethe IyÉand Iu circuitry betweenthetwo translinearloops.

Page 27: circuitos translineares

24

5.3�

Synthesis of a Two-Quadrant Translinear Multip lier

Suppose that we want to implementa circuit that multiplies two quantities, x and y. Further,suppose thatx canbeeitherpositiveor negativeandthaty is strictly positive. Thus, theirproduct,z, which is given by

z   xy, (19)

canbeeitherpositiveor negative. Weshall representy by Iy¡£¢ Iu and weuseadif ferential represen-tationfor x andz, as describedin Section3; that is, werepresentx by

x   x ¤¦¥ x § ,

where x ¤©¨ I ¤x ¢ Iu andx §©¨ I §x ¢ Iu. Likewise,werepresentz by

z   z¤ ¥ z§ ,

where z¤ ¨ I ¤z ¢ Iuª andz§ ¨ I §z ¢ Iu.Next, we substitute these definitionsfor x, y, and z into Eq. 19 to get

I ¤zI«uª ¥ I §z

I«u

  I ¤xI«uª ¥ I §x

I«u

Iy¡I«uª ,

whichwe canrearrangeto obtain

Iu I ¤z ¥ Iu I §z   Iy¡ I ¤x ¥ Iy¡ I §x .

Onestraightforward way to decompose this equationinto a pair of translinear-loopequationsis to equateindividually thepositive andnegative terms on eachsideof theequation. Using thisdecomposition, we obtainthefollowing pairof translinear-loopequations:

Iuª I ¤zCW

  Iy¡ I ¤xCCW

and Iu I §zCW

  Iy¡ I ¤xCCW

. (20)

Figure10ashowsapairof translinearloopswith alternatingtopologiesthatimplementsEq. 20.Figure 10b shows one possible biasing arrangementfor these loops; we use diodeconnectionsfor eachof thecounterclockwiseelementsandEPconnectionsfor eachof theclockwiseelements.Again,theexactvalueof thevoltageVref is notcritical—it shouldbehighenoughallow anadequateswing on the common-emitternodewhile keepingthe feedbacktransistor actingproperly. Notethat in eachloop, we have a copy of Iy¡ forced

¬into a diode-connectedTE whose emitter is fixed

at Vref . Thus, we caneliminateoneof these stagesand connectthediode-voltageto both loops.Additionally, we supply a copyof Iuª to

­both loops, and aswe just observed, thegateof bothTEs

will beat thesamepotential. Thus, we caneliminateoneof the Iu states, too. The consolidatedtwo-quadrantmultiplier isshown in Fig. 10c.

Page 28: circuitos translineares

25

6 The Multiple-Input Translinear Element

ehaverecentlydescribedanew translinearcircuit primitive, calledthemultiple-inputtranslinearelement(MITE) [84,85]. Suchan elementproducesanoutputcurrent, I , that is exponentialin aweightedsum of its K inputvoltages, V1 thr

­oughVK , given by

I ¯'° Is± e K²k³ 1 ´ k

µ V¶ kµ5· U ¸ UT

¹, (21)

where Vkº is thekth input voltage, » k

º is a dimensionless positive weight thatscalesVkº , and U is

theemitter voltageof theMITE. HereIs± , ° , and UT are thesame asthey were for theidealTE. Sodefined,theMITE hasK differenttransconducances, eachof which is linear in theMITE’s outputcurrent.

Figure11ashowsa circuit symbol for an idealK -inputMITE. This symbol lookslike an idealTE whose gatevoltageis set by a K -inputcapacitive voltagedivider, where thekth divider ratiois given by a nearby » k. The inputsdo not needto be capacitive, but we shall assume that theinput terminalsdraw a negligible amountof DC current andthatwe cancontrol thevaluesof theweightsproportionally. In many cases, we shall beinterestedprimarily in thenumberof identicalunitweights, eachwith value » , couplingan inputvoltageintoaMITEratherthantheactualweightvaluesinvolved. In suchcases, we shall omit the » associatedwith eachof theinputs.

Figures11b through11g show six dif ferent practical circuit implementationsof the MITE.For thefirst of these MITEs, shown in Fig. 11b,we use a resistive voltagedivider to implementtheweightedvoltagesummationand a bipolar transistor to implementtheexponentialvoltage-to-current transformation. In this case, theweight associatedwith eachinput is proportional to theconductancethroughwhichthatinputcouplesinto thebaseof thebipolar. Here,wemust buffertheinputvoltagesintotheresistivenetwork so, in acircuit, thenetwork neithersuppliescurrent to norsinkscurrent fromtheinputnodes. Thisresistor-bipolarcircuit isonlyagoodMITEimplementationover thosecollectorcurrentsfor whichthebaseimpedanceof thebipolartransistor is muchgreaterthantheresistancesin theresistivenetwork. Whenthebaseimpedancebecomescomparableto theresistancesin theresistor network,thebasevoltageis clampedby thebase-emitterjunctionandthecollectorcurrent thenincreasesonly linearly, insteadof exponentially, with theinputvoltages.

In subthreshold, the drain current of the K -input floating-gateMOS (FGMOS) transistor isproportionaltotheexponentialof aweightedsumof its K control-gatevoltages[61]. Consequently,we canimplementa MITE using a singlesubthreshold FGMOStransistor, as shown in Fig. 11c.In this case, theweightof eachinput is proportional to thecapacitancethroughwhich that inputcouplesinto thefloatinggate.ThesubthresholdFGMOStransistor isagoodMITE implementationover the entire rangeof subthreshold currents. The main limitation of thesubthreshold FGMOStransistor asa MITE is theexistenceof a parasitic gate-to-draincapacitance,which results from asmall regionof overlapbetweenthepolysilicon gateandthedraindif fusionregionthatarisesduringprocessing. Because thegateof a FGMOS transistor is floating,an increase in thedrain voltagecouplesinto thefloatinggatethroughthisoverlapcapacitance,therebyincreasing thesubthresholddrain current exponentially. In principle, we candecrease this coupling as much as we like by

Page 29: circuitos translineares

26

VK½ GK

½G2¾

G1

V2

V1

U

VK

C1

V2

V1C2

CK½ U

I

VK½

C1

C2

CK

V2¾V1

Vcas¿

U

I

VK½

C1

C2¾

CK½V2

V1

U

VK

C1

C2

CK

V2¾V1

VbÀU

VK

C1

C2

CK

V2¾V1

VbÁU

I

VK

w 1

V2

V1 w 2¾

w K½ U

(a)

(b)

(c)

(d) (e)

(f)

(g)

Figure 11: Multiple-inputtranslinearelements(MITEs). (a) Circuit symbol for an idealK -inputMITE. Suchanelementproducesanoutputcurrent thatisexponentialinaweightedsumof its inputvoltages. Parts b throughg show six differentMITE implementationscomprising (b) a resistivevoltagedivider and a bipolar transistor, (c) a single subthreshold floating-gateMOS (FGMOS)transistor, (d) a cascodedsubthreshold FGMOS transistor, (e) a subthreshold FGMOS transistoranda bipolartransistor, (f) afloating-gatesourcefollowerandasubthresholdMOStransistor, and(g) a floating-gatesource follower and a bipolar transistor. For eachof the five FGMOS MITEimplementations, shown in partsc throughg,wecanusetheamountof floating-gatechargeto storeelectronicallyadjustable,nonvolatile multiplicativescalefactorsthatwe canuse to build adaptiveinformation-processingsystemsor to compensatefor devicemismatch.

making theFGMOStransistor narrower(therebydecreasing theoverlapcapacitance)or by makingthe control-gatecapacitanceslarger (therebyincreasing the total floating-gatecapacitanceand,hence,decreasing the drain capacitive-divider ratio), or by using both techniques. However, inpractice,neitherof these solutionsare attractive. A bettersolution to this problemis to cascodethesubthreshold FGMOStransistor, as shown in Fig. 11d. We canthink of thecascodetransistoras a source follower with a constant input voltage, Vcas; thus, it fixes the drain voltageof theFGMOS transistor (i.e., the source follower’s output voltage), effectively reducingthe change

Page 30: circuitos translineares

27

in current throughboth transistors resulting from a changein the drain voltage of the cascodetransistor. The cascodedsubthreshold FGMOS transistor is an excellent MITE implementationover thesubthreshold rangeof currents.

Figure11edepictsatwo-transistorMITEcomprisingaK -inputsubthresholdFGMOStransistorandabipolartransistor. Intuitively, thisbipolar-FGMOSMITEworksasfollows. ThesubthresholdFGMOStransistor producesacurrent thatis exponentialin theweightedsum of theinputvoltages;again,theweightof eachinput is proportional to thecapacitancethroughwhich thatinputcouplesinto the floatinggate. The bipolar transistor thenactsas a current-gainstageby multiplying thesubthreshold FGMOS transistor current by thebipolar’s forward current gain. Consequently, theupperendof thecurrentrangeover whichthistwo-transistorcircuit isagoodMITE implementationis extendedover thatof thesubthresholdMOStransistor by thebipolar’scurrent gain, Ã . Becausethedrainof theFGMOStransistor isheldatafixedpotential,thisMITEis insensitiveto theparasiticdrain-overlapcapacitance.

Thefinaltwo MITEs, shown in Figs. 11f and11g,aresimilar—eachcomprisesatwo-transistorFGMOSsourcefollowerandathirdtransistor thathasanexponentialcurrent–voltagecharacteristic.Intuitively, the floating-gatevoltagedevelops as a weightedsum of the K input voltagesvia acapacitive voltagedivider. In the source-follower configuration, the FGMOS transistor’s sourcevoltageis approximatelya linear functionof thefloating-gatevoltage. Consequently, thesourcevoltageis also a weightedsum of theinput voltages. The third transistor thengeneratesa currentthat is exponentialin this sourcevoltage. In the MITE of Fig. 11f, the exponentialelementis asubthreshold MOS transistor, whereas, in that of Fig. 11g, the exponentialelementis a bipolartransistor. Because thedrainsof theFGMOStransistorsare heldat afixedpotential,these MITEsalso donotsuffer from thedrain-overlapcapacitanceproblem.

Because thesource-followercircuit configurationdoesnot dependon theform of thecurrent–voltagerelationshipof theMOStransistor, thesethree-transistorcircuitsaregoodMITE implemen-tationsevenwhenwe biastheFGMOSsource follower with anabove-threshold current. For thecircuit of Fig. 11f, biasing theFGMOSsourcefollowerwith anabove-thresholdcurrent allows usto maketheoutputMOStransistoraswideasnecessary togetalargerrangeof exponentialcurrentswithouthaving to maketheFGMOStransistor, and,hence,thefloating-gatecapacitancelarge.Theabove-threshold biasgivestheFGMOSsourcefollowerenoughbandwidthto drive the large gatecapacitanceof awideoutputMOStransistor. Thecircuitof Fig.11gisagoodMITEimplementationonly whenthebasecurrent is negligible comparedwith thesource-followerbiascurrent. Thus, forthecircuit of Fig. 11g,biasing theFGMOS sourcefollower with above-threshold currentsallowsusto operate thisMITE athighcurrent levels and,thus, potentiallywith highbandwidths.

For eachof thefiveFGMOS-transistor–basedMITEimplementationsjust described,thefloating-gatecharge linearly shif ts theweightedsum of thecontrol-gatevoltages. Whenmappedthroughtheexponential,this voltageoffset translatesinto a multiplicativefactorthatscalestheoutputcur-rent. Thus, we canthink of thefloating-gatechargeasdeterminingan electronicallyadjustable Äparameter, which we canuse to store adaptableweightsfor building learning systemsor to com-pensatefor scale-factorerrorsresulting from device mismatch.Noneof theFGMOS-basedMITEimplementations, exceptfor thesinglesubthresholdFGMOStransistor, isaffectedadversely by the

Page 31: circuitos translineares

28

effectÅ

wÆ niÇwÆ nkÇVk

ÈVi É nÇQnÇInÇ

causeÊ

cause

causeÊ

effect

wÆ ii

Qi

IËi

ViÉ i

IËi

causeÊ

wÆ ii

Qi

IËi

ViÉ i

IËi

VjÌ

wÆ ij

causeÊ effectÅ

(a) (b) (c)

igure12: Threebasic circuit stages, eachcomprisingasingleMITE. (a) A voltage-in,current-out(VICO) stage. (b) A current-in, voltage-out (CIVO) stage. (c) A voltage-in, voltage-out (VIVO)stage.

parasitic overlap capacitances.

7 Multiple-Input Translinear ElementNetworks

IÎn thissection,weintroducethreebasic circuit stages, eachconstructedfromasingleMITE. These

threecircuit stagesarethebricksfrom which we build a class of low-voltagetranslinearcircuits,whichwecall MITEnetworks, thatareequivalentto theclassof translinear-loopcircuits. Then,weshall examinehow we cancompose thesestagesto make translinearcircuits.

7.1 Basic MITE Cir cuit Stages

Consider thethreebasic MITE circuit stagesthataredepictedin Fig. 12. Thefirst of thesecircuitsis avoltage-in,current-out (VICO) stage,shown in Fig. 12a.Here,weapplyinputvoltages, Vi andVkº , to two differentinputterminalsof MITE QnÏ , which, in response,generatesan outputcurrent,

InÏ . To see how In dependson Vi andVk, using Eq. 21,wewrite

In Ð eÑÓÒ niÔ V¶

i Õ Ò nkÔ V¶

kµ ÕQÖ×Ö×ÖÓØÚÙ UT Û

By breakingoutthefirst two termsof theweightedsummationandusing thefactthatexÜ Õ y Ý exÜ ey¡ ,we canrewrite theprecedingexpressionas

InÏ Ð eÒ niÔ V¶

i Ù UT¹eÒ nkÔ V

¶kµ Ù UT

¹. (22)

Page 32: circuitos translineares

29

The secondof the threebasic MITE stages, shown in Fig. 12b, is a current-in, voltage-out(CIVO) stage. Here, we source an input current, I i , into the outputof MITE Qi , and we feedthe outputvoltage,Vi , back throughthe self-coupling weight, Þ i i

ß . This feedbackconfigurationadjusts Vi

ß , so that the current sunk by MITE Qi jusà

t balancesthe inputcurrent, I i . A MITE inthis feedbackconfigurationis analogousto a diode-connectedtransistor, so we say that it is diodeconnectedthrough Þ i i . To determinehow theoutputvoltage,Vi , dependson theinputcurrent, I i ,we begin with Eq. 21,andsolve for Vi in

átermsof I i . So, we write

I i â eãåä ii Vi æQç×ç×çÓèÚé UT ,

whichwe rearrangeto find that

VißQê UTÞ i i

logë

I i ìîíïílí . (23)

The third basic MITE stageis avoltage-in,voltage-out (VIVO) stage,shown in Fig. 12c. Thisconfigurationis identicalto theCIVO stageof Fig. 12b,exceptthatwe now hold thecurrent, I i ,fixed,and weare insteadconcernedwith how theoutputvoltage,Vi

ß , dependsonaninputvoltage,V jð , whichweapplyto anotherof theinputterminalsof MITE Qi . Beginningwith Eq. 21,wewrite

thatI i â eñ ä ii Vi æ ä i j V j

ò æQç×ç×çôó�é UT¹,

whichwe rearrangeto solve for Vi iná

termsof V jð , as follows:

Viê ì Þ i j

Þ i iß V j

ð ìîílílí . (24)

Wecanusethecircuit stageof Fig.12cbothasaCIVOstageandasaVIVOstagesimultaneously.In this case, it is easy to see that Vi

ß dependson V jð and I i thr

­ougha linear combinationof of

Eqs. 23and24 as follows:

Viê UT

Þ i iß log I i

ß ì Þ i j

Þ i iß V j

ð ìîílílí . (25)

7.2 Elementary MITE Networks

IÎn this section,we shall examine two simple current-modeMITE circuits, eachcomprising two

CIVO stagesanda singleVICO stage. These two basic current-modecircuits illustrateall of thebasic intuitionbehindtheoperationof MITE networks.

In the first current-modecircuit, shown in Fig. 13a,we connectthe outputsof two differentCIVO stagesdirectly to a singleVICO stagethroughseparate inputs. To analyzethis circuit, weapplyEq. 22 to theoutputstage,obtaining

InÏ â eä niÔ V¶

i é UTeä nkÔ V¶

kµ é UT . (26)

Page 33: circuitos translineares

30

(a) (b)

wõ niö QnöI÷

ønöwõ kk

ùQkù

kùø

Ikù

wõ ii

Qi

i

Vi

øi

I i

Vkù

wõ nköwõ niö Qnö

Inö

ønöwõ jj

úQjú

I júø

I jú

wõ ii

Qi

I i

Vi

øi

I i

Vjú

wõ ij

Figure 13: Two basic current-modecircuits comprising two CICO stagesand oneVICO stage.Thesetwocircuitsillustrateall of theintuitionunderlyingtheclassof MITEnetworks(a)A product-of-power-law circuit. (b) A quotient-of-power-law circuit.

Substituting Eq. 23 into Eq. 26 for eachof Vi andVkº , weobtain

InÏüû expý

ni

UT

UTþ

ýi i

log I iß ÿ ����� exp

ýnk

UT

UTýkkº log Ik

ÿ ����� .

Whenwe breakout the first term in eachof the two summationsand regroup, this expressionbecomes

InÏüû expUT

UT

ýniýi iß log I i exp

UT

UT

ýnkýkkº log Ik . (27)

Note that, if MITEs Qi , Qk, and QnÏ are operating at thesame temperature, thentheprimarytemperature dependenceof the relationship among I i

ß , Ik, and In disappears from Eq. 27. Inthis intuitive analysis, we have not kept track of the scaling currents, Is± , which canbe stronglytemperaturedependent,but, as we have demonstratedpreviously [84], if theproductsof the inputcurrentsraised to theirrespectivepowershasunitsofAmperes(i.e., asopposedtoAmperesraised tosomeotherpowerthanunity), thentherelationshipbetweentheoutputcurrentandtheinputcurrentsis generally insensitive to isothermal variations. Now, because x log y � log yxÜ andelogx � x, wecanrewrite Eq. 27 as

InÏüû I�

ni�� � iii � I

�nkÔ� � kk

µk . (28)

Thus, theoutputcurrent is proportional to theproductof thetwo inputcurrents, eachof which israisedto apower thatis set by aratioof MITE weights.

For thesecondbasic current-modeMITE circuit, insteadof connectingtheoutputof thesecondCIVO stagedirectly to asecondinputof theoutputVICO stage,aswedoin thecircuit of Fig. 13a,we connecttheoutputof thesecondCIVO stageto theoutputstagethroughthefirst CIVO stage,

Page 34: circuitos translineares

31

asshown in Fig. 13b. Thisfirst CIVO stagebothgeneratesavoltagethatis logarithmic in theinputcurrent, I i , and servesasaVIVO stagefor thesecondCIVO stage. This connectionallows ustoobtainnegativepowers. To show that it will, we applyEq. 21 to theoutputstage,obtaining

In e� �

niÔ V¶

i ������� ��� UT¹. (29)

Substituting Eq. 25 into Eq. 29,weget

InÏ exp�

ni

UTþ UT�

i ilog I i � �

i j�i i

V jð ������� ,

into whichwe substituteEq. 23 for V jð , and thusobtain

In exp�

niÏUT

UT�i iß log I i � �

i j�i iß UT

þ�i iß log I i

ß ������� .

Now, if we breakout thefirst two termsof thesummationand regroup,wefind that

InÏ expUT

UT

�ni�i iß logë

I i exp � UT

UT

�ni�i i

�i j�j jð logë

I jð . (30)

Again,because x log y � log yxÜ andelogx � x, we canrewrite Eq. 30 as

In I�

niÔ � � iii � I � � �

niÔ � � ii ��� � i j � � j jò��

jð ,

which, in turn,becomes

In I�

niÔ � � iiiß

I« � � niÔ � � ii � � � i j � � j j

ò��jð . (31)

Thus, the outputcurrent is proportional to the quotientof the two input currents, eachof whichis raised to a power that is set by ratiosof MITE weights. Here,the powersarenot completelyindependentof eachother—however, for any valueof �

ni ! �i iß , wecanadjust thevalueof � i j

ß ! � j jð to­

set thepowerof I jð to­

whateverwewant.Thisquotient-of-power-law relationship isalso insensitiveto isothermal variations.

These two basic current-modeMITE circuits capture all of the intuition underlying MITE-network operation. We generate voltagesthat are logarithmic in the input currentsusing diode-connectedMITEs. Wesetpower lawsthroughratiosof MITE weights. Weobtainnegativepowersby using voltage-inversionstages. We get productsby summingtwo or more logarithmic voltageson MITEs. We have formalizedthis intuitive analysis andhave obtainedsystematicanalysis andsynthesis proceduresfor thisclass of nonlinearcircuits [84,86].

Page 35: circuitos translineares

32

In"

w# ni"w# nk"

Un"Vi

Vk$ Qn"%

n"

(a) (b) (c)

In"

w# ni"w# nk"

Un" Vi

Vk$Qn"%

n"

In"

w# ni"w# nk"

Un"Vi

Vk$ Qn"%

n"

Figure 14: The threetypesof moves thatwe canencounterin traversing a loopwithin a MITEnetwork.We cango (a) from an emitter to a controlgate,(b) from a controlgateto an emitter, or(c) from a control gateto anothercontrol gate.

8 Analysisof MITE Networks

In thissection,weshall developaby-inspectionanalysisprocedureforMITEnetworksbyextendingtheanalysis procedure for translinear loopsof subthreshold MOStransistors thatwe discussed inSection4.2. We have previously publishedanalysis proceduresfor MITE networks [84,87]. Theanalysismethodthatwedevelophereissomewhatmoregeneralandrequiresfewerinitial definitions.Additionally, we canuse this proceduredirectly to analyzesubthreshold MOStranslinearcircuitsthatmakeuseof thebackgate(i.e., thesubstrate)in additionto thefrontgate[81,88–91]. To do so,wesimply view thefour-terminalsubthresholdMOStransistor asatwo-inputMITE with aweightof & for thefrontgateandof 1 '(& for thebackgateandapply theprocedurethatweshall develop.

Aswegoaroundloopsin aMITEnetwork, wecantraverseaMITEinthreepossibleways, whicharedepictedin Fig. 14. As shown in Fig. 14a,wecantraverseMITE QnÏ , by goingfrom its emitter,Un, to oneof its control gates, Vk; thispossibility correspondsto goingthroughacounterclockwiseelementin a translinear-loopcircuit. In this case, we canrearrangeEq. 21 to obtainthefollowingrecursion relation:

eVkµ ) UT * eUnÔ ) UT

1),+ nkÔ InÏ-n Is±

1),+ nkÔjð/.0 k

eV¶

jò ) UT 1 +

njÔ ),+nkÔ . (32)

Conversely, as shown in Fig. 14b, we can traverse MITE Qn by2

going from oneof its controlgates, Vk, to its emitter, UnÏ ; this transition correspondsto goingthrougha clockwise elementin aconventionaltranslinear-loopcircuit. In thiscase,wecanrearrangeEq. 21 to obtainthefollowingrecursion relation:

eUnÔ ) UT * eV¶

kµ,) UT

+nkÔ -

n Is±InÏ j

ð3.0 k

eV jò ) UT

+njÔ . (33)

Finally, as shown in Fig. 14c, we can traverse MITE Qn by2

going oneof its control gates, Vk

to­

anotherof its control gates, Viß ; this transition hasno analogin conventionaltranslinear-loop

Page 36: circuitos translineares

33

circuits. In thiscase,we canrearrangeEq. 21 to obtainanotherrecursion relationship:

eV¶

i 4 UT¹65

eVkµ 4 UT

¹ 7�8 nkÔ 4 8 niÔ In9n I«s±

14 8 niÔeUnÔ 4 UT

¹ 14 8 niÔjð3:; i < k eV j

ò 4 UT¹ 7�8 njÔ 4 8 niÔ (34)

Thefinalproductin eachof thesethreerecursion relationshipsaccountsfor thecontributionsofperipheral control gates, whichdonot lie directlyontheparticularpaththroughtheMITE networkthatwehavechosen. Multiple translinearloopscanflow togetherthroughtheseextracontrol gates,like tributariesjoining to form a river. Translinear loopscansplit into multiple pathsand mergeback togetheragain. We shall call such translinear loopsconfluent. The existenceof confluenttranslinear loopsmakestheanalysis of MITE networks slightly more involvedthanconventionaltranslinear-loop circuits, because we may have to traverse several confluent translinear loopstoanalyzeagiven circuit completely. To analyzeaMITE network, wefirst identify aloopthroughthecircuit thattraversesmost of theMITEs. We proceedaroundtheloopfrom nodeto node,buildingupatranslinear-loopexpressionaswegoby applyingtherecursion relationshipappropriateto eachtransition. If there is a confluenceof translinear loops, we tracethrougheachoneuntil we havebuilt acompletetranslinear-loopexpression.

Weshall now illustratethisanalysis procedureby applyingit to several simpleMITE networks.Consider the MITE network shown in Fig. 15a,which comprises threetwo-input MITEs. Notethat all of the MITE emitters are groundedin this circuit. In this case, all of the eUnÔ 4 UT factorsin therecursion relationshipsevaluateto unity; consequently, we canignore themin applying therecursion relationships. Moreover, weshall show by constructionin Section9 thatany translinear-loopequationcanberealizedby aMITE network with groundedemitters. However, in somecases,it mayprove beneficialto have someMITE emittersat somepotentialotherthanground. In suchcases, we would have to keeptrackof theemitter factors. To analyzethecircuit of Fig. 15a,wefirst identify a loop throughthecircuit thattraverses as many of theMITEs aspossible. We beginat theemitterof MITE Q1, which is grounded,andproceedto nodeV1 thr

­oughMITE Q1. Then,

we move to nodeV2 thr­

oughMITE Q3= . Finally, we return to groundby moving to theemitter of

MITE Q2. This single looptraverses eachMITE in thecircuit; there are no confluentloops. Byfollowing theprocedure just described,we have that

>1? 14 2 I19

1 I«s

14 2

eV¶

14 UT

7 14 1 I393 I«s±

14 1

eV2@ 4 UT

¹

2 92 I«s

I«2

51,

which we can simplify to get 91

I1

I3=93

2 92

I2

51.

Page 37: circuitos translineares

34

(a) (b)

Q3

I3

Q1

I1

Q2

V2

IA2

V1

I1 IA2

B1

B2

B3

Q3

I3

Q1

IA1

Q2

V2

IA2

V1

IA1 I

A2

B1

B2

B3

Q4

IA4C

B4

Q1

V1

IA1

I1

B1

Q2

V2

IA2

I2

B2

Q3

V3

IA3

I3

B3

Vref Vref

(c)

Figure 15: Three MITE networks comprising two-inputMITEs thatcanbeanalyzedcompletelyby tracingasingle loop. (a) A two-inputgeometric-meancircuit. (b) A squaring-reciprocalcircuit.(c)A multiply-reciprocalcircuit.

By rearrangingtheprecedingequation,we obtainthefollowing translinear-loopexpression:

I3D3

2 E I1D1

I2FD2

,

whichwe cansolve for theoutputcurrent, I3, to get

I3

E D3G D1D

2I1I2.

Thus, the circuit of Fig. 15ais a two-inputgeometric-meancircuit. If eachMITE hasthe samevalueof

D(i.e.,

D1

E D2

E D3= E D

), thentheoutputcurrent is simply given by

I3

EI1I2.

Page 38: circuitos translineares

35

Next, consider the MITE network shown in Fig. 15b, which also comprisesthree two-inputMITEs. To analyzethis circuit, we first identify a loop throughthecircuit that traverses as manyof theMITEsaspossible. Webegin at theemitterof MITE Q1, which is grounded,andproceedtonodeV1 thr

­oughMITE Q1. Then,we move to nodeV2 thr

­oughMITE Q2. Finally, we returnto

groundby moving to theemitterof MITE Q3. Thissingle looptraverseseachMITE in thecircuit;onceagain, there are no confluentloopsfor us to trace. If we go aroundthis loop, applyingtherecursion relationship appropriateto eachmove, wefind that

H1I 1J 2 I1K

1 I«s

1J 2

eV¶

1J UT

L 1J 1 I2K2 I«s±

1J 1

eV2@ J UT

¹

2 K3 Is

I«3= M 1,

whichcansimplify to get K1

I1

I2FK2

2 K3

I3M 1.

By rearrangingtheprecedingexpression,we obtainthefollowing translinear-loopequation:

I2K2

2

M I1K1

I3=K3= , (35)

which, apartfrom a simplerenumberingof thecurrents, is identicalto thatwhich we derivedforthecircuit of Fig. 15a. This result shouldnot betoo surprising, because the two MITE networksshown inFig. 15havethesamebasic topology;they aremerelybiaseddif ferently. WecanrearrangeEq. 35 to obtainthefollowing expression for theoutputcurrent:

I3 MK

1K

3=K 2

2

I 22

I«1

.

Thus, the circuit of Fig. 15b is a squaring-reciprocalcircuit. Again, if eachMITE hasthe samevalueof

K(i.e.,

K1 M K

2 M K3= M K

), thentheoutputcurrent is simply given by

I3 M I 2F2

I«1

.

Next, consider theMITE network shown in Fig. 15c,which comprises four two-inputMITEs.To analyzethis circuit, we first identify a loop throughthe circuit that traverses as many of theMITEs aspossible. We begin at oneof thecontrol gatesof MITE Q1, which is connectedto Vref ,andproceedto nodeV1 thr

­oughMITE Q1. Then,we move to nodeV2

F thr­

oughMITE Q2F . Then,

we moveto V3= thr­

oughMITE Q3= . Finally, we returnto Vref thr

­oughMITE Q4. This single loop

Page 39: circuitos translineares

36

traverses eachMITE in thecircuit; onceagain,there are no confluentloopsfor us to trace. If wegoaroundthis loop,applyingtherecursion relationship appropriateto eachmove, wefind that

eVreN f O UT¹ P 1

1I1Q1 I«s±

11

eV¶

1O UT

P 11 I2Q

2 I«s

11

eV2@ O UT

¹

P 11 I3Q

3= I«s

11

eV¶

3R O UT

P 11 I4Q

4 I«s

11 S

eVreN f O UT¹,

whichcansimplify to get

eV¶

reN f O UT¹ Q

1

I«1

I2Q2

Q3

I«3

I4Q4

SeV¶

reN f O UT¹.

By rearrangingtheprecedingexpression,we obtainthefollowing translinear-loopequation:

I1Q1

I3Q3

S I2Q2

I4Q4

. (36)

WecanrearrangeEq. 36 to obtainthefollowing expression for theoutputcurrent:

I4S Q

2Q

4Q1Q

3= I«1 I«3

I«2

.

Thus, the circuit of Fig. 15c is a multiply-reciprocalcircuit. Again, if eachMITE hasthe samevalueof

Q(i.e.,

Q1

S Q2

S Q3= S Q

4S Q

), thentheoutputcurrent is simply given by

I4S I1 I3

I2.

For eachof theMITE networksthatwehaveanalyzedso far, weonly hadto traceasingle looparoundthenetwork to fully characterizethecircuit. Weshall now considerasimpleexamplewherewe must traceat least two confluenttranslinearloopsto fully analyzethecircuit. Figure16 showsa MITE network comprising four two-inputMITEs. Wecannotidentify a singleloopthroughthiscircuit thattraverseseachMITE—we must consider at least two loopsthatare confluentwith oneanother. To analyzethis circuit, we first identify a loop throughthecircuit that traverses as manyof theMITEs aspossible. As shown in Fig. 16a,we begin at theemitter of MITE Q1, which isgrounded,andproceedto nodeV1 thr

­oughMITE Q1. Then,we move to nodeV3 thr

­oughMITE

Q3. Then,we return to groundthroughMITE Q4. We havenot traversed MITE Q2 at all in thisloop. If we goaroundthis loop,applyingtherecursion relationship appropriateto eachmove, wefind that T

1U 1O 2 I1Q1 I«s±

1O 2

eV¶

1O UT

P 1O 1 I3Q3 I«s±

1O 1

eV3R O UT

¹

1 Q4 I«s

I«4

eV2@ O UT

¹ 1 S1, (37)

Page 40: circuitos translineares

37

(a)

(b)

Q1

I1

Q2

V2

I2

V1

I1 I2

Q4V

IW

4V

Q3

V3

I3

I3

X1

X2

X3

X4V

Q1

I1

Q2

V2

I2

V1

I1 I2

Q4

IW

4

Q3

V3

I3

I3

X1

X2

X3

X4

Figure 16: A MITE network comprising four two-inputMITEs. To analyzethis circuit, we mustconsiderconsider at least two loopsthatareconfluentwith oneanother. (a) Theprimary loopthatwe use to analyzethecircuit. (b) Theconfluentloop thatwe traceto completetheanalysis.

whichhasafactorof eV2Y UT , thatwewouldlike to express in termsof theMITE collectorcurrents.Wecanderivea suitableexpression for eV2

@ Y UT¹

by2

traversing theconfluentloop shown in Fig. 16b.If wegoaroundthissecondloop,applyingtherecursion relationship appropriateto eachmoveandsubstitute theresulting expression for eV

¶2@ Y UT

¹directly into Eq. 37,wefind that

112@ I1Z

1 I«s±

12@

eV¶

1Y UT

[ 11 I3

=Z3 I«s

11

eV3R Y UT

¹

1 Z4 I«s

I«4

112@ I1Z

1 I«s

12@

eV¶

1Y UT

[ 11 I2Z

2 I«s±

11

eV2@ Y UT

¹

1 \1.

By simplif ying theprecedingequation,we have that

Page 41: circuitos translineares

38

]1

I1

1 2 I3]3

]4_

I4_

]1

I1

1 2 I2]2 ` 1,

whichwe canrearrangeto obtainthefollowing translinear-loopequation:

I3]3= I2]

2 `I1]1

I4]4

. (38)

WecanrearrangeEq. 38 to obtainthefollowing expression for theoutputcurrent:

I4 `]

4]

1]2]

3= I«2 I«3

I«1

.

Thus, thecircuit of Fig. 16 is also a multiply-reciprocalcircuit. Again, if eachMITE hasthesamevalueof

](i.e.,

]1 `

]2 `

]3= `

]4 `

]), thentheoutputcurrent is simply given by

I4 `I2 I3

I«1

.

9 ABC’sof MITE-Netw ork Synthesis

In this section,we shall consider the basics of MITE-network synthesis. As wasthe case withtranslinear-loopcircuit synthesis, theproblemof synthesizingMITE networksis underconstrainedandtherearedesigntrade-offsinvolvedintheprocess. Onceagain,in ourbrief discussion,wecannotbeexhaustiveandweshall endeavor tomakethebasic procedureclearillustrateit with somesimpleexamples. The starting point for MITE-network synthesis is identicalto that of translinear-loopcircuit synthesis—a set of translinear-loopequationsderived from somefunctionalor behavioraldescriptionof thesystemto beimplemented.Also, wecanoftenconsolidateMITE networksin thesameway thatwe cantranslinear-loopcircuits, by merging redundantparts of thecircuits thatwehavesynthesized,so thefinalstepsaresimilar too. Consequently, weshall focusonthemiddlestepsin thesynthesis procedure—theconstructionof MITE networksfrom translinear-loopequations.

9.1a

Synthesizing Static MITE Networks

Aswith thesynthesisof translinear-loopcircuits, wecansummarizethesynthesisof MITEnetworksasfollows. First, we acquire a set of translinear-loopequationsfrom a behavioral or functionaldescription of the system that we want to implement. Next, we build a MITE network for eachof the translinear-loopequations, which involvesa building phase, a balancingphase, a biasingphase, and a completionphase. Finally, if possible, we consolidate the resulting MITE networksby merging partsof themwherepossible. Weshall discusseachof thesestepsin turn, thenweshalluse themto synthesizethreesimple MITE networks, a squaringcircuit, one-quadrantmultipliers,anda two-quadrantmultiplier.

Page 42: circuitos translineares

39

Acquiring a set of translinear-loop equations. We start the construction process with a set oftranslinear-loopequations, eachof theform

n b “CW”

I« knÔnÏdc

nÏ b “CCW”

I« knÔn , (39)

where “CW” denotesa set of clockwise currents and “CCW” denotesa set of counterclockwisecurrents(in thecontext of MITE networks, such designationsare not asmeaningful asthey are intranslinear-loopcircuits), andtheknÏ arepositive integerpowersto which thecurrentsare raised,such that

n b “CW”

ke

nÏ cnÏ b “CCW”

ke

n. (40)

With translinear-loop circuits, the reason for restricting the powersto be integersis obvious: Acurrent is raised to a given power because it passes throughan integer numberof TEs facinginthe samedirectionarounda loop. A current cannotpass througha fractionalnumberof TEs.However, with MITE networks, it is certainly possible to allow these powers to be positive realnumberssubjectto theconstraintexpressed in Eq. 40,but weshall restrict ourattentionhere to thecase of integer powers for two reasons. First, integer powers sufficefor many practicalpurposes.Second,with MITE networks these powers are set by ratiosof MITE weightsand we obtainthemost accurate ratios by connectingan integer numberof identicalunit cells in parallel with oneanother. The procedureby which we obtainsuchtranslinear-loopequationsis identicalto theonethat we described in Section 5.

Building MITE networks. For eachtranslinear-loopequation,webuild aMITE network. Webegina MITE network by picking a current from eachset (e.g., current I i

ß f¬rom the“clockwise” set and

current I jð f¬rom the“counterclockwise” set). We createa new MITE for eachoneandmakeanew

nodein thecircuit, couplingit intoMITE Qi thr­

oughk jð unitf inputsand into MITE Q j

ð thr­

oughkiß

unitf inputs, asshown in Fig. 17a.If kiß andk j

ð hag

vea factorin common,wecandividebothby thatfactorin determining thenumberof unit inputsfor eachconnection.For eachadditionalcurrentin thetranslinear-loopequation(e.g., current Ik

º from the“clockwise” set), wecreateanew MITE,andwe makea new nodein thecircuit, connectingit to an existing MITE whose current is fromtheopposite set (e.g., MITE Q j

ð ) throughkk unitf inputsand to MITE Qkº thr­

oughk jð unitf inputs, as

shown in Fig. 17b. Onceagain,if k jð andkk

º have a factorin common,we candivide bothby thatfactorin determining thenumberof unit inputsfor eachconnection.We continueaddingMITEsin this way until we have exhaustedall of thecurrentsin thetranslinear-loopequation.The orderin which we add MITEs andtheexisting MITEs to which we connectthemaffect thestructureofthefinalMITE network andthenumberof inputsrequired fan-in for eachMITE.

Oncewe have built thebasic MITE network for a translinear-loopequation,asjust described,we thenbalancethe fan-in of all MITEs in the network. Suppose that the largest MITE fan-inis K . We thenadd a sufficient numberof unit inputsto eachMITE, connectedto anappropriatevoltageVref , so they eachhavea fan-in of K , asshown in Fig. 17c.As longasthetranslinear-loopequationfrom which we started conforms to Eq. 40, the exact value of Vref is not critical—the

Page 43: circuitos translineares

40h

Qi

Vrefi

QkjIk

jQjkI j

k I i

Vrefikl

i

kl

kjK m kj

kkl

jk k

ljk

K m kjk

(c) (d)

Qi

Vrefi

Qkj

In

kj

Ikj

Qjk

In

jk

I jk I i

Vrefikl

i

kl

kjK m kj

kkl

jk k

ljk

K m kjk

QiQjkI

njk I

ni

kl

i kl

jk QiQk

jIn

kj

QjkI

njk I

ni

kl

i

kl

kjk

ljk k

ljk

(a) (b)

(e)

QiQkj

Ikj

In

kj

Qjk

I jk

In

jk I

ni

kl

i

kl

kjK

o m kjkk

ljk k

ljk

Ko m kj

k

igure 17: Stepsin theconstructionof MITE networks. (a) Beginning thenetwork. (b) Buildingthenetwork. (c) Balancingthenetwork. (d) Biasing thenetwork. (e)Completingthenetwork.

quiescentcollectorvoltagesin theMITE network will dependonthevalueof Vref , but aslongasallof thecollectorvoltagesstaysufficiently far awayfrom thepowersupplyrails, theMITE network’sbehavior is independentof thevalueof Vref .

We needto balancethe numberof inputsto eachMITE in the network because of the wayin which we implementtheweightedvoltagesummation. If we implementtheweightedvoltage

Page 44: circuitos translineares

41h

summation using a capacitivevoltagedivider, asdiscussed in Section6, theneachweightis equalto acouplingcapacitancedividedby atotalfloating-gatecapacitance.Thepower-law relationshipsimplementedby aMITE network aregiven by ratiosof weights. As designers, wewouldlike thesepowers to beindependentof thetotal floating-gatecapacitances, because they include(nonlinear)parasitic capacitances. By requiring the total floating-gatecapacitanceof eachMITE to be thesame,thetotalfloating-gatecapacitanceswill cancelin theweightratios, makingthemdependonlyon ratios of couplingcapacitors. Thebest way to ensure that the total floating-gatecapacitancesare thesame is to require thateachMITE have anidenticalcomplementof inputs. In thecontextof integernumbersof unit inputs, wewouldgiveeachMITE thesamenumberof unit inputs.

Biasing MITE networks. Theprocessof biasingaMITE network is considerablysimpler thanthatof biasing a translinear-loopcircuit. We simply force inputcurrentsinto thecollectors of someoftheMITEsanddiode-connectthemby connectingsomeof theircontrol gatesto theircollectors, asshown in Fig. 17d.Those MITEs thatarediodeconnectedbecomeinputs, while those thatarenotdiodeconnectedareoutputs. Otherbiasingschemesare certainly possible,but arenever needed.

CompletingMITE networks. It mayseemthatby addingunusedMITEs in theprocessof balancingthefan-in inaMITEnetwork, wearewasting resources. Indeed,suchunusedinputscanaccountforasignificantfractionof thetotal transconductanceof aMITE. Leaving themunusedleadsto largercollector-voltageswingsandahigherrequired power-supplyvoltage.It so happensthat,as longasthetranslinear-loop equationfrom which we startedconformsto Eq. 40, we canutilize all of theextra control gatesthatwe addduring thebalancingphase [84]. Intuitively, because thebehaviorof a MITE network is unaffectedby the valueof Vref , we canshort Vref to

­oneof the collector

voltagesin theMITE network without affectingthebehavior of thecircuit. This MITE-networktransformationiscalledcompletion[84]. Weconnectall of theunusedinputstooneof thecollectorvoltages, asshown in Fig. 17e. In doingso, we shouldgenerally avoid thecreationof feedbackloopsin theMITEnetwork thatcouldaffectits stability. Wecanalwaysdothisbychoosing aMITEthatonly hasself connections.

ConsolidatingMITEnetworks. Insomecases, aswith translinear-loopcircuits, afterwehavebiasedeachof theMITE networks in thecircuit, we will recognizesomeredundancy betweenthem. Forexample, if two MITEs in different networks pass the same current and their control gatesareconnectedin thesamemanner, thenthese MITEs are redundantandmay be shared betweentheMITE networks. Suchconsolidation is usually a goodidea,because it usually results in smallercircuits and fewer opportunities for errors resulting from device mismatch. Other, more subtleformsof MITE-network consolidationarepossible [92], but arebeyondthescopeof this report.

9.2a

Synthesisof a MITE-Network Squaring Circuit

Supposethatwewantto implementasquaringoperationwith astrictly positiveinputusing aMITEnetwork. That is, we wantto findaMITE network thatimplementstherelationship

x p y2, (41)

Page 45: circuitos translineares

42h

QxqIrxq

Qus QytIrus I

ryt

QxqIrxq

QytIryt

QxqIxq

Qus

Ius

Qyt

IytIus Iyt

(a) (b)

(c)

Figure18: Synthesisof aMITE-network squaringcircuit. (a) Beginningthenetwork. (b)Buildingthenetwork. (c) Biasing thenetwork.

where x u 0 and y u 0 are dimensionless quantities. Herey is theindependentvariable(i.e., theinput) and x is thedependentvariable(i.e., theoutput). First, we represent x by Ixvxw Iu andy byIy¡yw Iuª , where Iu is

átheunit current. Then,we substitute these definitionsof x and y into Eq. 41,

gettingIxvIuª{z Iy¡

Iu

2

,

whichwe caneasily rearrangeto obtainthefollowing translinear-loopequation:

Ixv I«uª

“CW”z I 2

Fy

“CCW”

. (42)

Starting from Eq. 42,we select Iy¡ f¬rom the“CCW” set and Ixv f

¬rom the“CW” set and makea

MITE for eachone.Then,wemakea new nodein thecircuit andcoupleit intoMITE Qxv thr­

oughtwo unit inputsand into MITE Qy¡ thr

­oughoneunit input,asshown in Fig.18a.Next, weselect Iu

f¬rom the“CW” set and makeanotherMITE for it. We makea new nodeandcoupleit into MITEQy¡ , which is our only choicein this case, throughoneunit inputandinto MITE Quª thr

­oughtwo

unit inputs, asshown in Fig. 18b. Next, we balancethe fan-in of all MITEs. In this case, each

Page 46: circuitos translineares

43h

Q|

z}V~

ref�Qu�

Iu�I�

u�Q|

y�Iy�

I�

y�Qx�

Ix�I�

x� I�

z}

Vref�Qz}Q

|u�

Iu�I�

u�Qy�

Iy�I�

y�Qx�

Ix�I�

x� I�

z}

Qz}Qu�I�

u�Qy�I�

y�Qx�I�

x� I�

z}Qz}

Vref�Q|

u�I�

u�Qy�I�

y�Qx�I�

x� I�

z}

Vref�

Qz}Qx�Ix� Iz}Qz}Qy�Iy�

Qx�Ix� Iz}

(a)

(c)

(b)

(d)

(e) (f)

Figure 19: Synthesis of a one-quadrantMITE-networkmultiplier. (a) Beginning the network.(b) Building the network. (c) Building thenetwork. (d) Balancingthenetwork. (e) Biasing thenetwork. (f) Completingthenetwork.

MITE hasthesamenumberof inputs, so thenetwork is alreadybalanced.Webiasthenetwork byforcing Iu intoMITE Qu anddiodeconnectingit throughits two unit inputs. Then,weforce Iy¡ intoMITE Qy¡ anddiodeconnectit throughoneof its control gates, asshown in Fig. 18c.Therearenounusedinputs, so theMITE network requiresno completion.Finally, no consolidationispossible.

9.3a

Synthesis of One-Quadrant MITE-Network Multip liers

Suppose thatwewantto implementa multiplicationoperation with strictly positive inputsusing aMITE network. That is, we wantto findaMITE network thatimplementstherelationship

z � xy, (43)

where x � 0, y � 0, andz � 0 are dimensionless quantities. Herex andy are the independentvariables(i.e., theinputs) andz is thedependentvariable(i.e., theoutput). First, werepresentx by

Page 47: circuitos translineares

44h

Ixvx� Iuª , y by Iy¡3� Iu andz by Iz� � Iuª , where Iu isá

theunit current.Then,wesubstitute thesedefinitionsof x, y, and z into Eq. 43,getting

Iz

Iu �IxvIuª

Iy¡Iu

,

whichwe caneasily rearrangeto obtainthefollowing translinear-loopequation:

Iz� Iu

“CW”� Ixv Iy¡“CCW”

. (44)

Startingfrom Eq. 44, we shall synthesize two dif ferentMITE networksto illustratehow thebuilding order can influencethe structureof the final MITE network. We begin the first MITEnetworkby selectingIz from the“CW” set and Ixv from the“CCW” setandmakeaMITE for eachone. Then,we makea new nodein thecircuit andcoupleit into MITE Qz thr

­oughoneunit input

andintoMITE Qxv thr­

oughoneunit input,asshown in Fig.19a.Next, weselect Iy¡ from the“CW”set and makeanotherMITE for it. We makea new nodeandcoupleit into MITE Qz thr

­oughone

unit inputandintoMITE Qy¡ thr­

oughoneunit input,asshown in Fig.19b. Next, weselect Iuª fro¬

mthe“CCW” set andmakeanotherMITE for it. We makea new nodeandcoupleit into MITE Qy¡thr­

oughoneunit inputandinto MITE Qu thr­

oughoneunit input,as shown in Fig. 19c. Next, webalancethefan-in of all MITEs. In thiscase,MITEs Qz andQy¡ ha

gve two inputs, whereasMITEs

Qxv andQuª hag

ve only one. To balancethefan-in in theMITE network, we addanotherunit inputto MITEs Qxv andQuª , eachconnectedto Vref , as shown in Fig. 19d. Next, webiasthenetwork byforcing Iu into MITE Quª , Iy¡ into MITE Qy¡ , and Ixv into MITE Qxv , and diodeconnecteachonethroughonecontrol gate,asshown in Fig. 19e.This MITE network implementsEq. 43,but it hastwo unused inputs. We canutilize these two inputsand completethenetwork by connectingVref

to­

thecollectorof MITE Quª , as shown in Fig. 19f. This MITE network also implementsEq. 43,but hasnounusedinputs. Finally, no consolidationis possible.

Webegin thesecondMITE network by selectingIz� fromthe“CW” set and Ixv from the“CCW”set and makea MITE for eachone. Then,we makea new nodein thecircuit andcoupleit intoMITE Qz� thr

­oughoneunit inputandintoMITE Qxv thr

­oughoneunit input,as shown in Fig. 20a.

Next, we select Iu from the“CCW” set andmakeanotherMITE for it. We makea new nodeandcoupleit intoMITE Qxv thr

­oughoneunit inputandintoMITE Qu thr

­oughoneunit input,asshown

in Fig. 20b. Next, we select Iy¡ from the “CW” set and makeanotherMITE for it. We makeanew nodeandcoupleit intoMITE Qy¡ thr

­oughoneunit inputandinto MITE Quª thr

­oughoneunit

input, as shown in Fig. 20c. Next, we balancethe fan-in of all MITEs. In this case, MITEs QxvandQuª have two inputs, whereasMITEs Qy¡ andQz� have only one. To balancethefan-in in theMITE network, weaddanotherunit inputto MITEs Qy¡ andQz� , eachconnectedto Vre� f , as shownin Fig. 20d. Next, webiasthenetwork by forcing Iuª into

áMITE Qu, Iy¡ into

áMITE Qy¡ , and Ixv into

áMITE Qxv , anddiodeconnecteachonethroughonecontrol gate,asshown in Fig. 20e.ThisMITEnetwork implementsEq. 43,but it hastwo unusedinputs. We canutilize these two unusedinputsandcompletethenetwork by connectingVref to

­thecollectorof MITE Qy¡ , as shown in Fig. 20f.

Notethat,if wehadconnectedVref to­

thecollectorof MITE Quª , thenwewouldhave introduceda

Page 48: circuitos translineares

45h

Q|

z}Qy�I�

y�Q|

u�I�

u�Qx�I�

x� I�

z}Qz}

Vref

Q|

y�I�

y�Qu�I�

u�Qx�I�

x� I�

z}

Vref

Q|

z}Qx�Ix� Iz}Qz}Qu�Iu�

Qx�Ix� Iz}

(a)

(c)

(b)

(d)

(e) (f)

Qz}Q|

y�Iy�

I�

y�Qu�

Iu�I�

u�Qx�

Ix�I�

x� I�

z}Q|

z}V~

ref

Qy�Iy�

I�

y�Q|

u�Iu�

I�

u�Qx�

Ix�I�

x� I�

z}

V~

ref

Figure 20: Synthesis of a one-quadrantMITE-networkmultiplier. (a) Beginning the network.(b) Building the network. (c) Building thenetwork. (d) Balancingthenetwork. (e) Biasing thenetwork. (f) Completingthenetwork.

positive feedbackloop into theMITE network with a loopgainof unity, makingthedesired MITEnetwork equilibriumanunstableone.If wehadconnectedVref to

­thecollectorof MITE Qxv , thenwe

wouldhave introduceda negative feedbackloop,creatingthepotentialfor instability. This MITEnetwork also implementsEq. 43,but hasnounusedinputs. Finally, no consolidationispossible.

We have synthesizedfour differentMITE networks (i.e., those shown in Figs. 19e,19f, 20e,and20f) thateachimplementEq. 43. The circuitsof Fig. 19 are more symmetric with respect tohow many stagesseparatethex andy inputsfrom thez outputthanthose of Fig. 20. Intuitively,we shouldexpectthat,a MITE network with fewer stageson averagebetweenthe inputsand anoutputswouldbelesssensitiveto mismatchin MITE weightvaluesthanwouldbeaMITE networkwith morestages. We have demonstratedthis fact for these four one-quadrantmultiplier circuitselsewhere [84]. The circuits shown in Fig. 19 dif fer from those shown in Fig. 20 in theorder inwhichweselectedthecurrentsin thebuilding processandwherewechoseto connecttheirMITEs.Becausethenumberof waysinwhichcurrentscanbechosenfromatranslinear-loopequationgrowsrapidly in thenumberof currents, it is difficult to say general thingsabouthow thechosenorder

Page 49: circuitos translineares

46h

Qz�Q�

u�I�

u�Iu�

Qy�I�

y�Iy�

Qx�I�

x�Ix� Iz� ��� �

�Q�

z� Qx�I�

x�Ix�Iz� � �

���

Qz�Q�

u�Iu�

I�

u�Qy�

Iy�I�

y�Qx�

Ix�I�

x� I�

z� ��� ��

Q�

z� Q�

u�Iu�

I�

u�Qy�

Iy�I�

y�Q�

x�Ix�

I�

x�I�

z� � ��

��

(a)

(b)

Figure 21: Synthesisof a two-quadrantMITE-networkmultiplier. (a)Two independentcopiesofthe one-quadrantmultiplier of Fig. 19f. (b) The final consolidatedtwo-quadrantMITE-networkmultiplier circuit. Herewehave sharedthe Iy¡ and Iuª circuitry betweenthetwo MITE networks.

affectstheperformanceof thefinal MITE network. However, we shall makesomeobservations.First, themoreMITEsthatweconnectto any givenMITE, thelargertherequired fan-in perMITEin thenetwork asawhole,but theless theaveragenumberof intermediatestagesbetweenany twoMITEs. We have shown previously [84] that any translinear-loopequationcanbe implementedasa MITE network with a maximum of oneMITE betweenany pair of MITEs. MITE networkswith fewerintermediatestagesshouldbelesssensitiveto offsetandnoiseaccumulationthanMITEnetworkswith more intermediatestages. Additionally, theresponse time of a MITE network withfewerintermediatestageswill befasterthanthatof aMITE networkwith moreintermediatestages,because of parasitic nodecapacitances.

9.4a

Synthesis of a Two-Quadrant MITE-Network Multip lier

Supposethatwewantto implementacircuit thatmultipliestwoquantities,x andy, wherex canbeeitherpositiveor negativeandthaty is strictly positive. Thus, their product,z, which is given by

z � xy, (45)

Page 50: circuitos translineares

47h

canbe eitherpositive or negative. We shall represent y by Iy¡3� Iu andwe shall use a differentialrepresentationfor x andz, as describedin Section3; thatis, we representx by

x � x ��� x � ,

where x ��� I �x � Iu andx ��� I �x � Iu. Likewise,werepresentz by

z � z��� z� ,

where z��� I �z � Iuª andz��� I �z � Iu.Next, we substitute these definitionsfor x, y, and z into Eq. 45 to get

I �zIuª � I �z

Iu� I �x

Iuª � I �xIu

Iy¡Iuª ,

whichwe canrearrangeto obtain

Iu I« �z � Iu I

« �z � Iy¡ I« �x � Iy¡ I

« �x .

Onestraightforward way to decompose this equationinto a pair of translinear-loopequationsis to equateindividually thepositive andnegative terms on eachsideof theequation. Using thisdecomposition, we obtainthefollowing pairof translinear-loopequations:

Iuª I« �z

CW

� Iy¡ I« �x

CCW

and Iu I« �z

CW

� Iy¡ I« �x

CCW

.

By following theprocedure shown in Fig. 19 for eachof these translinear-loopequations, weobtainthetwo independentMITE networks shown in Fig. 21a. Notethat in eachMITE network,we supply a copyof Iu to

­a MITE that is diodeconnectedthroughtwo unit inputs. The collector

voltagesof these two MITEs shouldbe identical,so we canshare a single MITE Qu between2

thetwo networks. Also, in eachnetwork, we supply a copyof Iy¡ to

­a MITE that is diodeconnected

througha single control gateand its othercontrol gateis connectedto an identicalvoltage. Thus,theircollectorvoltagesarealso identical,andweshouldbeabletoshareasingleMITE Qy¡ between

2thetwo circuits. Theconsolidatedtwo-quadrantMITE-networkmultiplier is shown in Fig. 21b.

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48h

References

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