Critical Signal Flow for Power Estima-tion: The Road to Billion Gate SoC Power

Verification

Chungki Oh,

Jianfeng Liu, Seokhoon Kim, Kyung-Tae Do,

JungYun Choi, Hyo-Sig Won, Kee Sup KimJeongwon Kang, Kamlesh Madheshiya, Arti

Dwivedi

Design Technology Team

System LSI DivisionSamsung Electronics

Ansys Apache

Table of Contents

Mobile SoC Design Trend

Challenges in SoC Power Analysis

Power Critical Signal Flow in RTL/Gate power analysis

Summary

Mobile SoC Design Trend

The design size of mobile SoC has been increasing at a rapid speed Fierce competition in mobile market has driven SoC design to provide high perfor-

mance and numerous functionality, which was only previously available in PC and laptop

To meet the power wall of mobile design and leverage the additional capacity in sili-con processing scaling, multiple cores and parallelism are popular in current SoC de-sign

Billion

Gate

SoC

SoC consumer portable design complexity trends- ITRS, 2011 edition

Challenges in SoC Power Analysis

The era of billion gate SoC design put significant challenges for power analysis Simulation is needed to analyze the dynamic power accurately. However, for billion

gate SoC, the simulation runtime is becoming too long for reasonable design cycle The simulation waveform generated from simulation can occupy more than hundreds

of GigaBytes, which puts significant burden on power analysis tools to deal with.

10’s of modes

Millions of clocks

. .

. .

Video stream-ing

GPS + Voice Call

Web + Email

RTL Power Estimation Flow

Basic concept of RTL power estimationInputs: RTL-coded design, power library, capacitance model, activity file1. Elaborate: RTL design is compiled and elaborated into an interconnection of

primitive gates2. Calculate Power: Design is mapped to the target technology and average/time-

based power analysis is performed based on switching activity

To obtain reasonable accuracy, simulation is needed for vector-based power estimation

PowerArtist

Elaborate

Calculate Power

RTL(Verilog/VHDL)

RTL power report

Power Library(.lib)

Activity File(.vcd/.fsdb/.saif)

Capacitance model

Verilog Simulation

Micro-architecturalInferred netlist

Critical Signal Extraction with PowerArtist Generate a significantly smaller power-critical-signals-only FSDB

from the Emulator/Simulator

Full FSDB

Verilog Simu-lation

RTL Test Bench

testbench.top_inst.temp_outtestbench.top_inst.temptestbench.top_inst.entestbench.top_inst.outtestbench.top_inst.clktestbench.top_inst.inCtestbench.top_inst.inBtestbench.top_inst.inA

initial befin$fsdbDumpfile(“pa_extracted.fsdb”);$fsdbDumpvarsByFile(“sig_file_name”);end

RTL

Power-Critical Signal Extraction

PowerArtist

Verilog Simulation

Partial FSDB

Critical Signal List

Test Bench

Power-Critical Functional-Debug Signals

Identify Power-Critical Signals

Power Analysis + Debug

L1

Apache PowerArtist

Reduced FSDB

Simulator/Emulator

Optimized for power analysis over entire simulation duration

Identify Function-Critical Signals

Functional Debug

L2

Functional Debug Tools

Reduced FSDB

Simulator/Emulator

Optimized for functional debug over limited clock cycles

The Principle of Power-Critical Signal Flow Power-critical signals

Activity for only a subset of signals is necessary for accurate power estimation Critical signals consists of signals such as sequential and module in/out ports

Non-critical signals Activity propagation can be performed for the remaining signals based-on activity

propagation formulae of various cell types

IO cells

Flip-Flops

ICGCs

Latches

PI & PO

MUX

Power-Critical Signal Flow with PowerArtist Application

Power-critical signals can be extracted for both RTL and gate-level designs Critical signals can be utilized in simulation as well as emulation flows

Impact Activity file dumped only for power-critical signals saves simulator/emulator and power analysis

runtime and memory resource with small error in power analysis Power-critical signal flow enables power analysis of huge design for which power estimation

used to be unrealizable

Elaborate

Calculate Power

RT/Gate-level design

RTL Power Report

Power Library

Partially dumped Activity File

Wire Load Model

Simulation/Emulation

Micro-architecturallyInferred netlist

Crit. Sig. Extraction

Crit. sig. list Test Bench

Time &

Mem-

ory

Saving

Time &

Mem-

ory

Saving

Power-Artist

Critical Signal Flow for RTL Power Estimation Experimental result with Design-A in RTL

The first experiment was done with a multimedia codec IP design Design size is about 8 Million Gates, with 32nm library

CP

U t

ime

Impact on CPU time

69%

Time

reduc-

tion

46%

Mem-

ory

saving 5%

Power

mis-

match

58%

Disk

sav-

ing

Impact on memory resource & power result

Critical Signal Flow for RTL Power Estimation (2) Experimental result with Design-B in RTL

The second experiment was done with quad-core CPU block Design size is Tens of Million Gates, with 32nm library

CP

U t

ime

[hr]

117

2412

14

78%

Time

reduc-

tion

Impact on CPU time

42%

Mem-

ory

saving

2%

Power

mis-

match

73%

Disk

sav-

ing

Impact on memory resource & power re-sult

Critical Signal Flow for Gate-level Power Estimation Experimental result with Design-A in Gate-level

The third experiment was done with same design as the first one but in gate-level Design size is about 8 Million Gates, with 32nm library

69%

Time

reduc-

tion

CP

U t

ime

Impact on CPU time

87%

Mem-

ory

saving9%

Power

mis-

match

97%

Disk

sav-

ing

Impact on memory resource & power re-sult

Summary

In the era of billion gate SoC chip design, the runtime and generated waveform database size are challenging issues for accurate power estimation.

To solve this challenge, we have proposed to use a subset of the full signal list in the design when dumping the waveform. We have introduced the methodology on how to choose this signal subset for good power correlation while keep this signal subset small enough.

The PowerArtist power critical signal flow has been verified by extensive experiments covering both RTL and gate-level power estimation flows.

Our experimental results show that critical signal flow cut the runtime by 70-80%, simulation waveform size by 60-97%, while keeping the power correlation within less 10% mismatch.