CHPPE 2016 Research Highlights

2015 Neil Ave, STE 205

Columbus, OH 43210

http://chppe.osu.edu/

2

Table of Content

► Chapter 1: Passive Components and GaN Transistors

– Asymmetrical SuperCap Research Highlights

– Ultra-Wide Gap AlGaN Channel Transistors

– Dielectric/III-Nitride Based MOSFETs

► Chapter 2: Applications of Power Electronics Circuits

– Dynamic, On-Chip Power Supply Grids

– Low-Noise, Low-EMI Switching Power Converters

– Energy Harvesting Platforms

– Si-WBG HyS (Hybrid Switch)

– Three Level T-Type Power Electronics Building Block

– Effects of RWP and Filters on WBG Device Switching

– Evaluation of a Interleaved Zero Current Switching Inverter against Interleaved

Hard Switching Inverters

3

Table of Content

► Chapter 2: Applications of Power Electronics Circuits (cont.)

– Power Loss Model for MHz Critical Conduction Mode Power Factor Correction

Circuits

– Adaptive Constant Power Control and Power Loss Analysis of a MHz GaN based

High Power Density AC/DC Converter for Low Power Applications

– Touch Current Suppression for Semiconductor-Based Galvanic Isolation

– Electromagnetic Noise Mitigation for Ultra-fast On-die Temperature Sensing in

High Power Modules

– 10 kW High Power Density GaN-based Three Phase Inverter

– SiC based Modular Multilevel Converter

– 1.7 kV SiC Power Module Gate Drive Design for MMC

– Medium Voltage SiC Power Module Evaluation and Gate Drive Design

– Comparison on GaN Device Based LLC, Phase-Shift Bridge and Phase-shift QSC

Circuits

4

Table of Content

► Chapter 2: Applications of Power Electronics Circuits (cont.)

– Power Module Packaging and High Power Density Three-Phase Inverter Design

– Comparison of A Novel 4-Level Hybrid Clamped Converter and A 4-Level MMC

for Motor Drive Application

– Design of 30kVA Inverter Using SiC MOSFET for 180℃ Ambient Temperature

Operation

► Chapter 3: High Voltage

– Low Pressure Partial Discharge

– Efficiency and Electromagnetic Interference Analysis of Wireless Power

Transfer for High Voltage Gate Driver Application

► Chapter 4: Microgrid and Distributed Energy Resources

– Study of DC Arc Fault in Power Distribution System on Mild Hybrid Electric

Vehicles

– Intelligence Relay for Islanded Microgrid

5

Table of Content

► Chapter 4: Microgrid and Distributed Energy Resources (cont.)

– Control Method to Prevent Microgrid Collapse

– Viterbi Algorithm Based Distribution System Restoration

– Smart Loads to Prevent Stalling of Microgrid

► Chapter 5 Electric Machine Design and Analysis

– PM synchronous machine with high power density and high efficiency

– Copper cage induction machine for EV applications

– Other electric machine and control

6

Chapter 1

Passive Components

7

SuperCap Research highlights

Hao Yang Contact: Dr. Wu Lu (lu.173@osu.edu)

8

Asymmetrical SuperCap Research Highlights► Hybrid electrodes combine the

advantage of high power density, long cycling stability of carbon electrodes and the high energy density of metal oxides

► Asymmetrical structure extends the potential window of existing electrolytes leading to high energy density

MWCNTGraphene

MoO3

WO3

V2O

5

RuO2Co

3O

4

MoO2

Fe3O

4

CuO

TiO2

In2O

3

Cu2O

SnO2CoO

Wo

rk F

un

cti

on

/eV

MnO2

Metal Oxides

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

8

7

6

5

4

Cation

Total potential window

E=E0+E

1+E

2

E2

The chemisorption of H+

OH-

H+

Ele

ctro

chem

ical

Pot

entia

l /eV

MnO2

MoO3

The chemisorption of OH-

E1

E0

Anion

Hao Yang Contact: Dr. Wu Lu (lu.173@osu.edu)

9

Ultra-Wide Gap AlGaN Channel Transistors• Ultra-wide bandgap AlGaN – EG_AlN (6.2 eV) > EG_GaN (3.4 eV)

• Breakdown field: FBR_AlN (15 MV/cm) > FBR_GaN (3 MV/cm)

• Could enable high power / high threshold normally-off transistors

Sanyam Bajaj, Faith Akyol, Sriram Krishnamoorthy and Yuewei Zhang

0 5 10 15 200

10

20

30

40

50

60

VGS

= -2 V

I D (

mA

/mm

)

VDS

(V)

VGS

= 2 V

0 50 100 150 200 2500

20

40

60

80

100

120

140 VGS

= -9 V

IS

IG

ID

I D,I

S,I

G (A

/mm

)

VDS

(V)

LGD

= 1.1 m

(compliance)

Heterostructure engineered graded ohmic

contacts

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91E-7

1E-6

1E-5

1E-4

1E-3

0.01

0.1

France et al.

APL (2007)

Wang et al.

El. Mat. (2004)

Srivastava et al.

El. Mat. (2009)

Yun et al.

EDL (2006)

This work

Baca et al.

APL (2016)Yafune et al.

El.Lett. (2014)

Yafune et al.

JJAP (2011)

Nanjo et al.

APL (2008)

Yafune et al.

JJAP (2011)

C (

.cm

2)

Al composition in AlGaN channel

GaN HEMTs [ref]

Al0.75Ga0.25N channel MISFET with

low RC

IDS_MAX of 60 mA/mm ;

3T breakdown of 200 V/μm

Contact: Dr. Siddharth Rajan(rajan.21@osu.edu)

10

Dielectric/III-Nitride Based MOSFETs

• Interface control enables high-performance MOSFETs

• Low hysteresis, subthreshold slope

• High mobility and on-off ratio

- Normally-off MOSFET

- Vth = +1.08 V (at ID = 10-3 mA/mm)

- ∆V = 100mV

- Saturation Ids ~ 320 mA/mm

- Maximum gm = 90 mS/mm

- Subthreshold swing = 67 mV/dec.

- Mobility = 225 cm2/V-s

0.4um0.4um

GaN

SG

DAl0.26Ga0.74N

10nm Al2O3

6um2um

0 20 40 60 80 100-6

-4

-2

0

2

4

GaN

Al 2

O3

EV

E

nerg

y (

eV

)

Distance (nm)

Ga-polar

EC

-4 -2 0 2 40.0

0.2

0.4

0.6

0.8

1.0

2D

EG

de

ns

ity(x

10

12,c

m-2)

C (F

/cm

2)

VG (V)

F = 100 kHz

Forward scan (-4V to 4V)

3

6

9

12

15

-4 -2 0 2 4 610

-10

10-8

10-6

10-4

10-2

100

102

104

IGS

VG(V)

~1010

SS = 67 mV/dec.

I D

(mA

/mm

)

ID

LG = 5m

LGS

,LGD

< 1m

VD = 10V

0 2 4 6 8 100

50

100

150

200

250

Mo

bilit

y [

cm

2V

-1s

-1]

2DEG desnsity [x1012

cm-2]

Low field mobility

VD = 0.5V

FEg

m/ [C

oxx(W/L

G)xV

D]

-4 -2 0 2 4 60

70

140

210

280

350

gm(m

S/m

m)

I D(m

A/m

m)

VG(V)

0

20

40

60

80

100

Contact: Dr. Siddharth Rajan(rajan.21@osu.edu)Sadia K. Monika, Sanyam Bajaj

11

Chapter 2

Applications of Power Electronics Circuits

12

Dynamic, On-Chip Power Supply Grids

Dynamic Voltage and Load Operation

Summary:

► Goal Large number of dynamic and highly-efficient on-chip power supplies

► Purpose Adaptive, real-time powering of highly integrated systems

► Approach Multi-frequency SIMO and MIMO power converters with fully-

integrated outputs in nanometer CMOS

► Applications System-on-Chip and multi-core processors

Contact: Dr. Ayman Fayed (Fayed.1@osu.edu)Muhammad Ahmad to continue future work

A 5-output implementation

in 65-nm CMOS Characterization Setup

13

Low-Noise, Low-EMI Switching Power Converters

Low and high frequency spectral behavior

Summary:

► Goal Switching schemes to eliminate spurious noise and

reduce EMI

► Purpose Enable using switching power converters within

noise-sensitive devices to achieve much higher power efficiency

► Approach Spur-free spread-spectrum switching techniques

► Applications Wireless communication devices

Contact: Dr. Ayman Fayed (Fayed.1@osu.edu)Muhammad Ahmad to continue future work

Hysteretic Implementation in 0.35-µm CMOS

14

Energy Harvesting Platforms

MPPT operation with 3-point sampling

Summary:

► Goal Energy harvesting platforms with regulated battery management

► Purpose Significant improvement in system running time with a much less number of batteries and less device weight

► Approach Single-step, multi-input multi-output power converters using a single inductor to harvest solar, mechanical,

thermal, and wireless energy

► Applications Portable soldier, biomedical implants, sensor grids, and IoT devices

Contact: Dr. Ayman Fayed (Fayed.1@osu.edu)Ahmed Abdelmoaty and Sita Asar to continue future work

Battery charging and

discharging phases

15

Si-WBG HyS (Hybrid Switch)

Amol Deshpande Contact: Dr. Fang Luo (luo.571@osu.edu)

Motivation:

High Power Density and High Efficiency for High Power Converters►Recommended maximum switching frequency for IGBTs < 20 kHz

Challenges to replace Si IGBT with WBG device►WBG power devices are available in small die sizes only

►Need to parallel multiple devices for high current

►Emerging technology/Reliability is under evaluation

►Expensive

A Mixed Technology Switch

Applications: Electric Propulsion Aircrafts/EVs

Proposed ConceptSwitching Energy Comparison

Research Outcomes:►>75 kHz switching frequency for High Power Converters

►>50% savings in switching loss

►Die Size Optimization Algorithm/ 6:1 (Si:SiC) Die Current Ratio

►Relaxed Thermal Management System

►79% Cost Reduction compared to a single WBG Switch

► Influence of parasitics in the interconnections

Proposed Gate Control

Dynamic Current Sharing: Influence of Interconnect Parasitic Inductance

Switching Frequency Limits

16

Three Level T-Type Power Electronics Building Block

Amol Deshpande, Kailin Chen, Yingzhuo Chen, Balaji Narayanasamy, Arvind Shanmuganaathan Contact: Dr. Fang Luo (luo.571@osu.edu)

1. DC+

2. DC Neutral

3. DC-

4. AC

5. Common Source

Motivation:►Specific Power Density: 25 kW/kg

►Low Profile/Footprint & Good Form Factor

►Minimum Loop inductance

►Low Switching and Conduction Losses

Approach and Research Outcomes:Si-SiC HyS (Hybrid Switch) for low losses

Multi-Layer (5) Busbar Concept

Minimum Loop inductance

►< 25 nH excluding Modules

►< 40 nH including Modules

Low Weight using Aluminum Bars

PCB Capacitor Bank

Coldplate

Gate Driver

HyS:

Si IGBT Module

SiC MOSFET ModuleDiscrete based HyS

Multi-layer Busbars

17

Effects of RWP and Filters on WBG Device Switching

►Highlights of Work:

• Effects of RWP (Reflected Wave Phenomenon) Currents & Voltages on device switching is studied

• Cable and motor load reduce the device dv/dt and increase switching losses

• Output inductor increases losses but increases damping time for reflected wave and does not reduce dv/dt at motor terminals

• RC filter reduce dv/dt at load but increase switching losses

• A combination of Laux and RC terminal network identified for reduced losses

• Simulation and experimental verification using Double Pulse Test of CREE C2M0080120D & C4D20120D

+

-

STH

STL

Lo

ad

VTL

+

-ITL

Cable

+

-

Vlo

ad

LauxVDC

Condition Eon (µJ) Eoff (µJ) Etotal(µJ) Vload(V)dv/dt at

load (V/ns)

4m + Motor 24.7 266.2 290.9 759 8.3

4m + Cable + Laux 25.2 242.7 267.8 818 3.6

4m + Cable + RC 24.7 265.9 290.6 610 4.3

4m + Cable + RC + Laux 25.3 252.2 277.4 574 2.6

Impedance comparison

(as seen by top device)

Increased Damping Time of RW

(comparison w/ and w/o Laux)

Schematic of Test Setup

Contact: Dr. Fang Luo (luo.571@osu.edu)Balaji Narayanasamy, Arvind Shanmuganaathan and Amol Deshpande

18

Evaluation of a Interleaved Zero Current Switching Inverter against Interleaved Hard Switching Inverters

Yingzhuo Chen, Arvind Shanmuganaath Sathyanarayanan, Balaji Narayanasamy, Wenda Feng Contact: Dr. Fang Luo (luo.571@osu.edu)

Motivation:► interleaved technique

►Zero Current Transition without complex circuit

►Reducing passive components with same active switches

Conclusion:

1. Both topologies achieve evenly distributed loss on phases within switching

cycle, thus requiring the same current rating device

2. Device output capacitance resonates with small interphase inductor, thus

generating additional conduction and switching loss

3. Turn-on loss reduction is related to switching frequency and inductance

value indirectly

4. Inductor loss in IZCTI is higher than its in IHSI in high switching frequency

5. DM noise from 4 MHz to 40 MHz is effectively attenuated in IZCTI compared

to IHSI

Topology of IZCTI Topology of IZCTI

7uH7uH

300uH300uH

Switching on Trajectory of IHSI Switching Trajectory of IZCTI

Efficiency of IZCTI Efficiency of IHSI

Input DM Noise Comparison

Volume Comparison of Two Sets of Inductors

19

Power Loss Model for MHz Critical Conduction Mode

Power Factor Correction Circuits

Contact: Dr. Jin Wang (wang.1248@osu.edu)Chengcheng Yao, Yue Zhang, Xuan Zhang, Huanyu Chen and He Li

Vgs

IL

Iac

Vds

t

t

tt1 t2 t3 t4 t5 t6

0 20 40 60 80 100 120 140 160 180

Grid Phase (deg)

0.5

1

1.5

2

2.5

3

3.5

Fre

qu

ency

(H

z)

106

1.30

1.80

2.30

2.80

3.30

3.80

90%

91%

92%

93%

94%

95%

96%

10 30 50 70

Loss

(W

)

Eff

icie

ncy (

%)

Output Power (W)

Experimental Efficiency Estimated Efficiency

Experimental Ploss Estimated Ploss

t

I III IIIII

Iac IL_peakIL IL_valley

Ind

ucto

r C

urren

t (A

)

σ σ

MHz CrM Mode PFC Difference:► Larger negative inductor peak current.► Longer duration of non-energy transfer stage.

Switching Frequency Estimation(Compared w\ Traditional Model)

Inductor Current Model

Generic Inductor Current Behavior

Traditional Model Estimation Experimental ResultsNew Model Estimation

Efficiency and Power Loss Estimation

Model Improvement:► Switching frequency estimation error improved from over 50%

to less than 10%.► Accurate power loss and efficiency estimation.

20

Adaptive Constant Power Control and Power Loss Analysis of a MHz GaN

based High Power Density AC/DC Converter for Low Power Applications

Motivation: at MHz fs, dc-link cap size -> bottleneck of further power density improvement

Achievements:► Power loss model of constant power operation with MHz switching frequency► Improved light load efficiency with adaptive constant power control

Contact: Dr. Jin Wang (wang.1248@osu.edu)Chengcheng Yao, Yue Zhang, Xuan Zhang, He Li and Huanyu Chen

-20

0

20

40

60

80

100

120

140

10 20 30 40 50 60 70

CO

NS

TP

A

NG

LE

(D

EG

)

OUTPUT POWER (W)

Adapti ve ConstP Control

Optimal ConstP

Without ConstP control: additional cap needed

kSS

D

S1

N1

NAUX

Cout

Vo

S Q

-QR

S1

+

-

S1 ON: -Vin/N

Vo

ZCD Signal Processing

Delay Td

Ramp

Feedback

Compensation

Constant Power

Control

Vshunt

OVP

OCPFiltering Disable S1

MCU: 28027

R1

R2

-

+

VZCD

VAUX

Comp.

Gate

drive

ePWM

DAC Vth_ZCD

C1

R3

S1 OFF: (Vout-Vin)/N

Higher Theta_P,

Smaller efficiency

Higher Eff but sill meets the

voltage ripple requirement

Digital control diagram A 70 W prototype Experimental waveform at 60 W

21

Touch Current Suppression for Semiconductor-Based Galvanic Isolation

Semiconductor-based Galvanic Isolation:► The switches delivers DM load power during the ON states.

► The switches sustain the CM isolation voltage and block the

CM leakage current during the OFF states.

CM Leakage Current (ICM) Analysis:► A pulse CM leakage current is generated at every turn-on event,

charging up the switch Coss, and it repeats at fsw .

► ICM ↓ needs Coss ↓ , and also fsw ↓?

CM leakage current

COSS COSSCOSS energy

gets dissipated

S1: OFF S3: ONVds_S3

CM Leakage Current (ICM) Reduction:

Enabling Technology – WBG Power Devices:► High isolation voltage rating High breakdown voltage.

► Low CM leakage current Low output capacitance Coss

► High efficiency Low on-resistance Rds_on

Xuan Zhang, Chengcheng Yao, Huanyu Chen and He Li Contact: Dr. Jin Wang (wang.1248@osu.edu)

An example of the ac switch

When the ac switch

is ON:

DM current

When the ac switch

is OFF:

CM leakage current

COSS

C2

S3

S2 S4

ZTC (body Impedance)

VCM

Vin

ICM (ITC)

DM current in the first half switching cycleDM current in the next half switching cycle

S1

C1

C3

RLoad

Line-frequency CM leakage current

t0

ITC

VCM

Vac

C3

ZTC (body Impedance)

Vin

S11

ITC

Rload

VCM

S12 S31 S32

S21 S22 S41 S42

C2

20 dB reduction of leakage current achieved

22

Electromagnetic Noise Mitigation for Ultra-fast On-die Temperature Sensing in High Power Modules

Achievement: With the proposed noise compensation methods, temperature sensing with a 0.8 us time constant is achieved.

On-die Temperature Sensing Diode► Strong noises coupled to the sensor during switching

► Temperature sensing time constant around several milliseconds

Noise Compensation and Sensing methods

Noise Coupling Mechanisms

Contact: Dr. Jin Wang (wang.1248@osu.edu)Chengcheng Yao, Pengzhi Yang and Mingzhi Leng

23

10 kW High Power Density GaN-based Three Phase Inverter

► To improve three phase inverter’ power density by utilizing high

voltage high current GaN HEMTs;

► To investigate existing issues of implementing GaN HEMTs into high

power application.

Enhanced System Reliability

Phase-leg Design

Motivations

He Li, Xiao Li, Zhengda Zhang Contact: Dr. Jin Wang (wang.1248@osu.edu)

E-mode GaNE-mode GaN

► Low stray inductance, low dc resistance and low thermal resistance

design insures the high efficiency operation of the inverter.

Single Phase-Leg Board Side View of the Phase-leg

Overcurrent Protection

SLRon

Roff Doff

Beadon

VDDPWM

OUT

IN

Falling edge

detection chip

SH

SCM

Active Miller Clamping Circuit

EMI Noise Control

Van: 250 V/div Ia: 25 A/div

Ib: 25 A/div Vbn: 250 V/div Time: 2 ms/div

Experiment Results

50 kHz, 10 kW Operation Efficiency Curve

Peak: 98.8%

4*6 cm2

24

SiC based Modular Multilevel Converter

► To improve medium voltage variable frequency motor drive system

power density and efficiency by utilizing high voltage high current

SiC power modules;

Motivations

Contact: Dr. Jin Wang (wang.1248@osu.edu)

Submodule Performance

System specifications:

1.7 kV/300 A SiC MOSFET

Power Modules Evaluation

Design of MMC Single Arm

MMC SMs Design

VDS: 1,160 V

VGS: 20 V

ID: 300 A

Turn-off Transient Turn-on Transient

(100 ns/div)

Input Voltage 7 kV Output Frequency 0-1 kHz

Input Power 1 MVA Number of Level 6

Output Voltage 4.16 kV Submodule Voltage 1.16 kV

Optical Fiber Communication

Based SM Gate Drive Board

He Li, Amol Deshpande, Gengyao Li, Yingzhuo Chen, Balaji Narayanasamy

25

1.7 kV SiC Power Module Gate Drive Design for MMC

Design Target and Challenges

Contact: Dr. Jin Wang (wang.1248@osu.edu)

Overcurrent Protection

Gate Drive Board Design

Driving capability

•Strong gate current

•+20/-5 V gate voltage

Reliability•Comprehensive protection functions

•Topology with excellent EMI immunity capability

Insulation

•3 kV working insulation within gate drive board

•10 kV gated drive board external insulation to house keeping power supply

Housekeeping

Power Supply

Isolated

DC/DC

Isolated

DC/DC

Gate Drive

IC

Optical

Fiber

6 W, 10 kV 3 W, 3 kV STGAP1S

DSP/

FPGA

Signal

Receiver

24 V 5 V

Gate Drive

IC

Optical

Fiber

STGAP1S

Signal

Receiver

24 V 5 V

Isolated

DC/DC

5 V

Isolated

DC/DC

6 W, 10 kV

Isolated

DC/DC

3 W, 3 kV

GND1 GND2

GND4

GND3

GND5

GND6

20, -5 V

20, -5 V

CM EMI ControlOptical Fiber Communication

Based SM Gate Drive Board

Size: 103 mm * 77 mm

Vgs: 20 V

Id: 600 A

Vds: 1,160 V

1,160V/600A Overcurrent protection in 1.5 µs

DSP

OF TransceiverOF Receiver

Vgs

Gate Drive System Delay

Driving system delay from DSP to MOSFET: 400-450 ns

He Li, Gengyao Li

26

Medium Voltage SiC Power Module Evaluation and

Gate Drive Design

Medium voltage double pulse test

platform for device dynamic

evaluation

Voltage rating Current rating

SiC Module1 15 kV 10 A (@ 25 ºC)

SiC Module2 4.5 kV 76 A (@ 25 ºC)

Device tested:

High voltage lab at The Ohio

State University

Research outcomes:

► Device static, dynamic, and package evaluation

► Gate driving circuit design

High insulation voltage

High common mode transient immunity (CMTI)

Comprehensive protection functions

Contact: Dr. Jin Wang (wang.1248@osu.edu)Boxue Hu, He Li, Chengcheng Yao, Xuan Zhang

Three 1.7 kV SiC schottky diode in series

4.5 kV United SiC power module

20 kV 5.2 nF Ceramic capacitor

Designed gate drive board

20 kV, 875 µH inductor

15 kV, 1 µF Capcitor

Grounding sheet

100 ns/div

(10 V/div) Vgs

(2 A/div) Id

(1 kV/div) Vds

(1 kV/div) Vds

(10 V/div) Vgs

100 ns/div

(2 A/div) Id

Double pulse test results for

15 kV SiC MOSFET

27

Comparison on GaN Device Based LLC, Phase-Shift Bridge and

Phase-shift QSC Circuits

Research Targets:

► Theoretically compare the efficiency, power density and cost of

three DC/DC circuits

► Compare circuits performance when currently available GaN

devices employed

► Evaluate circuits potential and predict the influence of future

generations of GaN devices on the circuit selection

Contact: Dr. Jin Wang (wang.1248@osu.edu)Boxue Hu and Xuan Zhang

S3

S4

S5

S6

Vin Cin Cout RL

Lr

Lm

S2 Cr

S1

LLC resonant circuit

S3

S4

S5

S6

Vin

C1

Cout RL

Lr

Lm

S2 Cr

S1

C2

Phase-shift bridge circuit

S1

S1

C1 C2

S2 S3

S4

S5

S6

Vin Cin Cout RL

Llk

Lm

Phase-shift QSC circuit

1 kW phase shift QSC prototype:

► GaN devices employed for all the

switches.

► Reduced voltage stress on primary side

components: 2/3 Vdc (switches) and

1/3 Vdc (transformer).

► Peak efficiency (preliminary): 94.4%.

► Zero voltage switching in a wide range.

500 ns/div

Vtrans_pri: 100 V/div

Vtrans_sec: 60 V/div

ILlk: 40 A/div

28

Power Module Packaging and High Power Density Three-

Phase Inverter DesignDouble-End Sourced Layout Design Improved Dynamic Performance Improved Thermal Performance

Three-Phase

Inverter Adopting

DES Layout

Miao Wang, Dr. Fang Luo, Dr. Longya Xu Contact: Dr. Longya Xu (longyaxu@gamil.com)

29

Comparison of A Novel 4-Level Hybrid Clamped Converter

and A 4-Level MMC for Motor Drive Application

Cost : 40% Reduction from MMC

Capacitor

Voltage (p.u)

Phase

Current (V)

Phase

Voltage (V)

4L- HCC @ 5 Hz 4L- MMC @ 5 Hz

HCC MMC HCC MMC

Vo (THD%) Io (THD%) Vcap IswitchVo_max fswitchVo (THD%) Io (THD%) Vcap Iswitch

fswitch

almost identical performance at 60Hz Improved performance at 5Hz : • 2 times larger available phase voltage

• 2 times smaller Vcap ripple and smaller THD % and losses

Performance comparison between HCC and MMC

InductorCapacitorSwitch

36

2418

6 30

MMC HCC

$ 26,000

$ 14,000

Topology of one phase hybrid

clamped converter (HCC)

System cost comparison

Jianyu Pan, Dr.risha Na, and Dr. Longya Xu

31.6% 32.1%

1.5%1.6%

8.0% 7.9%

1.9k 2.0k

232 A 238 A0.9

0.4

122%

160%

3.4%

0.8%

9.5 %

4.8 %

1.9 k2.6 k

278 A232 A

Contact: Dr. Longya Xu (longyaxu@gamil.com)

30

Feng Qi , Miao Wang and Dr. Longya Xu

Design of 30kVA Inverter Using SiC MOSFET for 180℃Ambient Temperature Operation

Motivation

Develop a 30kVA inverter for a wide temperature range from -10℃ to

180℃ Demonstrate the performance of a high temperature (HT) and low cost

gate driver circuit

Challenge: Optimize the system configuration and thermal

management

System Design

High tempearture gate driver and inverter

Experimental Result

Room temperature at 25℃ High temperature at 180℃

HT 30kVA inverter HT gate driver

3D model of HT inverter

Recorded Temperature profile of HT inverter

Contact: Dr. Longya Xu (longyaxu@gamil.com)

31

Chapter 3

High Voltage

32

Low Pressure Partial DischargeSummary

► In aircraft, PD occurs at a lower voltage level due to lower pressure at higher altitudes

► Existing standards do not adequately cover testing procedures suitable for low pressure conditions

► The goal of this project is to provide a testing procedure for future PD test standards

► This project includes 60 Hz AC testing and pulse voltage testing on various aircraft application components

► The pressure levels for this project range from 87 Torr (50,000 feet) to 760 Torr (sea level)

Zhuo Wei, Khalid Alkhalid, Faisal K. Alsaif, Jeff A. Hensal, and J. Martin Troth Contact: Dr. Jin Wang (wang.1248@osu.edu)

Twisted pair testing sample and the low

pressure chamber

Sample result illustrating PD pulses on current waveform

Blue: Voltage, Green: Current

200 V /div

400 uA /div

4 ms /div

33

Jianyu Pan, Feng Qi, Haiwei Cai, and Dr. Longya Xu

Jianyu Pan

Motivation

Isolated gate driver is required to operate high-voltage voltage source

controlled switches.

Isolation requirement can be as high as several kVs.

Develop a coreless power supply for gate driver with strong insolation,

high efficiency, and low parasitic capacitance

System Design

Radiated EMI Analysis

Transfer efficiency and power test

Efficiency and Electromagnetic Interference Analysis of Wireless

Power Transfer for High Voltage Gate Driver Application

Transmitter board

Gate Driver board

WPT model

• Maximum Efficiency: 90%

• Maximum Transfer power: 9W

• Parasitic capacitance: 1.7 pF

Contact: Dr. Longya Xu (longyaxu@gamil.com)

34

Chapter 4

Operation and Protection of Microgrids and Vehicle Power Systems

35

Study of DC Arc Fault in Power Distribution

System on Mild Hybrid Electric Vehicles

Research contents:

► Study possible DC arc failure modes and their impacts on the

power distribution system of mild HEVs

► Study the relationship of DC arc characteristics with parameters

e.g. voltage, current, gap length, temperature

► Develop a DC arc detection and protection system features in

fast, accurate detection/protection with cost effective MCUs.

Contact: Dr. Jin Wang (wang.1248@osu.edu)Boxue Hu, Yousef M. Abdullah, Zhuo Wei and Yafeng Wang

DC arc test setup

DC Power Supply

Load Bank

Arc Generator

Cooling Fan

Motor Control Unit

Measurement Scope

Measurement Probes

DC

DC

10000 uF

5 mohm

5 mohm

60 uH 5 mohm

48 V Battery

12 V Battery

2 uH 8 mohm

2 uH 8 mohm

2 uH

8 mohm

Fault 1

Fault 2

Fault 3

10000 uf

Co

nsta

nt

po

we

r lo

ad

2 uH 8 mohm

2 uH 8 mohm2 uH 8 mohm

2 uH 8 mohm2 uH2 uH 8 mohm

8 mohm

Simulation model for a power

distribution system

Iarc: 5 A/div

Varc: 10 V/div 400 ms/div

Before arc Gap opening Stable arc

Preliminary DC arc test

waveform

36

Intelligence Relay for Islanded Microgrid

Contact: Dr. Mahesh Illindala (Illindala.1@osu.edu)

Vabc

Iabc

ΔVa ΔVb ΔVc

Iabc

D

V0

I0

CWTV0

CWTI0

SNGU

SNGI

Central

controller

INFO

Relay INFO

ΔV and ΔI calculator

Directional

element

50/51 TD-R

TD-F

Reverse

Forward

Overcurrent protection element

Continuous

Wavelet

Transform

(CWT)

calculator

Sign

(SGN)

calculator

Sign

(SGN)

comparato

r

High impedance element Eop

EHIF

Trip

CB

trip

Tripping

element

Data

processing

CS1 CS2 Interface element

CS1 RS1

RS1 RS2

,RS1

RS

CS2 RS2

Trip

Transient

energy

calculato

r

ΔIa ΔIb ΔIc

S Sign

(SGN)

calculator

D

Sequence

calculator

Vabc

Iabc

Vabc(bus)

Vabc(DG)

25C

Phase

angle and

frequency

calculator

Δ|V|

Δf

Δθ

Synchronism check element

CB

close

1. Enable plug-and-play of DER

2. Detect high impedance

3. Avoid unnecessary loss of DERs

4. Economical, reliable and fast bus protection

Kexing Lai, Dr. Mahesh Illindala

37

Control Method to Prevent Microgrid Collapse

Contact: Dr. Mahesh Illindala (Illindala.1@osu.edu)Mariana Pulcherio, Ajit Renjit and Dr. Mahesh Illindala

38

Viterbi Algorithm Based Distribution System Restoration

Contact: Dr. Mahesh Illindala (Illindala.1@osu.edu)Chen Yuan, Dr. Mahesh Illindala

39

Smart Loads to Prevent Stalling of Microgrid

Contact: Dr. Mahesh Illindala (Illindala.1@osu.edu)Abrez Mondal, Dr. Mahesh Illindala

40

Chapter 5

Electric Machine Design and Analysis

41

PMSM with High Power Density and Efficiency

Predicted power and efficiency mapThermal and stress analysis

PMSM Designed and Analyzed:

FEM Analysis of EM Design

Research outcomes:

► High power density: 13-14kw/kg at

350kw

► High efficiency: 97.2-99.3% over a wide

operating range

► Thermal analysis verifies the package

► Structure analysis verifies speed

~21,000rpm

► Potential application for next-generation

of electrified airplane

Contact: L. Xu, email at xu.12@osu.edu)Pina Ortega L. Xu, and H. Wang

Parameter Value Unit

Stator OD 230 mm

Stator ID 211 mm

Stack Length 93 mm

Br (NdFeB 38EH) 1.23T @ (20-

200)C

Lamination Material VAC48, M19

Lamination Thickness 0.3 mmAir Gap Thermal Conductivity 5 x 0.026 W/m/K

with forced Liquid cooling jacket

Sleeve Thickness = 1mm, deeformation = 80 microns with stress

~ 30MPa at 21,000 rpm

42

Copper cage induction machine for EV tractionDesign Targets:► Compact size: 5-6kw/kg► Efficiency: >95%► Wide speed range: 0-15,000rpm

Solutions: Copper rotor IM for small slip

losses and high torque production:

High torque for EV application:Taking 2017 Toyota Camry hybrid for example:

With an optimized two-stage gearbox, 0-60

mph of 4.9 s (faster than any conventional

production car other than a Tesla), a top speed

of 98 mph, and otherwise excellent

performance. If a three-speed gearbox is used,

the top speed becomes 176 mph.

The performance of the designed IM :

200 kw at the speed of 10,000 rpm

with the total losses =5.4kw for

Efficiency=97.3%

300 kw at the speed of 15,240 rpm

with the total losses =6kw and

Efficiency=98%

Contact: L. Xu, email at xu.12@osu.edu)L. Xu and H. Wang

43

CHPPE Sponsors

Existing Members at Different Levels

44

Please Contact CHPPE Faculties

for Further Information.

Thank you!