CURRICULUM VITAE

Career Goal:

To work with an organization that provides good opportunity to explore my knowledge in the

domain of VLSI (Physical) design. “To experience the challenges of a working engineer in Lower

Node and a healthy but competitive environment of industry, enabling to extract the best out of

me which is conducive to learn and grow as professional, thereby directing my future endeavors

as an asset to the organization"

Master of Engineering 2015-2017 2015-2017

VLSI Systems Design SPI:- 8.00/10

Marwadi Education Foundations Group of Institutions, Rajkot

Bachelor Of Engineering 2009-2013

Electronics and Communication CGPA:-6.90/10

Shantilal Shah Engineering college,

Bhavnagar

GATE Exam University Valid Year Marks GATE Score

IIT Kharagpur 2014-2016 24.33 329

10th and 12th Year Percentage Board

H.S.C 2009 51.40% GSHEB

S.S.C 2007 66.77% GSHEB

Experience (6 Month Training + 1 year Projects)

Company name Year Post City

2016-Running

Project Trainee

(Physical design) Ahmedabad

Graduation

Post-Graduation

Name: Chirag Dave

Email: chiragvlsi92@gmail.com

Contact No. : 9624896709

DOB: 18/08/1992

PROJECTS

Working on System IP Tooling (ARM) for SoC.

Working on 28nm JDS Networking Block Netlist to GDS-II on Synopsys Tools Netlist to GDSII for networking blocks closure with Optimization of Timing (M.E.- Final year

Project-90nm)-Synopsys Tool ASIC flow for 16-bit ALU up to GDS-II.

Design 32bit counter simulate and synthesis and place & route & Optimize Power, delay.

GSM based wireless electricity billing system with data recovery.

Skills

VLSI Backend Design Tools

IC Compiler(P & R), Prime time(STA),

ARM Socrates (for IP),

VLSI Frontend Design Tools

Design Compiler, Xilinx 14.1, HDL Designer

(Mentor Graphics),Questa sim, Pyxis, H

Spice, LT Spice, Leonardo spectrum

HDL/Programming Languages C,C++,VB, VHDL, Verilog,

Tools MATLAB, LabVIEW, Multi-Sim,

Tanner(p-spice)

Computer Skills OS-Windows(XP/7/8) and Linux

Scripting Language Perl , TCL , Ruby

Kits knowledge Spartan III,&VI, Altera (FPGA kits),

Co-Curricular Activities

PG associative in MEFGI.

Writing Book on Physical Design “All in One for P.D.”

Write Two Review Paper on Timing Optimization Techniques.

Online courses logic to layout course, EDA design, 1rs@semiconductor(digital), advanced

logic synthesis, Perl scripting, tools operating courses.(running)

Training program on “TESTING AND VERIFICATION OF VLSI DESIGN”.

Workshop on “CONSTRAINT OPTIMIZED MICRO ARCHITECTURE DESIGN AND

IMPLEMENTATION ON FPGA” association with IEEE Gujarat Section.

AREA OF INTEREST

Physical design (VLSI back-end design)

(Dave Chirag)