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TRANSCRIPT
SmartPM Workshop, Ireland, 18/3/2010
Dion Manessis, Lars Boettcher, Andreas Ostmann, Stefan Karaszkiewicz
Fraunhofer Institute for Reliability and Microintegration (IZM)
Gustav-Meyer-Allee 25, Berlin 13355, Germany
Phone: +49 (30) 46403-788
E-mail: [email protected]
Chip embedding technologies for power
components
SmartPM Workshop, Ireland, 18/3/2010
Outline
Introduction to Chip in Polymer - Embedding Technology
Technology
Process overview
Package development
Embedded Power Packages
Reliability
Conclusions
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SmartPM Workshop, Ireland, 18/3/2010
Interconnect Evolution
chip & wire flip chip chip embedding
established since
40 yearssmallest in 2D smallest in 3D
First level chip interconnection technologies inside a package:
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SmartPM Workshop, Ireland, 18/3/2010
Where to Use Embedding?
Complex Systems Packages / System in Packages / Modules
many different components
high risk in yield
one / few components
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SmartPM Workshop, Ireland, 18/3/2010
Packages with Embedded Components
Chip embedding technology enables the manufacturing of
thin planar packages and stacked SiPs
chip + passive
flat single chip package
package on package
package stack
SiP with sequential
build-up layersstack of tested
packages / Sipsflat packages / SiPs
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SmartPM Workshop, Ireland, 18/3/2010
heavy ribbon bonding on IGBT and DCB
Al wire bond on PCB
Power Electronic Packaging - Wire & Ribbon Bonds
• Al ultrasonic heavy wire bonds
• 100 – 500 µm wire thickness
• Al heavy ribbon bonding
heavy wire bonding on IGBT and DCB
SmartPM Workshop, Ireland, 18/3/2010
Concept of prototype module
cooling liquid
AlN - DCB
rubber seal
distance sheet cooling liquid
Cross section of module
Power Electronic Packaging - Soldered Module
Prototype module
power module with double sided water cooling
IGBTs and diodes soldered to DCB substrate
reduction of thermal resistance by 40 %
increased lifetime of module
high reliability
SmartPM Workshop, Ireland, 18/3/2010
Chip Embedding Technology
via to substrate via to chip
chip RCC
core substrate adhesive
Advantages
• reduced package thickness
• 3D stacking capability
• improved electrical performance
• good thermal performance
• EMI shielding capability
Features
• chip embedded in planar substrate
• direct Cu contact to chip
• no wires, no solder bumps
• very thin package
• power and logic integration possible
SmartPM Workshop, Ireland, 18/3/2010
Process Flow Chip Embedding Technologies
face down
better fine pitch capability
chip attach
embedding by
lamination
via drilling
Cu plating and
structuring
face up
electrical and thermal backside contact
SmartPM Workshop, Ireland, 18/3/2010
Upgrade of equipment for 18”x24” panel embedding
Lauffer lamination press, 4 stages, oil heated
Schmoll 2-spindle drilling machine
Siemens Microbeam laser drilling machine
Orbotech Paragon 9000 Laser Direct Imaging
Schmid Develop, Etch & Strip horizontal line
Ramgraber automatic via filling and plating tool
Lemmen manual bench for surface finish
Siplace CA3 high-speed SMD and bare die placer
Mahr high accuracy optical inspection
Flying probe in-circuit tester
SmartPM Workshop, Ireland, 18/3/2010
Chip Embedding – Process
Die Bonding – Methods Die Bond Materials
Non conductive:
Dicing die attach film (DDAF) on
wafer backside
Printing of B-stage adhesive paste
Conductive
screen printing of Ag-filled paste
stencil printed solder and reflow
Requirements
handling of very thin chips (50 µm)
thin and uniform bond line (10-20
µm)
very high placement accuracy
Die bonded chips on copper substrate
SmartPM Workshop, Ireland, 18/3/2010
Lamination
embedding of chips by vacuum
lamination of RCC
use of epoxy-based RCC
optimized lamination profile to ensure
void and damage free embedding of Si
chips
no chip movement during lamination
process
combination prepreg and RCC or Cu foil
for thicker Si chips
Chip
AdhesiveSubstrate
Epoxy
Dielectric lamination
x-section embedded Si chip
Chip Embedding – Process
SmartPM Workshop, Ireland, 18/3/2010
Micro via formation
Laser drilling
R&D environment:
• pulsed UV laser, enabling ablation of
metal and epoxy layers
• high flexibility
Production environment:
• dual beam UV / CO2 laser
• LDI Cu structuring and CO2 laser
accurate micro via alignment
Laser drilled micro via
Chip Embedding – Process
SmartPM Workshop, Ireland, 18/3/2010
Via metallizationCopper plating
cleaning of drilled micro via, desmear
activation of dielectric surface:
• non conductive Pd activation and
eless copper
• conductive Pd activation and direct
electro plating of Cu
filling of blind via
• highly reliable micro via
• best possible leveling of surface for
following process
Cu filled micro / 120µm pad pitch
Chip Embedding – Process
SmartPM Workshop, Ireland, 18/3/2010
Conductor line formationCopper structuring
Subtractive:
Laser direct structuring
Laser structured etch mask
Laser direct imaging LDI
Photosensitive dry film etch mask
Additive:
Laser direct imaging LDI
Photosensitive dry film plating
mask
Res
ist
laye
r
Copper etched
Stru
ctu
red
tin
laye
rChip Embedding – Process
SmartPM Workshop, Ireland, 18/3/2010
Concepts for Power Packages and Modules
MOSFET MOSFET
single chip packages for MOSFETs and IGBTs
module with power and logic
IGBT IGBT
logic ICR C
IGBT logic IC
SmartPM Workshop, Ireland, 18/3/2010
Embedded Power MOS Package
Package
150 µm thick power MOS transistor
chips die bonded with solder on 36 µm
copper foil
200 µm thick package
package outline 3.2 x 3.2 mm²
assembly like standard SMD
RDSon measured with 7 – 8 mOhm
SmartPM Workshop, Ireland, 18/3/2010
HERMESHigh Density Integration by Embedding Chips for Reduced Size Modules and Electronic Systems
Project
EU funded project, FP 7 program, duration 05/2008 - 04/2011
Total budget ca.15 M€
Project Goal
Industrialisation of the HIDING DIES chip embedding technology
Improvement of technology towards finer pitch, use of new material
developments, process innovation and equipment improvements
Strong focus on future implementing of the technology in a
manufacturing environment / value chain
Consortium
11 partners; technology provider, end-user, testing, research institutes
Early Adopters Group with potential end-users
SmartPM Workshop, Ireland, 18/3/2010
Embedded Power Packages
Challenges
Various chip thickness of vertical power
IC and back side metallization
further wafer thinning not possible
Embedding option
Use of RCC layer for embedding
Use of “dual layer” RCC material
• Glass reinforced 1st layer
• Thicker 2nd resin layer without
reinforcement for embedding of chip
Use of combination of prepreg and RCC
foil
SmartPM Workshop, Ireland, 18/3/2010
Face up Demonstrator Stack up
Power-RTV
220µm Si Chip
Micro via to Chip padThrough via
Thermal laminateAdhesive
•CoolMOS Chip: 3,5x 4,9 mm² / Thickness: 220µm
•Ag glue die attach
•Via to chip: 50µm, via to substrate: 250µm
•Three copper layer
•Cu Line width: 1.3mm
•Cu thickness: 70µm /all three layers
•Dielectric Thickness: 280µm (4x1080 + 1x1037 PP)
SmartPM Workshop, Ireland, 18/3/2010
Recent ProjectsPCB manufacturers exploring embedding technologies
EU project HERMES
industrialization of embedding technology
German project VISA
development of fully integrated power switches
EU project TIPS
development of ultra-thin package stacks
SmartPM Workshop, Ireland, 18/3/2010
Emb
edd
ing
Pro
cess
MOSFET Packages
top and bottom contact thick chip embedding ultra low cost
System in Package
multiple layers passive components MEMS embedding
High Frequencies low loss materials tight impedance control 77 GHz automotive radar
Chip Embedding– Process
SmartPM Workshop, Ireland, 18/3/2010
• 2.5x2.5 mm² chips, 50 µm thickness
• chips bonded on 650 µm FR4 core substrate
• chip embedding into 80 µm RCC
Reliability of Packages / Modules with Embedded Chips
Temperature storage
condition 150 °C
1000 hours passed
Humidity storage
condition 85 °C / 85 % rh
2000 hours passed
Thermal shock
air-to-air shock -55 / +125 °C
18000 cycles passed
EU project Hiding Dies
Industry project Dual Chip SiP • realization of 800 SiPs
• 2 embedded chips
• 16x16 mm² size
Industry project Planar Power Module• realisation of > 3000 packages
• embedded power MOSFET
• 2.4 mm package sizeall tests passed for industrial package qualification
moisture sensitivity
JEDEC test
level 2A passed
Humidity storage
condition 85 °C / 85 % rh
1000 hours passed
Thermal shock
air-to-air shock -55 / +125 °C
1000 cycles passed
SmartPM Workshop, Ireland, 18/3/2010
Conclusion
Chip Embedding Technology – Chip in Polymer
Reliable and cost-effective embedding technology for the
realization of modules and System-in-Packages
Development in several projects with industry and R&D centers
Industrialization of the technology within the “HERMES” project
Package realization:
• Single and multi die packages
• reliability comparison to conventional packages
Applications
• multiple levels of embedded chips, multiple lamination cycles
• embedding of ultra-thin chips in flex
• power modules
• radar application of 77 GHz
SmartPM Workshop, Ireland, 18/3/2010
Thank you very much for your attention!
Contact: Dion Manessis