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1518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 9, SEPTEMBER 2003

40-GHz Transimpedance Amplifier With DifferentialOutputs Using InPInGaAs Heterojunction

Bipolar TransistorsCharles Q. Wu, Emilio A. Sovero, Member, IEEE, and Bruce Massey, Member, IEEE

AbstractHigh-gain and high-bandwidth transimpedance am-plifiers (TIAs) are required for fiber-optic receiver modules. Thispaper reports on the design, fabrication, and characterization ofa 40-Gb/s TIA for SONET/SDH STS-768/STM-256 applicationsbased on an InPInGaAs single heterojunction bipolar transistor(SHBT) process developed at Vitesse Semiconductor Corporation(VitesseIndium PhosphideRelease1 or VIP-1). This amplifiercon-sists of a single-ended input transimpedance pre-amplifier and adifferential output post-amplifier. The measured differential tran-simpedance is 1800

with 3-dB bandwidthgreaterthan 40 GHz.The high gain of this circuit eliminates the need for a standalonelimiting amplifier between the conventional transimpedance pre-amplifier and the demultiplexer in short-reach applications.

Index Terms40 Gb/s, post-amplifier, single heterojunctionbipolar transistor (SHBT), transimpedance amplifier (TIA).

I. INTRODUCTION

OPTICAL fiber transmit systems with a data rate of40 Gb/s (STS-768) are currently under development. Atypical fiber-optic communication receiver system is illustrated

in Fig. 1. The optical signal is first detected and converted

to electronic current by a photodetector. A transimpedance

amplifier (TIA) is used to convert the current swing to a voltage

swing at its output. A post-amplifier is typically utilized to

amplify the signal into a clock and data recovery unit (CDR),

and then into a demultiplexer (DEMUX) which deserializes the

high-speed data into a parallel data stream [1].

InPInGaAs-based heterojunction bipolar transistor (HBT)

TIAs have been reported in recent years [2][5]. Previously re-

ported designs [2], [3] used an emitter follower as the output

buffer. This resulted in high bandwidth performance but suf-

fered high return loss ( ) that causes time-domain jitter. To

improve the return loss and increase the transimpedance gain,

an integrated version of the transimpedance pre-amplifier and

post-amplifying stages with differential outputs was designed.

In contrast to most distributed amplifier designs with ac-coupledoutputs, this lumped-design has dc-coupled outputs. This elim-

inates the requirement for a dc block (capacitor or bias-T) be-

tween the TIA and CDR/DEMUX. In addition, the InPInGaAs

material system allows monolithic integration of the TIA with a

p-i-n photodetector.

Manuscript received January 15, 2003; revised April 30, 2003.The authors are with Vitesse Semiconductor Corporation, Camarillo, CA

93021 USA (e-mail: [email protected]).Digital Object Identifier 10.1109/JSSC.2003.815927

Fig. 1. Block diagram of a typical 40 Gb/s optical receiver module. PA:post-amplifier.

Fig. 2. Measured f and f performance with various collector current Iof a transistor with effective emitter area of 1.2 m 2 4.3 m.

II. DEVICE PERFORMANCE AND PROCESSING

InPInGaAs single heterojunction bipolar transistor (SHBT)

devices based on the Vitesse Indium Phosphide Release 1

(VIP-1) process have a dc current gain of 30, of

150 GHz, and of 150 GHz, as shown in Fig. 2. High

and are achieved at much lower current density

( 1 mA/ m ) compared with the state-of-the-art SiGe HBT

devices. This advantage enables designs of low power con-sumption.

The VIP-1 process has vertical mesa isolated n-p-n bipolar

transistors with self-aligned base. Both transistors and diodesare scalable. The minimum effective emitter width is 0.8 m.

Further lithographic improvement can easily increase the and

for future applications. Proprietary contacts with low resis-

tance and high thermal stability over 400 C enable high wafer

yield and good reliability. The VIP-1 process also features three

layers of aluminum interconnect metal, precision resistors, and

MIM capacitors on 4-in InP wafers.

0018-9200/03$17.00 2003 IEEE
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WU et al.: TIA WITH DIFFERENTIAL OUTPUTS USING InPInGaAs HBTs 1519

Fig. 3. TIA block diagram.

Compared with other technologies, insulating InP substrate

allows higher bandwidth interconnects (limiting aspect of

40-Gb/s receiver design). It has very low noise. The

high breakdown voltage ( 4 V) of InP transistors is

also suitable for output driving stages. Comparing to SiGeprocess, lower of InP HBTs gives more headroom for the

same power-supply designs. In addition, both and

can be tailored with appropriate epi design. With the help of

these process advantages, a 40-Gb/s 16 : 1 multiplexer (MUX)

with integrated pseudorandom bit sequence (PRBS) 2 1

generator (close to 5000 HBTs) has been demonstrated [10].

The 40-Gb/s TIA circuits have been fabricated based on the

same process. The results are reported in the following.

III. CIRCUIT DESIGN

The functional block diagram of the TIA is depicted in Fig. 3.

The pre-amplifier is designed to have a transimpedance gainof 250 with the input port optimized for packaging with a

50-GHz bandwidth p-i-n photodetector. The post-amplifier con-

sists of a gain stage and an output buffer. It has a single-ended

voltage gain of 12 dB and the simulated output return loss ( )

is lower than 10 dB up to 60 GHz. This integration is targeted

to achieve the differential gain of 2 k and the bandwidth of 40

GHz needed for OC-768 photoreceiver modules.

The transimpedance pre-amplifier uses a conventional

common-emitter feedback architecture (Fig. 4) with a single

power supply. This architecture has better noise performance

compared with the common-base approach [9]. A peaking

capacitor is used to increase the overall bandwidth in

contrast of inductor peaking [4]. Two diodes and resistorprovide the dc offset regulation to increase the dynamic range

(maximum input current) of the pre-amplifier up to 5 mA

(peak-to-peak). To optimize the tradeoff between bandwidth,

noise, and dynamic range, extensive simulations have been run

to select the most appropriate values of and

transistor sizes. The design was simulated with the 50-GHz

photodetector model and a 120-pH bond-wire inductance

between the photodetector and the TIA. The pre-amplifier

without the bond wire has also been characterized and is

reported in this paper.

The post-amplifier has two stages: the gain stage and the

output buffer. Fig. 5 illustrates the schematic of the first stage

Fig. 4. Schematic of transimpedance pre-amplifier.

Fig. 5. Schematic of one stage of the post-amplifier.

of the post-amplifier. It is a modified Cherry Hopper design [5],

[6]. The gain is controlled by current source , andprovide feedback from the output to the collector of . This

parallel-feedback design has wider bandwidth than the conven-

tional Cherry Hopper circuit [6]. This stage also provides a con-

version of the single-ended input signal to differential output.

The output buffer is an additional gain stage and uses the

same architecture. A traditional Cherry Hopper circuit is not de-

sirable for dc-coupled current mode logic (CML)-type output

buffers due to the nonzero voltage offset. In this modified archi-

tecture, the feedback transistor bypasses the current from

, bringing the high level close to 0 V. and also im-

prove the return loss ( ). In contrast to standard CML, this

output buffer produces a higher gain bandwidth product.
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Fig. 6. Schematic of emitter followers.

Fig. 7. Chip photograph of the TIA circuit.

Two emitter followers were added between gain stages to pro-

vide dc left shifting. With proper design, the output impedance

is adjusted to be more inductive, resulting in a peaking of the

gain response and an improved bandwidth [9]. and are

used to damp possible local resonances (Fig. 6).

For a 40-GHz or higher speed design, the distributed effectsof the RF and ground interconnects have to be taken into ac-

count [5], [8]. In general, the length of high-speed signal and

ground paths should be reduced to a minimum. A photograph of

the IC is shown in Fig. 7. The overall chip size is approximately

1 mm 1 mm. In addition, the power supply is decoupled with

on-chip bypass capacitors of 60 pF. Serial damping resistors

(36 ) are also used in conjunction with the bypass capacitors

to dampen any potential resonances [7]. To minimize undesired

feedback and possible oscillation, the power-supply lines be-

tween pre-amplifier and post-amplifier are separated on chip.

Future versions will reduce the length of output 50- transmis-

sion lines to a minimum.

Fig. 8. Transimpedance gain of the pre-amplifier over the frequency.

Fig. 9. Transimpedance test methodology comparison.

IV. CHARACTERIZATION OF PRE-AMPLIFIER ANDPOST-AMPLIFIER STAGES

The effective transimpedance gain without photodetector

was testedon wafer with coplanar probes. It wascalculated from

measured S-parameters based on the equation

with equal to 50 [4]. The probes have been calibrated to

assure the accuracy of all S-parameters.

The of the pre-amplifiers (50- load) with different feed-

back resistors of 270350 has been characterized (Fig. 8). A

3-dB bandwidth of more than 40 GHz and gain of 4547 dB

(180230 ) have been achieved.A test chip has been designed to verify the transimpedance

over frequency. It uses a 1-k resistor to convert the input

voltage swing to the current swing into the TIA [3]. Measured

bandwidth closely matches the value calculated from the

measured S-parameters, as shown in Fig. 9.

Instead of 50 , lower input impedance of the TIA can in-

crease the RC-limited bandwidth of the detector [5]. Measured

input impedance of the reported design is 35 .

To demonstrate the TIA output capability, a 40-Gb/s eye di-

agram measurement (2 1 PRBS) of the post-amplifier stage

only on a different test chip is presented in Fig. 10. The input

signal is 100 mV . Therefore, the post-amplifier (12-dB gain)
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Fig. 10. The 40-Gb/s eye diagram of the post-amplifier.

Fig. 11. Measured S-parameters (single-ended) of the TIA.

Fig. 12. Transimpedance gain of the TIA over the frequency.

demonstrates output amplitude of 400 mV (800-mV differen-

tial).

V. EXPERIMENTAL RESULTS OF THE COMBINED CIRCUIT

The whole TIA IC dissipates 600 mW at a power supply of

5.2 V and an ambient temperature of 27 C. The circuit also

operates at 85 C with no performance degradation.

Fig. 11 shows the measured S-parameters. is lower than

8 dB up to 60 GHz. Local variation of is less than 0.5 dB.

As shown in Fig. 12, the whole circuit exhibits a single-ended

transimpedance gain of 59 dB (1800- differential) and

3-dB bandwidth of 42 GHz. Measured gain is 1 dB less than

the simulated result. The difference was mainly caused by

slightly lower sheet resistance of the resistors versus simulation.

Fig. 13. Phase and group delay variation of the transimpedance over thefrequency.

Fig. 14. Large-signal measurement of the TIA.

The phase of varies linearly with frequency, indicating a

small group delay ( 10 ps), as shown in Fig. 13. This result

also verified the accuracy of the test setup calibration.

Simulated rms input-referred noise current is 4.5 A

(060 GHz). This value translates into an input sensitivity

of 63 A at a bit-error rate (BER) of 10 . However, the

measured input referred noise is 7 A. The difference is

mainly due to the undesired transimpedance peaking as shown

in Fig. 13.

An input current of 100 A to 5 mA has been applied tothe circuit. The measured output swing amplitude is illustrated

in Fig. 14. The output starts to limit at 400800 A. Before the

limiting point, the slope in the figure shows a single-ended tran-

simpedance of 900 , or a differential value of 1800 . Beyond

800 A, the output swing is limited to 480 mV.

Fig. 15 shows 10-Gb/s data eyes of the TIA output with

2 1 PRBS input. The measured dynamic range of the TIA

is 45 mA. The output rise/fall time was mainly limited by the

edge rate of the input signal rather than the TIA. Plans are to

integrate a 4050-GHz photodetector or an equivalent LRCtest

module [3] and a 40-Gb/s signal source to the TIA for final

40-Gb/s BER test.
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Fig. 15. The 10-Gb/s output eye diagram of the TIA.

TABLE ISUMMARY OF MEASUREMENT RESULTS

VI. SUMMARY AND CONCLUSION

These measured results demonstrate that InPInGaAs tech-

nology is preferred for design and fabrication of 40-Gb/s TIA.

Integration of the transimpedance pre-amplifier and differential

post-amplifier on the same IC has been discussed. The perfor-

mance of the TIA is summarized in Table I. The 42-GHz band-

width and 1800- differential gain have been measured. Thetransimpedance bandwidth product of 76 THz is one of the

highest values reported to date. High dynamic range of up to

45 mA and good of less than 8 dB from 0 to 60 GHz

are also shown in Table I.

ACKNOWLEDGMENT

The authors wish to thank M. Van Dyke and L. Bunz for test

and characterization support, B. Li and P. Partyka for transistor

modeling, and B. Mayampurath, M. Dru, L. Wiederspahn, and

A. Huelsman for valuable suggestions.

REFERENCES

[1] E. A. Sovero, A. Hendarman, B. Massey, C. Q. Wu, B. McDonough Sr.,N. Hendrickson, A. Huelsman, and I. Deyhimy, Recent progress in 40Gb/s IC/OEIC design and manufacturing, in Proc. Laser and Electro-Optic Society (LEOS) Meeting, Nov. 2001, pp. 501502.

[2] A. Huber, D. Huber, T. Morf, H. Jackel, C. Bergamaschi, V. Hurm, M.Ludwig, and M. Schlechtweg, Monolithic, high transimpedance gain(3.3 k ), 40 Gb/s InP-HBT photoreceiver with differential outputs,

Electron. Lett., vol. 35, no. 11, pp. 897898, May 27, 1999.

[3] J. Mullrich, H. Thurner, E. Mullner, J. F. Jensen, W. E. Stanchina, M.Kardos, and H.-M. Rein, High-gain transimpedance amplifier in InP-based HBT technology for the receiver in 40-Gb/s optical-fiber TDMlinks, IEEE J. Solid-State Circuits, vol. 35, pp. 12601265, Sept. 2000.

[4] R. K. Montgomery, A. Feygenson, P. R. Smith, R. D. Yadvish, R. A.Hamm, and H. Temkin, A 28-GHz transimpedance pre-amplifier withinductive bandwidth enhancement, in IEEE Int. Electron Devices

Meeting Tech. Dig., San Francisco, CA, Dec. 1992, pp. 423426.[5] H. D. Huber, R. Bauknecht, C. Bergamaschi, M. Bitter, A. Huber, T.

Morf, A. Neiger, M. Rohner, I. Schnyder, V. Schwarz, and A. Jackel,InPInGaAs single HBT technology for photoreceiver OEICs at 40Gb/s and beyond, J. Lightwave Technol., vol. 18, pp. 9921000, July2000.

[6] N. Ishihara, O. Nakajima, H. Ichino, and Y. Yamauchi, 9 GHzbandwidth, 820 dB controllable-gain monolithic amplifier usingAlGaAsGaAs HBT technology, Electron. Lett., vol. 25, no. 19, pp.13171318, Sept. 14, 1989.

[7] W. Pohlmann,A silicon-bipolar amplifierfor 10 Gb/swith 45-dB gain,IEEE J. Solid-State Circuits, vol. 29, pp. 551556, May 1994.

[8] H.-M. Rein and M. Moller, Design considerations for very-high-speedSi-bipolar ICs operating up to 50 Gb/s, IEEE J. Solid-State Circuits,vol. 31, pp. 10761090, Aug. 1996.

[9] H. H. Kim, C. A. Burrus, and J. Bauman, A Si BiCMOS trans-impedance amplifier for 10-Gb/s SONET receiver, IEEE J. Solid-StateCircuits, vol. 36, pp. 769776, May 2001.

[10] A. Hendarman, E. A. Sovero, X. Xu, and K. Witt, STS-768 multiplexerwith full rate output data retimer in InP HBT, in IEEE GaAs IC Symp.Tech. Dig., Oct. 2002, pp. 211214.

[11] C. Q. Wu, E. A. Sovero, and B. Massey, 40 GHz transimpedance am-plifier with differential outputs usingInP/InGaAs heterojunction bipolartransistors, in IEEE GaAs IC Symp. Tech. Dig., Oct. 2002, pp. 6368.

Charles Q. Wu received the B.S. degree in materialsscience and engineering from the University ofScience and Technology of China, Hefei, China, theM.S. degree in materials science and engineeringfrom the University of California at Los Angeles,and the second M.S. degree in electrical engineeringfrom the University of Southern California, LosAngeles, in 1990, 1993, and 2000, respectively.

Since 1996, he has been a Member of TechnicalStaff with Vitesse Semiconductor Corporation,Camarillo, CA, where he is currently a Senior

Member of the Physical Media Devices group working on analog circuit designfor 10/40-Gb/s optical communication systems.

Emilio A. Sovero (M85) received the B.S. degree

in engineering, the M.S. degree in mechanical en-gineering, and the Ph.D. degree in applied physicsand information science from the California Instituteof Technology, Pasadena, in 1970, 1971, and 1977,respectively.

He was a Senior Scientist with Rockwell Inter-national Science Center, Thousand Oaks, CA, until2000. He worked in III-V semiconductor (GaAsand InP) circuit development for microwave andmillimeter-wave integrated circuits, for high power

and low noise. He holds six U.S. patents for his work in this area. Since 2000,he has been with Vitesse Semiconductor Corporation, Camarillo, CA, wherehe is currently a Principal Engineer involved in various aspects of circuitdevelopment and design using Vitesse internal InP foundry. The applicationsinclude 40- and 10-GB/s circuit for telecommunications applications. Hiscurrent areas of interest are broad-band analog amplifiers and millimeter-waveamplifiers using InP bipolar circuits.


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Bruce Massey (M87) received the B.S. degree inengineering physics from the University of Maine atOrono in 1985, and attended advanced courses at theUniversityof Southern California,Los Angeles, from1988 to 1990.

He worked on CMOS mixed-signal design and onthe GaAs Pilot Line at TRW and infrared circuit andsystems design at the Hughes SantaBarbara ResearchCenterprior to joining Vitesse Semiconductor Corpo-

ration, Camarillo, CA, in 1995. He is currently a Se-nior Memberof Technical Staffin thePhysical MediaDevices group. His research interests include high data-rate analog circuit de-sign and development.

Mr. Massey is a member of the IEEE Solid-State Circuits Society, the IEEEMicrowave Theory and Techniques Society, and the IEEE Components, Pack-aging, and Manufacturing Technology Society.

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