CHDStdand

Related StandardsEfforts

CHDStdand

Related StandardsEfforts

b

Technology Trend The Physics

Decreasing Gate Length 50 m transistors by 2000

Increased file & file sizes Increased Power

Decreasing Metal Pitch

GHz range in by 1999

Coupled effectsReliability issues

Decreasing Clock Cycle

GHz range by 1999

Inductive effectsReflections

The Physics of SmallThe Physics of Small

Den

sity

Frequency

• Analysis Time to Design Change (design cycle time)• Minimize Data Redundancy (data management)• Maximize Design Reuse (productivity)• Minimize File Translation (cycle time)

• Full Scope Model (complex analysis)• Common Analysis Engine (convergence)

• Concurrent Design and Analysis (cycle time)

• Supplier Technology Characterizations (accuracy)

Harness the Physics of SmallHarness the Physics of Small

Ability to

integrate tools of choice

GoalsGoals

Develop an open industry wide model for chip design and analysis data (CHDStd) - comprehensive data scope and unambiguous API access

Demonstrate value proposition with SEMATECH companies

Achieve commercial adoption of database servers and EDA applications using the specification

Gain formal standards accreditation

Develop an open industry wide model for chip design and analysis data (CHDStd) - comprehensive data scope and unambiguous API access

Demonstrate value proposition with SEMATECH companies

Achieve commercial adoption of database servers and EDA applications using the specification

Gain formal standards accreditation

CHDStd ElementsCHDStd Elements

IDM

AP

I

Layout

Electrical

Physical

Netlist

Design LibraryDesign Library

ElectricalSpecs.

Constraints

Layer Rules

Wire/Via/PadModels P

DL

AP

I

Process LibraryProcess Library

Physical

Properties

Function

Power

Delay

OL

A A

PI

Cell Library Cell Library

Hw/SwLogicCircuitPlaceWireother

PerfTimingPowerNoiseTestother

CommonDatamodel

ConcurrentComm.

DesignDesign AnalyzeAnalyze

Methodology

EDA Applications

Common Data AccessCommon Data Access

Data Repository

Flow & Data Management

CHDStdCHDStd

Effective Integration of AllEffective Integration of All

CHDStdCHDStd

Comprehensive Data Scope – Design Library (IDM)

• hierarchical connectivity network for the design• physical characteristics (wires, shapes, area, placement, constraints, etc.)• electrical characteristics (parasitics, delays, constraints, etc.)

– Technology Library (OLA)• delay and power calculation, logic function, block attributes• cell physical properties (OLA-P)

– Process Definition Library (PDL) • physical and electrical models, design rules, constraints• process characterization (SIPPs)

– Engineering Change Order (ECO) language

Full Application Program Interface (API)

Comprehensive Data Scope – Design Library (IDM)

• hierarchical connectivity network for the design• physical characteristics (wires, shapes, area, placement, constraints, etc.)• electrical characteristics (parasitics, delays, constraints, etc.)

– Technology Library (OLA)• delay and power calculation, logic function, block attributes• cell physical properties (OLA-P)

– Process Definition Library (PDL) • physical and electrical models, design rules, constraints• process characterization (SIPPs)

– Engineering Change Order (ECO) language

Full Application Program Interface (API)

Interface

Physical Constraints

Folded Occurrence

Vie

ws

Netlis

t

Load/Save

Layout

PersistentStore

HierarchicalHierarchical

SelectableSelectable

Incre

men

tal

Incre

men

tal

Electrical

Design Library (IDM)Design Library (IDM)

Placement Wiring

IDM HighlightsIDM Highlights

Proven– Based on technology in use at IBM

Extensible– Property, Group, Rule Box

Hierarchical– Full hierarchy preserved on both folded and occurrence models

Incremental– Application selectable data and views– Formal mechanisms defined for incremental support

Concurrent– Facilities to manage EDA design and analysis applications working

on same design library concurrently, reducing costly sequential steps

Proven– Based on technology in use at IBM

Extensible– Property, Group, Rule Box

Hierarchical– Full hierarchy preserved on both folded and occurrence models

Incremental– Application selectable data and views– Formal mechanisms defined for incremental support

Concurrent– Facilities to manage EDA design and analysis applications working

on same design library concurrently, reducing costly sequential steps

Cell Library (OLA)Cell Library (OLA)

Open Library API - simple cells through complex cores– Delay and Power calculations

– Block function

– Block characteristics used for Synthesis, Test, etc.

– Block Physical characteristics• Based on LEF Data Model

Direct Access Compiled• IP Protection• Speed• Size

ASCII Equivalent (ALF) from OVI• Diagnosis and repair

Based on DPCS (IEEE 1481) Architecture

Open Library API - simple cells through complex cores– Delay and Power calculations

– Block function

– Block characteristics used for Synthesis, Test, etc.

– Block Physical characteristics• Based on LEF Data Model

Direct Access Compiled• IP Protection• Speed• Size

ASCII Equivalent (ALF) from OVI• Diagnosis and repair

Based on DPCS (IEEE 1481) Architecture

OLA - PhysicalOLA - Physical

Adds cell physical characterization to OLA– Extended OLA API

– Extended ALF file format

Based on proven LEF data model

Transfer of LEF format from Cadence to enhance migration

Adds cell physical characterization to OLA– Extended OLA API

– Extended ALF file format

Based on proven LEF data model

Transfer of LEF format from Cadence to enhance migration

OLA-PhysicalOLA-Physical

Translate Compile AP

I

DCLALFTimingPower

FunctionPhysical

Rea

der

Ttr

ansl

ate

DPCM

LEF

EDAApps

Migration

Strategic- Field Repair

Strategic- Flow

Today

Technology/PackageTechnology/Package

Wiring layersPlacement area

Wiring areaI/O area

Terminal placementWiring models & constraints

Via modelsPower models & constraints

Placement models & constraintsPre-placed structures

Technology/PackageTechnology/Package

Wiring layersPlacement area

Wiring areaI/O area

Terminal placementWiring models & constraints

Via modelsPower models & constraints

Placement models & constraintsPre-placed structures

Application AreasApplication Areas

PlacementPower

Application AreasApplication Areas

PlacementPower

ConstraintsConstraints

Cell size, placement and wiring porosity, ..

Net - length, resistance,

capacitance, delay,..

Port and wiring constraints

ConstraintsConstraints

Cell size, placement and wiring porosity, ..

Net - length, resistance,

capacitance, delay,..

Port and wiring constraints

Process Definition Library (PDL)Process Definition Library (PDL)

Describes technology characteristics and constraints– Technology design groundrules

– Chip background and image descriptions

– Design constraints

Describes technology characteristics and constraints– Technology design groundrules

– Chip background and image descriptions

– Design constraints

SIPPsSIPPs

A single technology characterization– Tool-independent

– Electrically accurate

– Flexible for different abstraction levels

– Extensible enough for future processes technology

Advantages– Supplier characterizes process in one format

– Tools have standard access to characterization• Designer gets better correlation of results

– Design can use multiple extractors in flow• Allowing selective accuracy vs. speed tradeoffs

Based on technology from Frequency Technology and OEA international

A single technology characterization– Tool-independent

– Electrically accurate

– Flexible for different abstraction levels

– Extensible enough for future processes technology

Advantages– Supplier characterizes process in one format

– Tools have standard access to characterization• Designer gets better correlation of results

– Design can use multiple extractors in flow• Allowing selective accuracy vs. speed tradeoffs

Based on technology from Frequency Technology and OEA international

T

Dj+2

CDL

RsKjswcovj+1

Rvi

a Vw

mingapj

Edge

Kj+3

Kj+2

SIPPs Physical Model ConceptSIPPs Physical Model Concept

Layer by Layer Description of substrate, dielectrics, and metal•Metal dimensions and resistivities•Dielectric thicknesses and permitivity•Metal and trench coatings•Dimension losses•Air gaps•Temperature and spacing variations•Process variations

CHDStd Plug and PlayCHDStd Plug and Play

Integration Use ModelsIntegration Use Models

Application

Integrated Functions

.

Interfaced Functions

Translate

Application

Application

OperationalMemory

orData

Repository

Application(Private Model)

Map

CHDStd API

API is point of integrationrather than translated files

Application(Private Model)

CHDStd Reference ServerCHDStd Reference Server

Add Delete

TraverseAPI

Load Save

API

ApplicationApplication

FileRepository

MemoryStructures

Reference Server Use Model OptionsReference Server Use Model Options

Add Delete

TraverseAPI

Load Save

API

ApplicationApplication

FileRepository

MemoryStructures

Add Delete

TraverseAPI

Load Save

API

ApplicationApplication

FileRepository

Add Delete

TraverseAPI

Load Save

API

ApplicationApplication

FileRepository

MemoryStructures

MemoryStructures

CHDStd ReferenceCHDStd ReferenceServerServer

Customer DevelopedCustomer DevelopedServerServer

Reference API withReference API withCustomer RepositoryCustomer Repository

Net

addNetdeleteNet

reconnectNet

Cell

addCelldeleteCellmoveCellswapCells

disconnectCell

Port

addPortdeletePortmovePortswapPorts

connectPortdisconnectPort

Other

changeChildDefupdateCellPropertyupdatePortPropertyupdateNetProperty

Engineering Change Orders (ECO)Engineering Change Orders (ECO)

Defines delta modifications to a design– Add, delete and modify cells, ports or nets as well as their

placement and properties

Allows incremental design changes between sessions and across design teams

Facilitates managed EC process across the design team

Defines delta modifications to a design– Add, delete and modify cells, ports or nets as well as their

placement and properties

Allows incremental design changes between sessions and across design teams

Facilitates managed EC process across the design team

TransistorLevel Timing

Analysis Design Model

IDM

Synthesis TimingDesignPlanner

Cell LibraryCell LibraryCell LibraryCell Library

ProcessVariationModeler

Design LibraryDesign LibraryDesign LibraryDesign Library

Power Network Analysis Signal Integrity

Verification

DelayPower

FunctionPhysical

IEEE 1481

Extractor(s)

Putting it Together - CHDStdPutting it Together - CHDStd

Place & Route

Technology/ProcessParameters

PDLProcess LibraryProcess LibraryProcess LibraryProcess Library

OLA

Want More Information?Want More Information?

Specifications at:

www.si2.org/CHDStd

www.si2.org/ola

www.si2.org/sipps

Specifications at:

www.si2.org/CHDStd

www.si2.org/ola

www.si2.org/sipps