chapter8 retiming

8/8/2019 Chapter8 Retiming

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Retiming: Sequential digital circuit optimization

Theerayod Wiangtong25/01/05


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Introduction

T

register i

x

combinational logic with register j

propagation delay x

arrival time si arrival time sj

Synchronous Digital Circuits


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Approaches to synchronous logic

optimization

Optimize combinational logic only.

Optimize register position only:

Retiming.

Optimize overall circuit: Peripheral retiming.


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Example: Minimize delay

6

ij

55A

B

C

5

23

B C

12

A

max

12D

65

D

si = sj


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Retiming

6

ij

5 5A B

C12D

Shift registers around to improve circuit performance.

6

ij

5 5A B

C12D


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Optimal Retiming

si = sj

6

ij

5 5A B

C12D

5

16

B C

12

A

max 6 5

D

Minimum clock periodwith zero skew


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Retiming

Allow synthesis tool to automatically move register

stages delay on each side of the F/Fs Does not change total delay of the circuit Just

improves the balance of delays


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Example: Minimize Registers


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Fundamental criteria

u vw(u,v)

r(v)r(u)

> 0w(u,v) + r(v) - r(u)

After retiming, every wire must have nonnegative register

count:

O(E) linear constraintsE : # wires

w(u,v): original nonnegative register count of wire (u,v)


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Structural constraints

u v1

12

> 01 + r(v) - r(u)


count:




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u v

12


> 01 + 1 - r(u)


count:



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u v

12


> 01 + 1 - 2


count:



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Legal register moves

Retiming Lag/Lead


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So, what is retiming?

Structural optimization methods.

Retiming. Modeling:

Retiming for minimum delay.

Retiming for minimum area.


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Synchronous logic modeling

State-based model:

Transition diagrams or tables.

Explicit notion of state.

Implicit notion of area and delay.

Structural model:

Synchronous logic network.

Implicit notion of state.

Explicit notion of area and delay


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Synchronous network graph

Synchronous network graph:

Vertices equations I/O , gates.

Edges dependencies nets.

Weights synch. delays registers.


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Example


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Example


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Rules of retiming

Move register position.

Do not modify combinational logic.

Preserve network structure:

Modify weights. Do not modify graph structure.


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Example


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Retiming

Global optimization technique [Leiserson].

Changes register positions:

affects area:

changes register count.

affects cycle-time:

changes path delays between register pairs.

Solvable in polynomial time.


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Assumptions

Vertex delay is constant:

No fan-outdelay dependency. Graph topology is invariant:

No logic transformations.

Synchronous implementation: Cycles have positive weights.

Edges have non-negative weights.

Consider topologicalpaths: No false path analysis.


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Example

Retiming of a vertex:

Integer.

Lag: registers moved from output to input (+).

Lead: registers moved from input to output (-).

Retiming of a network:

Vector of vertex retiming.


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Example

r = -[11222100]T


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Definitions and properties

See example9.3.9 pp 465


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Legal retiming


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Refined analysis

Least register path:

.

Over all paths between viand vj.

Critical delay:

.

Over all the paths from vito vjwith weight W(vi, vj).

There exists a vertex pair vi, vjwhose D(vi, vj)bounds the cycle-time.


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Example


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Minimum cycle-time retiming

Find minimum value of the clock period such that thereexist a retiming vector where:

Solution: Given a value of :

solve linear constraints.

methods:

Bellman-Ford or derivate. MILP. Relaxation.


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Example

See 9.3.10 pp 466


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Minimum area retiming problem

Find a retiming vector that minimizes the

number of registers. Simple area modeling:

Every pos.-weighted edge -> register.

Total register area cost equals total of weights.

Register sharing model:

Every set of positively-weighted edges withcommon tail -> shift-register.

Register area cost equals maximum of weights onoutgoing edges.


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Example


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Summary of retiming

Sequential optimization technique for:

Cycle time or register area.

Applicable to:

Synchronous logic models.

Architectural data-path models:

Resources with delays.

Exact algorithm in polynomial time.

Problems: Delay modeling.

Network granularity.

chapter8 retiming

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