chapter2 manufacturing process 6pp
TRANSCRIPT
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EE415 VLSI Design
ManufacturingManufacturingProcessProcess
[Adapted f rom RabaeysDigital Integrated Circuits , 2002, J. Rabaeyet al.and presentation by J.Christiansen/CERN]
EE415 VLSI Design
Fabrication
WafersProcessing
Processed
Wafer
Chips
Masks
EE415 VLSI Design
Traditional CMOS Process
EE415 VLSI Design
A Modern CMOS Process
p-
p-epi
p well n well
p+n+
gate oxide
Al (Cu)
tungsten
SiO2
SiO2
TiSi2
Dual-Well Trench-Isolated CMOS
field oxide
EE415 VLSI Design
oxidation
optical
mask
process
step
photoresistcoatingphotoresistremoval (ashi ng)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single
photolithographic cycle (from [Fullman]).
Photo-Lithographic Process
EE415 VLSI Design
Growing the Silicon Ingot
From Smithsonian, 2000
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EE415 VLSI Design
Patterning - Photolithography
1. Oxidation
2. Photoresist (PR) coating
3. Stepper exposure4. Photoresist development and
bake
5. Acid etchingUnexposed (negative PR)Exposed (positive PR)
6. Spin, rinse, and dry
7. Processing stepIon implantationPlasma etchingMetal deposition
8. Photoresist removal (ashing)
mask
SiO2 PR
UV light
EE415 VLSI Design
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
l One full photolithography
sequence per layer
(mask)l Built (roughly) from the
bottom up
5 metal 2
4 metal 1
2 polysilicon
3 source and drain
diffusions
1 tubs (aka wells,active areas)
exception!
EE415 VLSI Design
Example of Patterning of SiO2
Si-substrate
Silicon base material
Si-substrate
3. Stepper exposure
UV-light
Patternedoptical mask
Exposed resist
1&2. After oxidation and
deposition of negativephotoresist
PhotoresistSiO2
Si-substrate
Si-substrate
SiO2
8. Final result after
removal of resist
Si-substrate
SiO2
5. After etching
Hardened resist
SiO2
Si-substrate
4. After development and
etching of resist, chemical orplasma etch of SiO
2
Hardened resist
Chemical or plasmaetch
EE415 VLSI Design
Diffusion and IonImplantation
1. Area to be doped is
exposed
(photolithography)
2. Dif fusion
or
Ion implantation
EE415 VLSI Design
Deposition and Etching
1. Pattern masking(photolithography)
2. Deposit material over
entire waferCVD (Si3N4)chemical deposition
(polysilicon)sputtering (Al)
3. Etch away unwanted
materialwet etching
dry (plasma) etchingEE415 VLSI Design
Planarization: Polishing theWafers
From Smithsonian, 2000
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EE415 VLSI Design
Self-Aligned Gates
1. Create thin oxide inthe active regions,thick elsewhere
2. Deposit polysilicon
3. Etch thin oxide fromactive region (polyacts as a mask for thediffusion)
4. Implant dopant
EE415 VLSI Design
Simplified CMOS InverterP-well Process
cut line
p well
EE415 VLSI Design
P-Well Mask
EE415 VLSI Design
Active Mask
EE415 VLSI Design
Poly Mask
EE415 VLSI Design
P+ Select Mask
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EE415 VLSI Design
N+ Select Mask
EE415 VLSI Design
Contact Mask
EE415 VLSI Design
Metal Mask
EE415 VLSI Design
VLSI Fabrication: The Cycle
EE415 VLSI Design
l The n -well CMOS process starts with a
moderately doped (impurity concentrationless than 1015 cm -3) p-type siliconsubstrate.
l Then, an oxide layer is grown on theentire surface. The first lithographic maskdefines the n-well region. Donor atoms,usually phosphorus, are implantedthrough this window in the oxide. Thisdefines, the active areas of the nMOS andpMOS transistors.
l Thin gate oxide is grown on top of theactive regions. The thickness and thequality of the gate oxide are criticalfabrication parameters, since they affectthe characteristics of the MOS transistor,and its reliability.
CMOS N-well Process (contd)
EE415 VLSI Design
CMOS N-well Process (contd)
l The polysilicon layer isdeposited using chemical
vapor deposition (CVD) andpatterned by dry (plasma)etching.
l The created polysilicon lineswill function as the gateelectrodes of the nMOS and the
pMOS transistors and theirinterconnects.
l Also, the polysilicon gates act
as self-aligned masks for thesource and drain implantationsthat follow this step.
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EE415 VLSI Design
CMOS N-well Process (contd)
l Using a set of two masks, then+ and p+ regions are
implanted into the substrateand into the n- well,respectively.
l The ohmic contacts to thesubstrate and to the n-well areimplanted in this process step.
EE415 VLSI Design
CMOS N-well Process (contd)
l An insulating silicon dioxidelayer is deposited over the
entire wafer usingCVD.
l Then, the contacts are definedand etched away to expose the
silicon or polysilicon contactwindows.
EE415 VLSI Design
CMOS N-well Process (contd)
l Metal is deposited over theentire chip surface usingmetal
evaporation, and the metal linesare patterned through etching.
l Since the wafer surface is non-
planar, the quality and theintegrity of the metal linescreated in this step are very
critical and are essential forcircuit reliability.
EE415 VLSI Design
CMOS N-well Process (contd)
l The composite layout and theresulting cross-sectional view of
the chip, showing one nMOSand one pMOS transistor (built-in n-well), the polysilicon and
metal interconnections.
l The final step is to deposit thepassivation layer(overglass -
for protection) over the chip,except for wire-bonding pad
areas.
EE415 VLSI Design
Advanced Metallization
EE415 VLSI Design
From Design to Reality
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EE415 VLSI Design
Design
Rules
EE415 VLSI Design
CMOS Process LayersLayer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
EE415 VLSI Design
Layers in 0.25 mCMOS process
EE415 VLSI Design
Design Rules
l Interface between the circuit designer and process
engineer
l Guidelines for constructing process masks
l Unit dimension: minimum line width
scalable design rules: lambda parameter
absolute dimensions: micron rules
l Rules constructed to ensure that design works even
when small fab errors (within some tolerance) occur
l A complete set includes
set of layers
intra-layer: relat ions between objects in the same layer
inter-layer: relations between objects on different layers
EE415 VLSI Design
3D Perspective
Polysilicon Aluminum
EE415 VLSI Design
Why Have Design Rules?
l To be able to tolerate some level of fabricationerrors such as
1. Mask misalignment
2. Dust
3. Process parameters
(e.g., lateral diffusion)
4. Rough surfaces
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EE415 VLSI Design
Intra-Layer Design RuleOrigins
l Minimum dimensions (e.g., widths) of objects on each
layer to maintain that object after fab minimum line width is set by the resolution of the
patterning process (photolithography)
l Minimum spaces between objects (that are not
related) on the same layer to ensure they will not
short after fab
0.3 micron
0.3 micron
0.15
0.15
EE415 VLSI Design
Inter-Layer Design RuleOrigins
1. Transistor rules transistor formed by
overlap of active and poly layers
Transistors
Catastrophicerror
Unrelated Poly & Diffusion
Thinner diffusion,but still working
EE415 VLSI Design
Inter-Layer Design RuleOrigins, Cont
2. Contact and via rules
M1 contact to p-diffusion
M1 contact to poly
Mx contact to My
Contact Mask
Via Masks
0.3
0.14
both materialsmask misaligned
M1 contact to n-diffusion
Contact: 0.44 x 0.44
EE415 VLSI Design
Intra-Layer Design Rules
Metal2
4
3
10
90
Well
Active
3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
EE415 VLSI Design
Transistor Layout
1
2
5
3
Transistor
EE415 VLSI Design
Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
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EE415 VLSI Design
Select Layer
1
3 3
2
2
2
WellSubstrate
Select
3
5
EE415 VLSI Design
IC Layout
EE415 VLSI Design
CMOS Inverter Sticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by
compaction program
EE415 VLSI Design
CMOS Inverter max Layout
VDD
GND
NMOS (2/.24 = 8/1)
PMOS (4/.24 = 16/1)
metal2
metal1polysilicon
InOut
metal1-poly via
metal2-metal1 via
metal1-diff via
pfet
nfet
pdif
ndif
EE415 VLSI Design
Layout Editor
EE415 VLSI Design
Design Rule Checker
poly_not_fetto all_diff minimum spacing = 0.14 um.
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EE415 VLSI Design
CMOS Inverters
Polysilicon
In
Ou t
Metal1
VDD
GN D
PMOS
NMOS
1.2m=2
EE415 VLSI Design
Well-well spacing = 9
M1- M1 spacing = 3
M1width = 4
Active to well edge = 5
Min active width = 3
Poly overlap of active = 2
M2 - M2 spacing = 4
All distances in
Layout Design Rule Violation
EE415 VLSI Design
Bui l di ng an Invert er
A
VCC
VSS
A
Output
Step1 Step2
A
OutputP
N
A
P diffusion
N diffusion
Step3 Step4
VCC
Output
VSS
With permission of William BradburyEE415 VLSI Design
Bui ld i ng a 2 Input NOR Gat e
A A BA B A BB
A
B
Out
P
Output
Sharednode
A B
A
B
P
NN
Step 1 Step 3
O
utput
Out
p
ut
S
hared
nod
e
VSS
VCC
VSS
Step 2
P
N
Step 4
VSS
O
utput
VC
C
With permission of William Bradbury
EE415 VLSI Design
Buil ding a 2 Input NAND Gate
With permission of William Bradbury
A A BA BB
Step 1 Step 3
Out
put
Outpu
t
Sha
red
node
VSS
VCC
VSS
Step 2
P
N
Step 4
A B
VSS
Ou
tput
VC
C
Sharednode
Output
P BA P
AN
BN
A
B
Out
EE415 VLSI Design
Combini ng Logi c Funct i ons
With permission of William Bradbury
AOut
B
B
B
B
B
AP
Out
P
B
A
BN
N
AB
VCC
VSSB
B
VSS
VCC
Out
AB
Out
B
VSS
VCC
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EE415 VLSI Design
Cel l Symbol t o Logic to
Transi st or Schemat i c to Layout
With permission of William Bradbury
INPUT OUTPUT
LD LD
SRAM
OUTPUT
P 1.4N 1.4
LD
LD
P 1.8N 2.0
P 2.0N 2.0
P .5/1.0N .6/1.0
INPUT B
A
SRAMBIT LOGIC
Minimum poly widthL = 0.20
OUTPUT
SRAMBIT TRANSISTORSCHEMATIC
INPUT P2, 1.8
N2, 2.0
P3, .5/1.0
P4, 2.0
N4, 2.0P1, 1.4N1, 1.4
LD
LD
B
A
N3, .6/1.0
Note the listingof the L dimensionwhich is not the minimum defined by
theprocess
EE415 VLSI Design
Schemat i c to Transistor
With permission of William Bradbury
AINPUT
LD
P1
VCC
A
B
P2VCC
OUTPUTB
P4
VCCA
B
P3
A
INPUT
LD
N1
VSS
A
BN2
VSS
B
OUTPUT
N4
VSSA
B
N3
EE415 VLSI Design
Assembl i ng the Transist ors by
Type and Node Name
With permission of William Bradbury
VCC
A
B
A
INPUT
LDVCC
A
B
VCC
OU
TPUT
B
VSS
A
INPUT
LD VSS
B
OUTPUT
VS
S
A
B
B
EE415 VLSI Design
Connecti ng the Nodes
With permission of William Bradbury
INPUT
VCCAA
INPUT
LD
A
VC
C
B
B
VCC OUTPUT
B
VSS
A
LD
B
OUTPUT
VSS
A
B
VSS
B
EE415 VLSI Design
Connecti ng the Dotes
With permission of William Bradbury
INPUT
VCC
A
B
A
I
NPUT
LD
VCCB
VCC
OU
TPUT
B
VSSA
IN
PUTLD
VSS
B
OUTP
UT
A
B
A
BA
UNMERGED DATA:
Notice the addition of contactswhere necessary and also the use of
redundant contacts to improvereliability
VSS
EE415 VLSI Design
Cleani ng Connecti ons and
Complet i ng the layout
With permission of William Bradbury
.
P-TAP
V
CCB
A
VCC
B
OUTP
UT
VSS
AINPUT
VSS
B
OUTPUT
VSS
B
A
A
B
OUTPUTINPUT
LD
B
B
B
P-IMPLANT
N-TAPN-WELL
P1
P2
P3
P4
N1 N3 N4
N-IMPLANT
N2
VCC
INP
UT
A
LDDD
Added:1.Taps
2.Implants3.Cell boundry
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EE415 VLSI Design
Using st i cks
With permission of William Bradbury
.
N diffusion
Metal1
P diffusion
Contact
Poly
B AB
VSS
VCC
Output
EE415 VLSI Design
Same cel l , di ff erent shape
With permission of William Bradbury
.
ABB
VSS
VCC VCC
Out
AB
VCC
B
OutB
VSS
B AB
VSS
VCC
Output
EE415 VLSI Design
Cel l s Designed for Shari ng
With permission of William Bradbury
.
1Bit
1Bit
MemoryRow 1
CompareRow1
ReferenceVoltageSense
Ckt.forOneRow
Height of 1MemoryBit
1Bit
1Bit
MemoryRow1
CompareRow1
ReferenceVoltageDual
SenseAmpCell Height
CompareRow2
MemoryRow2
ReferenceVoltage
Dual SenseAmps Dual WriteLineCkts
CourtesyMentorGraphicsCorp. LayoutcreatedusingIC -Station.
EE415 VLSI Design
Cel l s Designed for Shar ing
With permission of William Bradbury
.
EE415 VLSI Design
Packaging
EE415 VLSI Design
Packaging Requirements
l Electrical: Low parasiticsl Mechanical: Reliable and robust
l Thermal: Efficient heat removal
l Economical: Cheap
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EE415 VLSI Design
Chip to package connection
l Wire bonding
Only periphery of chip available for IO connections
Mechanical bonding of one pin at a time (sequential)
Cooling from back of chip
High inductance (~1nH)
l Flip-chip
Whole chip area available for IO connections
Automatic alignment
One step process (parallel)
Cooling via balls (front) and back if required
Thermal matching between chip and substrate required
Low inductance (~0.1nH)
EE415 VLSI Design
Bonding Techniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
EE415 VLSI Design
Tape-Automated Bonding (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder BumpFilm + Pattern
Sprocket
hole
Polymer film
Leadframe
Test
pads
EE415 VLSI Design
New package types
l BGA (Ball Grid Array)
Small solder balls to connect
to board
small
High pin count
Cheap
Low inductance
l CSP (Chip scale Packaging)
Similar to BGA
Very small packages
Package inductance:
1 -5 nH
EE415 VLSI Design
Flip-Chip Bonding
Solder bumps
Substrate
Die
Interconnect
layers
EE415 VLSI Design
Package-to-Board Interconnect
(a) Through-Hole Mounting(b) Surface Mount
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EE415 VLSI Design
Package Types
EE415 VLSI Design
Package Parameters
EE415 VLSI Design
Signal Interface
l Transfer of IC signals to PCB Package inductance.
PCB wire capacitance.
L - C resonator circuit generating oscillations.
Transmission line effects may generate reflections
Cross-talk via mutual inductance
L
C
Package
ChipPCB trace
L-C Oscillation
Z
Transmission line reflections
R
f =1/(2(LC)1/2 )
L = 10 nHC = 10 pF
f = ~500MHz
EE415 VLSI Design
Packaging Faults
Small Ball Chip Scale Packages (CSP) Open
EE415 VLSI Design
CSP Assembly on 6 mil Via in 12 mil pad
Void over via structure
Packaging Faults
EE415 VLSI Design
Multi-Chip Modules
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EE415 VLSI Design
Multiple Chip Module (MCM)
l Increase integration level of system (smaller size)
l Decrease loading of external signals > higher performance
l No packaging of individual chips
l Problems with known good die: Single chip fault coverage: 95%
MCM yield with 10 chips: (0.95)10 = 60%
l Problems with cooling
l Still expensive
EE415 VLSI Design
Complete PC in MCM