chapter01-os7e
DESCRIPTION
ppTRANSCRIPT
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Chapter 1Computer
System OverviewSeventh Edition
By William Stallings
Operating
Systems:Internals
and Design
Principles
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Operating Systems:Operating Systems:
Internals and Design PrinciplesInternals and Design Principles
“No artifact designed by man is so convenient for this kind of functional description as a digital computer. Almost the only ones of its properties that are detectable in its behavior are the organizational properties. Almost no interesting statement that one can make about an operating computer bears any particular relation to the specific nature of the hardware. A computer is an organization of elementary functional components in which, to a high approximation, only the function performed by those components is relevant to the behavior of the whole system.”
THE SCIENCES OF THE ARTIFICIAL ,
Herbert Simon
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Operating SystemOperating System
Exploits the hardware resources of one or more processors to provide a set of services to system users
Manages secondary memory and I/O devices
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Basic ElementsBasic Elements
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ProcessorProcessor
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Main MemoryMain Memory
VolatileContents of the memory is lost when the computer is shut down
Referred to as real memory or primary memory
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I/O ModulesI/O Modules
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System BusSystem Bus
Provides for communication among processors, main memory, and I/O modules
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Top-Level Top-Level ViewView
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MicroprocessorMicroprocessor
Invention that brought about desktop and handheld computing
Processor on a single chipFastest general purpose processorMultiprocessorsEach chip (socket) contains multiple processors (cores)
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Graphical Processing Graphical Processing Units (GPUs)Units (GPUs)
Provide efficient computation on arrays of data using Single-Instruction Multiple Data (SIMD) techniques
Used for general numerical processing
Physics simulations for gamesComputations on large spreadsheets
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Digital Signal Digital Signal ProcessorsProcessors
(DSPs)(DSPs)Deal with streaming signals such as audio or video
Used to be embedded in devices like modems
Encoding/decoding speech and video (codecs)
Support for encryption and security
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System on a ChipSystem on a Chip(SoC)(SoC)
To satisfy the requirements of handheld devices, the microprocessor is giving way to the SoC
Components such as DSPs, GPUs, codecs and main memory, in addition to the CPUs and caches, are on the same chip
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Instruction ExecutionInstruction Execution
A program consists of a set of instructions stored in memory
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Basic Instruction CycleBasic Instruction Cycle
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The processor fetches the instruction from memory
Program counter (PC) holds address of the instruction to be fetched next
PC is incremented after each fetch
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Instruction Register Instruction Register (IR)(IR)
Fetched instruction is loaded into Instruction Register (IR)
Processor interprets the instruction and performs required action:
Processor-memory
Processor-I/O Data processing Control
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Characteristics of a Characteristics of a Hypothetical MachineHypothetical Machine
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Example of Program Execution
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InterruptsInterrupts
Interrupt the normal sequencing of the processor
Provided to improve processor utilization
most I/O devices are slower than the processor processor must pause to wait for device wasteful use of the processor
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Common
Classes
of Interrupts
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Flow of Control
Without
Interrupts
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Interrupts: Short I/O Wait
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Transfer of Control via Interrupts
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Instruction Cycle With Instruction Cycle With InterruptsInterrupts
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Program
Timing:
Short I/O Wait
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Program
Timing:
Long I/O wait
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Simple
Interrupt
Processing
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Multiple InterruptsMultiple Interrupts
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Memory HierarchyMemory Hierarchy
Major constraints in memory amount speed expense
Memory must be able to keep up with the processor
Cost of memory must be reasonable in relationship to the other components
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Memory RelationshipsMemory Relationships
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The Memory HierarchyThe Memory Hierarchy
Going down the hierarchy:
decreasing cost per bit increasing capacity increasing access time decreasing frequency
of access to the memory by the processor
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Performance of a Simple Performance of a Simple
Two-Level MemoryTwo-Level Memory
Figure 1.15 Performance of a Simple Two-Level Memory
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Memory references by the processor tend to cluster
Data is organized so that the percentage of accesses to each successively lower level is substantially less than that of the level above
Can be applied across more than two levels of memory
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Invisible to the OS
Interacts with other memory management hardware
Processor must access memory at least once per instruction cycle
Processor execution is limited by memory cycle time
Exploit the principle of locality with a small, fast memory
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Contains a copy of a portion of main memory
Processor first checks cache
If not found, a block of memory is read into cache
Because of locality of reference, it is likely that many of the future memory references will be to other bytes in the block
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Cache and Main
Memory
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Cache/Main-Memory StructureCache/Main-Memory Structure
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I/O TechniquesI/O Techniques
∗ When the processor encounters an instruction relating to I/O, it executes that instruction by issuing a command to the appropriate I/O module
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Programmed I/OProgrammed I/O
The I/O module performs the requested action then sets the appropriate bits in the I/O status register
The processor periodically checks the status of the I/O module until it determines the instruction is complete
With programmed I/O the performance level of the entire system is severely degraded
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Interrupt-Driven I/OInterrupt-Driven I/O
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Interrupt-Driven I/OInterrupt-Driven I/ODrawbacksDrawbacks
Transfer rate is limited by the speed with which the processor can test and service a device
The processor is tied up in managing an I/O transfer
a number of instructions must be executed for each I/O transfer
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Direct Memory AccessDirect Memory Access (DMA) (DMA)
∗ Performed by a separate module on the system bus or incorporated into an I/O module
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Transfers the entire block of data directly to and from memory without going through the processor
processor is involved only at the beginning and end of the transfer
processor executes more slowly during a transfer when processor access to the bus is required
More efficient than interrupt-driven or programmed I/O
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Symmetric Multiprocessors Symmetric Multiprocessors
(SMP)(SMP)
A stand-alone computer system with the following characteristics: two or more similar processors of comparable capability processors share the same main memory and are
interconnected by a bus or other internal connection scheme
processors share access to I/O devices all processors can perform the same functions the system is controlled by an integrated operating
system that provides interaction between processors and their programs at the job, task, file, and data element levels
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SMP OrganizationSMP Organization
Figure 1.19 Symmetric Multiprocessor Organization
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Multicore ComputerMulticore Computer
Also known as a chip multiprocessor
Combines two or more processors (cores) on a single piece of silicon (die)
each core consists of all of the components of an independent processor
In addition, multicore chips also include L2 cache and in some cases L3 cache
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Intel Core i7Intel Core i7
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Intel Intel Core Core i7i7
Figure 1.20 Intel Corei7 Block Diagram
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SummarySummaryBasic Elements
processor, main memory, I/O modules, system bus
GPUs, SIMD, DSPs, SoC Instruction execution
processor-memory, processor-I/O, data processing, control
Interrupt/Interrupt Processing Memory Hierarchy Cache/cache principles and designs Multiprocessor/multicore