7.1 REPRESENTATION OF FLOATING-POINT NUMBERS

N = F x 2E

Examples of floating-point numbers using a 4-bit fraction and 4-bit exponent:

F = 0.101 E = 0101 N = 5/8 x 25

F = 1.011 E = 1011 N = –5/8 x 2–5

F = 1.000 E = 1000 N = –1 x 2–8

NormalizationUnnormalized: F = 0.0101 E = 0011 N = 5/16 x 23 = 5/2Normalized: F = 0.101 E = 0010 N = 5/8 x 22 = 5/2

Unnormalized: F = 1.11011 E = 1100 N = –5/32 x 2–4 = –5 x 2–9

(shift F left) F = 1.1011 E = 1011 N = –5/16 x 2–5 = –5 x 2–9

Normalized F = 1.011 E = 1010 N = –5/8 x 2–6 = –5 x 2–9

Representation of ZeroF = 0.000, E = 1000 or 0.000 x 2-8

Add ExponentsMultiply Fractions

F=0

Set E = –8

Done

Done

FOverflow

Set F = 1/2 E <= E+1

FNormalized

ExpOverflow

Shift F Left E <= E-1

Set Indicator

Y

Y

Y

Y

N

N

N

N

Start

Figure 7-1 Flowchart for Floating-Point Multiplication

1 023

0123

5-bit Full Adder

Y

4 XSM8IncDec

Load

Adx

St

Mdone

FZ

FV

Fnorm

EV

Load

Adx

SM8

RSF = Inc

LSF = Dec

Done

V

MainControl

E1

Load

E2

Figure 7-2(a) Exponent Adder and Fraction Multiplier

1 0230123

A (accumulator)

4-bit Full Adder

1's Complementer

C1 023

LoadAdSh Sh

RSF

LSF

B

F1

Load

MultiplyControl

Mdone

Adx

M

Sh

AdSh

Cm

F2

FFigure 7-2(b) Exponent Adder and Fraction Multiplier

1

Load

St0

Mdone

S1 / Adx

0

S0 /

S2 /

FZ

Fnorm

LSF

0

1

0

FVSM8

RSF

01

1

01

S3 / Done

RSF

St

EV

1

V

add exponents,start multiply

MultiplierFraction

Control

1

0

Figure 7-3 SM Chart for floating-Point Multiplication

S1

S2S3

S4

S0 Adx M/AdShAdx M'/Sh

M/AdSh

M/AdSh

M/Cm AdShM'/ShM'/Sh

M'/Sh

–/Mdone

Adx'/0

Figure 7-4 State Graph for Multiplier Control

Figure 7-5(a) VHDL Code for Floating-Point Multiplierlibrary BITLIB;use BITLIB.bit_pack.all;entity FMUL is

port (CLK, St: in bit; F1,E1,F2,E2: in bit_vector(3 downto 0);F: out bit_vector(6 downto 0); V, done:out bit);

end FMUL;architecture FMULB of FMUL issignal A, B, C: bit_vector(3 downto 0); -- fraction registerssignal X, Y: bit_vector(4 downto 0); -- exponent registerssignal Load, Adx, Mdone, SM8, RSF, LSF, NC: bit; signal AdSh, Sh, Cm: bit;signal PS1, NS1: integer range 0 to 3; -- present and next statesignal State, Nextstate: integer range 0 to 4; -- mulitplier control statealias M: bit is B(0); constant one:bit_vector(4 downto 0):="00001";constant neg_one:bit_vector(4 downto 0):="11111";beginmain_control: process

beginLoad <= '0'; Adx <= '0'; -- clear control signalsSM8 <= '0'; RSF <= '0'; LSF <= '0';case PS1 is

when 0 => done<='0'; V<='0'; -- clear outputsif St = '1' then Load <= '1'; NS1 <= 1; F <= "0000000"; end if;

when 1 => Adx <= '1'; NS1 <= 2;

Figure 7-5(b) VHDL Code for Floating-Point Multiplier

when 2 => if Mdone = '1' then -- wait for multiplyif A = "0000" then SM8 <= '1'; -- zero fractionelsif A = "0100" and B = "0000" then -- fraction overflow

RSF <= '1'; -- shift AB rightelsif A(2) = A(1) then -- test for unnormalized

LSF <= '1'; -- shift AB leftend if; NS1 <= 3;

end if;when 3 => --test for exp overflow

if X(4) /= X(3) then V <= '1'; else V <= '0'; end if;done <= '1';F <= A(2 downto 0) & B; --output fractionif ST = '0' then NS1<=0; end if;

end case;wait until rising_edge(CLK);

PS1 <= NS1;wait for 0 ns; --wait for state changeend process main_control;

mul2c: process --2's complement multiplybeginAdSh <= '0'; Sh <= '0'; Cm <= '0'; --clear control signalscase State is

when 0=> Mdone <= '0'; --start multiplyif Adx='1' then

if M = '1' then AdSh <= '1'; else Sh <= '1'; end if;Nextstate <= 1;

end if;

Figure 7-5(c) VHDL Code for Floating-Point Multiplier

when 1 | 2 => --add/shift stateif M = '1' then AdSh <= '1'; else Sh <= '1'; end if;Nextstate <= State + 1;when 3 =>if M = '1' then Cm <= '1'; AdSh <= '1'; else Sh <='1'; end if;Nextstate <= 4;when 4 => Mdone <= '1'; Nextstate <= 0;

end case;wait until rising_edge(CLK);State <= Nextstate;wait for 0 ns; --wait for state changeend process mul2c;

update: process --update registersvariable addout: bit_vector(4 downto 0);beginwait until rising_edge(CLK);if Cm = '0' then addout := add4(A,C,'0');

else addout := add4(A, not C,'1'); end if; --add 2's comp. of Cif Load = '1' then X <= E1(3)&E1; Y <= E2(3)&E2;

A <= "0000"; B <= F2; C <= F1; end if;if ADX = '1' then addvec(X,Y,'0',X,NC,5); end if;if SM8 = '1' then X <= "11000"; end if;if RSF = '1' then A <= '0'&A(3 downto 1);

B <= A(0)&B(3 downto 1);addvec(X,one,'0',X,NC,5); end if; -- increment X

Figure 7-5(d) VHDL Code for Floating-Point Multiplier

if LSF = '1' thenA <= A(2 downto 0)&B(3); B <= B(2 downto 0)&'0';addvec(X,neg_one,'0',X,NC,5); end if; -- decrement X

if AdSh = '1' thenA <= (C(3) xor Cm) & addout(3 downto 1); -- load shifted adderB <= addout(0) & B(3 downto 1); end if; -- output into A & B

if Sh = '1' thenA <= A(3) & A(3 downto 1); -- right shift A & BB <= A(0) & B(3 downto 1); -- with sign extend

end if;end process update;

end FMULB;

Figure 7-6(a) Test Data for Floating-Point Multiply

list f x f1 e1 f2 e2 v doneforce f1 0111 0, 1001 200, 1000 400, 0000 600, 0111 800force e1 0001 0, 1001 200, 0111 400, 1000 600, 0111 800force f2 0111 0, 1001 200, 1000 400, 0000 600, 1001 800force e2 1000 0, 0001 200, 1001 400, 1000 600, 0001 800force st 1 0, 0 20, 1 200, 0 220, 1 400, 0 420, 1 600, 0 620, 1 800, 0 820force clk 0 0, 1 10 -repeat 20run 1000

Figure 7-6(b) Simulation Results for Floating-Point Multiplyns delta f x f1 e1 f2 e2 v done 0 +0 0000000 00000 0000 0000 0000 0000 0 0 0 +1 0000000 00000 0111 0001 0111 1000 0 0 (0.111 x 21) x (0.111 x 2-8) 10 +1 0000000 00001 0111 0001 0111 1000 0 0 30 +1 0000000 11001 0111 0001 0111 1000 0 0150 +2 0110001 11001 0111 0001 0111 1000 0 1 = 0.110001 x 2-7170 +2 0000000 11001 0111 0001 0111 1000 0 0200 +0 0000000 11001 1001 1001 1001 0001 0 0 (1.001 x 2-7) x (1.001 x 21)250 +1 0000000 11010 1001 1001 1001 0001 0 0370 +2 0110001 11010 1001 1001 1001 0001 0 1 = 0.110001 x 2-6390 +2 0000000 11010 1001 1001 1001 0001 0 0400 +0 0000000 11010 1000 0111 1000 1001 0 0 (1.000 x 27) x (1.000 x 2-7)430 +1 0000000 00111 1000 0111 1000 1001 0 0450 +1 0000000 00000 1000 0111 1000 1001 0 0570 +1 0000000 00001 1000 0111 1000 1001 0 0570 +2 0100000 00001 1000 0111 1000 1001 0 1 = 0.100000 x 21590 +2 0000000 00001 1000 0111 1000 1001 0 0600 +0 0000000 00001 0000 1000 0000 1000 0 0 (0.000 x 2-8) x (0.000 x 2-8)630 +1 0000000 11000 0000 1000 0000 1000 0 0650 +1 0000000 10000 0000 1000 0000 1000 0 0770 +1 0000000 11000 0000 1000 0000 1000 0 0770 +2 0000000 11000 0000 1000 0000 1000 0 1 = 0.0000000 x 2-8790 +2 0000000 11000 0000 1000 0000 1000 0 0800 +0 0000000 11000 0111 0111 1001 0001 0 0 (0.111 x 27) x (1.001 x 21)830 +1 0000000 00111 0111 0111 1001 0001 0 0850 +1 0000000 01000 0111 0111 1001 0001 0 0970 +2 1001111 01000 0111 0111 1001 0001 1 1 = 1.001111 x 28 (overflow)990 +2 0000000 01000 0111 0111 1001 0001 0 0

AC(F1)

FractionAdder

ExponentAdder

X(E1) Y(E2)B(F2)

Input

Figure 7-7 Bus Structure for Floating-Point Multiplier

GND

D0D1D2D3CEC

CLR

Q0Q1Q2Q3L1

C

DB0DB1DB2DB3

F1_Register

F10F11F12F13

FRACTIONADDER

F1[3-0]F1[3-0]

F2[3-0]

FS[4-0]FSUM[4-0]

A[3-0]CLR

B3S1S2S3F1C3LSFADSHRSFSHC

FVFZFN

FVFZFN

LSFADSHRSFSHC

CLRB3

FSUM1FSUM2FSUM3FSUM4

FSUM[4-0]

FSUM0

DB[3-0]

A_Register

B_Register

A[3-0]

B[3-0]B[3-0]

Data_Out1A0A1A2

A0A1A2B[3-0]

A0A0S0

LZLSFRSF

ADSHSHC

LFZLSFRSFADSHSHC

D2_4EL1L2L3L4E

A0

A1

B0B1B2B3

IPAD4I3I2I1I0

IBUF4ST

SW0SW1

LD

ADXB0C

ADX

B0C

Multiplier

ADSHCDSH

MDONE

MDONEADSH

CDSH

MDONE

C2

CFVFZFN

C2

C

FVFZ

FN

ST

DONE

CLR

ADX

RSF

LSF

DONE

CLR

ADX

RSF

LSF

MAIN

SM8 SM8

CO

FD4CE

CO

Figure 7-8(a) Top-level Schematic for Floating-Point Multiplier

DB

E1_Register (X)DONE DONE

DB[3-0]

E1[4-0]S4

L3RSFLSFCADX

IN4

LE1RSFLSFCADX

VV

V

E1[4-0]

Data_Out2

E1[4-0]

ExponentAdder

ADXRSFLSF

S4S4

ADX

E1[4-0]

S[3-0]

E2[3-0]

E2[3-0]E20E21E22E23

E2_Register (Y)

L4C

D0D1D2D3CEC

CLR

Q0Q1Q2Q3

GND

DB0DB1DB2DB3

DB3DB2DB1DB0

DB[3-0]

BUFG

BUFG

C

C2

OSC4

F15F490

F15KF500K

FBM

IPAD4I3I2I1I0

D3D2D1D0

IBUF4 T BUFT4

SM8 SM8

INDE

LD

DB

Figure 7-8(b) Top-level Schematic for Floating-Point Multiplier

CMDONE

FVFNORM

FZ

ST

C2

D Q

C

FDD Q

C

FD

D Q

C

FD

D Q

C

FD

D Q

C

FD

DONE

CLR

ADX

RSF

LSF

SM8

Q0

Q1

Q2

Q3

Figure 7-9 Main Control for Floating-Point Multiplier

FDD Q

C

FDD Q

C

FDD Q

C

FDD Q

C

ADX

C

BO

SH

CO

ADSH

MDONEQ4

Q3

Q2

Q1

Figure 7-10 Multiplier Control

S1S2S3F1C3

LSF

ADSHRSFSH

C

CLR

B3

CLRCKS1S0SRIDCBASLI

QAQBQCQD

X74_194

A0A1A2A3

FV

FZ

FN

A[3-0]

Name=A.1

Figure 7-11 A Register

E10E11E12E13E14 E1[4-0]

Q0Q1Q2Q3Q4

RD5CR

D0D1D2D3D4CCERD

GND

DB0

DB1

DB2

DB3

DB[3-0]

IN4M2-1

D0D1

SEQ

SM8LE1ADXDCIC

CDONE

V

SM8

Figure 7-12 E1 Register

E2[3-0]E20

E21

E22

E23

B0

B1

B2

B3

B0B1B2B3

A0A1A2A3

CIE1[4-0] E10

E11E12E13 S0

S1S2S3

S0S1S2S3

S[3-0]

BUFT4T

ADD4

ADX

DE

IN

E14

CO

Figure 7-13 Exponent Adder

S4

FLOATING POINT ADDITION (from page 259)

(F1 x 2E1) + (F2 x 2E2) = F x 2E

Example 1: Add F1 x 2E1 = 0.111 x 25 and F2 x 2E2 = 0.101 x 23

Unnormalize 0.101 x 23 = 0.0101 x 24 = 0.00101 x 25

Add fractions (0.111 x 25) + (0.00101 x 25) = 01.00001 x 25

Fix Overflow F x 2E = 0.100001 x 26

Example 2: (1.100 x 2–2) + (0.100 x 2–1)= (1.110 x 2–1) + (0.100 x 2–1) (after shifting F1)

= 0.010 x 2–1 (result of adding fractions is unnormalized)

= 0.100 x 2–2 (normalized by shifting left and subtracting one from

exponent)

FLOATING POINT ADDITION SUMMARY (from page 260)

1) If exponents are not equal, shift the fraction with the smallest exponentright and add 1 to its exponent; repeat until the exponents are equal.

2) Add the fractions.

3) (a) If fraction overflow occurs, shift right and add 1 to the exponent tocorrect the overflow.(b) If the fraction is unnormalized, shift left and subtract 1 from exponentuntil the fraction is normalized.(c) If the fraction is 0, set the exponent to the appropriate value.

4) Check for exponent overflow.