chapter 6: synthesis of combinatorial and sequential logic 2016/ece4242/chap6a.pdf · 1. detect and...

Chap 6a Copyright 2011 Greg Tumbush v1.2

Chapter 6: Synthesis of Combinatorial and Sequential Logic

1

What is synthesis?

• Synthesis is the mapping of your code to a mixture of logic gates and registers. • The available logic gates and registers are determined from the technology library you are targeting.

Synthesis Tool

Verilog/VHDL

Technology Library

Gate Level Netlist

Technology Library • Specific to every fab vendor, TSMC, IBM, ON, etc. • Specific to each technology node 0.13um, 90nm, 45nm, 28nm

• TSMC FinFET nodes: current -16nm, future roadmap -10nm, 7nm • Have specific versions, low leakage, different voltage ranges, etc. • We are using the OSU 0.5um library. http://www.uccs.edu/~gtumbush/4242/OSU_cell_library/osu_cell_library.html

2 Chap 6a Copyright 2011 Greg Tumbush v1.2

Chap 6a Copyright 2011 Greg Tumbush v1.2 3

Inverter Layout

n-diffusion

p-diffusion

polysilicon

input

output

Vdd

GND


A digital designer must understand:

• How to write Verilog or VHDL to create combinatorial logic • How to write Verilog or VHDL to create sequential logic • How language constructs synthesize

• How to write synthesizable code

always @(posedge clk or negedge reset)

always @(negedge clk or posedge set)

vs

A*8 A << 3 vs

initial while/forever/repeat

Synthesis Example 1

module mux2_1( input wire i0, i1, sel, output wire out ); assign out = sel ? i1:i0; endmodule

Synthesis

module mux2_1 ( i0, i1, sel, out ); input i0, i1, sel; output out; wire n6; INVX1 U4 ( .A(n6), .Y(out) ); MUX2X1 U5 ( .B(i0), .A(i1), .S(sel), .Y(n6) ); endmodule

MUX2X1 Function Y=!(S?(A:B)) INVX1 Function Y=!A

SBASY


Synthesis Example 2 `default_nettype none module dff( input wire clk, reset, data_in, output reg data_out ); always @(posedge clk or posedge reset) begin if (reset) data_out <= 1'b0; else data_out <= data_in; end endmodule

module dff ( clk, reset, data_in, data_out ); input clk, reset, data_in; output data_out; wire n1; DFFSR data_out_reg ( .D(data_in), .CLK(clk), .R(n1), .S(1'b1), .Q(data_out) ); INVX1 U5 ( .A(reset), .Y(n1) ); endmodule

DFFSR Function FLIPFLOP{ DATA=D CLOCK=CLK PRESET=!S CLEAR=!R Q=P0002 QN=P0003 } Q=P0002

INVX1 Function Y=!A


Synthesis Example 3

00

01

10

11

0 1ABC

0

1

1

0

1

0

0 1

CBACf

00

01

10

11

0 1ABC

0

1

1

0

1

0

0 1

ABCBACf

1-Hazard Elimination

`default_nettype none module redundant( input wire A, B, C, output wire F ); assign F = (A && C) || (B && !C) || (A && B); endmodule

module redundant ( A, B, C, F ); input A, B, C; output F; wire n5; INVX1 U4 ( .A(n5), .Y(F) ); MUX2X1 U5 ( .B(B), .A(A), .S(C), .Y(n5) ); endmodule

CBACCBACf 7 Chap 6a Copyright 2011 Greg Tumbush v1.2

What Synthesis Tools are Available?

•ASIC • Synopsys Design Compiler – 67% • Magma BlastCreate – 21% (Synopsys bought Magma in 2012) • Cadence Encounter RTL (Get2Chip, RTL Compiler, Ambit) – 22%

•FPGA • Synopsys Synplify • Mentor Precision • Xilinx ISE (ISE deprecated, Vivado supported) •Altera Quartus II (Intel bought Altera in 2015)


Exercise: Hand Synthesize the following code

module comb_dff( input wire clk, reset, data_in, inv_flag, output reg data_out ); always @(posedge clk or posedge reset) begin if (reset) data_out <= 1'b0; else begin if (inv_flag) data_out <= ~data_in; else data_out <= data_in; end end endmodule


Synthesis Tool Tasks


1. Detect and eliminate redundant logic 2. Detect combinatorial feedback loops 3. Exploit don’t care conditions 4. Detect unused states 5. Detect and collapse equivalent states 6. Make state assignments 7. Synthesize optimal multi-level realizations of logic

Optimizations for Combinatorial Logic

• Decomposition • Extraction • Factoring • Substitution • Elimination (Flattening)


Goal is smallest area that meets timing constraints

Decomposition • Expresses a single boolean function in terms of new nodes • Reuses these new nodes to create a smaller (but possibly slower circuit) • Example 6.1


dcbdcaabdabcF

dcbadcabF )()(

)()( dcabdcabF

dcYabXLet and

YXXYF

Decomposition - Circuit


dcbdcaabdabcF

a b c d

F

dcY

abX

YXXYF

a b c d

F

X

Y

Decomposition

Extraction • Expresses multiple boolean function in terms of new nodes • Reuses these new nodes to create a smaller (but possibly slower circuit)

• Example 6.2


cdeHebaG

ecdbaF

)(

)(

a

F

cd

bcd

e

a

Gebecde

H

cdeH

ebeaG

ebcdacdF

Extraction (cont)


cdeHebaG

ecdbaF

)(

)(

e .+

a

bc

d

.. +

e

.

G

F

H

e .+

a

bc

d

.. +

e

.

G

F

H

X

Y

F

cd

a

e

H

bX

Y

e

e

G

Factoring •Factorization seeks the factored representation of a function with the fewest number of literals. • Reuses these new nodes to create a smaller (but possibly slower circuit)

• Example 6.3


ebdbcadacF

.

+

a

F

b c d e

.

.

.

edcbaF ))((

+

a

F

b c d e

.+

+

a+b

c+d

Factoring

Substitution •Sustitution seeks to express a boolean function in terms of its inputs and another function. • Reuses these new nodes to create a smaller (but possibly slower circuit)

• Example 6.4


cbaFbaG

Substitution

cGFbaG

a b c

+

+

F

G

a

b

c +

+

F

G

Elimination or Flattening • Flattening rolls back decomposition transformation • Results in a faster but larger circuit.

• Example 6.5


dcGbGGaF

Flattening

bdcadacF

bdcadcF

)()(

a b c

+

+

F

.d

.

G

a b c

+ F

d

.

.

.

Exercise: Hand synthesize the following code to find the smallest circuit

module extraction( input wire A, B, C, D, output wire out1, out2 ); assign out1 = D && (A || B); assign out2 = (B && C) || (A && C); endmodule


Evaluate for size using the OSU 0.5um cell library.

Synthesis Example 6.7: module or_nand( input wire enable, x1, x2, x3, x4, output wire y ); assign y=~(enable && (x1 || x2) && (x3 || x4)); endmodule


x1

y

enable

x2

x3x4

oai22X1

nand2X1invX1

6.2.1 Synthesis of Priority Structures • An if statement implies priority • Only if all if branching is mutually exclusive will a non-priority structure be synthesized.


module mux_4pri (input a, b, c, d, sel_a, sel_b, sel_c, output reg y); always @ (sel_a or sel_b or sel_c or a or b or c or d) begin if (sel_a) y = a; else if (!sel_b) y = b; else if (sel_c) y = c; else y = d; end // always endmodule

6.2.1 Synthesis of Priority Structures • A case statement implies priority • Only if all case items are mutually exclusive will a non-priority structure be synthesized.


module opcode (input wire [3:0] opcode, output reg add, sub, inv, div); always @ (opcode) begin add = 1’b0; sub = 1’b0; inv = 1’b0; div = 1’b0; // defaults casex (opcode) 4'b1xxx: add = 1’b1; 4’bx1xx: sub = 1’b1; 4’bxx1x: inv = 1’b1; 4’bxxx1: div = 1’b1; endcase end // always endmodule

6.2.1 Synthesis of Priority Structures


module mux_4pri_2 (input a, b, c, d, input [1:0] sel, output reg y); always @ (sel or a or b or c or d) begin

end endmodule

case (sel) 2'b00: y = a; 2'b01: y = b; 2'b10: y = c; default: y = d; endcase

or

if (sel == 2'b00) y = a; else if (sel == 2'b01) y = b; else if (sel == 2'b10) y = c; else y = d;

Exercise: Priority Encoder?

`default_nettype none module priority_or_not ( input wire A input wire [1:0] current_state, output reg [1:0] next_state );

always @(current_state or A) begin case(current_state) begin 2'b00: next_state = 2'b01; 2'b01: next_state = 2'b10; 2'b10: next_state = 2'b11; 2'b11: next_state = 2'b00; endcase end

endmodule 24 Chap 6a Copyright 2011 Greg Tumbush v1.2

Does the following code imply a priority encoder or not?

Resource Sharing Careful coding can cause the synthesis tool to share a resource.


module add (input wire data_a, data_b, data_c, data_d, sel, output wire [1:0] y_out ); wire [1:0] data_a_plus_data_b, data_d_plus_data_d; assign data_a_plus_data_b = data_a + data_b; assign data_c_plus_data_d = data_c + data_d; assign y_out = sel ? data_a_plus_data_b : data_c_plus_data_d; endmodule

Resource Sharing (cont.)


Use large resources like adders/multipliers like an ALU, i.e. mux the operands to the inputs of the resource

module add2 (input wire data_a, data_b, data_c, data_d sel, output wire [1:0] y_out); assign y_out = sel ? (data_a+ data_b) : (data_c + data_d); endmodule

Resource Sharing (cont.)


Same results for:

module add2 (input wire data_a, data_b, data_c, data_d, sel, output wire [1:0] y_out); reg [1:0] data_a_plus_data_b, data_c_plus_data_d; always @* data_c_plus_data_d = data_c + data_d; always @* data_a_plus_data_b = data_a + data_b; assign y_out = sel ? data_a_plus_data_b : data_c_plus_data_d; endmodule

module add2 (input wire data_a, data_b, data_c, data_d, sel, output reg [1:0] y_out); always @* begin if (sel) y_out = data_a + data_b; else y_out = data_c + data_d; end endmodule

Versus

2 adders

1 adder

Resource Sharing exercise


Redesign the following to use 1 multiplier. What is the size of out_multab, out_multac , and out?

`default_nettype none module resource_sharing (input wire multab, input wire [31:0] a, b, c, output wire [??:0] out); wire [??:0] out_multab = a*b; wire [??:0] out_multac = a*c; assign out = multab ? out_multab : out_multac; endmodule

Exploiting Don’t Cares


Assigment to x can reduce logic by exploiting don’t cares

module alu_with_z1 (input wire [3:0] data_a, data_b, input wire [2:0] opcode, output reg [3:0] alu_out); always @ (opcode or data_a or data_b) begin case (opcode) 3'b001: alu_out = data_a | data_b; 3'b010: alu_out = data_a ^ data_b; 3'b110: alu_out = ~data_b; default: alu_out = 4'bx; endcase end endmodule

data_a

data_b

opcode

decodeopcode

alu_out

Exploiting Don’t Cares (cont.)


module alu_without_z (input wire [3:0] data_a, data_b, input wire [2:0] opcode, output reg [3:0] alu_out); always @ (opcode or data_a or data_b) begin case (opcode) 3'b001: alu_out = data_a | data_b; 3'b010: alu_out = data_a ^ data_b; 3'b110: alu_out = ~data_b; default: alu_out = 4'b0; endcase end endmodule

data_a

data_b

opcode

decodeopcode

alu_out

4'b0

6.4 Synthesis of tri-state Devices and Bus Interfaces


In section 3.3 we saw how tri-state devices can be used to allow multiple masters to share a bus.

Master 2 out

... slavein

Master 1 out

Master n out

...

en_n

en_2

en_1

How is this decribed in verilog?

6.4 Synthesis of tri-state Devices and ...


assign data_bus = en_1 ? mstr1_out : 32’bz; assign data_bus = en_2 ? mstr2_out : 32’bz; ....... assign data_bus = en_n ? mstrn_out : 32’bz;

Master 2 out

... slavein

Master 1 out

Master n out

...

en_n

en_2

en_1

mstr1_out

mstr2_out

data_bus

mstrn_out

32

32

32

32

Mid-term Study Guide

• POS versus SOP

• Fill out K-Map given a function and convert to circuit

• Static 1/0 hazard

• FSM design (see lecture 2)

• Propagation delay, setup/hold

• Blocking versus non-blocking

• Verilog operators


chapter 6: synthesis of combinatorial and sequential logic 2016/ece4242/chap6a.pdf · 1. detect and...

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