chapter 6 multimulti--channel buffered serial port channel...

Chapter 6Chapter 6MultiMulti--channel Buffered Serial Port channel Buffered Serial Port

(McBSP)(McBSP)

ObjectivesObjectives

�� Definition of Terms: Definition of Terms: �� Bit, word or channel, frame and phase.Bit, word or channel, frame and phase.

�� Understand basic serial port operation.Understand basic serial port operation.

�� Understand clock generation.Understand clock generation.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 6, Slide 2

�� Pin polarity.Pin polarity.

�� Serial port interrupts.Serial port interrupts.

�� Describe multiDescribe multi--channel operation.channel operation.

�� Programming the serial port.Programming the serial port.

Basic Definitions: Basic Definitions: BitsBits, , WordsWords ??CLKCLK

b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b0

FSFS

a1a1 a0a0DataData

DataData


SP Ctrl (SPCR)SP Ctrl (SPCR)

Rcv Ctrl (RCR)Rcv Ctrl (RCR)

Xmt Ctrl (XCR)Xmt Ctrl (XCR)

Rate (SRGR)Rate (SRGR)

Pin Ctrl (PCR)Pin Ctrl (PCR)

Serial PortSerial Port

b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b0

WordWord

a1a1 a0a0

BitBit

DataData

�� ““ WordWord” or “” or “ channelchannel” contains #bits specified by” contains #bits specified byWDLEN1WDLEN1(8, 12, 16, 20, 24, 32).(8, 12, 16, 20, 24, 32).

RWDLEN1RWDLEN15577

XWDLEN1XWDLEN15577

�� ““ BitBit ” ” -- one data bit per SP clock period. one data bit per SP clock period.

Basic Definitions: Basic Definitions: FrameFrame??

w0w0 w1w1 w2w2 w3w3 w4w4 w5w5 w6w6 w7w7

FrameFrameWordWord

w6w6 w7w7DataData

FSFS








�� ““ FrameFrame” ” -- contains one or multiple wordscontains one or multiple words

�� FRLEN1FRLEN1specifies #words per frame (1specifies #words per frame (1--128)128)

RWDLEN1RWDLEN1

5577

XWDLEN1XWDLEN1

5577

RFRLEN1RFRLEN1

881414

XFRLEN1XFRLEN1

881414

WordWord

Basic Definitions Basic Definitions --PhasePhase

FSFS

Phase 1Phase 1 Phase 2Phase 2

AA BB332211DataData

FrameFrame

�� Note: dualNote: dual--phasephaseused in Audioused in AudioCodec97 (AC97) StdCodec97 (AC97) Std

�� Each PHASE can contain different #bits (Each PHASE can contain different #bits (WDLEN1WDLEN1// 22) and #words ) and #words �� Each FRAME can contain Each FRAME can contain only 1 or 2only 1 or 2PHASES (PHASES (PHASEPHASE).).








RFRLEN1RFRLEN1 RWDLEN1RWDLEN1

55881414 77

XFRLEN1XFRLEN1 XWDLEN1XWDLEN1

55881414

RFRLEN2RFRLEN2 RWDLEN2RWDLEN2

23232424 21213030


23232424 21213030

PHASEPHASE

3131

PHASEPHASE

3131 77


�� Each PHASE can contain different #bits (Each PHASE can contain different #bits (WDLEN1WDLEN1// 22) and #words ) and #words ((FRLEN1/2FRLEN1/2 ) .) .

Basic Definitions Basic Definitions -- PhasePhase

FSFS

AA BB332211


DataData

FrameFrame

88 1616

�� Each PHASE can contain different #bits (Each PHASE can contain different #bits (WDLEN1WDLEN1// 22) and #words ) and #words �� Each FRAME can contain 1 or 2 PHASES (Each FRAME can contain 1 or 2 PHASES (PHASEPHASE).).








RFRLEN2RFRLEN2PHASEPHASE RWDLEN2RWDLEN2 RFRLEN1RFRLEN1 RWDLEN1RWDLEN1558823232424 1414212130303131 77

XFRLEN2XFRLEN2PHASEPHASE XWDLEN2XWDLEN2 XFRLEN1XFRLEN1 XWDLEN1XWDLEN1558823232424 1414212130303131 77

�� From above example some of the bit fields of RCR and XCR can From above example some of the bit fields of RCR and XCR can be initialised as shown below.be initialised as shown below.

11

11

00010001

00010001

010010

010010

00100010

00100010

000000

000000

�� Each PHASE can contain different #bits (Each PHASE can contain different #bits (WDLEN1WDLEN1// 22) and #words ) and #words ((FRLEN1FRLEN1// 22) .) .


ExerciseExercise

FSFSAA11


DataData

FrameFrame

�� Fill in the control values for the example above.Fill in the control values for the example above.

1616 2020

22 33 44 55 BB CC


�� Fill in the control values for the example above.Fill in the control values for the example above.

RFRLEN2RFRLEN2PHASEPHASE RWDLEN2RWDLEN2 RFRLEN1RFRLEN1 RWDLEN1RWDLEN1558823232424 1414212130303131 77

XFRLEN2XFRLEN2PHASEPHASE XWDLEN2XWDLEN2 XFRLEN1XFRLEN1 XWDLEN1XWDLEN1558823232424 1414212130303131 77


Definitions Definitions -- ReviewReview

b1b1 b2b2

CLKCLK

Word 1Word 1

Phase 2Phase 2Phase 1Phase 1

FSFS


Word 2Word 2 Word 3Word 3


Frame 1Frame 1

Phase 2Phase 2Phase 1Phase 1







RFRLEN1RFRLEN1RWDLEN1RWDLEN1

55881414 77


55881414

RFRLEN2RFRLEN2RWDLEN2RWDLEN2

23232424 21213030


23232424 21213030

3131

3131 77

PHASEPHASE

PHASEPHASE


Frame 2Frame 2

McBSP Block Diagram (Read)McBSP Block Diagram (Read)

CPUCPU

PPeerriipphh

RINTRINT

RRBBRR

DDRRRR3232

DRDR RSRRSR


DMADMA

hheerraall

BBuuss

REVTREVT

CLKRCLKR

FSRFSR

McBSP Block Diagram (Write)McBSP Block Diagram (Write)

DXDXDDXX

CPUCPU

PPeerriipphh

RINTRINT

RRBBRR

DDRRRR3232

DRDR RSRRSR

XINTXINT

XSRXSR


DXDX XXRR

DMADMA

hheerraall

BBuuss

REVTREVT

CLKXCLKX

FSXFSX

CLKRCLKR

FSRFSR

XEVTXEVT

XSRXSR

McBSP Block Diagram (Configuration)McBSP Block Diagram (Configuration)

RBRRBRRSRRSR DRRDRR

XSRXSR DXRDXR

MultiMulti--Channel BufferedChannel BufferedSerial Port (McBSP)Serial Port (McBSP)

PPeerriipphh

DRDR

DXDX

CPUCPU


hh

BBuuss

CLKRCLKRCLKXCLKX

FSXFSXDMADMA

Peripheral BusPeripheral Bus

Serial PortSerial PortControl LogicControl Logic

SPCRSPCRRCRRCR

XCRXCR ??

??FSRFSR

Serial Port Serial Port -- Basic OperationBasic Operation

RBRRBRRSRRSR DRRDRR

XSRXSR DXRDXR


PPeerriipphh

DRDR

DXDX

CPUCPU


hh

BBuuss

CLKRCLKR

FSRFSR

CLKXCLKX

FSXFSXDMADMA

“RECEIVE”“RECEIVE”“TRANSMIT”“TRANSMIT”Peripheral BusPeripheral Bus


SPCRSPCRRCRRCR

XCRXCR PCRPCR

SRGRSRGR

McBSP Registers (1)McBSP Registers (1)RSRRSR Receive Shift RegReceive Shift Reg

RBRRBR Receive Buffer RegReceive Buffer Reg

DRRDRR Data Receive RegData Receive Reg

XSRXSR Transmit Shift RegTransmit Shift Reg

DXRDXR Data Transmit RegData Transmit Reg

ReceiveReceive

TransmitTransmit


SPCRSPCR Serial Port Control RegSerial Port Control Reg

RCRRCR Receive Control RegReceive Control Reg

XCRXCR Transmit Control RegTransmit Control RegControlControl

Configure CLK and FS as inputs or outputsConfigure CLK and FS as inputs or outputs


CLKRCLKR

CLKXCLKX

FSRFSR


SPCRSPCRRCRRCR SRGRSRGR


�� FSR, FSX, CLKR and CLKX can be configured FSR, FSX, CLKR and CLKX can be configured either as inputs or outputs, depending on the either as inputs or outputs, depending on the application.application.

FSXFSXSPCRSPCR

XCRXCR PCRPCR

Configure CLK and FS as inputs or outputsConfigure CLK and FS as inputs or outputs


CLKRCLKR

CLKXCLKX

FSRFSR




FSXFSXSPCRSPCR

XCRXCR PCRPCR

CLK/FS ModeCLK/FS Mode0: Input0: Input

1: Output1: Output







CLKRMCLKRMFSRMFSRM

1010

FSXMFSXM

1111

CLKXMCLKXM

8899

Generating CLK and FS as outputGenerating CLK and FS as output

‘C6000‘C6000

FSRFSRFSXFSX

CLKRCLKRCLKXCLKX








CLKRMCLKRMFSRMFSRM

1010

FSXMFSXM

1111

CLKXMCLKXM

8899

CLK/FS ModeCLK/FS Mode0: Input0: Input

1: Output1: Output

Generating the CLK as outputGenerating the CLK as output

‘C6000‘C6000

FSRFSRFSXFSX

CLKRCLKRCLKXCLKX

Sample Rate Generator (SRGR)Sample Rate Generator (SRGR)

CLKSMCLKSM

CLKOUT1CLKOUT1

CLKSCLKSCLKGDVCLKGDV

CLKGCLKG








CLKSMCLKSM

2929

CLKSMCLKSM

�� CLKGDVCLKGDV-- divide down (1divide down (1--255)255)�� CLKGCLKG= (input clock) / (1 + = (input clock) / (1 + CLKGDVCLKGDV))�� Max transfer rate = CLKG = 150 MHz/2 = 75 Mb/sMax transfer rate = CLKG = 150 MHz/2 = 75 Mb/s

�� CLKSMCLKSM -- selects clock src (selects clock src (CLKOUT1 CLKOUT1 oror CLKSCLKS))

CLKGDVCLKGDV

0077

Generating the FS as outputGenerating the FS as output

‘C6000‘C6000

FSRFSRFSXFSX

CLKRCLKRCLKXCLKX

Sample Rate Generator (SRGR)Sample Rate Generator (SRGR)

CLKSMCLKSM

CLKGDVCLKGDVCLKGCLKG

FPERFPER FSGFSGCLKOUT1CLKOUT1

CLKSCLKS








CLKSMCLKSM

CLKSMCLKSM

2929

CLKGDVCLKGDV

0077

FSGMFSGM

2828

FWIDFWID

881515

FPERFPER

2727 1616

�� FPER: FPER: frame sync period (12 bits)frame sync period (12 bits)

�� FWID:FWID: frame sync pulse width (8 bits)frame sync pulse width (8 bits)

�� FSGM: FSGM: 0 0 -- FS gen’d on every DXR XSR copyFS gen’d on every DXR XSR copy1 1 -- FS gen’d by FSGFS gen’d by FSG

��






ReceiveReceive

TransmitTransmit




XCRXCR Transmit Control RegTransmit Control Reg

SRGRSRGR Sample Rate GeneratorSample Rate Generator

ControlControl

Configure CLK and FS pin polarityConfigure CLK and FS pin polarity


CLKRCLKR

CLKXCLKX

FSRFSR




FSXFSXSPCRSPCR

XCRXCR PCRPCR

CLK/FS PolarityCLK/FS Polarity0: Falling edge0: Falling edge

1: Rising Edge1: Rising EdgeSP Ctrl (SPCR)SP Ctrl (SPCR)






CLKRPCLKRPFSRPFSRP

22

FSXPFSXP

33

CLKXPCLKXP

0011







�� Serial port status and interrupts.Serial port status and interrupts.



RRDY/XRDY Status and InterruptsRRDY/XRDY Status and Interrupts

CPUCPU

RINTRINTXINTXINT

EDMAEDMA

SyncSync

�� RRDY/XRDY displays the RRDY/XRDY displays the “status” of the read and “status” of the read and transmit ports:transmit ports:

�� 0: not ready.0: not ready.

�� 1: ready to read/write.1: ready to read/write.

RBRRBR DRRDRR

XSRXSR DXRDXR

RRDYRRDY=1=1

XRDYXRDY=1=1

“Ready to Read”“Ready to Read”

�� There are 3 methods for There are 3 methods for detecting if data is ready:detecting if data is ready:

�� Poll Poll SPCRSPCRbits via s/w.bits via s/w.


SyncSyncXRDYXRDY=1=1

“Ready to Write”“Ready to Write”

SP Ctrl (SP Ctrl (SPCRSPCR))






RRDYRRDY

11

XRDYXRDY

1717

�� Poll Poll SPCRSPCRbits via s/w.bits via s/w.

�� Config CPU ints Config CPU ints (RINT/XINT).(RINT/XINT).

�� Program DMA sync events.Program DMA sync events.

Other sources of Interrupts (R/XINT)Other sources of Interrupts (R/XINT)

CPUCPURINTRINT

RRDY RRDY ((RINTM=00bRINTM=00b ))End of Block (RCV) End of Block (RCV) ((RINTM=01RINTM=01 ))New FSR (frame begin)New FSR (frame begin) ((RINTM=10bRINTM=10b ))Receive Sync ErrorReceive Sync Error ((RINTM=11bRINTM=11b ))

XRDY XRDY ((XINTM=00bXINTM=00b ))

“Trigger Event”“Trigger Event”


XINTXINT

XRDY XRDY ((XINTM=00bXINTM=00b ))End of Block (XMT) End of Block (XMT) ((XINTM=01bXINTM=01b ))New FSX (frame begin) New FSX (frame begin) ((XINTM=10bXINTM=10b ))Transmit Sync Error Transmit Sync Error ((XINTM=11bXINTM=11b ))







RRDYRRDY

11

XRDYXRDY

1717

XINTMXINTM

20202121

RINTMRINTM

4455


�� Definition of Terms:Definition of Terms:�� Bit, word or channel, frame and phase.Bit, word or channel, frame and phase.









MultiMulti--Channel operationChannel operation

Ch0Ch0 Ch1Ch1 Ch31Ch31 Ch0Ch0 Ch1Ch1 Ch31Ch31DR/XDR/X

FSR/XFSR/X

. . .. . . . . .. . .


How do you enable/disable each channel?How do you enable/disable each channel?

MultiMulti--Channel operationChannel operation

Ch0Ch0 Ch1Ch1 Ch31Ch31 Ch0Ch0 Ch1Ch1 Ch31Ch31DR/XDR/X

FSR/XFSR/X

. . .. . . . . .. . .

�� You can You can enableenableor or disabledisableany channel.any channel.


�� You can You can enableenableor or disabledisableany channel.any channel.

Master (MCR)Master (MCR)

Rcv En (RCER)Rcv En (RCER)

Xmt En (XCER)Xmt En (XCER)

MultiMulti--ChannelChannel

RCER/XCER Enable BitsRCER/XCER Enable BitsEnableEnable [1][1]DisableDisable [0][0]

003131

003131

RCERRCER

XCERXCER

00111111……00

MemoryMemory

44 33 22 11Frame 3Frame 3

MultiMulti--channel examplechannel example

11

11Frame 1Frame 1

44 33 22

33

1144 33 22Frame 2Frame 2

FFrraammeerr


1133

......

331133

�� Allows multiple channels (words) to Allows multiple channels (words) to be be independentlyindependentlyselected for selected for transmit and receive.transmit and receive.

MMccBBSSPP

MemoryMemory


11

11Frame 1Frame 1

44 33 22

11


FFrraammeerr

MultiMulti--channel and EDMA combination used channel and EDMA combination used for channel sortingfor channel sorting


�� EDMA’s can sort each channel EDMA’s can sort each channel into separate buffers!into separate buffers!

3333

......

1111

33

MMccBBSSPP

EEDDMMAA

MemoryMemory


11

11Frame 1Frame 1

44 33 22

11


FFrraammeerr

EDMA Channel SortingEDMA Channel Sorting


3333

......

1111

33

MMccBBSSPP

EEDDMMAA

�� EDMA’s flexible (indexed) addressing allows EDMA’s flexible (indexed) addressing allows it to sort each channel into separate buffers!it to sort each channel into separate buffers!

�� How do you select channels? ...How do you select channels? ...

Enable/Disable ChannelsEnable/Disable Channels

�� RCER / XCER registers allow you to enable or RCER / XCER registers allow you to enable or disable only 32disable only 32--channels.channels.

�� So how does the C6000 supports 128 channels?So how does the C6000 supports 128 channels?






003131

003131

RCERRCER

XCERXCER

00110011……

128 Channels!128 Channels!00--1515 1616--3131 3232--4747 4848--6363 6464--7979 8080--9595 9696--111111 112112--127127ChannelsChannels

AA BB

To be able to support 128 channels the following applies:To be able to support 128 channels the following applies:�� Channels are broken into Channels are broken into BLOCKBLOCK’s (16 contiguous channels).’s (16 contiguous channels).

�� Up to 32 channels (2 Up to 32 channels (2 BLOCKBLOCK’s) can be enabled at any one time.’s) can be enabled at any one time.

Channels are enabled via _CER registers and _BLK bits in MCR.Channels are enabled via _CER registers and _BLK bits in MCR.

InterruptInterrupt


�� Channels are enabled via _CER registers and _BLK bits in MCR.Channels are enabled via _CER registers and _BLK bits in MCR.

�� After 16 channels, McBSP issues After 16 channels, McBSP issues END_OF_BLOCKEND_OF_BLOCKinterrupt.interrupt.

�� CPU ISR reCPU ISR re--programs RCER (or XCER) for channels 32programs RCER (or XCER) for channels 32--47 and so 47 and so on.on.





003131

003131

RCERRCER

XCERXCER

AA1515--00BB1515--00

AA1515--00BB1515--00

15151616

15151616







ReceiveReceive

TransmitTransmit




XCRXCR Transmit Control RegTransmit Control Reg

SRGRSRGR Sample Rate GeneratorSample Rate Generator

PCRPCR Pin Control RegPin Control Reg

ControlControl

MCRMCR MultiMulti--Channel Ctrl RegChannel Ctrl Reg

RCERRCER Rcv Channel Enable RegRcv Channel Enable Reg

XCERXCER Xmit Channel Enable RegXmit Channel Enable Reg


�� Definition of Terms:Definition of Terms:�� Bit, word or channel, frame and phase.Bit, word or channel, frame and phase.









Programming the Serial PortProgramming the Serial Port

�� There are three methods available for There are three methods available for programming the serial port:programming the serial port:1.1.Writing directly to the serial port registers.Writing directly to the serial port registers.2.2.Using the Chip Support Library (CSL).Using the Chip Support Library (CSL).3.3.Graphically using the DSP/BIOS GUI Graphically using the DSP/BIOS GUI

configuration tool.configuration tool.


3.3.Graphically using the DSP/BIOS GUI Graphically using the DSP/BIOS GUI configuration tool.configuration tool.

Programming the Serial Port Programming the Serial Port -- DirectDirect

(A)(A) Writing directly to the serial port Writing directly to the serial port registers:registers:�� Although this method is straight forward, it relies Although this method is straight forward, it relies

on a good understanding of the serial port on a good understanding of the serial port functionality.functionality.

�� This method can be tedious and is prone to errors.This method can be tedious and is prone to errors.


#include <c6211dsk.h>#include <c6211dsk.h>

void mcbsp0_init(){

*(unsigned volatile int *)McBSP0_SPCR = 0; *(unsigned volatile int *)McBSP0_PCR = 0; *(unsigned volatile int *)McBSP0_RCR = 0x10040;*(unsigned volatile int *)McBSP0_XCR = 0x10040;*(unsigned volatile int *)McBSP0_DXR = 0;*(unsigned volatile int *)McBSP0_SPCR = 0x12001;

}

Programming the Serial Port Programming the Serial Port -- CSL (1/4)CSL (1/4)

(B)(B) Using the Chip Support Library:Using the Chip Support Library:�� The CSL provides a C language interface The CSL provides a C language interface

for configuring and controlling the onfor configuring and controlling the on--chip chip peripherals, in this case the Serial Ports.peripherals, in this case the Serial Ports.

�� The library is modular with each module The library is modular with each module corresponding to a specific peripheral. corresponding to a specific peripheral.


corresponding to a specific peripheral. corresponding to a specific peripheral. This has the advantage of reducing the This has the advantage of reducing the code size.code size.

�� Some modules rely on other modules also Some modules rely on other modules also being included, for example the IRQ being included, for example the IRQ module is required when using the EDMA module is required when using the EDMA module.module.

�� CSL programming procedure:CSL programming procedure:(1)(1) Create handles for the serial ports:Create handles for the serial ports:

(2)(2) Open the serial port:Open the serial port:


MCBSP_Handle hMcbsp;


(2)(2) Open the serial port:Open the serial port:

hMcbsp = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);

�� CSL programming procedure:CSL programming procedure:(3)(3) Create a configuration structure for serial Create a configuration structure for serial

port:port:�� \\LinksLinks\\McBSP_Config_Struct.pdfMcBSP_Config_Struct.pdf




�� CSL programming procedure (cont):CSL programming procedure (cont):(4)(4) Configure the serial port:Configure the serial port:

(5)(5) Close the Serial Port after use:Close the Serial Port after use:

MCBSP_config(hMcbsp,&ConfigLoopback);


(5)(5) Close the Serial Port after use:Close the Serial Port after use:

MCBSP_close(hMcbsp);


Practical example on DSP Code 6711Practical example on DSP Code 6711�� Project name: Project name: mcbsp_dynamiccfg.pjtmcbsp_dynamiccfg.pjt

�� Location: Location: \\CodeCode\\Chapter 06 Chapter 06 -- McBSPMcBSP\\Dynamic_CSL_ConfigDynamic_CSL_Config\\


Programming the Serial Port using the Programming the Serial Port using the DSP/BIOS GUIDSP/BIOS GUI

(C)(C) DSP/BIOS GUI Interface:DSP/BIOS GUI Interface:�� With this method the configuration structure With this method the configuration structure

is created graphically and the setup code is is created graphically and the setup code is generated automatically.generated automatically.


�� Procedure:Procedure:(1)(1) Create a configuration using the Create a configuration using the

MCBSP Configuration manager (eg. MCBSP Configuration manager (eg. mcbspCfg0).mcbspCfg0).




�� Procedure:Procedure:(2)(2) Right click on mcbspCfg0 and select Right click on mcbspCfg0 and select

“Properties”, see figures below, and then “Properties”, see figures below, and then select “Advanced” and fill all parameters select “Advanced” and fill all parameters as shown below:as shown below:



�� Procedure:Procedure:(3)(3) Select the serial port you would like to use Select the serial port you would like to use

from the MCBSP Resource manager (eg. from the MCBSP Resource manager (eg. Mcbsp_Port1).Mcbsp_Port1).

Right click and select properties.Right click and select properties.Select the mcbspCfg0 configuration just created. Select the mcbspCfg0 configuration just created.


Select the mcbspCfg0 configuration just created. Select the mcbspCfg0 configuration just created.


�� Procedure:Procedure:(4)(4) A file is then generated that contains the A file is then generated that contains the

configuration code. The file generated for configuration code. The file generated for this example is shown on the next slide.this example is shown on the next slide.



/* Do *not* directly modify this file. It was *//* generated by the Configuration Tool; any *//* changes risk being overwritten. */

/* INPUT mcbsp1.cdb */

/* Include Header File */#include "mcbsp1cfg.h"

/* Config Structures */MCBSP_Config mcbspCfg0 = {

0x00008000, /* Serial Port Control Reg. (SPCR) */0x000000A0, /* Receiver Control Reg. (RCR) */0x000000A0, /* Transmitter Control Reg. (XCR) */0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */


0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */0x00000000, /* Multichannel Control Reg. (MCR) */0x00000000, /* Receiver Channel Enable(RCER) */0x00000000, /* Transmitter Channel Enable(XCER) */0x00000A00 /* Pin Control Reg. (PCR) */

};

/* Handles */MCBSP_Handle hMcbsp1;

/** ======== CSL_cfgInit() ======== */void CSL_cfgInit(){

hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);MCBSP_config(hMcbsp1, &mcbspCfg0);

}


Few remarks:Few remarks:

(1) Notice that values in the code generated are the (1) Notice that values in the code generated are the same as the values inserted using the GUI interface.same as the values inserted using the GUI interface.


/* Do *not* directly modify this file. It was *//* Config Structures */MCBSP_Config mcbspCfg0 = {

0x00008000, /* Serial Port Control Reg. (SPCR) */0x000000A0, /* Receiver Control Reg. (RCR) */0x000000A0, /* Transmitter Control Reg. (XCR) */0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */0x00000000, /* Multichannel Control Reg. (MCR) */0x00000000, /* Receiver Channel Enable(RCER) */0x00000000, /* Transmitter Channel Enable(XCER) */0x00000A00 /* Pin Control Reg. (PCR) */

};


Few remarks:Few remarks:

(2) Do not forget to close the serial port after use.(2) Do not forget to close the serial port after use.

(3) To visualise the output (3) To visualise the output of the logprintf () of the logprintf () function make sure function make sure that the that the Message Log Message Log


that the that the Message Log Message Log window is open window is open (DSP/BIOS > Message (DSP/BIOS > Message Log).Log).

Programming the Serial Port Programming the Serial Port -- CSL (4/4)CSL (4/4)Practical examplePractical example

�� Project name: Project name: mcbsp_staticcfg.pjtmcbsp_staticcfg.pjt

�� Location: Location: \\CodeCode\\Chapter 06 Chapter 06 -- McBSPMcBSP\\Static_CSL_ConfigStatic_CSL_Config\\

�� Extra Topic: Extra Topic: Digital LoopbackDigital Loopback


Chapter 6Chapter 6MultiMulti--channel Buffered Serial Port channel Buffered Serial Port

(McBSP)(McBSP)-- End End --

Digital Loopback (DLB)Digital Loopback (DLB)

DRDRCLKRCLKRFSRFSR

FSXFSXCLKXCLKXDXDX

RCVRCV

XMTXMT

McBSPMcBSP


�� Allows testing of the Serial Port code without the need Allows testing of the Serial Port code without the need of an external device.of an external device.

�� Digital Loopback internally connects the rcv/xmt ports Digital Loopback internally connects the rcv/xmt ports together as shown.together as shown.

�� No hardware (pin connections) necessary.No hardware (pin connections) necessary.

�� Interrupts are generated as normal (as programmed).Interrupts are generated as normal (as programmed).

Digital Loopback (DLB)Digital Loopback (DLB)

�� You can set the digital loop back by setting a You can set the digital loop back by setting a bit in the SPCR or graphically using the GUI bit in the SPCR or graphically using the GUI interface as shown:interface as shown:


SPCRSPCR003131 1515

DLBDLB

chapter 6 multimulti--channel buffered serial port channel...

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