chapter 6: implementation of arm based sensor

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CHAPTER 6: IMPLEMENTATION OF ARM BASED SENSOR NODES

6.1 INTRODUCTION

In this chapter, the design of sensor node [76] using ARM processor is discussed.

Sensor node design is an important concern in WSN’s employment. Now a day’s

WSN are used in tiny [77], secure and high end embedded applications. Capability

of WSN to attain data sensing and distributed data processing has led to

applications of measuring and tracking. The properties of embedded sensor

devices (motes) [76] determine the strength of WSN. The most important idea of

this work is to optimize the power [88] [93]and service of sensor nodes, by

evaluating the processing unit and transceiver unit of sensor nodes [77 ]. The

proposed sensor node is developed using LPC 2148 [95], LPC 2378 [96] and

AT91SAM9263 [97] ARM processors as processing unit and CC2500, CC2530

radio as communication unit. The performance analysis and comparison of design

parameters of proposed motes with existing motes is done.

6.2 FEATURES OF ARM IN WSN

ARM [98] is RISC architecture. ARM instructions are 32-bit long and most of them

have a regular three-operand encoding. ARM architecture features a large register

file with 16 general-purpose registers. All of the above features facilitate RISC

pipelining of the ARM architecture.

However, the desire to keep the architecture and its implementation as simple as

possible has prompted several design decisions that deviated from the original RISC

architecture. The classical RISC approach requires the execution stage of any

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instruction to complete in one cycle. This is essential for building an efficient 3-stage

fetch-decode-execute pipeline. While most ARM [98] processors support one

instruction per cycle, data transfer instructions are one important exception.

Completing a simple store or load instruction in one cycle would require performing

two memory accesses in a single cycle: one to fetch the next instruction from

memory, and the other to perform the actual data transfer. Performing two memory

accesses in one cycle would, in its turn, requires Harvard architecture with separate

program and data memory, which was considered too expensive by the designers of

the first ARM processor. However, in order to achieve better utilization of the

pipeline during 2-cycle instruction executions, they introduced an auto-indexing

addressing mode, where the value of an index register is incremented or decremented

while a load or store is in progress. While all modern ARM implementations have

separate instruction and data caches and can complete a memory transfer in one

cycle, they still support the auto-indexing mode that proved to improve performance

and code size of ARM programs.

ARM [98] supports multiple-register-transfer instructions that allow loading or

storing up to 16 registers at once. While violating the one cycle per instruction

principle, they significantly speed up performance-critical operations, such as

procedure invocation and bulk data transfers, and lead to more compact code.

In summary, the ARM architecture [98] offers all the benefits of the RISC approach,

such as pipeline-friendliness and simplicity, while deviating from it in a few aspects,

which makes it even more appealing to embedded systems developers.

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Figure 6.1 Architecture of ARM 7

The ARM provides 16 general purpose registers in the user mode. Register 15 is the

program counter, but can be manipulated as a general purpose register. The general-

purpose register number 14 has is used as a link register by the branch-and-link

instruction. Register 13 is typically used as stack pointer. The architecture of ARM 7

is shown in Figure 6.1

The current program status register (CPSR) contains four 1-bit condition flags

(‘Negative’, ‘Zero’, ‘Carry’, and ‘Overflow’) and four fields reflecting the execution

state of the processor. The ‘T’ field is used to switch between ARM and Thumb

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instruction sets. The ‘I’ and ‘F’ flags enables normal and fast interrupts respectively.

Finally, the ‘mode’ field selects one of seven execution modes [98]:

User mode is the main execution mode. By running application software in

user mode, the operating system can achieve protection and isolation. All

other execution modes are privileged and are therefore only used to run

system software.

The fast interrupts processing mode is entered whenever the processor

receives an interrupt signal from the designated fast interrupt source.

Normal interrupts processing mode is entered whenever the processor

receives an interrupt signal from any other interrupt source.

The software interrupts mode is entered when the processor encounters

software interrupt instruction. Software interrupts are a standard way to

invoke operating system services on an ARM.

Undefined instruction mode is entered when the processor attempts to

execute an instruction that is supported neither by the main integer core nor

by one of the coprocessors. This mode can be used to implement coprocessor

emulation.

System mode is used for running privileged operating system tasks.

Abort mode is entered in response to memory faults.

In addition to user-visible registers, ARM provides several registers available in

privileged modes only (shaded registers). SPSR registers are used to store a copy of

the value of the CPSR register before an exception was raised. Those privileged

modes that are activated in response to exceptions have their own R13 and R14

registers, which allows avoiding saving the corresponding user registers on every

exception. In order to further reduce the amount of state that has to be saved during

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handling of fast interrupts, ARM provides 5 additional registers available in the fast

interrupt processing mode only.

Figure 6.2 Registers in ARM7

ARM Core Instruction Set [98]

The ARM architecture has a normal 32 bit ARM7 instruction set and compressed 16

bit instruction set called “Thumb”. ARM7 instructions have a complex behavior.

ARM Data Types [98]

ARM processor can support following data types:

8 bit signed and unsigned bytes;

16 bit signed and unsigned half-words;

32 bit signed and unsigned words

But shorter than 32 bit data types are supported only by data transfer functions but

when internally processed they are extended to 32 bit size. ARM7 core doesn't

support floating point data types they can only be interpreted by software.

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ARM Memory Organization [98]

ARM is capable to store words in two ways depending on which significant byte is

stored. If word MSB is stored at highest byte then the operation is called “little-

endian” and if MSB is stored at lowest position, then it is called “big-endian”.

Usually it is easier to work with little-endian for people as they expect to be LSB at

lowest position.

Pipeline [98]

The first pipeline stage reads an instruction from memory and increments the value

of the instruction address register, which stores the value of the next instruction to be

fetched. This value is also stored in the PC register. The next stage decodes the

instruction and prepares control signals required to execute it on. The third stage

does all the actual work like it reads operands from the register file, performs ALU

operations, reads or writes memory, if necessary, and finally writes back modified

register values. In case the instruction being executed is a data processing instruction,

the result generated by the ALU is written directly to the register file and the

execution stage completes in one cycle. If it is a load or store instruction, the memory

address computed by the ALU is placed on the address bus and the actual memory

access is performed during the second cycle of the execute stage.

Co-processors [98]

The ARM architecture supports a general mechanism for extending the instruction

set through the addition of coprocessors. For example, the ARM floating point unit is

implemented as a coprocessor. Another example of a coprocessor is the system

control coprocessor that manages MMU, caches, TLB, and the write buffer.

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6.3 DESIGN OF SENSING UNIT, PROCESSING UNIT AND

COMMUNICATION UNIT

Sensor nodes are equipped with sensing unit, processing unit, communication unit

and power management unit [78]. Each and every node is capable to perform data

gathering, sensing, processing and communicating with other nodes. The sensing unit

which senses the environment, the processing unit which computes the confined

permutations of the sensed data, and the communication unit performs exchange of

processed information [79] among neighbour sensor nodes. The processor executes

different tasks and controls the functionality of other components. The required

services from processing unit are pre-programmed and loaded into the processor of

sensor nodes. The energy utilization rate [88] of the processor varies depending upon

the nodes. The performance variation of the processor is identified from evaluating

factors like processing speed, data rate, memory and peripherals supported by

processors [80]. Mostly ATMEGA 128L, MSP 430 controllers are used in

commercial motes [80]. The computations [81] are performed in the processing unit

and the acquired result is transmitted to the base station through the communication

unit.

In communication unit, a common transceiver act as a communication unit [80] and

it is mainly used to transmit and receive the information among the nodes and to the

base station and vice versa. It is used to facilitate the different sensor nodes to

communicate with each other and with base station. Radio frequency (RF) is mainly

used for node-to-node communication since it does not require any line of sight

(LOS). There are four states in the communication system: transmit, receive, idle and

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sleep. CC2500 transceiver unit is the most suitable unit for sensor node. It is based

on 0.18 µm CMOS technology. It is designed for low power wireless applications [ ]

because of its small size, low cost, higher frequency (2400-2483.5 MHz), low current

consumption (13.3 mA in receiver, 250 kbps & input 30 dB above sensitivity limit),

and 500 kbps data rate. It is also called as true single chip 2.4 GHz transceiver and it

is intended for the short range device (SRD) and industrial, scientific and medical

(ISM) frequency band. CC2500 provides better hardware [80] support for packet

handling, data buffering, clear channel assessment. It provides good flexible support

for address checking, synchronous word detection and automatic CRC handling in

packet oriented systems.

WSN architecture fall into either distributed approach or hierarchical approach.

Based on the application WSN architecture is selected .The entire strength and

efficiency of WSN depends on the type of architecture selected and types of sensor

nodes used. In this work, the design of sensor node is developed with ARM series

LPC 2148, LPC 2378 and AT91SAM9263. Sensor node with LPC 2148 is acting as

processing nodes, node with LPC 2348 is acting as a high end processing node or a

cluster head node and node with AT91SAM9263 is acting as a smart sink node.

In WSN, sensor node should be effectively designed and developed. In the initial

stage the selection of sensors processor like LPC2148, LPC2378 &

AT91SAM9263 and transceiver devices like (Xbee / CC2500 / CC2530) [80] [81]

are chosen depending upon the application. In this work LPC 2378 motes with

CC2500 radio transceivers are used with 500 K-band data rate, transmission power

is 30 dB and receiver sensitivity is 108 dB at 2.4 kilo baud. CC2500 [82] operates

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at 2.4 GHz with higher flexibility and greater data rate than other radios.

The CC2500 is most significant energy saving radio transceiver compared with

other radio. After the device selection, they should be analyzed and tested in the

effective design of WSN. To form a WSN, N number of sensor nodes can be

developed. If similar types of sensor nodes are used, then homogeneous network

[83] will be formed. If they are different in nature, heterogeneous network [83] will

be formed. Software programs based on requirements should be loaded in each

sensor node processor for its functions. Sensing unit collects [84] the sensing

information and processing unit processes it. This same procedure is followed for

every sensor node. Cluster head gathers information and it is transmitted to the base

station.

6.3.1 LPC 2148: Low End Sensor Node

LPC 2148 [95] is supported by a large number of real time operating systems like

VX works, Win CE, µCOS II, etc. LPC2148 motes operate at 60 MHz frequency and

have 8 KB-40 KB on-chip SRAM and 32 KB-512 KB RAM chip flash memory. It

also provides 8 KB on-chip RAM accessibility to USB by DMA. Two on-board 10

bit ADC is available at the rate conversion time as low as 2.44 µs per channel. For

serial interface with LPC 2148 [95], external peripherals like two UARTs, two fast

I2C bus (400 KB per second), one SPI and SSI are used. There are two power saving

modes included in this processing unit called idle and power down mode. These

processing units are waking up from power down mode via external interrupt. It also

includes single on board 10bit DAC along with two 32 bit timers/counters for data

processing. The processor LPC 2148 is a pre-programmed device. The WSN

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designer preloads the required functionalities into the sensor node through

application programs. The processor processes the acquired result from the ADC. For

ensuring security this processed data from the motes may be protected from

eavesdropper by crypto algorithm and key which preloaded into the processor. Each

processor consists of both RAM and FLASH memory. FLASH memory is used to

store the sensed data and other data used for computation. FLASH memory is used to

store the application program and system program to process the code in the sensor

node.

6.3.2 LPC 2378: High End Sensor Node

LPC 2378 [96] operates at a high frequency of 72 MHz and it has 8 KB-40 KB on-

chip SRAM on ARM local bus for high performance data access. Within that 16KB

SRAM for Ethernet interface and 32KB-512KB RAM chip flash memory is present.

One on-board 10 bit ADC is available and for serial interface from LPC 2148 to

external peripherals four UARTs, three fast I2C bus (400KB / S), one SPI and two

SSP are available. For serial communication, three independent oscillators are used

which are main oscillator, internal RC oscillator, & RTC oscillator. Ethernet MAC

with associated DMA controller and CAN controllers with 2 channels are used with

2 AHB buses. There are two power saving modes included in this processing unit

called idle and power down mode. These processing units are waking up from power

down mode via external interrupt. It also includes single 10 bit DAC, four 32 bit

timers/counters for data processing.

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6.3.3 AT91SAM 9263: Cluster Head

AT91SAM 9263 [97] used as cluster head operates at 220 MIPS at 200 MHz. It has

a 80 KB of internal SRAM, external memory and it has minimum of 100000

write/erase cycles and 10 years of data retention. It has a shutdown controller and

shut down power management controller which includes backup, slow clock, idle,

suspends & active mode. For serial interface, it has three UARTs, two SPI

controllers, one I2C-bus controllers, two SSC controller, two MCI, five 32 bit

parallel input/output controllers, two independent external memory buses, USB 2.0,

full-speed host double port and device port 12 Mbps. For timer it has one three

channel 16 bit timer / counters, and two RTT and for interrupt, it has advanced

interrupt controller.

The major features of LPC 2148, LPC 2378 and AT91SAM9263 are incorporated

in the WSN design [84], to reduce the computational overhead of existing L and H

sensor node. In many applications [85], sensor node met with a lot of computational

overhead. For example in KMS [84], each node will store and manipulate ‘n’

number of ‘m’ size keys and it consumes a lot of power and time. Normal

processor like ATMEGA128L and MSP 430 will have high computational rate

compared to ARM and as a result it will reduce the overall system performance and

efficiency. Hence the proposed motes using ARM are deployed in smart

applications [86] and it will reduce the computational rates. The general scenario

for WSN development [87] and single sensor node development process is

explained in Figure 6.3 and Figure 6.4 respectively. Table 6.1 shows the comparison

details about LPC 2148, LPC 2378 & AT 01SAM 9263 in terms of processor, frequency,

141

memory and peripherals supports.

Figure 6.3 WSN Development

Figure 6.4 Sensor Node Development Process

141




141




142

Table 6.1: Comparison of LPC 2148, LPC 2378 & AT 01SAM9263 [95] [96] [97]

Parameters LPC 2148 LPC 2378 AT91SAM9263

Processor16 bit / 32-bitARM7TDMI-S

16 bit / 32-bitARM7TDMI-S

32bit -ARM926EJ-Sprocessor

OperatingFrequency

Enables High Speed60Mhz Operation

Enables High Speed74Mhz Operation

Enables High Speed220MIPS at 200Mhz

Flash512KB used for both code and data storage

512KB Flash used forboth code and data storage

External memory (NOR, NAND, SDRAM)

Write/EraseCycles

Minimum of 100000write/erase cycles and 20 years of dataretention.



Static RAM

32 KB of Static RAM 32 kB of Static RAM

One - 80KB of InternalSRAM8 KB SRAM for USB

16 kB SRAM blockserving as a buffer for theEthernet controller8 kB SRAM associated with the USBdevice

Power Saving ModeIdle, Power Down

Idle, Sleep & PowerDown

Shutdown controller –shutdown Power management Controller– Backup, Slow clock, Idle, Suspend &Active Mode

ADC

Two 8 channels ADC10-bit successive approximation analog todigital converter.

One 8 Channel ADC10-bit successive approximation analog todigital converter.

External ADC

DAC One 10 bit DAC One 10 bit DAC External DAC

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SerialInterface

Two UARTs Four UARTs Three UARTsOne SPI controller One SPI controller Two SPI controller

Two I2C-bus controllers2Three I C-buscontrollers

One I2C-bus controllers

One SSP controllerTwo SSP controllers withFIFO & Multiprotocol capabilities

Two SSC controller, TwoMCI, five 32bit Parallel input/outputcontrollers

Two AHB buses Two independent externalmemory buses

USB 2.0 Full-speedCompliant device controller with 8 KB ofon-chip RAM access to USB by DMA.

USB 2.0 full-speed device with on-chipPHY and associated DMA controller.

USB 2.0 Full-speed Host double port,device port – 12Mbps.

Interrupt9 edge sensitive ExternalInterrupt

50 edge sensitiveinterrupt inputs

Advanced InterruptController

Timers/Counters

Two 32 bitTimers/Counters

Four 32 bitTimers/Counters

One three channel 16 bitTimer / counters, Two RTT

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The experimental setup using LPC 2148, LPC 2378 and AT91SAM 9263 node with

X bee based wireless interface card are shown in Figure 6.5 and the sample result is

shown in Figure 6.6.

Figure 6.5 Experimental Set-up Using LPC 2148, LPC 2378and AT91SAM 9263

Figure 6.6 Sample Results

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6.4 PSEUDO CODE FOR SENSOR NODE COMMUNICATION

Using embedded C, the code for pair wise key establishment [34] and data

communication [89] between low end node to low end node, low end node to high

end node, high end node to cluster head and cluster head to the base station are

developed [90] and loaded into each sensor node. In the following section the pseudo

code for node to node communications are discussed.

Assume LPC 2148/LPC 2378 as sensor node, AT 91 SAM 9263 as cluster head

6.4.1 Node to Node Communication [87] [89] [92] [93] [94]

Start

HAL layer, UART port, Zigbee stack are initialized

Predefined Lower triangular matrix is initialized.

Event_ process ( ) function is called and it starts to monitor for any event.

Under an AE_ data request by node2, which has same group and cluster id, periodicmessage function is triggered.

An initial check of the authentication token is carried out if void, then keygenfunction is triggered

A Row of the lower triangular matrix from node1 is transmitted to node2.

The row received at node2 is multiplied with its own row of the lower triangularmatrix in it.

A key is generated in this process.

Node2 appends the key with its row of L matrix and transmits to node1.

Node1 multiplies the received row and its row, thus a key is generated.

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If the key generated at mode1 and node2 are one and the same on an authenticationtoken is sent to node2.

Authentication token confirms the key and also defines the presence of that nodeunder network.

Message communication between node1 and node2 is established under theencryption done by the key generated.

End

6.4.2 Node to Node Communication: Low End Node to High End Node [87] [89]

[92] [93] [94]

Start

LPC2148, HAL layer, UART port, Zigbee stack are initialized.

Predefined, the Lower triangular matrix is initialized.


Under an AF_ data request by node2 (LPC 2378), which has same group and clusterid, periodic message function is triggered.

An initial check of the authentication token is carried out if void, then keygenfunction is triggered.

A row of the lower triangular matrix from LPC 2148 is transmitted to LPC 2378

The row received at LPC2378 is multiplied with its own column of the triangularmatrix in it.

A key is generated.

LPC 2148 multiplies the received row and its column, thus a key is generated.

If the key generated at LPC 2378 and LPC 2148 are one and the same andauthentication token is sent to LPC 2378.


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Message communication between LPC 2378 and LPC 2148 is established under theencryption done by the key is generated.

End.

6.4.3 Node to Node Communication Low end Node to Low End Node [87] [89]

[92] [93] [94]

Start

LPC 2148, HAL layer, UART port, Zigbee stack are initialized.

Predefined, the Lower triangular matrix is initialized.


Under an AF_ data request by LPC 2148, which has same group and cluster id,periodic message function is triggered.


A row of the lower triangular matrix from LPC 2148 is transmitted to LPC 2148.


A key is generated.

LPC 2148, appends the key with its row of L matrix and transmits to LPC 2148

LPC 2148 multiplies the received row and its column, thus a key is generated.

If the key generated at LPC 2148 and LPC 2378 are one and the same andauthentication token is sent to LPC 2148.


Message communication between LPC 2148 and LPC 2378 is established under theencryption done by the key is generated.

End.

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6.4.4 Node to Node Communication Low end Node to Cluster Head [87] [89]

[92] [93] [94]

Start

AT 91SAM 9263, HAL layer, UART port, Zigbee stack are initialized,

Predefined, L matrix is initialized

AT 91SAM 9263, waits for its node under same cluster Id to get initialized.


Under an AF_ data request by LPC 2148, which has same group and cluster id,periodic message function is triggered.


A row of the lower triangular matrix from AT 91 SAM 9263 is transmitted to LPC2148


A key is generated.

LPC 2148, appends the key with its row of L matrix and transmits to AT 91 SAM9263

AT 91 SAM 9263, multiplies the received row and its column, thus a key isgenerated.

If the key generated at LPC 2148 and AT 91 SAM 9263 is one and the same andauthentication token is sent to LPC 2148.


Message communication between AT 91 SAM 9263 and LPC 2378 is establishedunder the encryption done by the key is generated.

If another LPC 2148 adds to the network then again the whole process is repeatedand also the key of the first LPC 2148 is also changed.

If a node is removed from the network, then again the whole process is repeated andalso the key of first paired LPC 2148 is also changed.

End.

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6.4.5 Node to Node Communication Cluster Head to Cluster Head [87] [89] [92]

[93] [94]

Start




AT 91SAM 9263 pairs with its nodes under same cluster id.

AT 91SAM 9263 waits for its request call and also searches for CH, with same group

Id.

Event _ process ( ) function is called and it starts to monitor for any event.

Under an AF _data request by AT 91 SAM 9263, which has same group and clusterid, periodic message function is triggered.


A row of the lower triangular matrix from LPC 2148 is transmitted to AT 91 SAM9263

The row received at AT91 SAM 9263 is multiplied with its own column of thetriangular matrix in it.


AT 91 SAM 9263, appends the key with its row of L matrix and transmits to AT 91SAM 9263


If the key generated at AT91 SAM 9263 and AT 91 SAM 9263 are one and the sameand authentication token is sent to AT 91 SAM 9263.


Message communication between AT 91 SAM 9263 and LPC 2378 is establishedunder the encryption done by the key is generated.

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If the AT 91 SAM 9263 is going out of network the key to cluster heads alone ischanged.

If an AT 91 SAM 9263 is coming into the network then the key for cluster headsalone is changed.

End.

6.4.6 Node to Node Communication Cluster Head to Base Station [87] [89] [92]

[93] [94]

Start


Xbee stack is connected to serial port to an i3 processor is initialized.



AT 91SAM 9263 pairs with its nodes under same cluster id.

AT 91SAM 9263, the wait and searches for i3: xbee protocol data request.


Under an AF_ data request by i3, which has same group and cluster id, periodic

message function is triggered.


A row of the lower triangular matrix from LPC 2148 is transmitted to i3

The row received at i3 is multiplied with its own column of the triangular matrix init.


I3, appends the key with its row of L matrix and transmits to AT 91 SAM 9263

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If the key generated at AT 91 SAM 9263 and i3 are one and the same and

authentication token is sent to i3 and this happens vice versa too.


Message communication between AT 91 SAM 9263 and i3 is established under theencryption done by the key is generated.

End.

In Table 6.2 the time period for key generation, key establishment, key distribution,

key management and data encryption are calculated for the various processors. The

result shows that the ARM series provides the lowest processing time for all the

process.

Table 6.2 Timing Analysis

ProcessorTime for Keyestablishment

Time forKey

Distribution

Time forKey

generation

Time for KeyManagement

Time forencryptionAlgorithm

8051178ms 180 ms 240ms 120 ms 150 ms

ATMEGA128L

165 ms 165 ms 165ms 91 ms 97.4 ms

MSP 430145 ms 142 ms 140ms 55 ms 59 ms

ARMLPC2148

110 ms 115 ms 110 ms 45 ms 40.2 ms

ARMLPC2378

105 ms 110 ms 102 ms 40 ms 37.4 ms

AT91SAM9263

71 ms 75ms 99 ms 35ms 33.3ms

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Table 6.3 Motes Comparison

Specification MicaZ TelosB IRIS Sun SPOT iMOTEProposedMOTE

ProcessorATMEGA

128LMSP430F1611

ATMEGA128L

ARM920 PXA271

LPC2148LPC2378AT91SAM9263

Ram/Flash/

Eeprom

4K/128K

10K/48K/1M

8K/640K/

4K

512K/4M

64K/512K

8K - 40K/32K –512K

RadioChipconCC2420

ChipconCC2420

AtmelATRF230

ChipconCC2420

ZeevoBT CC2530

Bandwidth250KBPS 250 KBPS 250 KBPS 250 KBPS 720 KBPS 12 Mbps

Clock 8 MHz 8 MHz 8 MHz 75 MHz12-48MHz

25 MHz

Datarate(kbps)

250 250 250 250 254 38.4

Supplyvoltage (v)

2.7-3.3 1.8 2.7-3.3 3 3.2-4.5 3.3

Currentrating (active

mode)8mA 1.8mA 8mA 40 µA 80 µA 23 µA

Currentrating

(sleep mode)<15µA 5.1µA 8mA 40µA 390µA 15µA

6.5 IMPLEMENTATION OF TSFS IN ARM NODES

An efficient light weight TSFS (Transposition, Substitution, Folding, and Shifting)

symmetric block encipherment algorithm [75] is used for encryption and decryption

[26] of sensor node data. Any cryptographic algorithm [91] depends upon the key

used and further the strength of it depends on the length of key.

Figure 6.7 Functional Blocks of TSFS

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In TSFS four keys are used and each key is of length 16 bit. These four keys can be

expanded to required number of sub keys using key expansion techniques i.e., the

given key say for example k11 is expanded into four key (k10, k11, k12, k13) as follows:

Arrange the given key k11 in the form of 4x4 matrix. All the four keys are obtained as

shown in Table 6.4

Table 6.4 Key Expansion Process

Key Row 0 Row 1 Row 2 Row 3K10 NS s-1 s-2 s-3

K11 s-1 s-2 s-3 NS

K12 s-2 s-3 NS s-1

K13 s-3 NS s-1 s-2

Note: NS- No Shift, S-1 Shift One, S-2 Shift Two and S-3 Shift Three

For Example the key expansion for Kij is shown below in Figure 6.8.

Figure 6.8 Key Expansion

Finally each key is expanded to four key with a total of 16 keys. After key

expansion, the actual encryption process [92] takes place which undergoes four

phase such as transposition, substitution, folding and shifting. Each phase undergoes

154

four rounds using the four expansion key. Transposition [27] changes the location of

the value rather than changing the value. Substitution cipher replaces one value with

another. For this multiple hashing techniques are used. In hashing techniques,

multiple additive and multiplicative cipher techniques are used.

After substitution [27], the next phase is folding where the matrix is folded

horizontally, vertically and diagonally. In shifting phase the bits are shifted by using

any one of the following methods: Logical Shift Left (LSL), Logical Shift Right

(LSR), Arithmetic Shift Right (ASR), Rotate Right (RR) and Rotate Right Extended

(RRE). Each bit can be shifted one or more times.

Hardware implementation of TSFS is explained below:

The program for TSFS is written using embedded C and is loaded into the processor

unit of the sensor nodes. The sensing unit of the sensor node senses the real time

parameter which is then processed by the processing unit of the sensor node. Then it

encrypts the sensed value using TSFS algorithm, and transmits it to other nodes

through the transceiver. At the receiver end the inverse algorithm of TSFS is loaded

into the sensor node, by which the original data of the sensor node is recovered.

The detailed timing analysis of TSFS in various microcontrollers is made and the

results are tabulated in Table 6.5. From that analysis it is concluded that the LPC

2148 [95], LPC 2378 [96] and AT91SAM9263 [97] provides better results in terms

of speed, efficiency and reliability. In key generation process LPC 2148, LPC 2378,

AT91SAM9263 processors follows independent key generation algorithm. The main

idea behind that is to generate 32 bit random secret value as key used in sensor node.

For generating the secret session key value, the ARM node process the ADC value,

DIP switch condition, PRNG value and the round function value. Here ARM node

155

acts as the crypto device to generate the secret session key value. The total time

required also tabulated in Table 6.6

Table 6.5 Timing Analysis for TSFS Algorithm

Processors Transposition Substitution Folding Shifting Etsfs

8051 36 ms 35 ms 42 ms 37 ms 150 ms

ATMega

128L28 ms 20.6 ms 25.3 ms 23 ms 97.4 ms

MSP 430 16 ms 19 ms 14 ms 11ms 59 ms

LPC2148 12.4 ms 9.6 ms 7.8 ms 10.8 ms 40.2 ms

LPC2378 12.1 ms 9.1 ms 6.9 ms 10.1 ms 37.4 ms

AT91SAM

926311.4 ms 8.6 ms 6.6 ms 9.8 ms 33.3ms

Table 6.6 Timing Analysis for Key Generation in TSFS Algorithm

Processors Time in ms

KEY Generation using ARM LPC2148 110 ms

KEY Generation using ARM LPC2378 102 ms

KEY Generation using AT91SAM9263 99 ms

6.5.1 Pseudo code for TSFS Algorithm

Begin

Initialize Baud-Rate for LPC2148 / LPC 2378/ AT91SAM9263

Set the Desired frequency

Calculate the value of the Divisor with the use of Baud-Rate and Frequency

UART-initialization

Assign the Control Bit for serial transmission to perform

Set the LSB and MSB bit for Data Transmission

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Main

Kij: = Key with ‘i’ and ‘j’ as loop increment and counter

Arr[i][j]:= data input in matrix

n:= integer number

Transposition

Key Kij is given and ‘j’ gets incremented

Arr[i][j]:=Kij Arithmetic with given data

Temp:=Arr[i][j]

Arr[i][j]:=Arr[i+n][j+n]

Arr[i+n[j+n]:=Temp

Substitution

Key Kij is given and ‘j’ is incremented

Arr[i][j]:=Kij Arithmetic with previous output

Temp1:=Arr[i][j]

n:= Arr[i][j]

Folding



Arr[i][j]:= Diagonal folding of Matrix Arr[i][j]

Arr[i][j]:= Horizontal folding of Matrix Arr[i][j]

Arr[i][j]:= Vertical folding of Matrix Arr[i][j]

Shifting



Arr[i][j]:= Barrel Shifting of Arr[i][j] by n

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Output:=Arr[i][j]

In Key Kij:=‘i’ gets incremented after the above processes performed and isrepeated

End Main

End

6.5.2 Pseudo Code for Key Generation Used in TSFS Algorithm

Begin

Initialize Baud-Rate for LPC2148 / LPC 2378/ AT91SAM9263

Set the Desired frequency

Calculate the value of the Divisor with the use of Baud-Rate and Frequency

ADC-initialize

Set the control bit for ADC Process

UART-initialization

Assign the Control Bit for serial transmission to perform

Set the LSB and MSB bit for Data Transmission

ADC-conversion

Assign PINSEL for ADC Conversion and for Serial Transmission

Check the ADC conversion by using the Data Register in the ADC

Perform shifting and logical operation to store the result of the conversion

Generate random value of 8-bit using

A=: 8-bit arithmetic with 8-bit logical with 8-bit

B=: 8-bit arithmetic with 8-bit logical with 8-bit

After padding 8-bit value of ADC value converted to 32-bit output

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Pseudo-Random Value

Generate random value of 32-bit using

x=: 32-bit arithmetic with 32-bit logical with 32-bit

y=: 32-bit arithmetic with 32-bit logical with 32-bit

z=: 32-bit value output

Switch-initialize

If (switch condition is met)

Return the corresponding switch value

Else

Return zero

Switch Process

x=: perform 8-bit arithmetic operation with the return value of the switch

u=: 8-bit arithmetic with 8-bit to convert into 16-bit value

v=: convert the 16-bit value to 32-bit value output

Round Function

C=: Key1 logical with Key2 logical with Key3

Arr [] =: C

Arr [odd] =: Perform Logical with Arr [odd] value

Arr [even] =: Perform Logical with Arr [even] value

Arr [odd] Logical with Arr [even] to generate 32-bit Key value

End

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Input Transposition SubstitutionQ F 14 4 4 Q F 14 $ 5 C &14 K L 12 L 12 K 14 7 @ 5 D7 6 13 19 6 13 19 7 G % T Q7 17 7 3 7 3 7 17 * H P A

W q 9 D & A K 6 * H P A65 18 * & U & H 9 D 5 @ 73 L # 0 8 # J 3 Q T % G1 16 87 $ 6 P % @ $ C 5 &

Output Shifting Folding

Figure 6.9 Data Processing in TSFS

Finally, the input from the sensor node given to the TSFS algorithm is

“QF14414KL1276131971773”, after implementing TSFS algorithm in multiple

round, the obtained output is “Wq9D6518*&3L#011687$”. The step by step process

is shown in Figure 6.9 above.

The result of hardware implementation for secret key generation using LPC 2148,

LPC 2378 and AT91SAM 9263 is shown in Figure 6.10, Figure 6.11 and Figure 6.12

respectively.

Figure 6.10 Secret Key Generation Using LPC 2148

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Figure 6.11 Secret Key Generation Using LPC 2378

Figure 6.12 Secret Key Generations Using AT 91 SAM9263

The hardware implementation of TSFS algorithm in LPC 2148 is shown in Figure

6.13 and Figure 6.14.

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Figure 6.13 Transposition & Substitution Result in LPC 2148

Figure 6.14 Folding & Shifting Result in LPC 2148

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6.6 CONCLUSION

This chapter explains the hardware implementation of WSN using LPC 2148, LPC

2378 and AT91SAM 9263. Various parameters [93] such as time for key

establishment, time for key distribution, time for key generation, time for key

management [94] and total time for data encryption and decryption [92] are

considered for the proposed sensor nodes and the results are tabulated in Table 6.2.

Table 6.3 shows the details about the various parameters of motes. The total time

required for transposition, substitution, folding and shifting was calculated and the

results are tabulated in Table 6.5. The total time for key generation for each node is

calculated and the results are tabulated in and Table 6.6.

The following are the strengths of LPC 2148, LPC 2378 and AT91SAM 9263 are

observed over existing motes:

Low power consumption

Heterogeneous nature

Low computation cost

Compatible with almost all peripherals

Easy to incorporate RTOS services

chapter 6: implementation of arm based sensor

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