chapter 6 exclusive-or and exclusive-nor gates copyright ©2006 by pearson education, inc. upper...
TRANSCRIPT
Chapter 6
Exclusive-OR and Exclusive-NOR Gates
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
All rights reserved.
William KleitzDigital Electronics with VHDL, Quartus® II Version
The Exclusive-OR Gate
• HIGH output if one input or the other input is HIGH, but not both.
• Logic Symbol - See Figure 6-3
• Truth Table - See Table 6-1
• Boolean equation– X = AB + AB
• Comparator
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-3
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
The Exclusive-NOR Gate
• The complement of the exclusive-OR
• Logic Symbol - See Figure 6-4
• Truth Table - See Table 6-2
• Boolean equation– X = AB + A B
• Comparator
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-4
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Parity Generator / Checker
• Electrical noise in the transmission of binary information can cause errors
• Parity can detect these types of errors
• Parity systems– odd parity– even parity
• Adds a bit to the binary information
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Parity Generator / Checker
• See Figure 6-8
• Error indicator output
• Even- and odd-parity generators– see Figure 6-9
• Integrated-Circuit Parity Generator/Checker– 74280 TTL IC– Function Table - see Figure 6-12
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-8
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-9
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-12
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
System Design Applications
• See example 6-5, 6-6, and 6-7
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-13
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-14
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-15
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
CPLD Design Applications with VHDL
• Used to simulate combinations of inputs and observe the resulting output to check for proper design operation.
• See examples 6-8, 6-9, and 6-10
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
CPLD Design Applications with VHDL
• Example 6-8, the 74280 parity geneator using the Quartus II Macrofunction– build a block design file– build a vector waveform file– provide a binary count on the 9 bit input so that
several combinations of odd and even parity are generated
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-16
Figure 6-17
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
CPLD Design Applications with VHDL
• Example 6-9, parallel binary comparator– reproduce the parallel binary comparator of
example 6-6– complete the circuit using bdf and VHDL entry
methods– test operation
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-18
Figure 6-19
Figure 6-20
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
CPLD Design Applications with VHDL
• Example 6-10, CPLD controlled inverter– reproduce the controlled inverter of
example 6-7– complete the circuit using bdf and VHDL entry
methods– test operation
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Figure 6-21
Figure 6-22
Figure 6-23
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Summary
• The exclusive-OR gate outputs a HIGH if one or the other inputs, but not both, is HIGH.
• The exclusive-NOR gate outputs a HIGH if both inputs are HIGH or if both inputs are LOW.
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Summary
• A parity bit is commonly used for error detection during the transmission of digital signals.
• Exclusive-OR and NOR gates are used in applications such as parity checking, binary comparison and controlled complementing circuits.
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version
Summary
• CPLDs can be used to implement circuits containing the exclusive gates
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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William KleitzDigital Electronics with VHDL, Quartus® II Version