Chapter 6

Arithmetic

Addition

0 1 1 1

+ 0 0 1 1 1 1 0 0 0

1 1 0 1

Carry in

Carry out

7

+ 6

13

si =

ci +1 =

Figure 6.1. Logic specification for a stage of binary addition.

1

0

0

0

1

0

1

1

0

0

1

1

0

11

0

0

1

1

0

1

001

0

0

0

0

1

1

1

1

0

0

0

0

1

111

xi yiCarry-inci

Sumsi

Carry-outci +1

xi yi ci xi yi ci xi yi ci xi yi ci xi yi ci=+ + +

yi ci xi ci xi yi+ +

+ +

DNF (disjunctive

normal form)

Logic for a Single Stage

FA

xn-1

cn

sn-1

yn-1

FA

x0

c1

s0

y0

FA

x1

Cn-1

s1

y1

… c0

Least significant bit (LSB) position

Most significant bit (MSB) position

N-bit ripple carry adder

n-bit adder

Xkn-1

ckn

skn-1

ykn-1 X0

cn

s0

y0Xn

Cn-1

S2n-1

yn

… c0

Cascade of k n-bit adders

n-bit adder

n-bit adder

…

S(k-1)n Sn

… …Sn-1

X2n-1y2n-1

…Xn-1

yn-1

Add/Subcontrol

n-bit adder

xn 1- x 1 x 0

cn

sn 1- s 1 s 0

c 0

yn 1- y 1 y 0

Figure 6.3. Binary addition-subtraction logic network

…

… …

…

FA

Xn-1

cn

sn-1

yn-1

FA

X0

c1

s0

y0

FA

X1

Cn-1

s1

y1

… c0

Least significant bit (LSB) position

Most significant bit (MSB) position

N-bit ripple carry adder

Timinginputs

result

Timing

• Gate delays– Propagation through the circuit over the longest path

• From x0 …y0 at the LSB position

• To cn, Sn-1 at MSB

• Cn-1 available in 2(n-1) “gate delays”

• Sn-1 available 1 delay later

• Cn 1 delay later

– Total of 2n gate delays

– + 2 more to set overflow

Logic for a Single Stage

2 “gate delays”

1 “gate delay”

FA

Xn-1

cn

sn-1

yn-1

FA

X0

c1

s0

y0

FA

X1

Cn-1

s1

y1

… c0

Least significant bit (LSB) position

Most significant bit (MSB) position

N-bit ripple carry adder

2(n -1) gate delays to

here

1 more gate delay to here

1 more gate delay to here

2n gate delays + 2 more to set “overflow”

Timing

• 2 n gate delays: n = 8, 32, 64

• Need for “fast adder”

• Carry lookahead

si =

ci +1 =

xi yi ci xi yi ci xi yi ci xi yi ci xi yi ci=+ + +

yi ci xi ci xi yi+ +

+ +

ci+1 = xi yi + (xi + yi) ci

ci+1 = Gi + Pi Ci

where Gi = xi yi and Pi = xi + yi

(G = “generate” P = “propagate”)

ci+1 = Gi + Pi Gi-1 + Pi Pi-1 ci-1

…

ci

ci+1 = Gi + Pi Gi-1 + Pi Pi-1Gi-2 + …

+ Pi Pi-1…P1G0 + Pi Pi-1 …P0C0

Then, the expression for any carry is:

For a 4-bit adder:

c0 = G0 + P0 c0

c1 = G1 + P1 G0 + P1P0 c0

c2 = G2 + P2 G1 + P2P1 G0 + P2P1P0 c0

c3 = G3 + P3 G2 + + P3P2 G1 + P3P2 P1G0 + P3P2P1P0 c0

Bit-stage cell

xi yi ci+ +=

Gi = xi yi Pi = xi + yi Same as

Unless xi + yi = 1 and then Gi = 1 and it doesn’t matter what Pi is

xi yi+

The “calculation” from the preceding chart

4 bits => “fan-in to last (left-most) gate is 5 -- the limit for practical application

4-bit carry-lookahead adder

Figure 6.5. 16-bit carry-lookahead adder built from 4-bit adders

(Similarly for 32-bit or 64-bit adders)

Carry-lookahead logic

4-bit adder 4-bit adder 4-bit adder 4-bit adder

s15-12

P3IG3

I

c12

P2IG2

I

c8

s11-8

G1I

c4

P1I

s7-4

G0I

c0

P0I

s3-0

c16

x15-12

y15-12

x11-8

y11-8

x7-4

y7-4

x3-0

y3-0

.

G0II P0

II

(13) Multiplicand M11

(143) Product P

(11) Multiplier Q10

01

11

1 1 0 11011

00001011

01 0 0 1 1 1 1

x

(a) Manual multiplication algorithm

Multiplication of Positive Numbers

Multiply “by hand” or programmatically

Uses lots of gates (transistors), lots of space on a chip (64 x 64, say)

Delay--signal propagation from upper right to lower left--for an n x n array: 6(n-1) gate delays

Control Sequencer

n-bit adder

Add/Noadd control

MUX

Multiplier Q

m0

C

Multiplicand M

Register A (initially 0)

q0a0

mn-1

an-1 qn-1

Sequential circuit binary multiplier

(positive numbers)

Shift right

0 0

• Multiplicand in M, Multiplier in Q,

• A initially 0, C initially 0

• C is the carry from the adder

• C, A and Q combined will hold the partial product

• LSB in Q will determine the Add/Noadd to determine if M is to be added to the partial product

• C, A and Q are shifted right after each add so LSB in Q always hold next multiplier bit (previous LSB is discarded)

• Control sequencer will shift and add n times

Initial configuration

First cycle

Second cycle

Third cycle

Fourth cycle

C A Q

0 1101 1011 Add0 0110 1101 Shift

1 0011 1101 Add0 1001 1110 Shift

0 1001 1110 Add0 0100 1111 Shift

1 0001 1111 Add0 1000 1111 Shift

M 1101

0 0000 1011

Product

13x 11

143

Partial product

Signed Operands

• Positive multiplier and a negative multiplicand:

– partial product must be sign extended

(to the left as far as possible)

Maintains the sign of the partial product

Figure 6.8. Sign extension of negative multiplicand.

10

11 11 1 1 0 0 1 1

110110

10

1000111011

000000

1100111

00000000

110011111

( -13)

(-143)

(+11)

Sign extension is shown in red

• Negative multiplier:

– Replace both numbers with their two’s complement

(doesn’t change the sign of the result)

Proceed as before

Just add sign extension hardware to what was discussed for positive numbers

Signed Operands

Control Sequencer

n-bit adder

Add/Noadd control

MUX

Multiplier Q

m0

C

Multiplicand M

Register A (initially 0)

q0a0

mn-1

an-1 qn-1

Sequential circuit binary multiplier (signed numbers)

Shift right

0 0

Maintain a sign-extended partial product

(always positive)

Figure 6.9. Normal multiplication scheme.

0

0 0

1 0 1 1 0 1

0

0 0 0 0 0 01

00110101011010

10110101011010

0000000000000

011000101010

0

00

1+ 1+ 1+ 1+

Multiplier 0011110 requires adding 4 shifted versions of the multiplicand

0011110 (30) can also be viewed as the difference between two numbers (32 and 2)

0100000 (32)

- 0000010 (2)

0011110 (30)

Figure 6.9. Booth multiplication scheme.

0

1

0 1 0 1 1 1

0000

000000000000001 1 1 1 1 1 1 0 1 0 0 1

00

0

0 0 0 1 0 1 1 0 1

0 0 0 0 0 0 0 0

0110001001000 1

2's complement of the multiplicand

0

0

0

0

1+ 1-

0

0

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0

Figure 6.10. Booth recoding of a multiplier.

001101011100110100

00000000 1+ 1-1-1+1-1+1-1+1-1+

Multiplier

Biti Biti 1-

Version of multiplicandselected by bit i

0

1

0

0

01

1 1

0 M

1+ M

1 M

0 M

Figure 6.12. Booth multiplier recoding table.

Figure 6.13. Booth recoded multipliers.

1

0

1110000111110000

001111011010001

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0

000000000000

00000000

1- 1- 1- 1- 1- 1- 1- 1-

1- 1- 1- 1-

1-1-

1+ 1+ 1+ 1+ 1+ 1+ 1+ 1+

1+

1+1+1+

1+

Worst-casemultiplier

Ordinarymultiplier

Goodmultiplier

Figure 6.20. Longhand division examples.

1101

1

1314

26

21

274 100010010

10101

1101

1

11101101

10000

13 1101

Divisor M

n-bit adder

Control Sequencer

Shift left

Dividend QQuotient setting

Add/Subtract

Circuit for binary division

Division

n times:

• 1) Shift A and Q left 1

• 2) Subtract M from A, result in A

• 3)

– if sign of A is 1, set q0 to 0 and add M back to A (restore A

– otherwise set q0 to 1

Floating Point Representation

• Need for more than just (say) 32-bit integers– Need larger numbers– Need fractions (some very small)

• Integers

– d31, d30, …. d0 . The binary point

or

– . d31, d30, …. d0

The binary point

• Neither is satisfactory• Need the binary point to “float”

• Scientific notation

• .12345 1.234 x 10-2

• 1234.5 1.234 x 103

• 12.345 1.234 x 10

Floating Point Representation

An E of 0 means 2-127

E of 127 means 20

E of 255 means 2128

IEEE standard (Intel and other processors conform)

binary point

Normalization and the “hidden bit”

0 10001000 0010110…

0 10000101 010110…

0.0010110… x 29

1.0110… x 26

the “hidden bit” (always a 1)

Unnormalized:

Normalized:

Single precision: ~7 decimal digits of “precision”

(7 significant digits)

in range 2-127 to 2128 (or 10-38 to 1038 )

Double precision: ~16 decimal digits

in range 2-1022 to 21023 (or 10-308 to 10308 )

Special Values

• E = 0 M = 0 value is 0

• E = 255 M = 0 value is “infinity” (result of divide by 0)

• E = 0 M /= 0 “denormal numbers”

smaller than the smallest

“normal number”

gradual underflow

• E = 255 M /= 0 NaN

result of an invalid operation(undefined)

e.g., 0/0, sqrt(-1)