chapter 5 transistors bjt part ii

8/12/2019 Chapter 5 Transistors BJT Part II

1/11

Biasing for the BJT

For amplifier applications, the Q-

point is located in the region in which

high voltage, current, and/or power

can be achieved.

For example, in this circuit, to

establish this Q-point, a dc bias

voltage VBE is applied to the base

and small ac signal vbe is added to

vary the base voltage around this

value.

Two practical biasing circuits used for

a BJT are:

Four-Resistor Bias Network

Two-Resistor Bias Network


2/11

BJT Biasing | Four-Resistor Bias Network

It is desirable that the Q-point is not affected by the properties of

the transistors.

One of the best circuit to stabilize the Q-point is the Four-resistor

bias.

21

21

21

1

|

NetworkBiasBaseofEquivalentThevenin

RR

RR

RRR

R

VV THCCEQ


3/11


Forward active region is correct

Q-point is (202 A, 4.29 V)

Thevenin Equivalent ofBase Bias Network

VEQ =VCCR1

R1 +R2= 4 V

RTH = R1R2

R1 +R2=12 kW

VEQ =IBREQ +VBE+IERE

IB =VEQ -VBE

REQ + bF+1( )RE

IB =4V- 0.7V

12kW+ 76( )16kW = 2.69 mA

IC=bFIB = 202 mA

IE= bF+1( )IB = 204 mA

VCE

=VCC

-IC

RC

-IE

RE

= 4.29 V


4/11

All calculated currents > 0, VBC= VBE- VCE= 0.7 - 4.32 = - 3.62 V

Hence, base-collector junction is reverse-biased, and assumption offorward-active region operation is correct.

Load-line for the circuit is:

The two points needed to

plot the load line are (0, 12

V) and (314 mA, 0). The

resulting load line is plotted

on the common-emitter

output characteristics.

IB = 2.7 mA - the intersection

of the corresponding

characteristic with load line

gives the Q-point: (200 mA,

4.3 V)

CC

F

ECCCCE II

RRVV 3820012



5/11

BJT Biasing | Four-Resistor Bias DesignObjectives

We know that

We desire IB > IB for b > 50.

IC@IE=VEQ -VBE-IBREQ

RE@VEQ-VBE

RE for IBREQ


6/11

BJT Biasing | Four-Resistor Bias DesignGuidelines

Choose Thvenin equivalent base voltage

Select R1 to set I1 = 9IB.

Select R2 to set I2 = 10IB.

RE is determined by VEQ and the desired IC.

RC is determined by desired VCE.

VCC

4VEQ

VCC

2

R1 =VEQ

9IB

R2 =VCC-VEQ

10IB

RE@VEQ -VBE

IC

RC@VEQ -VBE

IC-RE


7/11

Four-Resistor Bias for BJT | DesignExample

Problem: Design 4-resistor bias circuit with given parameters.

Given data:IC= 750 mA,bF= 100, VCC = 15 V, VCE= 5 V

Assumptions: Forward-active operation region, VBE = 0.7 V

Analysis: Divide (VCC- VCE) equally betweenREandRC. Thus, VE= 5 V

and VC= 10 V; Choose nearest 5% resistor values.

RC=VCC-VC

IC= 6.67 kW 6.8 kW

RE=VE

IE= 6.60 kW 6.8 kW

VB =VE+VBE= 5.7 V

IB = IC

bF= 7.5 mA

I2 =10IB = 75.0 mA

I2 = 9IB = 67.5 mA

R1 = VB

9IB= 84.4 kW82 kW

R2 =VCC-VB

10IB=124 kW120 kW


8/11

BJT Biasing | Two-Resistor Bias Example

Problem: Find the Q-point a forpnp transistor in a 2-resistor bias circuit

with given parameters. Given data:bF= 50, VCC = 9 V

Assumptions: Forward-active operation region, VEB = 0.7 V

Analysis:

Forward-active region operation is

correct Q-point is : (6.01 mA, 2.88 V)

9 =VEB +18000IB +1000 IC+IB( )

9 =VEB +18000IB +1000 51IB( )

IB =9-0.7

69000

V

W=120 mA IC= 50IB = 6.01 mA

VEC=

9-

1000 IC+

IB( )=

2.88 V VEC>

VBE


9/11

Tolerances & Worst-Case AnalysisExample

Problem: Find worst-case values of IC

and VCE

in the circuit below.

Given data:bFO

= 75 with 50% tolerance, VA

= 50 V, 5 % tolerance on VCC

, 10%tolerance for each resistor. R1 = 18 kW, R2 = 36 kW.

Simplified Analysis:

To maximizeIC , VEQ should be maximized,REshould be minimized and the opposite for

minimizingIC. Extremes ofREare: 14.4 kW and

17.6 kW.

To maximize VEQ, VCCandR1 should be

maximized,R2 should be minimized and

opposite for minimizing VEQ.

IC@IE@

VEQ -VBE

RE

VEQ=

VCCR1

R1 +R2=

VCC

1+ R2 R1( )


10/11

Tolerances & Worst-Case AnalysisExample (cont.)

VEQ

max=

12V(1.05)

1+ 36kW(0.9) 18kW 1.1)( ) = 4.78 V V

EQ

min=

12V(0.95)

1+ 36kW(1.1) 18kW 0.9)( ) = 3.31 V

ICmax

@4.78V-0.7V

16kW 0.90( )= 283 mA IC

[email protected]

16kW 1.1( )=148 mA

VCC=12V5%

R1 =18kW10%

R2 = 36kW10%

VEQ =VCCR1

R1 +R2=

VCC

1+ R2 R1( )REQ =

R1R2R1 +R2

=R1 R2


11/11

Tolerances & Worst-Case AnalysisExample (cont.)

Extremes of VEQ are: 4.78 V and 3.31 V.

Extremes for ICare: 283 mA and 148 mA.

To maximize VCE ,ICandRCshould be minimized, and opposite for minimizing VEQ.Extremes of VCEare: 7.06 V (forward-active region) and

0.471 V (saturated, hence calculated values for

VCEandICactually not correct).

VCE=VCC-ICRC-IERE@VCC-ICRC-VEQ -VBE

RERE

VCE@VCC-ICRC-VEQ +VBE

VCEmax

=12V 1.05( )-0.148mA 22kW( ) .9( )-3.31+ 0.7= 6.73 V

VCEmin

=12V 0.95( )- 0.283mA 22kW( ) 1.1( )- 4.78+0.7= 0.471 V

chapter 5 transistors bjt part ii

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