President University Erwin Sitompul SDP 5/1

Lecture 5

Semiconductor Device Physics

Dr.-Ing. Erwin SitompulPresident University

http://zitompul.wordpress.com

2 0 1 3

President University Erwin Sitompul SDP 5/2

Chapter 5pn Junction Electrostatics

Semiconductor Device Physics

President University Erwin Sitompul SDP 5/3

Step junctionidealization

Metallurgical JunctionChapter 5 pn Junction Electrostatics

Doping profile

President University Erwin Sitompul SDP 5/4

Poisson’s EquationChapter 5 pn Junction Electrostatics

S 0K

E v DD E

S 0K

S 0x K

E

Poisson’s equation is a well-known relationship in electricity and magnetism.

It is now used because it often contains the starting point in obtaining quantitative solutions for the electrostatic variables.

In one-dimensional problems, Poisson’s equation simplifies to:

President University Erwin Sitompul SDP 5/5

Equilibrium Energy Band DiagramChapter 5 pn Junction Electrostatics

pn-Junction diode

President University Erwin Sitompul SDP 5/6

Band diagram

c ref

1( )V E E

q

Qualitative ElectrostaticsChapter 5 pn Junction Electrostatics

Equilibrium condition

Electrostatic potential

( )V x dx E

President University Erwin Sitompul SDP 5/7

Electric field

Qualitative ElectrostaticsChapter 5 pn Junction Electrostatics

Equilibrium condition

Charge density

dV

dxE

S 0K

Ex

S 0

( )x xK

E

President University Erwin Sitompul SDP 5/8

Formation of pn Junction and Charge DistributionChapter 5 pn Junction Electrostatics

D A( )q p n N N qNA– qND

+

President University Erwin Sitompul SDP 5/9

Formation of pn Junction and Charge DistributionChapter 5 pn Junction Electrostatics

President University Erwin Sitompul SDP 5/10

DF i n-side

i i

( ) ln lnNn

E E kT kTn n

bi F i n side i F p side( ) ( )qV E E E E

Ai F p-side

i i

( ) ln lnNp

E E kT kTn n

A Dbi 2

i

lnN N

qV kTn

Built-In Potential Vbi

Chapter 5 pn Junction Electrostatics

For non-degenerately doped material,

• Vbi for several materials:Ge ≤ 0.66 VSi ≤ 1.12 VGeAs ≤ 1.42 V

President University Erwin Sitompul SDP 5/11

A1

S

( )qN

x x c

E

A

S

qNd

dx

E

Dn

S

( ) ( )qN

x x x

E

Ap

S

( ) ( )qN

x x x

E

with boundary E(–xp) = 0

with boundary E(xn) = 0

The Depletion ApproximationChapter 5 pn Junction Electrostatics

On the p-side, ρ = –qNA

On the n-side, ρ = qND

President University Erwin Sitompul SDP 5/12

A p

D n

, 0 , 0 0,

qN x xqN x x

otherwise

Ap p

S

Dn n

S

( ), 0

( )( ), 0

qNx x x x

xqN

x x x x

E

2Ap p

S

2Dbi n n

S

( ) , 02

( )( ) , 0

2

qNx x x x

V xqN

V x x x x

Step Junction with VA = 0Chapter 5 pn Junction Electrostatics

Solution for ρ

Solution for E

Solution for V

President University Erwin Sitompul SDP 5/13

Relation between ρ(x), E(x), and V(x)Chapter 5 pn Junction Electrostatics

1.Find the profile of the built-in potential Vbi

2.Use the depletion approximation ρ(x) With depletion-layer widths xp, xn unknown

3.Integrate ρ(x) to find E(x) Boundary conditions E(–xp) 0, E(xn)0

4.Integrate E(x) to obtain V(x) Boundary conditions V(–xp) 0, V(xn) Vbi

5.For E(x) to be continuous at x 0, NAxp NDxn

Solve for xp, xn

President University Erwin Sitompul SDP 5/14

2 2A Dp bi n

S S

( ) ( )2 2

qN qNx V x

A p D nN x N x

Step Junction with VA=0Chapter 5 pn Junction Electrostatics

At x = 0, expressions for p-side and n-side for the solutions of E and V must be equal:

President University Erwin Sitompul SDP 5/15

S An bi

D A D

2

( )

Nx V

q N N N

S Dp bi

A A D

2

( )

Nx V

q N N N

n px x W

Dn

A

Nx

N

Depletion Layer WidthChapter 5 pn Junction Electrostatics

Eliminating xp,

Eliminating xn,

Summing Sbi

A D

2 1 1V

q N N

Exact solution, try to derive

President University Erwin Sitompul SDP 5/16

S bi Dn p n

D A

2 , 0

V NW x x x

q N N

S bi2 VW

q N

S bi Ap n p

A D

2 , 0

V NW x x x

q N N

One-Sided JunctionsChapter 5 pn Junction Electrostatics

If NA >> ND as in a p+n junction,

If ND >> NA as in a n+p junction,

Simplifying,

where N denotes the lighter dopant density

President University Erwin Sitompul SDP 5/17

D Abi 2

i

lnN NkT

Vq n

S bi

D

2 VW

qN

n 0.115 mx W

Dp n

A

Nx x

N

Example: Depletion Layer WidthChapter 5 pn Junction Electrostatics

A p+n junction has NA 1020 cm–3 and ND 1017cm–3, at 300 K.

a) What isVbi?

b) What is W?

c) What is xn?

d) What is xp?

17 20

10 2

10 1025.86 mV ln 1.012 V

(10 )

1/ 214

19 17

2 11.9 8.854 10 1.0120.115 m

1.602 10 10

30.115 m 10 1.15 Å

President University Erwin Sitompul SDP 5/18

Step Junction with VA 0Chapter 5 pn Junction Electrostatics

• To ensure low-level injection conditions, reasonable current levels must be maintained VA should be small

President University Erwin Sitompul SDP 5/19

Step Junction with VA 0Chapter 5 pn Junction Electrostatics

In the quasineutral, regions extending from the contacts to the edges of the depletion region, minority carrier diffusion equations can be applied since E ≈ 0.

In the depletion region, the continuity equations are applied.

President University Erwin Sitompul SDP 5/20

A Dbi

i i

ln lnN NkT kT

Vq n q n

Sp n bi A

A D

2 1 1W x x V V

q N N

S Dp bi A

A A D

2,

Nx V V

q N N N

S An bi A

D A D

2 Nx V V

q N N N

Step Junction with VA 0Chapter 5 pn Junction Electrostatics

Built-in potential Vbi (non-degenerate doping):

A D2

i

lnN NkT

q n

Depletion width W :

,Dp

A D

Nx W

N N

W

NN

Nx

DA

An

President University Erwin Sitompul SDP 5/21

Effect of Bias on ElectrostaticsChapter 5 pn Junction Electrostatics

• If voltage drop â, then depletion width â• If voltage drop á, then depletion width á

President University Erwin Sitompul SDP 5/22

Linearly-Graded JunctionChapter 5 pn Junction Electrostatics

S

1dx

E V dx E

President University Erwin Sitompul SDP 5/23

1. (6.4)Consider a silicon pn junction at T = 300 K with a p-side doping concentration of NA = 1018 cm–3. Determine the n-side doping concentration such that the maximum electric field is |Emax| = 3×105 V/cm at a reverse bias voltage of VR = 25 V.

Chapter 5 pn Junction Electrostatics

Homework 4

Due: 17.09.2013.

2. (7.6)Problem 5.4Pierret’s “Semiconductor Device Fundamentals”.