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Inverter
Chapter 5Chapter 5
The InverterThe InverterV1. April 10, 03V1.1 April 25, 03V2.1 Nov.12 03
Inverter
Objective of This ChapterObjective of This Chapter
Use Inverter to know basic CMOS Circuits OperationsWatch for performance Index such as
Speed (Delay calculation)Optimal Transistor Sizing for speed and EnergyPower Consumption and Dissipation
Inverter
The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance
Vin Vout
CL
VDD
Inverter
CMOS InverterCMOS Inverter
Polysilicon
In Out
VDD
GND
PMOS
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
A=WxL
Inverter
Two InvertersTwo Inverters
Connect in Metal
Share power and ground
Abut cells
VDD
Vin Vout
Vin
Vout
Inverter
CMOS InverterCMOS InverterFirstFirst--Order DC AnalysisOrder DC Analysis
VOL = 0VOH = VDD
VDD VDD
Vin = VDD Vin = 0
VoutVout
Rn
Rp
Inverter
Delay Definitions (circuit speed)Delay Definitions (circuit speed)
Vout
tf
tpHL tpLH
trt
Vin
t
90%
10%
50%
50%
Inverter
CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response
tpHL = f(Ron.CL)= 0.69 RonCL
V outVout
R n
R p
V DDV DD
V in = V DDV in = 0
(a) Low-to-high (b) High-to-low
CLCL
ln(2)=0.69
Inverter
Voltage TransferVoltage TransferCharacteristicCharacteristic
Inverter
PMOS Load LinesPMOS Load Lines
VDS,p
IDp
VGSp=-2.5
VGSp=-1VDS,p
IDnVin=0
Vin=1.5
Vout
IDnVin=0
Vin=1.5
Vout
IDn
(Vdd = 2.5V in 0.25um CMOS Process)(Vt = 0.4V as shown in Table 3-2)
pDSDDout
pDnD
pGSDDin
VVV
II
VVV
,
,,
,
+=
−=
+=
pDnD
pGSDDin
II
VVV
,,
,
−=
+=pDSDDout VVV ,+=
Inverter
CMOS Inverter Load CharacteristicsCMOS Inverter Load Characteristics
IDn
Vout
Vin = 2.5
Vin = 2
Vin = 1.5
Vin = 0
Vin = 0.5
Vin = 1
NMOS
Vin = 0
Vin = 0.5
Vin = 1Vin = 1.5
Vin = 2
Vin = 2.5
Vin = 1Vin = 1.5
PMOS
Inverter
CMOS Inverter VTCCMOS Inverter VTC
Vout
Vin0.5 1 1.5 2 2.5
0.5
11.
52
2.5
NMOS resPMOS off
NMOS satPMOS sat
NMOS offPMOS res
NMOS satPMOS res
NMOS resPMOS sat
VM: Vin = VoutSwitching Threshold Voltage
Inverter
Switching Threshold as a Function of Switching Threshold as a Function of Transistor RatioTransistor Ratio
NMOS and PMOS are in Saturation Modes
For r = 1, and saturated velocity NMOS = 2 PMOS, Wp = 2Wn
),,when (1 TpTnDSATDD
DDM VVVV
rrVV >>
+≈
Inverter
Switching Threshold as a Function of Switching Threshold as a Function of Transistor RatioTransistor Ratio
100
101
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8M
V(V
)
W p/W n
2 3 4
Inverter
Simulated VTCSimulated VTC
0 0 .5 1 1 .5 2 2 .50
0 .5
1
1 .5
2
2 .5
Vin
(V )
Vou
t(V)
Inverter
Impact of Process VariationsImpact of Process Variations
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
V out(V
)
Good PMOSBad NMOS
Good NMOSBad PMOS
Nominal
Good definition: Smaller oxide thickness, smaller L, higher W, smaller VT
Inverter
Propagation DelayPropagation Delay
Inverter
CMOS InvertersCMOS Inverters
Polysilicon
InOut
Metal1
VDD
GND
PMOS
NMOS
1.2 µm=2λ
Inverter
CMOS Inverter Propagation DelayCMOS Inverter Propagation Delay
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
Inverter
The Transistor as a SwitchThe Transistor as a SwitchVG S ≥ V T
RonS D
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
Inverter
The Transistor as a SwitchThe Transistor as a Switch
0 .5 1 1 .5 2 2 .50
1
2
3
4
5
6
7x 1 0
5
VD D
(V )
Req
(Ohm
)
Inverter
The Transistor as a SwitchThe Transistor as a Switch
Inverter
0 0 .5 1 1 .5 2 2 .5
x 1 0- 1 0
-0 .5
0
0 .5
1
1 .5
2
2 .5
3
t (s e c )
Vou
t(V)
Transient ResponseTransient Response
tp = 0.69 CL (Reqn+Reqp)/2
?
tpLHtpHL
Inverter
Delay (speed degrade) as a function of VDelay (speed degrade) as a function of VDDDD
0 .8 1 1 .2 1 .4 1 .6 1 .8 2 2 .2 2 .41
1 .5
2
2 .5
3
3 .5
4
4 .5
5
5 .5
VD D
(V )
t p(nor
mal
ized
)
DSATnn
LpHL
DSATnTnDD
VkLWCt
VVV
')/(52.0
2/when
≈
+>>
Similar to Rn curve!Sharp change at 2Vt
Inverter
Design for Speed PerformanceDesign for Speed Performance
Keep loading capacitances (CL) smallIncrease transistor ratio (W/L) (adding CMOS gain)
Watch out for self-loading (for the previous stage)!
Increase Vdd! Trade power/energy dissipation for performance!
Inverter
Propagation delay v.s. Transistor sizePropagation delay v.s. Transistor sizeNMOS-to-PMOS Ratio:
Symmetrical tpHL and tpLH PMOS is 2.5~3.5 wider than NMOS in width under same LIs there better propagation delay (tp), or a better N-to-P ratio for overall tp can be found?
Consider two identical cascaded CMOS inverters. The approximated load cap of the 1st gate is
WgngpdndpL CCCCCC ++++= )()( 2211
11 , dndp CC Is drain capacitance of PMOS and NMOS of 1st stage
22 , gngp CC Is gate capacitance of PMOS and NMOS of 2nd stage
Inverter
Propagation delay v.s. Transistor sizePropagation delay v.s. Transistor size
When the PMOS device is made β times larger than the NMOS ThenCL becomes From (5.20), we have
where is the resistance ratio of equal-size NMOS
and PMOS
n
p
LWLW
)/()/(
=β
2211 and gngpdndp CCCC ββ ≈≈
WgndnL CCCC +++= ))(1( 21β
[ ]
[ ] )1())(1(345.0
)())(1(269.0
21
21
βγβ
ββ
++++=
++++=
eqnWgndn
eqpeqnWgndnp
RCCC
RRCCCt
eqn
eqp
RR
=γ
Inverter
1 1 .5 2 2 .5 3 3 .5 4 4 .5 53
3 .5
4
4 .5
5x 1 0
- 1 1
β
t p(sec
)
NMOS/PMOS ratioNMOS/PMOS ratio
tpLH tpHL
tp
β = Wp/Wn
Fig. 5-18
)(1(21 gndn
Wopt CC
C+
+= γβ
γβ =
>>+
opt
Wgndn CCC 21when 1.9
From Table 3.3β= 31Κ/13Κ = 2.4
Inverter
Inverter SizingInverter Sizing
Inverter
Inverter ChainInverter Chain
CL
If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?
May need some additional constraints.
In Out
1 f2f1
Inverter
Notation Definition Notation Definition
unitR
•Unit-size NMOS Transistor: the NMOS with minimumLmin and Wmin that meets the layout design rule (assume L is fixed, and W is varied)
• : Intrinsic Cap. of unit-size NMOS transistor• : Channel resistance of unit-size NMOS transistor• : Gate cap of unit-size NMOS transistor• : Channel resistance of W-sized NMOS transistor• : Self-loading or intrinsic cap of the inverter (diffusion cap and gate-drain overlap (Miller) cap)
gC
unitC
WR
intC
Inverter
Inverter DelayInverter Delay• Minimum length devices, L=0.25µm• Assume RP = 2RN and WP = 2WN =2W
• same pull-up and pull-down currents• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
WNN
unitunit
P
unitunitP RR
WWR
WWRR ==
≈
= )2(
tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):
2W
W
unitunit
gin CWWC 3=Load for the next stage:
(R of unit size NMOS)
Inverter
Inverter with LoadInverter with Load
Load (CL)
Delay
CL
tp = k RWCL
RP
RW
•k is a constant, equal to 0.69•Assumptions: no load zero delay
2W
W
tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL
Inverter
Inverter with Load and Para. Cap.Inverter with Load and Para. Cap.
Load
Delay
Cint CL
Delay = kRW (Cint + CL) = kRWCint + kRWCL
= Delay (Internal) + Delay (Load)= kRW Cint(1+ CL /Cint)
CN = Cunit
CP = 2Cunit
2W
W
Inverter
Delay FormulaDelay Formula( )
( ) ( )γ/1/1
~
0int ftCCCkRt
CCRDelay
pintLWp
LintW
+=+=
+
Cint = γCg,in with γ ≈ 1f = CL/Cg,in: Effective fanout
RW = Runit / W ; Cint =WCunit
tp0 = 0.69RunitCunit (Intrinsic or unloaded delay)Not function of transistor size!!
Inverter
Apply to Inverter ChainApply to Inverter Chain
CL
In Out
1 2 N
tp = tp1 + tp2 + …+ tpN
+ +
jgin
jginunitunitpj C
CCRt
,
1,1~γ
LNgin
N
i jgin
jginp
N
jjpp CC
CC
ttt =
+== +
=
+
=∑∑ 1,
1 ,
1,0
1, ,1
γ
Inverter
Optimal Tapering for Given NOptimal Tapering for Given NDelay equation has (N-1) unknowns, Cgin,2 ~ Cgin,N
Minimize the delay, find (N – 1) partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
- Each stage has the same effective fanout (Cout/Cin)- Each stage has the same delay
1,1,, +−= jginjginjgin CCC
Inverter
Optimum Delay and Number of StagesOptimum Delay and Number of Stages
1,/ ginLN CCFf ==
When each stage is sized by f and has same effective fanout f
N Ff =
( )γ/10N
pp FNtt +=
Minimum path delay
Effective fanout of each stage:
Inverter
ExampleExample
CL= 8 C1
In Out
C11 f f2
283 ==f
CL/C1 has to be evenly distributed across N = 3 stages:
Inverter
Optimum Number of StagesOptimum Number of StagesGiven load, CL and given input capacitance CinFind optimal sizing f
( )
+=+=
fffFt
FNtt ppp lnln
ln1/ 0
0γ
γγ
0ln
1lnln2
0 =−−
⋅=∂
∂
fffFt
ft pp γ
γ
For γ = 0, f = e, N = lnF
fFNCfCFC in
NinL ln
ln with ==⋅=
( )ff γ+= 1exp
Inverter
Optimum Effective Optimum Effective Fanout Fanout ff( )ff γ+= 1exp fopt = 3.6 for γ=1, fopt = 2.718 for γ=0
Inverter
Normalized delay function of Normalized delay function of FF( )γ/10
Npp FNtt +=
Inverter
Buffer DesignBuffer Design
1
1
1
1
8
64
64
64
64
4
2.8 8
16
22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
Without considering the internal capacitance
Inverter
Power DissipationPower Dissipation
Inverter
Where Does Power Go in CMOS?Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
Inverter
Dynamic Power ConsumptionDynamic Power Consumption
2
000
)( DDLoutLDDout
LDDDDVDDVDD VCdvCVdtdt
dvCVdtVtiE ∫∫∫∞∞∞
====
Inverter
Dynamic Power DissipationDynamic Power Dissipation
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Need to reduce CL, Vdd, and f to reduce power.
Vin Vout
CL
Vdd
Not a function of transistor sizes!
2)(
2
00
DDLout
outLoutVDDC
VCdtvdt
dvCdtvtiE ∫∫∞∞
=== Energy in CL
Inverter
Node Transition Activity and PowerNode Transition Activity and PowerConsider switching a CMOS gate for N clock cycles
EN CL Vdd• 2 n N( )•=
n(N): the number of 0->1 transition in N clock cycles
EN : the energy consumed for N clock cycles
Pavg N ∞→lim
ENN-------- fclk•= n N( )
N------------N ∞→
lim C•
LVdd•
2 fclk•=
α0 1→n N( )
N------------N ∞→
lim=
Pavg = α0 1→ C• LVdd• 2 fclk•
e)Capacitanc Effective:(
)( 2210
Eff
CLKDDEffCLKDDLAVG
C
fVCfVCP ⋅⋅=⋅⋅⋅= →α
Inverter
Switching Activity (Example 5.12)Switching Activity (Example 5.12)
25.08/210 ==→α
Inverter
Transistor Sizing for Minimum EnergyTransistor Sizing for Minimum EnergyGoal: Minimize Energy of whole circuit while maintaining the speed speed performance
Design parameters: f and VDD
tp ≤ tp,ref of referenced circuit with f=1 and Vdd =Vref
1Cg1
In
fCext
Out
TEDD
DDp
pp
VVVt
fFftt
−∝
++
+=
0
0 11γγ
)/( 1gext CCF =
)2/( DSATTTE VVV +=
Inverter
Transistor Sizing (2)Transistor Sizing (2)Performance Constraint (γ=1) Vdd(f)
Energy for single transition
Energy ratio of the design and reference circuit
( ) ( ) 13
2
3
2
0
0 =+
++
−
−=
+
++
=F
fFf
VVVV
VV
FfFf
tt
tt
TEDD
TEref
ref
DD
refp
p
pref
p
+++
=
FFf
VfV
EE
ref
DD
ref 422)(
2
[ ] ])1)(1[(1 12
12 FfCVFffCVE gDDgDD +++=++++= γγγ
Inverter
Transistor Sizing (4)Transistor Sizing (4)VDD=f(f) E/Eref=f(f)
Required Supply Voltage Energy v.s. Sizing factor
Inverter
Sizing factor for Speed and EnergySizing factor for Speed and Energy
Device sizing, combined with supply voltage reduction, is a very effective way in reducing energy consumption of a logic network.
The gain can be up to 10 for large fanout.
Oversizing beyond the optimal value comes at a hefty price in energy.Optimal size for energy is smaller than the optimal sizing for performance.
For example, f(energy) = 3.53, f(performance) = 4.47= , for F=20
20
Inverter
Short Circuit Currents (during switching)Short Circuit Currents (during switching)
Vin Vout
CL
Vdd
I VD
D (m
A)
0 .15
0.10
0.05
Vin (V)5 .04.03.02. 01.00.0
Inverter
Minimizing ShortMinimizing Short--Circuit PowerCircuit Power
Inverter
Neil Weste Textbook
Inverter
Leakage CurrentLeakage Current
Sub-threshold current is one of most compelling issuesin low-energy circuit design!!
DDstatstat VIP =
Inverter
ReverseReverse--Biased Diode LeakageBiased Diode Leakage
Np+ p+
Reverse Leakage Current
+
-Vdd
GATE
IDL = JS × A
JS = 10-100 pA/µm2 at 25 deg C for 0.25µm CMOSJS doubles for every 9 deg C!
Inverter
SubthresholdSubthreshold Leakage ComponentLeakage Component
Inverter
SubthresholdSubthreshold Leakage Component (2)Leakage Component (2)
Inverter
Putting All TogetherPutting All Together
•In a typical CMOS circuits, the capacitive dissipation is by far the dominant factor.
•Leakage is ignorable at present, but will be major issue in deep-submicron CMOS circuits.
leakDDspeakDDDDL
statdpdynatotal
IVftIVVC
PPPP
++=
++=
→102 )(
Inverter
Principles for Power ReductionPrinciples for Power ReductionPrime choice: Reduce voltage!
Recent years have seen an acceleration in supply voltage reductionDesign at very low voltages still open question (0.6, … , 0.9 V by 2010!)
Reduce switching activity (at different levels)Reduce physical capacitance
Device Sizing: for example, for F = 20fopt(energy)=3.53, fopt(performance)=4.47.
Inverter
PowerPower--Delay Product (PDP)Delay Product (PDP)
PDP stands for the average energy consumed per switching event (0 1, 1 0)
pavtPPDP =)2/(1max ptf =
2
2
max2 DDL
pDDLVCtfVCPDP ==
Inverter
EnergyEnergy--Delay Product (EDP)Delay Product (EDP)Measure of both Performance and Energy
The value of supply voltage that simultaneously optimizes performance and energy. For Vt=0.5V, the VDD is around 1V.
pDDL
pavp tVCtPtPDPEDP2
22 ==×=
)21.5(2/, DSATTTETEDD
DDLp VVV
VVVCt +=−
≈α
)59.5(23,
)(2 ,
32
TEoptDDTEDD
DDL VVVV
VCEDP =−
=α
Inverter
EnergyEnergy--Delay Product (EDP)Delay Product (EDP)
VVVVVVV
VVVVVVVVVVVV
optDDpTEnTETE
pTEpDsatTp
nTEnDsatTn
2.18.0)2/3(8.02/)(
9.0,1,4.074.0,63.0,42.0
,,,
,,
,,
=×=⇒=+=
−=−=−=
===
Note:
Vdd for minimum EDPMay not be the Optimal Vdd for a given design problem (speed contraint)
Inverter
SummarySummary
Inverter Speed (delay), sizing, and power are discussed.The concept can be extended to complex gates in next chapter and future discussionsVery important for the 1st-order guess/approximation for designers in considering power/area/speed of the target CMOS circuits