chapter 5, inside digital design

7/28/2019 CHAPTER 5, Inside Digital Design

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CHAPTER 5

RISC Processor Design

The processor provides a mechanism where inputs are received, certain operation is performed on them

and output is generated. The operation performed by the processor depends on the instruction set of

the machine. The first point to designing a processor is thinking about the instruction set of the

machine.

Instruction Set architecture (ISA) describes instruction set, word size (as instruction are stored in

memory), address modes (like direct, Indirect, Indexed) and processor registers to support the

instruction set. The depth of ISA depends on function of the processor which might be General Purpose,

Media Processor, DSP Processor, Network Processor etc.

The second step is micro architecture; it defines Data Path and Storage elements. Microarchitecture

determines how a certain ISA will be implemented. There are certain type of microarchitecture which

are very popular i.e. RISC, CISC, MIPS, VLIW etc. The microarchitecture is classified on the basis of ISA

organization. RISC (Reduced Instruction Set Architecture) makes number of instructions very less, only

most needed instructions are added in ISA, this reduces the size of word size, busses, Memory Elements

and Instruction decoder. However the programmers have to work hard with fewer instructions, for

example if Instruction set does not contain instruction of multiply, it will be done by using Shift and Add

Instructions. CISC (Complex Instruction Set) takes the alternative approach in this concern, it include

more instructions. This increases the architectural complexity but reduces programmer labor.

We will address 8-Bit RISC Processor with 16 Instructions; the purpose of the design will to comprehend

the basics of Processor and its component design. This chapter requires complete understanding of

ASMD based designs and partitioning.


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5-1:ISA(Instruction Set Architecture)

Instruction Set architecture defines Instruction Set and Instruction word. The Instruction Set of any

processor depends on the operation a processor can perform. Media Processor will have instructions

supporting Media algorithms, similar can be deduced about DSP Processor. Instruction Set have set of

instructions capable of performing a certain job. Generally these Instructions are classified into Four

Categories on the basis of operation they perform Arithmetic, Logical, Memory based and Branching. In

this section we will defines a small processor as an example, table 5-1 present Instruction set for the

processor.

Table 5-1: Instructions Set for 8-Bit RISC Processor

ARITHMETIC ADD Addition 0000 ADD R1,R2 R1R1+R2

SUB Subtraction 0001 SUB R1,R2 R1R1-R2

MUL Multiplication 0010 MUL R1,R2 R1R1xR2

LOGICAL

(Move is

register

operation)

AND Logical AND 0011 AND R1,R2 R1R1&&R2

OR Logical OR 0100 OR R1,R2 R1R1||R2

CMP Complement 0101 CMP R1 R1!R1

SLR Shift Logical Right 0110 MOV R1,2 R1>>2

SLL Shift Logical Left 0111 SLL R1,AMT R1


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5-1-1: Instruction word design

The instruction set given in Table 5-1 give 16 instructions at assembly language. The next step is to define

instruction word, the purpose of Instruction word is to define mechanism to store the assembly based

program inside memory. The assembly mnemonics are given in table 5-1 with op code, the instructionword defines how are certain program in Assembly is represented in Machine Language.

5-1-2: Conversion of Assembly Program into Machine Level Language

RType- Register Type Instruction

The register type instruction has two Register fields of 2-Bits. The register File will contain Four

Registers. The instruction of RType Include all Arithmetic Instruction, AND, OR and CMP instructions. The

R-Type instrution is 1-byte.

SRType- Single Register Type Instruction

Single Register Type instruction include instructions with single register field. The remaining two bits are

either given for Immediate Value as in MOV instructions or to Give Shift Amount.

Branch Type Instruction

All branching instruction are two byte instruction with second byte containing 8-Bit Address to address

256x8 Memory. The Src and Des Register Fields are donot care.

Memory Type Instruction

The Memory Type Format is two byte instruction same as Branch, except for SRC/DES are not donot

care. In Read Instruction Destination register is given and write instruction has Source register enabled.

Figure 5-1: Instruction Word for the instruction set given in Table 5-1

OPCode(4Bits) Des Reg(2Bits) Src Reg(2Bits)

OPCode(4Bits) Des Reg(2Bits) Shift Amount /Immediate Value (2Bits)

OPCode(4Bits) XXXXXXXXXX XXXXXXXXXX

Address (8 Bits)

OPCode(4Bits) SRCReg(WR Instruction)

Address (8 Bits)

DesReg(RDInstruction)


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ISA also involve Address modes, however to keep the things simple we have not discussed address modes

in this design. To Illustrate the Translation of Assembly code into machine level code Example 5-1 gives

an assembly level code of program which sum all even numbers till 20. The memory of the design is Von

Neuman with logical partitioning of Memory; however buses are separate for address and data. First 200

locations contain Code memory and next 56 locations contain data memory.

Design Example 5-1: Translation of Assembly Level Code into Machine Level Code

The program will calcualte sum of even numbers till 20. Code is given in both C and aseembly level languages and

possible machine level is given below.

int sum;

for (int i=0;i


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Assembler maintains a table called Label Table, which is mostly used in Loops. The line-5 of assembly has

label LOOP the address of this label is 5. The Line 9 of Machine Level code contains address 5.

5-2:Micro Architecture

Data path of Processor is called Microarchitecture, it defines register File, ALU, Data bus, address bus ,

Registers associated and all other components.

Figure 5-2: Micro Architecture of 8-Bit RISC Processor(Width of bus is 1 otherwise indicated)

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CONTROLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU(3)

OpCode_ALU (3)

RW_Mem

Add2_RFile(4)

Add1_RFile(4)

RW_RFile

RST_PC

LD_PC

INC_PC

Add_Mem(8)

Din_Mem(8)

Dout_Mem(8)

Din_RFile(8)

Inst(8)

Data_IM(2)

ShAMT_ALU (2)


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Table 5-2: Summary of 8-Bit RISC Processor Micro Architecture Components

Register File Register File Contain Four Registers with two address lines for two consecutive reads and single

write at Address-1. Read Write control decides whether to read or write on the Register File. The

Data Write Input is connected to the data bus of the system shown in Bold Line in Figure 5-2.

ALU ALU take two 8-bit inputs and perform operation based on 4-Bit op code performed. As a result

ALU store the result in Data Register. The 3-Bit Flag is passed to control unit containing Flag for

Zero and 2-Bit Flag Bits for Comparison of Inputs. First 3-Bits of Opcode are passed to ALU, this is

for a reason that all ALU concerned instructions are covered in First three bits i.e. 4b0111.

PC Program Counter contains the current pointer to the program. Program counter can be Reset or

Incremented by the control unit. The Address Bus is connected to the Program Counter; its

loading is controlled by control Unit. This option is used in Branching.

Memory Memory contains 256 locations with each location is 8bit. The 256 location are divided into two

parts first 200 locations as Code Memory and the next 56 locations as Data Memory. This

architecture is Von Neuman Architecture with shared memory space. The Address of Memory is

taken from Address Register (AReg). The output of Memory is given to both Address and Data

Selection Multiplexers. The Memory Data put can go to address bus in case of two byte

instructions and to Data bus in case of one byte instructions. The First 8-bits of Two byte

instruction go to Data bus.

Mux_Data Data Multiplexer select the data input from ALU or memory. It takes data from ALU when the

result of ALU is to be stored in Register File and from Memory when data is to be stored in

Instruction Register (IR) called fetch.

Mux_Add Address Multiplexer selects address source from either Program counter (in fetch) or from

Memory (in case of Read/Write operations).

AReg Stores address for the memory, the address selection is done by Address multiplexer.

IR Instruction Register Stores the Current Instruction taken from Memory and passes it to control

unit.

Dreg Data Register stores the Result of ALU, this result is written in Register File in Next Clock Cycle.

5-3:Micro Architecture Operations

The Microarchitecture presented in the last section contains the entire program in the code memory. The

program is translated from assembly language to machine by assembler. The assembler writes this

program in the instruction memory of the processor. The processor brings this code line by line (location

by Location) from the memory to the instruction register (fetch). The First Stage for every location in

Memory or Every line in Assembly is fetch i.e. to bring the instruction from memory to Instruction


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register. Once the instruction is fetch the control Unit will execute the instruction depending on type of

instruction fetch. The Op Code of the instruction in focus is used to determine what action should be

taken to perform a relevant execution, this stage is called decode. The instruction is been fetch and it is

known what instruction is brought (decode), finally the instruction is execute. The results of the

execution are written back to the memory or register file, this step is called write back. The program is

present in the memory, data path fetch, decode, execute and write back the program location by

location. This operation is controlled by the Control Unit of the design.

Table 5-3: Summary of 8-Bit RISC Processor Micro Architecture Operations

Fetch Every instruction is Fetch from the memory, location by location. The address of the fetch is

maintained by Program counter. The instruction is fetch into instruction register which is finally

passed to Control Unit as shown in Figure 5-3.

Execute

Register Type

Instruction

Every instruction after been fetch is executed. The execution depends on Type of instruction. In

case of R Type instruction the register file passes the address of registers on which operation is

required. ALU is passed with these register which perform operation based on OP Code. The

results are stored in data register and Flags are passed to control Unit. This is shown in Figure 5-4.

Write Back

Register Type

The results stored in Data Register from Execution stage of Register Type instruction are passed to

register file. This is shown in Figure 5-5.

Fetch 2 Byte The address of second byte is brought from PC to Address register. This cycle is shared for branch

operation and memory based operation.

Branch

Instruction

Branch instructions are first fetch then the second byte instruction word is stored in to Program

Counter Creating a Jump on the required location. This is shown in Figure 5-6.

Read, Write

First Clock

Cycle

The read/write instructions are first Fetched. Both instruction share common First State. The

address stored in second byte of these instruction is not data itself but is indirect address of

location where is data is to be written or to be read. In this State the Second byte of data is stored

in Address register. This is sort of feedback of address.

Read Second

Clock Cycle

In second cycle of read data is read from the location referred. And the data is written into register File. The

first clock cycle of Read/Write is shown in Figure 5-7 while Second Clock Cycle of Read is shown in Figure 5-8.

Write Second

Clock Cycle

The second clock cycle of write is same as for read except for data is written from register file into memory

location indicated by address register as shown by Figure 5-9.

5-3-1: Fetch Operation

Figure 5-3 indicates fetching of Instruction from the memory. The program counter is initially zero it

points the first location of the memory, on each fetch it is incremented to the next location by the

program counter.


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The address in the program Counter is passed from MUX_ADD to the AReg(Address Register). The data in

the program memory is read and is passed to IR using MUX_DATA. This instruction is passed to control

unit. This job is fundamental to any instruction in the memory.

5-3-2: Execute and Write back in Register based instructions

Figure 5-4 show the execution of register based operation. Two addresses are passed to the register file,

resulting two connective reads. ALU takes this data and performs operation based on OPCode_ALU.

Figure 5-3: Fetch Operation Illustrated in Bold

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CONTR

OLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

RW_Mem

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Add_Mem

Din_Mem

Dout_Mem

Din_RFile

Inst

Data_IM

ShAMT_ALU


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It is a 3-bit field which tells ALU which operation is to be performed. If the instruction is shift based 2-Bit

ShAMT_ALU indicates amount of shift required. The result of Register Execution is stored into Data

Register and FLAG_ALU are passed to the control Unit. FLAG_ALU are 3-bit Containing Zero Flag and

Comparison Flag. The last two bits are comparison Flag, which combines to determine whether first

number is Greater than second (00), Equal to second (01) or less then second (10).

The second clock cycle of register based operation is shown in Figure 5-5 it is write back operation. The

result in Figure 5-4 is Stored in Data Register. Write back writes data from Data register to Register File.

the Destination register is indicated by the control unit.

Figure 5-4: Register based Operation, Execute Illustrated in Bold

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CONTROLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

RW_Mem

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Add_Mem

Din_Mem

Dout_Mem

Din_RFile

Inst

Data_IM

ShAMT_ALU


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5-3-3: Fetch 2 Byte

Both two words type instructions i.e. branching and memory based operations require program counter

address in the Address register to read second byte. This cycle is similar to normal fetch shown in Figure

5-3. The Fetch 2 byte is shared in both Branch and read, write instructions. After it is known after

decoding that Instruction is not HALT, R-Type or SR Type the processor goes to Fetch 2 Byte state.

Figure 5-5: Register based Operation, Write Back Illustrated in Bold

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CONTR

OLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

RW_Mem

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Add_Mem

Din_Mem

Dout_Mem

Din_RFile

Inst

Data_IM

ShAMT_ALU


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5-3-4: Execute in Branch based instruction

The Branch operation is shown in Figure 5-6, the Program Counter leaves it regular incremental process

and jumps to address either on certain condition or unconditionally. The instruction word in Figure 5-1

indicates that the address where the branch is taken is kept in the second byte of the instruction. The

second byte is read from the memory and store the result in program counter. The Dout_Mem is loaded

into PC by asserting LD_PC and making SEL_MADD as 0.

Figure 5-6: Branch Operation, Illustrated in Bold

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CON

TROLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

RW_Mem

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Add_Mem

Din_Mem

Dout_Mem

Din_RFile

Inst

Data_IM

ShAMT_ALU


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5-3-5: Read and Write Operations

The read and write instructions share common first Clock Cycle as shown in Figure 5-7. The read/write

instructions contain second byte with address. This is indirect address where the read/write is to be

done. The data in second byte of read/write is only an address referring to location where either data iswritten in memory or to be read from memory.

Figure 5-7: Read and Write Operation, First Clock Cycle

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CONTROLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

RW_Mem

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Add_Mem

Din_Mem

Dout_Mem

Din_RFile

Inst

Data_IM

ShAMT_ALU


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The DOut_Mem contains the second byte of instruction which is feed back to AReg(Address register). For

example the second byte of instruction contains 200 and this instruction is present at location 5 of

program memory, then 200 will be feed back into AReg.

As discussed in the Figure 5-7 that Address register will now contain the address at second byte of readinstruction For example 200 while PC will still hold the address of active program memory i.e. 5. First

address in PC is incremented to point to the next address i.e. 6.

Figure 5-8: Read Operation, Second Clock Cycle

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CONT

ROLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

RW_Mem

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Add_Mem

Din_Mem

Dout_Mem

Din_RFile

Inst

Data_IM

ShAMT_ALU


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Figure 5-8 explains the second clock cycle of read operation while Figure 5-9 explains second clock cycle

for Write operation. The AReg points to the indirect address, DOut_Mem has data from memory which is

passed to register file through MUX_DATA.

The second Clock Cycle of write instruction writes Data from Register File into Memory using Din_Mem.

The RW_RFile is selected to read data from the Register File and Add1_RFile indicates the address of

source register of the register file. The second address in this case is donot care, and does not carry any

Figure 5-9: Write Operation, Second Clock Cycle

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CONTROLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

RW_Mem

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Add_

Mem

Din_Mem

Dout_Mem

Din_RFile

Inst

Data_IM

ShAMT_ALU


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significance. Last but not least the move instruction passes the data to be moved on Data_IM line from

the control unit. It is passed from MUX_DATA to the register File.

5-4: HDL code for Micro Architecture

The discussion will focus on FPGA based design and Behavioral simulations. The first module we will

discuss is register file, containing 4 registers each of 8bit.

5-4-1: Register File

Figure 5-10 show the Block Diagram and Verilog code of Register File.

module RFile(input RW_RFile,input [1:0] Add1_RFile,input [1:0] Add2_RFile,input [7:0] Din_RFile, output reg [7:0]

DOut1_RFile,output reg [7:0] DOut2_RFile, input Clk,input Enb_RFile);

reg [7:0]RF[3:0];

always@(posedge Clk)

if(Enb_RFile==1)

if(RW_RFile==0)//Readbegin

DOut1_RFile


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5-4-2: Program File

Figure 5-11 Show Design of Program Counter, its a special register with increment, data loading and

Reset Facility in it. Program counter keep the current address of the program to be fetch, it is increment

once in all 1-Byte instructions and incremented twice in two byte instructions. Program Counter point thememory location by location, however the normal flow of program counter may change in case of branch

instructions.

5-4-3: General Purpose Register

Figure 5-12 shows an 8-bit register with loading control at the input. There are 3 instances of this register

including Data Register, Address Register and Instruction Register. All of these registers work in similar

fashion, the load signal enables loading of data in the respective register. The output of the register is

taken from the register. The data is always available at the output without any control signal.

module PC(input INC_PC,input RST_PC,input LD_PC, input[7:0] Din_PC,

output [7:0]DOut_PC,input Clk);

reg [7:0]RPC;

assign DOut_PC=RPC;


if(RST_PC)

RPC


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5-4-4: Arithmetic Logic Unit

Figure 5-13 Show the Code and Diagram for Arithmetic Logical unit. The first always block control the

operation of the ALU and the second Always block control the Flags of the ALU. The code for the

multiplexers is not given in this section and is left to reader while for memory Xilinx Core generator is

used. Xilinx Core generator provides a single port memory for Block RAMS of CLBs.

module Reg_8Bit(input [7:0] Din_Reg,input Clk, output [7:0] DOut_Reg,input LD_DReg);

reg [7:0]R;

assign DOut_Reg=R;


if(LD_DReg)

R


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Since the memory is only 256x8 so BRAM is enough for such a small memory requirement. However in

larger memory requirement SRAM is used. This requires either a SRAM core or SRAM controller code

which is discussed in latter chapters. The method to use Memory Core generator is described in

Laboratory manual and can be practiced by the students. The COE file contains the Program of machine

language to be executed on the processor, this file is used as initialization file for core generator.

5-4-5: Top Level Module of Data Path

The complete design for Data Path of the Processor is given in Figure 5-14. Two modifications are done in

the data path, Enb_RFile and Enb_Mem are added. These signals are used to enable/disable these two

case(OpCode_ALU)

3'b000:DOut_ALUShAMT_ALU;//slr

3'b111:DOut_ALU


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modules. Memory is not part of Data path so it shown as separate module. It is important to consider

the sequential and combinational elements. The drives are always wire and does not have storage

capabilities unless have register in them.

Figure 5-14: Modifications in Data Path (All wires are shown in Italic)

Register File

PC

Memory256x8

ALU

DREG

MUX_ADD

MUX_DATA

IR

AREG

C

ONTROLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Din_RFile

Inst

Data_IM

ShAMT_ALU

Enb_RFile

RW_MemEnb_Mem

Din_Mem

Add_Mem

DOut_Mem

DATA

PATH

BUS_

DATA

WRFOut12

WRFOut11

WALUOut

WDROut

BUS_DATA

WPCOut

BUS_ADD

BUS_ADD


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The code of data path given in figure 5-15, connection wires are shown as separate wires after port

definition is made.

All intermediate wires are shown in italic in figure 5-14. The address bus and data bus uses BUS_ADD or

BUS_DATA respectively. The interconnection WRFOut1 and WRFOut2 between Register File and

ALU. The outputs of Register Program Counter, ALU and Data Register is used by WPCOut,WALUOut

and WDROut respectively. There are three instances of Reg_8bit are used in the code Instruction

register, data register and address register. However for program counter uses separate module,

because it requires special function like increment of program counter.

module DP_RISC8Bit(input INC_PC,input LD_PC,input RST_PC,input RW_RFile, input [7:0] Add1_RFile,input [7:0]

Add2_RFile,input RW_Mem,input [2:0] OpCode_ALU, output [2:0] Flag_ALU,input [1:0] ShAMT_ALU, input

LD_DReg,input [7:0] Data_IM, input [1:0] Sel_MData, input Sel_MAdd,input LD_IR, output [7:0] Inst,input Clk,

input LD_AReg, output [7:0] Din_Mem, output [7:0] Add_Mem,input [7:0] DOut_Mem, input Enb_RFile);

wire [7:0]BUS_DATA,BUS_ADD;

wire [7:0]WRFOut1,WRFOut2,WPCOut,WALUOut,WDROut;

assign Din_Mem=WRFOut1;

RFile R1(.RW_RFile(RW_RFile),.Add1_RFile(Add1_RFile),.Add2_RFile(Add2_RFile),.Din_RFile(BUS_DATA),

.DOut1_RFile(WRFOut1) ,.DOut2_RFile(WRFOut2),.Clk(Clk),.Enb_RFile(Enb_RFile));

PC P1(.INC_PC(INC_PC),.RST_PC(RST_PC),.LD_PC(LD_PC),.Din_PC(BUS_ADD),.DOut_PC(WPCOut),.Clk(Clk));ALU A1(.OpCode_ALU(OpCode_ALU),.Flag_ALU(Flag_ALU),.ShAMT_ALU(ShAMT_ALU),.Din1_ALU(WRFOut1),

.Din2_ALU(WRFOut2),.DOut_ALU(WALUOut));

MUX_ADD MA1(.Din1_MADD(DOut_Mem),.Din2_MADD(WPCOut),.Sel_MADD(Sel_MAdd),.DOut_MADD(BUS_ADD));

Reg_8Bit DReg(.Din_Reg(WALUOut),.Clk(Clk),.DOut_Reg(WDROut),.LD_DReg(LD_DReg));

Reg_8Bit AReg(.Din_Reg(BUS_ADD),.Clk(Clk),.DOut_Reg(Add_Mem),.LD_DReg(LD_AReg));

MUX_DATA MD1(.DIn1_MData(WDROut),.DIn2_MData(Data_IM),.DIn3_MData(DOut_Mem),.DIn4_MData(8'dz),

.DOut_MData(BUS_DATA),.Sel_MData(Sel_MData));

Reg_8Bit IR(.Din_Reg(BUS_DATA),.Clk(Clk),.DOut_Reg(Inst),.LD_DReg(LD_IR));

endmodule

Figure 5-15:Putting it All together Data Path


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5-5: Control Unit Design of Processor

In the last section the design of data path was completed. The current section will focus on control unit

and its coding. At the end of this section we will design the top level module. The foundation for the

control unit is already been laid in the section 5-3 where operations of data path are explained. As a good

exercise for the reader try designing the control unit for yourself and then compare the design given in

this section. Most of the designs required modifications in data path before we can write code of control

unit. Two modifications are done in Figure 5-15 both register file and memory are added with enabled

signals. This is done to ensure that both register file and memory dont have any accidental data

operations.

Table 5-4: State for ASMD based design

Fetch In the fetch, address of PC is moved to address register. The content pointed by the address register is

carried to the instruction register. To achieve all these operations Fetch State is defined. It requires Address

and Data Multiplexers selection to take PC data on Address bus and Memory Out data on data bus

respectively. The load of Instruction register and Address register must be asserted.

Decode In decode the instruction received to the Control Unit is decoded. Program counter is incremented to

prepare for next instruction.

R Type Execute Two words from Register File are read and passed to ALU. The read addresses and read write signals are

required for Register File. The ALU requires OP Code to perform operation on the operands and Write the

data into data register.

R Type WB The data from the data register is written back to register file. R Type instruction two cycles to perform

Operation.

Fetch 2 Byte The Address in Program counter is loaded in address register. The state is same as fetch with only difference

that Memory out is not loaded in Instruction register.

Branch The branch instruction takes the data from the memory pointed by the Address register and store the

memory word into program counter.

RW Execute The first clock cycle of read and write operation is shared. The addresses for both read and write instruction

is stored on the second byte. In the first clock cycle the address is moved from second byte of Memory

location to the address register.

Read WB The read write back is second cycle of RW executed. In this cycle the data from memory pointed by addressregister is written in register file.

Write WB The Data from register file is written on memory by address pointed by address register.

Table 5-4 show possible states for the ASMD, Figure 5-15 show the modification in data path as required

by ASMD.


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Figure 5-16 shows the ASMD of the Processor with all states shown in table 5-4. Every instruction will be

fetch and decode, after decode the type of instruction defines which will be the next state. For R-Type

instruction Execute_Reg and Execute_WB. For Shift type instruction which is SR Type, Flow of R-Type

instructions are followed. While for Move Type instruction S_Exec_SR is acquired. All Two bytes

instructions S_Fetch2Byte is used. Branch instruction will use S_Branch. The read and write instruction

follow common execute cycle. After execute Read and write will use different write back stats.

Figure 5-16: Modifications in Data Path before writing ASMD of the control unit

Register File

PC

Memory

256x8ALU

DREG

MUX_ADDMUX_DATA

IR AREG

CONTR

OLUNIT

LD_IR

LD_AReg

Sel_MAdd

Sel_MData

LD_DReg

Flag_ALU

OpCode_ALU

RW_Mem

Add2_RFile

Add1_RFile

RW_RFile

RST_PC

LD_PC

INC_PC

Add_Mem

Din_Mem

Dout_Mem

Din_RFile

Inst

Data_IM

ShAMT_ALU

Enb_RFile

Enb_Mem


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Figure 5-17:ASMD of the RISC Processor

S_RST

RST_PC->1 LD_PC->0

LD_AReg->0 LD_IR->0

LD_DReg->0 Enb_RFile->0

Enb_Mem->0 INC_PC->0

DesReg->Inst[4:5] SrcReg->Inst[6:7]

SA->Inst[6:7] IVal->Inst[6:7]

OCode->Inst[0:3] INC_PC->1

LD_AReg->0 LD_IR->0

Enb_Mem->0 Enb_RFile->0

S_Decode

R-Type

S_WB_Reg

LD_Dreg->0 Sel_MData->0

RW_RFile->0 Enb_RFile->1

Add1_RFile->DesReg

SR-Type

S_Exec_SR

Data_IM->IVal Sel_MData->1

Enb_RFile->1 RW_RFile->0

ADD1_RFile->DesReg INC_PC->0

Shift Inst.

B TypeS_Branch

INC_PC->0 Sel_MAdd->0

LD_PC->1 LD_AReg->0

M Type

S_Exec_RW

Sel_MAdd->1 LD_AReg->0

INC_PC->1

RD

S_WB_RD

LD_AReg->0 Sel_MData->2


Add1_RFile->DesReg INC_PC->0

S_WB_WR

LD_AReg->0 Enb_RFile->1

RW_RFile->1 RW_Mem->1

Add1_RFile->DesReg

Enb_Mem->1 INC_PC->0

WR

S_Exec_Reg


Add1_RFile->DesReg

Add2_RFile->SrcReg

OpCode_ALU->OCode LD_DReg->1

INC_PC->0 ShAMT_ALU->SA

S_Fetch


LD_IR->1 Sel_MData->2

Enb_Mem->1 RST_PC->0

LD_PC->0 RW_Mem->0

Enb_RFile->0 INC_PC->0

S_HALT

HALT

S_Fetch2Byte


INC_PC->0


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5-5-1: Coding Control Unit

All States and Instructions are defined as constant in the start and Figure 5-17 shows the Implementation

of ASMD shown in figure 5-16. The implementation is orthodox ASMD style from chapter-3.

Figure 5-19 show the signal assignment of State transition reflected in Figure 5-18.

always@(posedge Clk or posedge RST)

if(RST==1)

State


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always@(State)

case(State)

S_RST:

begin

RST_PC


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5-5-2: Top Level Module of Processor

The last section of the chapter discusses the top level module of the processor.

S_WB_RD:

begin

LD_AReg


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5-6: Testing and Synchronization of Design

Testing such a large design requires organize pattern of testing, this is good point to share Organize

testing techniques. Chapter-14 will investigate SOC testing Techniques; however the current discussion

will reflect methodologies from Chapter-14. All testing requires three components.


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Exercise Problems5-1: If the instruction set given in Table 5-1 does not have multiply instruction we would require it using

assembly routine. Write Assembly routine to implement multiplication instruction using 15 Instructions

given in Table 5-1.

5-2: The processor in Figure 5-16 contain data path having two flags. Modify the flag mechanism and

add flagging mechanism with following flags.

Write Verilog code, behavioral level block for ALU module to implement the flagging Logic. Over Flow isdiscussed in 6-1-5.

5-3: The process discussed in section 5-3 contains mov instruction to move immediately value into

Din_Mem register File. Modify the architecture given in Figure P 5-3 to add a logic to move value from

register to register.

C AC OV Z CP1 CP2

Carry Auxiliary

Carry

Over Flow Zero Compare-1 Compare-2

RFile

ALU

MUX_DSEL

Data_IM Mem_Out


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5-4: The instruction register is passed directly to the control unit and it issues OpCode and Shift amount

to ALU, Source and destination address to Register File and determines the type of instruction. Come up

with the architecture where only 4-Bit instruction type is passed to the control unit. The source,

destination addresses and OpCode are directly passes in the datapath instead of routing through the

control unit. Draw the architecture of such configuration.

5-5: Assume that the memory is divided into 3 Partitions Code memory, Data Memory and The Stack.

Add two new instructions push and pop. The value to be pushed in the stack or popped form the stack is

taken or stored in the register file respectively.

Push R0 //Push Register R0 into Stack

Pop R0 //Pop Value from the top of the stack into Register R0

Recommend possible changes in data path and control Unit Draw relevant portion of data path only,

recommend changes in ASMD of control Unit after Fetch and decode. All other stages are not required.

5-6: Generally the registers in the processor are visible in the assembler. UART transmitter is used to

transmitt all values to the computer. Control Unit send all the registers to the computer once halt is

encountered in the program. Modify the ASMD to enable UART Transmission once HALT is encountered.

Code Memory

Data Memory

Stack

Processor

UART_

TX

Assembler


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5-7a: Consider Instruction set of 21 instructions given in the table P5-7. There are 16 registers and each

register is 16-bit wide. Design Instruction word for 16-Bit architecture.

ADD ADD R0,R1 CMP CMP R0 BRLT BRLT LABEL

ADDi ADDi R0,2 SLL SLL R0,1 BREQ BREQ LABEL

SUB SUB R0,R1 SLR SLR R0,1 BRG BRG LABEL

MUL MUL R0,R1 MOV MOV R0,3 JMP JMP LABEL

AND AND R0,R1 MOVR MOVR R0,R1 RD RD R0,200OR OR R0,R1 BRZ BRZ LABEL WR WR R0,200

XOR XOR R0,R1 BRNZ BRNZ LABEL HALT HALT

CONTROL

UNIT

Register File

ALU

UART_TX

RST_UART

t

t


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5-7b : The instruction set given in Pb 5-7a contains two instructions SLL and SLR for shifting operation.

Give the mechanism to merge the instructions into single shift instruction which can give shifting in both

directions .

5-8a: Section 5-6 defines the retiming of the processor where synchronization of data path and control

unit was done by premetive signal assignment. Another way of delaying the state transition of control

unit is to insert dummy states to generate no operation, This gives relaxation time for data path to

transact. Write the behavioural block for state transition of control unit or draw ASMD to reflect the

change through delay states.

5-8b: This problem is extensionof pb 5-8a. Another way of synchroniztion of data path and control unit

is to make the clock of control unit slow so that it transact accordingly. If control unit of processor is

made to move on slow clock what possible complication datapath can present.

5-9: If code and data memory were different, what difference will data path present. What otherregisters will be required? Give possible modification in ASMD of control Unit?

5-10: Consider mechanism of processor to handle routines/macros in assembly. Generally branches are

created towards sub routines. This requires special instruction to create a jump with return. More

registers are required to pass argument and to return the value from the register File. The 16x8 register

file is so divided that the last four registers can be used to pass four argument. The value is returned into

first argument register. If procedure call is not in progress these four register can be used as general

purpose registers. A new instruction JR(jump with return address) is added to return after jump.

Propose modification in control unit to accommodate this sort of jump.

5-11: The register file given Section 5-3 contains process where consective reads and writes are not

12 x 8

R0

R1

R2

R3


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possible. Modify the architecture in a way that data register is not requred. Change the register file

which can allow consective reads and write.

5-12:Figure 5-x presents modified Von Neuman architecture where the memory space is shared

between code and data. The von Neuman generally have data and address shared. Draw a data path

with shared data and address buses.

5-13: If the architecture is 32 bit and memory has each word equal to 1 byte. This means a oe instruction

will be stored on 4-Locations in the memory. The branch in this case relative to memory program

storage is deceptive. Think a way of achieving this possible type of branch. How to scale a address so

that a single branch represent 4-Locations Jump?

5-14a: In 32-Bit architecture PC will represent 232

memory. Similar can be said about AR, Suppose a

memory is of 216 location, hwo to ensure that memory cannot exceed 216 address possible location.

Think a way that lower left 16 bit only contain zero.

5-14b: The control unit can also be used to prevent PC of exceeding 216

locations. Device a mechanism

that control unit can prevent program counter for exceeding 216

Locations. Modify Data Path in a way

that it does not allow the address calculation more than the more then code memory.

ALU

DReg

RFile

MUX_DSEL

Add1_RFile

Add2_RFile


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5-15: The PC counter has control signal INC_PC which increment the program counter by 1. Suppose PC

does not have the signal to increment from Control Unit. Redraw the data path to accommodate

increment PC using ALU. What possible modification can be done to facilitate the ALU to increment the

PC.

5-16: The branchingmechanism of process given in Chapter-5 is absolute branching where PC is exactly

replaced with the address of branching. Another way of branching is PC relative addressing. For example

if PC Is currently at 20 and jump at 4 or 35 is required. Instead ofreplacing PC with 4 or 36, 16 is added

or subtracted from PC respectively. The branching process done by realtive of earlier PC address is called

PC relative address. Modify datapath and control unit to make PC relative addressing.

5-24: The multiplication of two 8-bit number can be a product ofa 16-bit. However the data register

attached with the ALU is only 8-bit. The architecture given in section 5-4 does not caters for this

constriants. The only wat to get out of this problem is to let the programmer know that the resultcannot exceed 8-bit. Suggest possible architecture for handling 16-Bit product results.

chapter 5, inside digital design

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