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Chapter 4

The Stack, Subroutines, Interrupts and Resets

In many computers, memory is divided into three distinct areas:- program area- data area- stack

The stack is an area of memory used for the temporary storage of information. Subroutines andinterrupts make use of the stack.

The stack pointer (SP) is a register within the P that contains the address of the next locationavailable for the stack.

The Ps internal logic causes the SP to decrement automatically when data is stored in the stack andto automatically increment when it is removed. Therefore, the SP must initially be set to thehighest address in the stack area (called the top of the stack).

e.g., if the stack is to occupy locations $0200 to $02FF then use LDS #$02FF instruction asinitialization before using the stack.

SP instructions are:

- DES SP - 1 SP- INS SP + 1 SP- LDS M:M + 1 SP (in immediate, direct, extended and indexed modes)- STS SP M:M + 1 (in direct, extended and indexed modes)- TXS IX - 1 SP- TSX SP + 1 IX- TYS IY - 1 SP- TSY SP + 1 IYPUSH and PULL Instructions

The push (PSH) and pull (PUL) instructions store and load data to and from the stack.

PSHA (or B or X or Y) instruction writes the contents of the specified register in the stack at the SPlocation (at the location whose address is contained in SP) and then decrements the SP once (forPSHA and PSHB) or twice (for PSHX and PSHY) because the original stack location is no longervacant but contains thepushed data.

PULA (or B or X or Y) instruction first increments the SP once to point to the last item that has beeninserted into the stack and then transfers the contents of the stack appropriately to the specifiedregister.

Note that once the contents of a stack location have been pulled, the location is considered vacant,although the data is still there. It will be overwritten by the next PUSH or other use of the stack. Alsonote that the stack acts as a Last-In-First-Out (LIFO) structure. A pull instruction retrieves theinformation that was last pushed onto the stack.

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Stack structure and stack operations

Subroutines

When the same function is required more than once in a program, it is frequently written as asubroutine, that is, a subprogram that can be used any number of times by the main program. Thiscapability is provided by the following three instructions;

o JSR (jump to subroutine)o BSR (branch to subroutine)o RTS (return from subroutine)

The following figure illustrates the use of the same subroutine by two different parts of the mainprogram. The subroutine located at $0200 can be entered from either location $0011 or $00CC byplacing a JSR (opcode = $BD) instruction at these addresses.

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Nested subroutines: Since PC saving and recovery is automatic by the use of stack, it is possible toexecute nested subroutines as follows.

Note that the stack state in the figure corrsponds to the time at which the processor executesinstructions within the second subroutine. Also note that if the stack is used for register savings in asubroutine, the recovery should be done in the reverse order and in a balanced fashion, otherwise thereturn address cannot be recovered properly into the PC.

Example: If a subroutine uses accumulators A and B and the CCR, how can the main programpreserve the contents of these registers?

The first four instruction of the subroutine may be

Opcode Mnemonic

36 PSHA37 PSHB07 TPA36 PSHA

which puts A, B and CCR on the stack as follows:

Contents of the stack after entering thesubroutine and executing the first fourinstructions

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Before returning to the main program, these registers should be restored in the subroutine in thereverse order before the RTS as follows:

Opcode Mnemonic

32 PULA06 TAP33 PULB32 PULA39 RTS

Example: Solve example 9 (square from a lookup table) as a subroutine and use it in a main programto calculate the square of two numbers stored in locations $41 and $42. Pass the input and theoutput parameters using accumulator A only. Store the result in $43 and $44.

label mnemonic commentSQR LDX #SQTAB load the base address of the table

TSTA check the input numberBEQ FOUND if it is zero, stop searching and goto FOUND

CONT INX otherwise; point to the next table entryDECA decrement ABNE CONT and repeat for a number of times

FOUND LDAA $00,X get the corresponding table entryRTS return from subroutine

MAIN LDAA $41 get the input dataJSR SQRSTAA $43 store the first resultLDAA $42JSR SQRSTAA $44 store the second result

END BRA END

Example: Write an M68HC11 program, which performs the following task:

There is a data array which starts in the memory location $0500. The length of the array is givenin the memory location $0040.

Some of the elements of the given array will be placed to another area in the memory starting atlocation $0900. Each element of the original array will be checked whether it is a 2-digit validBCD number or not and will be placed in the new array by reversing its bit order if it is valid, i.e,if the content of the memory location $0500, for example, is a valid 2-digit BCD numberX7X6X5X4X3X2X1X0 then X0X1X2X3X4X5X6X7 will be stored to the memory location $0900. Ifthe number is not a valid 2-digit BCD number, then it will not be stored. At the end, the memory

location $0041 will hold the total number of bytes in the new array.

Write the BCD checking part of your code as a subroutine.

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Solution: (write comments for the program as an exercise)

MAINLDS #$STACKBASELDX #$0500LDAB $40STAB BYTECOUNTLDY #$0900

CONTLDAA $00,XJSR CHKBCDBNE CONT2

VALIDLDAB #$08STAB BITCOUNT

CONTSHIFTLSLAROR $00,YDECBBNE CONTSHIFTINY

CONT2INXDEC BYTECOUNTBNE CONT

ENDBRA END

CHKBCDTABDAACBA

RTS

Interrupts and Resets

An interrupt is an hardware (sometimes software) initiated subroutine call or jump that interrupts thecurrently executing program. Depending on the type of the interrupt and the logic state of the I bit inthe condition code register, the CPU may suspend its normal operation and service the interrupt.

The software used in response to the interrupt signal is called an interrupt service subroutine. Afterthe interrupt service subroutine is executed, the CPU returns to the original program segment andresumes execution as if no interrupt has occurred. This requires the CPUs registers to be saved whenCPU services an interrupt and to be returned unaltered when the service subroutine is finished. An

interrupt service subroutine ends with an RTI instruction (not an RTS) that automatically restores theCPU registers.

Interrupt vectors

All resets and interrupts use vectors indicating the start address of reset or interrupt subroutines.68HC11 uses a vector table to store these vectors.

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The vector addresses are fixed and they are at a permanent part of the chip - usually at the ROM area.Hence, one has to tell the factory what to put in those areas before the mass production of the chip. Inorder to be able to change the start address of any interrupt subroutine, something called apesudovector is used in the development boards. For example in Motorola EVBU DevelopmentBoards, pesudovectors are reserved in the RAM area.

For each interrupt, the corresponding interrupt vector contains an address in the base page (memorylocations between $00 and $FF). The three-byte memory area starting from this RAM location is thenthe pseudovector for the corresponding interrupt. Hence the user places the actual service subroutineanywhere in the memory map and then writes a three byte jump instruction in the correspondingpseudovector, which effectively means that the associated subroutine is executed in the case of the

corresponding interrupt.

The IRQ vector (locations $FFF2 and $FFF3) of the chip on the EVBU development board contains$00EE. If the three byte RAM locations starting at $00EE is made to contain a JMP Addressinstruction (machine code $7E AdressH AddressL) then in the event of an IRQ interrupt, the programexecutes the code starting at locationAddress as illustrated below.

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When the signal at pin IRQ goes low, the CPU responds by putting the vector contents (i.e., $00EE)

to the PC, CPU then executes the instruction at $00EE, in this case JMP $C15A. Therefore, the actualservice subroutine starts at $C15A.

Interrupt masks and enables

An interrupt signal may or may not be recognized under programmers control by mostly setting theinterrupt mask bit (I bit) in the CPUs CCR. If I = 1, CPU does not recognize interrupt signals =>Interrupts are masked. I bit can be set by using the SEI instruction and cleared by using the CEIinstruction.

Stacking the registers

When an interrupt request occurs CPU pushes all CPU register values to stack in the order: PC, IY,IX, ACCA, ACCBA, CCR (pushing low byte first for 16-bit registers). When RTI is executed the datais pulled from the stack and the registers are restored.

For RESET: No stacking of the registers.

All interrupt service subroutines should end with an RTI instruction.

Hardware interrupts and resets

RESET: Executed whenever the chip is powered up and whenever the external RESET pin isactivated. Highest priority.

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Other processor resets: Computer Operating Properly (COP) failure reset, COP clock monitor failreset.

Nonmaskable interrupt (XIRQ): is used to handle the highest priority interrupts. When you power upor RESET 68HC11, XIRQ is masked, i.e. X bit in CCR is set. To clear X, TAP (Transfer from ACCAto CCR) instruction should be used.

Interrupt Request (IRQ): is maskable by setting bit I in the CCR.

IRQ versus XIRQ1. CPU can ignore the IRQ input if the I flag is 1; it can ignore XIRQ if the X flag is 1. However

I flag can be set and cleared any time by software. X flag can be cleared only once and then itremains at 0.

2. IRQ can be programmed as a level-sensitive or edge-sensitive input via the IRQE bit in theOPTION (at $1039) register. XIRQ is always level sensitive.

3. XIRQ input has higher priority over IRQ input. When they are activated simultaneously(while X=I=0), CPU will respond to XIRQ first.

Example of XIRQ interrupt

68HC11IRQ

XIRQ

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Software and CPU control interrupts

Software interrupt (SWI): SWI instruction forces the CPU to respond the same way as it does to anexternally generated interrupt. It is useful in debugging the programs. Not maskable by I or X bits inCCR.

Wait for Interrupt (WAI): When the WAI instruction is executed, 68HC11 reduces its power whilewaiting to be woken up. All registers are stacked and only an unmasked interrupt wakes up thecontroller.

STOP: When the STOP instruction is executed, if S bit in CCR is set, STOP performs like a NOP. If Sbit is reset, all internal clocks halt, thus halting the execution. To wake up the controller, RESET,XIRQ or IRQ (when I=0) must be used.

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Steps that 68HC11 follows to service the IRQ.