chapter 3 internal memory. objectives to describe the types of memory used for the main memory to...
TRANSCRIPT
Chapter 3Chapter 3
Internal MemoryInternal Memory
ObjectivesObjectives
To describe the types of memory used for To describe the types of memory used for the main memorythe main memory
To discuss about errors and error To discuss about errors and error corrections in the memory systemscorrections in the memory systems
To discuss more on advanced memory To discuss more on advanced memory organizationsorganizations
Key pointsKey points The two basic forms of semiconductor random access memory The two basic forms of semiconductor random access memory
are are dynamic RAM(DRAM)dynamic RAM(DRAM) and and static RAM(SRAM)static RAM(SRAM). SRAM is . SRAM is faster, expensive, less dense than DRAM and is used for faster, expensive, less dense than DRAM and is used for Cache and DRAM is used for main memory.Cache and DRAM is used for main memory.
Error correctionError correction techniques are commonly used in memory techniques are commonly used in memory systems. These involve adding redundant bits that are a systems. These involve adding redundant bits that are a function of the data bits to form an error-correcting code. If a bit function of the data bits to form an error-correcting code. If a bit error occurs, the code will detect and correct the error.error occurs, the code will detect and correct the error.
To compensate for the relatively To compensate for the relatively slow speed of DRAMslow speed of DRAM, a , a number of advanced DRAM organizations have been number of advanced DRAM organizations have been introduced. The two most common are synchronous DRAM and introduced. The two most common are synchronous DRAM and RamBus DRAM. RamBus DRAM.
Semiconductor Memory TypesSemiconductor Memory Types
OrganizationOrganizationThe basic element of a semiconductor memory is the memory The basic element of a semiconductor memory is the memory cell. All semiconductor memory cells share certain properties:-cell. All semiconductor memory cells share certain properties:-
They exhibit two stable states, which can be used toThey exhibit two stable states, which can be used to
represent binary 1 and 0represent binary 1 and 0
They are capable of being written into, to set the stateThey are capable of being written into, to set the state
They are capable of being read to sense the state.They are capable of being read to sense the state.
Memory Cell OperationMemory Cell Operation
Semiconductor MemorySemiconductor Memory RAM-random access memoryRAM-random access memory
Misnamed as all semiconductor memory is Misnamed as all semiconductor memory is random accessrandom access
Read/WriteRead/Write Volatile-RAM must be provided with constant Volatile-RAM must be provided with constant
power supply.power supply. RAM can be used only as Temporary storageRAM can be used only as Temporary storage Two traditional forms of RAM used in computers Two traditional forms of RAM used in computers
are Static or dynamic(DRAM, SRAM)are Static or dynamic(DRAM, SRAM)
Dynamic RAMDynamic RAM Bits stored as Bits stored as charge in capacitorscharge in capacitors and the presence or and the presence or
absence of charge in a capacitor is interpreted as a binary absence of charge in a capacitor is interpreted as a binary 1 or 01 or 0
Because of tendency to discharge, dynamic RAMs require Because of tendency to discharge, dynamic RAMs require periodic chargeperiodic charge refreshing to maintain data storage. refreshing to maintain data storage.
Used as main memoryUsed as main memory Simpler constructionSimpler construction Smaller per bitSmaller per bit Less expensiveLess expensive Need refresh circuitsNeed refresh circuits Slower - need refreshing processSlower - need refreshing process Essentially analogueEssentially analogue
Level of charge determines valueLevel of charge determines value
Dynamic RAM StructureDynamic RAM Structure
The address line is activated when the bit value from this cell is to be read or written. The transistor acts as a switch that is closed if a voltage is applied to the address line and opened if no voltage present on the address line.
DRAM OperationDRAM Operation WriteWrite
Voltage signals is applied to the bit line; a high voltageVoltage signals is applied to the bit line; a high voltagerepresents 1 and low voltage represents 0. A signal is represents 1 and low voltage represents 0. A signal is then applied to the address line, allowing a charge to then applied to the address line, allowing a charge to be transferred to the capacitor.be transferred to the capacitor.
ReadRead when the address line is selected, the transistor turns on and when the address line is selected, the transistor turns on and
the charge stored on the capacitor is fed out onto a bit line the charge stored on the capacitor is fed out onto a bit line and to a sense amplifier. The sense amplifier compares the and to a sense amplifier. The sense amplifier compares the capacitor voltage to a reference value and determines if the capacitor voltage to a reference value and determines if the cell contains a logic 1 or 0. The readout from the cell cell contains a logic 1 or 0. The readout from the cell discharges the capacitor, which must be restored to discharges the capacitor, which must be restored to complete the operation.complete the operation.
Static RAMStatic RAM Bits stored as on/off switchesBits stored as on/off switches No charges to leak because binary values are No charges to leak because binary values are
stored using traditional flip-flopstored using traditional flip-flop No refreshing needed when poweredNo refreshing needed when powered More complex constructionMore complex construction Larger per bitLarger per bit More expensive – complex logic gateMore expensive – complex logic gate Does not need refresh circuitsDoes not need refresh circuits FasterFaster Used as Cache memoryUsed as Cache memory
Stating RAM StructureStating RAM Structure
Static RAM OperationStatic RAM Operation
Transistor arrangement gives stable logic stateTransistor arrangement gives stable logic state State 1State 1
CC11 high, C high, C22 low low TT11 T T44 off, T off, T22 T T3 3 onon
State 0State 0 CC22 high, C high, C11 low low TT22 T T33 off, T off, T11 T T4 4 onon
Address line transistors TAddress line transistors T55 T T66 is switch is switch Write – apply value to B & compliment to BWrite – apply value to B & compliment to B Read – value is on line BRead – value is on line B
SRAM v DRAMSRAM v DRAM
Both volatileBoth volatile Power needed to preserve dataPower needed to preserve data
Dynamic cell Dynamic cell Simpler to build, smallerSimpler to build, smaller More denseMore dense Less expensiveLess expensive Needs refreshNeeds refresh Larger memory unitsLarger memory units
StaticStatic FasterFaster CacheCache
Read Only Memory (ROM)Read Only Memory (ROM)
Permanent storagePermanent storage NonvolatileNonvolatile
Microprogramming (Stallings Book ch.17)Microprogramming (Stallings Book ch.17) Library subroutines for frequently wanted Library subroutines for frequently wanted
functionsfunctions Systems programs (BIOS)Systems programs (BIOS) Function tablesFunction tables
Types of ROMTypes of ROM Written during manufactureWritten during manufacture
Very expensive for small runsVery expensive for small runs Programmable (once)Programmable (once)
Nonvolatile and may be written into only onceNonvolatile and may be written into only once Needs special equipment to program (tools)Needs special equipment to program (tools)
Read-mostly memory -> useful for applications in which Read-mostly memory -> useful for applications in which read operations are far more frequent than write operationread operations are far more frequent than write operation Erasable Programmable (EPROM)Erasable Programmable (EPROM)
Erased by UVErased by UV Electrically Erasable (EEPROM)Electrically Erasable (EEPROM)
Takes much longer to write than readTakes much longer to write than read Flash memoryFlash memory
Erase whole memory electricallyErase whole memory electrically
Error CorrectionError Correction
Hard FailureHard Failure Permanent defectPermanent defect
Soft ErrorSoft Error Random, non-destructiveRandom, non-destructive No permanent damage to memoryNo permanent damage to memory
Detected using Hamming error correcting Detected using Hamming error correcting codecode
Error Correcting Code FunctionError Correcting Code Function
Advanced DRAM OrganizationAdvanced DRAM Organization
Basic DRAM same since first RAM chipsBasic DRAM same since first RAM chips Enhanced DRAMEnhanced DRAM
Contains small SRAM as wellContains small SRAM as well SRAM holds last line readSRAM holds last line read
Cache DRAMCache DRAM Larger SRAM componentLarger SRAM component Use as cache or serial bufferUse as cache or serial buffer
Synchronous DRAM (SDRAM)Synchronous DRAM (SDRAM)
Access is synchronized with an external clockAccess is synchronized with an external clock Address is presented to RAMAddress is presented to RAM RAM finds data (CPU waits in conventional DRAM)RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, Since SDRAM moves data in time with system clock,
CPU knows when data will be readyCPU knows when data will be ready CPU does not have to wait, it can do something elseCPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data Burst mode allows SDRAM to set up stream of data
and fire it out in blockand fire it out in block DDR-SDRAM sends data twice per clock cycle DDR-SDRAM sends data twice per clock cycle
(leading & trailing edge)(leading & trailing edge)
SDRAMSDRAM
SDRAM Read TimingSDRAM Read Timing
RAMBUSRAMBUS Adopted by Intel for Pentium & ItaniumAdopted by Intel for Pentium & Itanium Main competitor to SDRAMMain competitor to SDRAM Vertical package – all pins on one sideVertical package – all pins on one side Data exchange over 28 wires < cm longData exchange over 28 wires < cm long Bus addresses up to 320 RDRAM chips at Bus addresses up to 320 RDRAM chips at
1.6Gbps1.6Gbps Asynchronous block protocolAsynchronous block protocol
480ns access time480ns access time Then 1.6 GbpsThen 1.6 Gbps
RAMBUS DiagramRAMBUS Diagram
DDR SDRAMDDR SDRAM
SDRAM can only send data once per SDRAM can only send data once per clockclock
Double-data-rate SDRAM can send data Double-data-rate SDRAM can send data twice per clock cycletwice per clock cycle Rising edge and falling edgeRising edge and falling edge
Cache DRAMCache DRAM
MitsubishiMitsubishi Integrates small SRAM cache (16 kb) onto generic DRAM Integrates small SRAM cache (16 kb) onto generic DRAM
chipchip Used as true cacheUsed as true cache
64-bit lines64-bit lines Effective for ordinary random accessEffective for ordinary random access
To support serial access of block of dataTo support serial access of block of data E.g. refresh bit-mapped screenE.g. refresh bit-mapped screen
CDRAM can prefetch data from DRAM into SRAM CDRAM can prefetch data from DRAM into SRAM bufferbuffer
Subsequent accesses solely to SRAMSubsequent accesses solely to SRAM