Chapter 3

Embedded Computing in the Emerging Smart Grid

Arindam Mukherjee, ValentinaCecchi, Rohith Tenneti, and Aravind Kailas

Electrical and Computer Engineering Department, University of North Carolina, Charlotte

Information technology back bone of smart grid

Data

•Smart meters in advanced metering infrastructure sensor/control information

•Renewable and less predictable power sources status/control information

•Data collected by remote terminal units from field units

Communication

• Secure transfer encryption/decryption

• State of the art transfer protocol for communication via power lines/wireless/dedicated wirelines

•Two way communication at all levels

Compute and Control

•Computations for signal processing

•Computations for cyber security

•Power flow calculations for control

•Intelligent control for optimal power usage

Computations in smart grid?• Analysis and Control

• Sensing and Measurement infrastructure

• Communication and security

Intel Atom (state of the art)

Advantages•In-order execution

• Low power• Lesser die space

Disadvantages•Memory access has long latencies for floating point and SIMD instructions

•In-order execution (Long latency)Intel Atom Pine trail

ARM Cortex A8 (state of the art)

Advantage•In-order cores

• Low power• Lesser area

Disadvantages•Deep pipelines, introduce latency•Instruction level parallelism cannot be exploited ARM Cortex A8 neon integer

pipeline

New processor?

• Microarchitecture is currently not optimized for the smart grid applications

• Customize architecture for specific computations for better efficiency

• Efficiency• Latency and throughput

requirements for real time applications

• Consume lesser power compared to state of the art processors

• One embedded processor to handle varied applications

Design space explorationIdentify the Application

E.g. Smart Grid Embedded Applications

Identify Benchmark

Programs to run on the Processor

Profile the Benchmarks

Multi CoreYes No

Find the Best Core for each kind of

computation in the

benchmarks

Find a Core suitable for all kinds of computation

s

Identify a Cycle Accurate

Simulator to explore

Heterogeneous Configurations in the micro-

Architecture and Architecture

Run the optimizing algorithm

(on Power/Latency/CPI/Area equations

) to identify the best

parameters of

architecture

Run the Simulator

with a specific

configuration

E.g. In smart Grid

ApplicationsWe Identify

Signal Processing,

Security Encryption, Power Flow

calculations as possible

benchmarks

In profiling we identify the compute/memory

intensive parts in the code and try to optimize

them before customizing the

architecture although it is a cyclic process

Design space exploration - Basic Steps

• Identify the application and profile the benchmarks

• Identify the processor simulators

• Optimize the architecture

Applications• Power flow studies – Aid in

control

• Fast fourier transform – Signal processing

• Blowfish encryption – Security

The benchmarks are optimized based on the architecture.

Processor simulators• Casper - A Sparc V9 based Cycle accurate chip-multithreaded Architecture

Simulator for Performance, Energy and aRea analysis. Based on open sourced Sun’s Ultra Sparc-T1 architecture.

• MPTLSim - A cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches

• MV5 - An Event-driven, Cycle-accurate Simulator for Heterogeneous Manycore Architectures

Casper Customize

•Cores on chip•Threads per core•L1, L2 cache size/associativity/banks•Size of load miss queue, missed instruction list, data fill queue, branch address buffer, store buffer, cache fill buffer•Set instruction/data cache latency

Measure•Power•Area•CPI•Throughput•Latency•Pipeline stalls•Wait time for threads•Instruction/data cache misses

MPTLSim• All parameters listed in Casper are configurable in MPTLSim

• Additional features

• Full system capability

• Implements branch prediction

• Out of order execution (no In-order execution)

• Configure RTL models of the pipeline units

MV5• Implements all features of the

earlier simulators (no support for full system emulation)

• Additional features• X-86, Alpha, Sparc all architectures

are supported• Heterogeneous configuration in

terms of the microarchitecture features like SIMD/Out of order/In order are supported

• Different On chip networks can be explored

• Run different benchmarks on different cores

Example configuration

L2 Cache

Out of Order

I-Cache D-Cache

SIMD SIMD

SIMD

L2 Cache

I-cache D-cache I-cache D-

cache

I-cache D-cache

L3

Main memory

SIMDI-cache D-

cache

Optimal configurationFew methods•Linear/Non-linear regression•Genetic algorithms•Artificial neural networks•Strength Pareto evolution•Fuzzy logic

Algorithms for best initial training set•Random sampling•Placket-Burman design of experiments•Latin hypercube

Open research

• Benchmark suite development for the smart grid applications

• Operating system for the smart grid applications